ROHM BU16006KV

HDMI Switch ICs
3 for input 1 output switch with
Termination sense
correspondence
(Sync with HPD_SINK)
BU16018KV
No.09063EDT02
●Description
BU16018KV is 3 for input 1 output HDMI/DVI switch LSI. Each port supports 2.25Gbps. (HDMI 1.3a).
This device control is simple. It requires only 3.3V source and a few GPIO controls.
Terminated resistors(50Ω) are integrated at each input port. When channel is not selected, termination resistors are turned
off. TMDS inputs are high impedance.
This device is integrated equalization function and DDC buffer function, so It can adapt long cable.
●Features
1) Supports 2.25 Gbps signaling rate for 480i/p, 720i/p, and 1080i/p resolution to 12-bit color depth
2) Compatible with HDMI 1.3a
3) Each port supports HDMI or DVI inputs
4) 5V tolerance to all DDC and HPD_SINK inputs
5) Integrated DDC buffer
6) Integrated switchable 50Ωreceiver termination
7) Integrated equalizer circuit to adapt long cable
8) High impedance outputs when disabled
9) HBM ESD Protection exceeds 10kV
10) 3.3V supply operation
11) VQFP80 package
12) ROHS compatible
●Applications
Digital TV, DVD Player, Set-Top-Box, Audio Video Receiver, Digital Projector, DVI or HDMI Switch Box
●Line up matrix
Part No.
Power
Supply
(V)
ESD
(KV)
BU16020KV
3 to 3.6
10
BU16018KV
3 to 3.6
10
BU16027KV
3 to 3.6
10
BU16006KV
3 to 3.6
10
BU16024KV
3 to 3.6
10
Input
(ch)
HDMI
4ch
HDMI
3ch
HDMI
3ch
HDMI
2ch
HDMI
1ch
Output
(ch)
Data rate
(Gbps)
Hot
Plug
Control
Termination
Sense
Correspondence
Switching
Method
DDC
Buffer
Equalizer
De emphasis
Package
RoHS
2
Yes
VQFP100
Yes
Yes
VQFP80
Yes
VQFP64
Yes
HDMI 1ch
2.7
Yes
Yes
GPIO/I C
Yes
Yes
(adaptive)
HDMI 1ch
2.25
Yes
Yes
GPIO
Yes
Yes
HDMI 1ch
2.25
Yes
Yes
GPIO
Yes
Yes
HDMI 1ch
2.25
Yes
Yes
GPIO
Yes
Yes
HDMI 1ch
2.25
Yes
Yes
-
Yes
Yes
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© 2009 ROHM Co., Ltd. All rights reserved.
1/19
Yes
(Always ON)
Yes
(Always ON)
Yes
VQFP64
Yes
VQFP48C
Yes
2009.05 - Rev.D
Technical Note
BU16018KV
●OUTSIDE DIMENSION CHART
BU16018KV
1PIN MARK
Lot No.
Figure 1-1 Outside dimension chart
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© 2009 ROHM Co., Ltd. All rights reserved.
2/19
2009.05 - Rev.D
Technical Note
BU16018KV
●BLOCK DIAGRAM
Figure 2-1 Block Diagram
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© 2009 ROHM Co., Ltd. All rights reserved.
3/19
2009.05 - Rev.D
Technical Note
BU16018KV
●PIN EXPLANATION
TEST3
GND
A34
B34
VCC
A33
B33
GND
A32
B32
VCC
A31
B31
GND
SCL3
SDA3
HPD3
VCC
OE
TEST2
1). PIN ASSIGNMENT
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
VCC
HPD2
SDA2
SCL2
GND
GND
B21
A21
VCC
B22
A22
GND
B23
A23
VCC
B24
A24
GND
VCC
HPD1
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
HPD_SINK
SDA_SINK
SCL_SINK
GND
GND
Z1
Y1
VCC
Z2
Y2
GND
Z3
Y3
VCC
Z4
Y4
GND
S3
S2
S1
TEST0
SDA1
SCL1
GND
B11
A11
VCC
B12
A12
GND
B13
A13
VCC
B14
A14
GND
VCC
VSADJ
PRE
TEST1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Figure 3-1 Pin Location
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© 2009 ROHM Co., Ltd. All rights reserved.
4/19
2009.05 - Rev.D
Technical Note
BU16018KV
2). PIN LIST
TERMINAL
NAME
No.
A11, A12, A13, A14
6, 9, 12, 15
A21, A22, A23, A24
68, 71, 74, 77
A31, A32, A33, A34
49, 52, 55, 58
B11, B12, B13, B14
5, 8, 11, 14
B21, B22, B23, B24
67, 70, 73, 76
B31, B32, B33, B34
48, 51, 54, 57
4, 10, 16, 24,
30, 36, 37, 47,
GND
53, 59, 65, 66,
72, 78
HPD1
80
HPD2
62
HPD3
44
HPD_SINK
TEST0,1,2,3
_______
OE
PRE
SCL1
SCL2
SCL3
SCL_SINK
SDA1
SDA2
SDA3
SDA_SINK
S1, S2, S3
VCC
VSADJ
Y1, Y2, Y3, Y4
Z1, Z2, Z3, Z4
I/O
I
I
I
I
I
I
O
O
O
I
1, 20, 41, 60
42
I
19
I
3
64
46
38
2
63
45
39
21, 22, 23
7, 13, 17, 27,
33, 43, 50, 56,
61, 69, 75, 79
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
18
I
34, 31, 28, 25
35, 32, 29, 26
O
O
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Port 1 TMDS positive inputs
Port 2 TMDS positive inputs
Port 3 TMDS positive inputs
Port 1 TMDS negative inputs
Port 2 TMDS negative inputs
Port 3 TMDS negative inputs
Ground
40
© 2009 ROHM Co., Ltd. All rights reserved.
DESCRIPTION
Port 1 hot plug detector output
Port 2 hot plug detector output
Port 3 hot plug detector output
Sink side hot plug detector input
High : 5-V power signal asserted from source to sink and
EDID is ready
Low : No 5-V power signal asserted from source to sink
or
EDID is not ready
Open or GND connect (recommend)
Output enable, active low
Output de-emphasis adjustment
High : ON, Low : OFF
Port 1 DDC bus clock line
Port 2 DDC bus clock line
Port 3 DDC bus clock line
Sink side DDC bus clock line
Port 1 DDC bus data line
Port 2 DDC bus data line
Port 3 DDC bus data line
Sink side DDC bus data line
Source selector input
Power supply
TMDS compliant voltage swing control. Connect to GND
via 4.64KΩ
TMDS positive outputs
TMDS negative outputs
5/19
2009.05 - Rev.D
Technical Note
BU16018KV
●EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
Control Input Stage
TMDS Output Stage
TMDS Input Stage
Vcc
Vcc
Vcc
Vcc
50Ω
50Ω
Ym
Bnm
Anm
Zm
Vcc
PRE
OE
S1
S2
S3
10mA
DDC Input/Output Stage
HPD Output Stage
HPD_SINK Input Stage
Vcc
Vcc
Vcc
SCL_SINK
SDA_SINK
SCLn
SDAn
HPD_SINK
Vcc
HPDn
※n=1,2,3 m=1,2,3,4
Figure 4-1 I/O pin schematic diagram
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© 2009 ROHM Co., Ltd. All rights reserved.
6/19
2009.05 - Rev.D
Technical Note
BU16018KV
●SOURCE SELECTION LOOKUP TABLE
CONTROL PINS
HPD_SINK
S1
S2
S3
H
H
X
X
H
L
H
X
H
L
L
H
H
L
L
L
L
H
X
X
L
L
H
X
L
L
L
H
L
L
L
L
I/O SELECTED
Y/Z
A1/B1
Terminations of A2/B2
and A3/B3 are
disconnected
A2/B2
Terminations of A1/B1
and A3/B3 are
disconnected
A3/B3
Terminations of A1/B1
and A2/B2 are
disconnected
None (Z)
All terminations are
disconnected
Disallowed
(indeterminate)State
All terminations are
disconnected
Disallowed
(indeterminate)State
All terminations are
disconnected
Disallowed
(indeterminate)State
All terminations are
disconnected
None (Z)
All terminations are
disconnected
HOT PLUG DETECT STATUS
SCL_SINK
HPD1
HPD2
SDA_SINK
HPD3
SCL1
SDA1
H
L
L
SCL2
SDA2
L
H
L
SCL3
SDA3
L
L
H
None (Z)
Are pulled HIGH by
external pull-up
termination
H
H
H
SCL1
SDA1
L
L
L
SCL2
SDA2
L
L
L
SCL3
SDA3
L
L
L
None (Z)
Are pulled HIGH by
external pull-up
termination
L
L
L
(1) H: Logic high; L: Logic low; X: Don’t care; Z: High impedance
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© 2009 ROHM Co., Ltd. All rights reserved.
7/19
2009.05 - Rev.D
Technical Note
BU16018KV
●ERECTRICAL SPECIFICATIONS
1.) ABSOLUTE MAXIMUM RATINGS
(1)
Over operating free-air temperature range (unless otherwise noted)
ITEM
MIN.
TYP.
MAX.
Power supply voltage(Vcc)
-0.3
4.0
DDC,HPD_SINK input voltage
-0.3
6.0
Differential input voltage
2.5
4.0
_____
PRE, S1, S2, S3, OE input voltage
-0.3
4.0
Power dissipation
1200 ※1
Storage temperature range
-55
125
※70mm×70mm×1.6mm glass epoxy board mount.(Reverse Cu occupation rate:15mm×15mm)
When it’s used by than Ta=25℃, it’s reduced by 12mW/℃.
2.) RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
VCC
Supply voltage
TA
Operating free-air temperature
TMDS DIFFERENTIAL PINS (A/B)
VID
Receiver peak-to-peak differential input voltage
VIC
Input common mode voltage
RVSADJ
Resistor for TMDS compliant voltage swing range
AVCC
TMDS output termination voltage
RT
Termination resistance
Signaling rate
CONTROL PINS (S1,S2)
VIH
LVTTL High-level input voltage
VIL
LVTTL Low-level input voltage
STATUS(HPD_SINK)
VIH
LVTTL High-level input voltage
VIL
LVTTL Low-level input voltage
DDC PINS (SCL_SINK, SDA_SINK,SDA[3:1],SCL[3:1])
VI(DDC)
Input voltage
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© 2009 ROHM Co., Ltd. All rights reserved.
8/19
UNIT
V
V
V
V
mW
℃
MIN.
3.0
0
TYP.
3.3
-
MAX.
3.6
70
UNIT
V
℃
150
VCC-0.6
4.6
3.0
45
0
4.64
3.3
50
-
1560
VCC+0.01
4.68
3.6
55
2.25
mVp-p
V
KΩ
V
Ω
Gbps
2
GND
-
VCC
0.8
V
V
2.4
GND
-
5.5
0.8
V
V
GND
-
5.5
V
2009.05 - Rev.D
Technical Note
BU16018KV
3.) ELECTRICAL CHARACTERISTICS
Over recommended operating conditions (unless otherwise noted))
LIMITS
PARAMETER
SYMBOL
Icc
Supply current
PD
Power dissipation
TMDS DIFFERENTIAL PINS (A/B; Y/Z)
Single-ended high-level output
VOH
voltage
Single-ended low-level output
VOL
voltage
Single-ended low-level swing
VSWING
voltage
Overshoot of output differential
VOD(O)
voltage
Undershoot of output
VOD(U)
differential voltage
VODE(SS)
RINT
⊿VOC(SS)
Steady state output differential
voltage
with de-emphasis
Input termination resistance
Change in steady-state
common-mode output voltage
between logic states
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© 2009 ROHM Co., Ltd. All rights reserved.
TEST CONDITIONS
VIH =Vcc, VIL =Vcc-0.4V,RVSADJ =
4.64kΩ
RT = 50Ω,AVcc = 3.3V
Anm/Bnm=2.25Gbps HDMI data
pattern
n = 1 or 2 or 3, m = 2, 3, 4
An1/Bn1 = 225 MHz clock
VIH =Vcc, VIL =Vcc-0.4V,RVSADJ =
4.64kΩ
RT = 50Ω,AVcc = 3.3V
Anm/Bnm=2.25Gbps HDMI data
pattern,
n = 1 or 2 or 3, m = 2, 3, 4
An1/Bn1 = 225 MHz clock
AVcc = 3.3V,
RT = 50Ω,PRE = 0V
PRE = Vcc
Anm/Bnm = 250 Mbps HDMI data
pattern ,
n = 1 or 2 or 3, m = 2, 3, 4
An1/Bn1 = 25 MHz clock
VIN = 2.9V
9/19
UNIT
MIN.
TYP.(1)
MAX.
-
120
150
mA
-
450
600
mW
AVcc-10
-
AVcc+10
mV
AVcc-600
-
AVcc-400
mV
400
-
600
mV
-
6%
15%
2xVswing
-
12%
25%
2xVswing
600
-
920
mVp-p
45
50
55
Ω
-
5
-
mV
2009.05 - Rev.D
Technical Note
BU16018KV
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
MIN.
TYP.(1)
MAX.
VI = 5.5V
-10
-
10
uA
VI = VCC
-10
-
10
uA
VO = 3.6V
VI L = GND
RL= 4.7kΩ
-10
-10
0.43
0.5
10
10
0.57
uA
uA
V
20
100
190
mV
0.43
0.5
0.57
V
20
100
190
mV
VI = 5.5V
VI = VCC
VO = 3.6V
VIL = GND
IOUT = 4mA
-10
-10
-10
-10
-
-
10
10
10
10
0.2
uA
uA
uA
uA
V
VIH = VCC
VIL = GND
-10
-10
-
10
10
uA
uA
VIH = 5.5V
VIH = VCC
VIL = GND
10
5
-10
50
30
-
100
80
10
uA
uA
uA
IOH = - 8mA
IOL = 8mA
2.4
0
-
Vcc
0.4
V
V
DDC Input and output
Tx : SCL_SINK , SDA_SINK
IlkT ①
Input leak current
IlkT
②
Input leak current
IOHT
IILT
VOLT
High-level output current
Low-level input current
Low-level output voltage
Low-level input voltage below
VOLT - VIL
output low-level voltage
VOLT
Low-level output voltage
Low-level input voltage below
VOLT-VIL
output low-level voltage
Rx : SCLn , SDAn ( n = 1, 2, 3 )
IlkR ①
Input leak current
IlkR ②
Input leak current
IOHR
High-level output current
IILR
Low-level input current
VOLR
Low-level output voltage
_____
CONTROL PINS (PRE, S1, S2, S3, OE)
IIH
High–level digital input current
IIL
Low–level digital input current
RL=4.7kΩ
STATUS PINS (HPD_SINK)
IIH
High–level digital input current
IIL
Low–level digital input current
STATUS PINS (HPD1, 2, 3)
VOH(TTL)
VOL(TTL)
TTL High–level output voltage
TTL Low–level output voltage
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© 2009 ROHM Co., Ltd. All rights reserved.
10/19
2009.05 - Rev.D
Technical Note
BU16018KV
SYMBOL
PARAMETER
TEST CONDITIONS
TMDS DIFFERENTIAL PINS (Y/Z)
Propagation delay time
tPLH
low-high-level
output
Propagation delay time
tPHL
high-low level
output
Differential output signal rise
tr
time
See Figure 5-2, AVCC = 3.3V,
(20%-80%)
RT = 50Ω, PRE=0V
Differential output signal fall
tf
time (20%-80%)
tsk(p)
Pulse skew (|tPHL - tPLH |)
Intra-pair differential skew, see
tsk(D)
Figure 5-3.
Inter-pair channel-to-channel
tsk(o)
(2)
output skew
tsk(pp)
Part to part skew(3)
tsx
Select to switch output
tdis
Disable time
ten
Enable time
DDC I/O PINS (SCLn, SCL_SINK, SDA,n SDA_SINK) (n = 1, 2, 3)
Propagation delay time,
tpdLHTR(DDC) low-to-high-level output
Tx to Rx
RL = 4.7KΩ CL = 100pF
Propagation delay time,
tpdHLTR(DDC)
high-to-low-level output
Tx to Rx
Propagation delay time,
tpdLHRT(DDC)
low-to-high-level output
Rx to Tx
RL = 1.67KΩ CL = 400pF
Propagation delay time,
tpdHLRT(DDC)
high-to-low-level output
Rx to Tx
tr Tx(DDC) Tx output Rise time
RL = 4.7KΩ CL = 100pF
tf Tx(DDC) Tx output Fall time
tr Rx(DDC) Rx output Rise time
RL = 1.67KΩ CL = 400pF
tf Rx(DDC) Rx output Fall time
Switch time from SCLn to
tsx(DDC)
CL=10pF
SCL_SINK
CIO
Input/output capacitance
VI=0V
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© 2009 ROHM Co., Ltd. All rights reserved.
11/19
LIMITS
UNIT
MIN.
TYP.(1)
MAX.
-
480
-
ps
-
500
-
ps
-
160
-
ps
-
160
-
ps
-
20
-
ps
-
35
-
ps
-
50
-
ps
-
400
8
5
7
-
ps
ns
ns
ns
-
650
-
ns
-
200
-
ns
-
500
-
ns
-
350
-
ns
-
800
150
950
50
-
ns
ns
ns
ns
-
800
-
ns
15
pF
2009.05 - Rev.D
Technical Note
BU16018KV
SYMBOL
PARAMETER
STATUS PINS(HPD1, 2, 3)
Propagation delay time,
tpdLH(HPD) low-to-high-level output from
HPD_SINK to HPDn(n=1,2,3)
Propagation delay time,
tpdHL(HPD) high-to-low-level output from
HPD_SINK to HPDn(n=1,2,3)
Switch time from port select to
tsx(HPD)
the latest valid status of HPD
TEST CONDITIONS
LIMITS
UNIT
MIN.
TYP.(1)
MAX.
CL=10pF
-
5
-
ns
CL=10pF
-
5
-
ns
CL=10pF
-
8
-
ns
Note:
1. All typical values are at 25℃ and with a 3.3V supply.
2. tsk(o) is the magnitude of the difference in propagation delay times between any specified terminals of channel of a
devices when inputs are tied together.
3. tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of channel two
devices, or between channel 1 of two devices, when both devices operate with the same source, the same supply voltages,
at the same temperature, and have identical packages and test circuits.
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© 2009 ROHM Co., Ltd. All rights reserved.
12/19
2009.05 - Rev.D
Technical Note
BU16018KV
●MEASUREMENT SYMBOL AND CIRCUIT
PARAMETER MEASUREMENT INFORMATION
AVcc
RT
RT
Zo = R T
TMDS
Receiver
Zo = R T
TMDS
Driver
Figure 5-1 Termination for TMDS Output Driver
PARAMETER MEASUREMENT INFORMATION (continued)
Vcc
RINT
RINT
VA
A
VID
TMDS
Receiver
TMDS
Driver
B
VB
RT
Y
VID = VA - VB
CL
0.5pF
Z
Vswing = VY - VZ
AVCC
VY RT
VZ
VA
DC Coupled
VCC
AC Coupled
VCC+0.2V
VB
Vcc-0.4 V
Vcc-0.2 V
VID
VID(pp)
0.4 V
VID
0V
-0.4 V
tPHL
tPLH
80%
VOD(O)
VOD(pp)
20%
tf
100%
0V Differential
0%
tr
VOD(U)
VOC
△VOS(SS)
Figure 5-2 Timing Test Circuit and Definitions
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© 2009 ROHM Co., Ltd. All rights reserved.
13/19
2009.05 - Rev.D
Technical Note
BU16018KV
VY
VOH
50%
VZ
VOL
tsk(D)
Figure 5-3 Definition of Intra-Pair Differential Skew
PARAMETER MEASUREMENT INFORMATION (continued)
A
Vcc V
Port 1
Vcc-0.4 V
B
A
Port 2
Vcc-0.4 V
Vcc V
B
A
Port 3
Vcc-0.4 V
B
Vcc V
VDD
2
S1
Clocking
VDD
0V
S2=VDD
S3=0V
OE
0V
tsx
Output
tsx
Y
75mV
Z
-75mV
75mV
HI-Z
tdis
-75mV
ten
Figure 5-4 TMDS Outputs Control Timing Definitions
VDD
2
HPD_SINK
VDD
2
HPD1
tpdHL(HPD)
tpdLH(HPD)
tsx(HPD)
2.4V
HPD2
HPD3
0V
S1
Vcc
2
S2
SDA_SINK
tpdHLRT(DDC) tpdLHRT(DDC)
80%
20%
tpdHLTR(DDC)
tpdLHTR(DDC)
1.5V
V IL
SDA1
80%
20%
1.5V
SDA2
SDA3
VDD
tSX(DDC)
0V
tfTX(DDC)
trTX(DDC)
tfRX(DDC)
RX to TX
trRX(DDC)
VDD
TX to RX
Figure 5-5 DDC and HPD Timing Definitions
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© 2009 ROHM Co., Ltd. All rights reserved.
14/19
2009.05 - Rev.D
Technical Note
BU16018KV
1). Y and Z terminal ESD diode notice.
Y and Z terminals are connected ESD diode.
When VCC+0.4 < AVCC.
BU16018KV flow leak current from AVCC to VCC.
In order to pass the compliance test.
You must use mandatory application, refer Figure 6-1 for “Repeater” or “output Buffer” application.
If you use “Repeater” or “output Buffer”
power down
controler
10kΩ
AVCC
VCC
10kΩ
10kΩ
TEST0
TEST2
TEST1
Figure 6-1 Leak current control
2). HPD_SINK Pull down resistance.
HPD_SINK is a 5V tolerant structure shown in Figure 6-2.
It needs some drive current to pull down HPD_SINK "H" to "L"([email protected]_SINK=2V).
So to pull down HPD_SINK, please use 10kΩ(or under 10kΩ) resistor.
VCC
BU16018KV
HPD_SINK
10kΩ
Figure 6-2 HPD_SINK I/O schematic
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© 2009 ROHM Co., Ltd. All rights reserved.
15/19
2009.05 - Rev.D
Technical Note
BU16018KV
3). About don’t use terminal.
Unused TMDS input channel can be opened.
BU16018KV
Vcc
R INT
R INT
RT
A
TMDS
Receiver
Y
TMDS
Driver
Z
B
AVcc
RT
Figure 6-3 TMDS Input Fail-Safe Recommendation
Unused DDC Buffers of R side polled up to Vdd
VCC
4.7k
T
RSCL
RSDA
TSCL
TSDA
R
Figure 6-4 DDC Buffers in BU16018KV
Open unused HPDn.
Figure 6-5 Open unused HPDn
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© 2009 ROHM Co., Ltd. All rights reserved.
16/19
2009.05 - Rev.D
Technical Note
BU16018KV
4). About serial connect notice.
When HDMI sw output connect to other HDMI sw input like following application.
There is possibility that. 1080p(12bit) image isn’t displayed. It’s depend on receiver IC characteristic.
When system is required 1080p (12bit), Rohm doesn’t recommend serial connect application.
Vcc
RINT
Vcc
RINT
RINT
RINT
RT
A
TMDS
Receiver
TMDS
Driver
B
Y
A
Z
B
TMDS
Receiver
TMDS
Driver
Y
Z
AVCC
RT
Figure 6-6 serial connect notice
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© 2009 ROHM Co., Ltd. All rights reserved.
17/19
2009.05 - Rev.D
Technical Note
BU16018KV
5). Offset voltage appearance.
If differential input is opened, offset voltage appear at differential output OE is set to low to avoid it.
Figure 6-7 Offset voltage avoid
6). Limitation of Master and slave direction.
Figure 6-8 Limitation of Master and slave direction
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© 2009 ROHM Co., Ltd. All rights reserved.
18/19
2009.05 - Rev.D
Technical Note
BU16018KV
 Ordering part number
B U 1 6 0 1 8
ROHM model name
K V
E 2
Package type
VQFP80
Packaging and forming specification
E2 =Reel-shaped emboss taping
Package specification
VQFP80
<Tape and Reel information>
14.0±0.2
12.0±0.1
60
41
20
1
0.5 ± 0.15
E2
direction is the 1pin of product is at the upper left when you hold
( The
)
reel on the left hand and you pull out the tape on the right hand
+0.05
0.145 -0.03
1PIN MARK
S
4 +6
–4
1.4 ± 0.05
0.1± 0.05
1.6MAX
1000pcs
Direction
of feed
1.0± 0.2
1.25
21
80
1.25
Embossed carrier tape (with dry pack)
Quantity
40
12.0 ± 0.1
14.0 ± 0.2
61
Tape
0.08 S
+0.05
0.2 -0.04
0.08
M
1pin
0.5±0.1
(Unit : mm)
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© 2009 ROHM Co., Ltd. All rights reserved.
Reel
19/19
Direction of feed
∗ Order quantity needs to be multiple of the minimum quantity.
2009.05 - Rev.D
Notice
Notes
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"Products"). If you wish to use any such Product, please be sure to refer to the specifications,
which can be obtained from ROHM upon request.
Examples of application circuits, circuit constants and any other information contained herein
illustrate the standard usage and operations of the Products. The peripheral conditions must
be taken into account when designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specified in this document.
However, should you incur any damage arising from any inaccuracy or misprint of such
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The technical information specified herein is intended only to show the typical functions of and
examples of application circuits for the Products. ROHM does not grant you, explicitly or
implicitly, any license to use or exercise intellectual property or other rights held by ROHM and
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R0039A