AMD A77E FusionController Hub Databook

AMD A77E Fusion
Controller Hub Databook
Publication No.
Revision
Date
53830
3.01
February 2014
Advanced Micro Devices
© 2013, 2014 Advanced Micro Devices Inc. All rights reserved.
The information contained herein is for informational purposes only, and is subject to change without notice.
While every precaution has been taken in the preparation of this document, it may contain technical
inaccuracies, omissions and typographical errors, and AMD is under no obligation to update or otherwise
correct this information. Advanced Micro Devices, Inc. makes no representations or warranties with respect to
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AMD, the AMD Arrow logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc. Other product names used in this
publication are for identification purposes only and may be trademarks of their respective companies.
Microsft, Windows and Windows Vista are registered trademarks of Microsoft corporation.
PCI Express and PCIe are registered trademarks of PCI-SIG.
53830
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Contents
Chapter 1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
1.1
Features of Bolton-E4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
1.2
Branding and Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
1.3
Bolton-E4 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
1.4
Conventions and Notations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
1.4.1
Pin Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
1.4.2
Pin Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
1.4.3
Numeric Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
1.4.4
Register Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
1.4.5
Acronyms and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Chapter 2
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
2.1
USB Controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
2.1.1
2.2
LPC ISA Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
2.2.1
2.3
USB Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
LPC Interface Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Real Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
2.3.1
Functional Blocks of RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
2.4
Serial ATA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
2.5
PCI Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
2.6
High Definition Audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
2.6.1
HD Audio Codec Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
2.7
Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
2.8
SMI/SCI Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
2.8.1
Event Sources for SCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
2.8.2
SMI Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
2.8.3
SMI/SCI Work Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
2.9
Power Management/ACPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Chapter 3
Ballout Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Chapter 4
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Contents
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4.1
APU Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
4.2
LPC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
4.3
Unified Media Interface (UMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
4.4
General Purpose PCI Express® Ports Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
4.5
PCI Interface (PCI Host Bus and Internal PCI/PCI Bridge) . . . . . . . . . . . . . . . . . . . .49
4.6
USB Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
4.7
SD Card Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
4.8
Serial ATA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
4.9
HD Audio Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
4.10
Real Time Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
4.11
Hardware Monitor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
4.12
VGA Translator Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
4.13
SPI ROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
4.14
Power Management Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
4.15
SMBus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
4.16
Reset Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
4.17
Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
4.18
ATE/JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
4.19
Integrated Micro-Controller (IMC) Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
4.20
Consumer Infrared Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
4.21
General Purpose I/O and General Event Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
4.22
Power and Ground Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
4.23
Miscellaneous Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
4.24
Integrated Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
4.25
Strap Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
Chapter 5
Power Sequence and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
5.1
Power-up/down Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
5.1.1
5.2
Power Rail Power-up/down Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
5.3
Reset Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
5.3.1
4
Power up Sequence Timing Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
KBRST# Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
Contents
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5.4
Power Button Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
Chapter 6
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
6.1
Power Rail Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
6.1.1
Absolute Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
6.1.2
Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
6.2
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
6.3
RTC Battery Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
6.4
States of Power Rails during ACPI S3 to S5 States . . . . . . . . . . . . . . . . . . . . . . . . .102
6.5
System Clock Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
6.5.1
System Clock Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
6.5.2
System Clock Input Frequency Specifications . . . . . . . . . . . . . . . . . . . . . . .102
6.5.3
AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
Chapter 7
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
7.1
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
7.2
Pressure Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
7.3
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
7.4
Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
Chapter 8
Testability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
8.1
XOR Chain Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
8.2
8.1.1
Test Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
8.1.2
Brief Description of an XOR Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
Description of the Bolton-E4 XOR Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
8.2.1
Unused Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
Appendix A Pin Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
Contents
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List of Figures
Figure 1.
Bolton-E4 Branding and Part Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Figure 2.
Bolton-E4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Figure 3.
USB Controller Block Diagram for Bolton-E4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Figure 4.
A Typical LPC Bus System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Figure 5.
Block Diagram of Internal RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Figure 6.
Block Diagram of the SATA Module of Bolton-E4. . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Figure 7.
HD Audio Codec Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Figure 8.
Bolton-E4 Clock Signals for External Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Figure 9.
Bolton-E4 Clock Signals for Internal Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Figure 10.
SMI/SCI Logic of Bolton-E4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Figure 11.
Bolton-E4 Ballout Assignment (Left). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Figure 12.
Bolton-E4 Ballout Assignment (Right) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Figure 13.
Straps Capture Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
Figure 14.
FCH Power Sequence (S5-to-S0-to-S5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Figure 15.
FCH Power Sequence (S3 to S0 to S3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Figure 16.
Timing for FCH PWR_GOOD De-asserted to RSMRST# De-asserted . . . . . . . . . . . .89
Figure 17.
Measurement for RSMRST# Timing (T2A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Figure 18.
3.3V_S5 Power-down Sequence Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Figure 19.
Power Rail Power-up Sequence Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
Figure 20.
ROM Reset Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
Figure 21.
Reset Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
Figure 22.
Timing Requirements for KBRST# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
Figure 23.
Power Button Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
Figure 24.
SPI Output Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
Figure 25.
SPI Iutput Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
Figure 26.
Bolton-E4 24.5 mm x 24.5 mm 0.8 mm Pitch 656-FCBGA Package Outline . . . . . . .109
Figure 27.
RoHS/Lead-Free Solder (SAC305/405 Tin-Silver-Copper) Reflow Profile . . . . . . . .114
Figure 28.
Test Mode Capturing Sequence Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
Figure 29.
A Generic XOR Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
List of Figures
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Figure 30.
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On-chip XOR Chain Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
List of Figures
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List of Tables
Table 1.
Bolton-E4 Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Table 2.
Pin Type Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Table 3.
Acronyms and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Table 4.
EHCI/xHCI Support for Power Management States . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Table 5.
EHCI/xHCI Power State Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Table 6.
LPC Cycle List and Data Direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Table 7.
SCI Event Sources and Mapping onto ACPI EventStatus . . . . . . . . . . . . . . . . . . . . . . .38
Table 8.
APU Interface Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Table 9.
LPC Interface Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Table 10.
UMI Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Table 11.
General Purpose PCI Express® Ports Interface Pin Descriptions . . . . . . . . . . . . . . . . .48
Table 12.
PCI Interface (PCI Host Bus and Internal PCI/PCI Bridge) Pin Description . . . . . . . . .49
Table 13.
USB Interface Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Table 14.
SD Card Interface Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Table 15.
Serial ATA Interface Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Table 16.
HD Audio Interface Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Table 17.
Real Time Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Table 18.
Hardware Monitor Interface Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Table 19.
VGA Translator Interface Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Table 20.
SPI ROM Interface Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Table 21.
Power Management Interface Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Table 22.
SMBus Interface Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Table 23.
Reset Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Table 24.
Clock Interface Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Table 25.
ATE/JTAG Interface Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Table 26.
Integrated Micro-Controller Interface Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . .65
Table 27.
Consumer Infrared Interface Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Table 28.
General Purpose I/O and General Event Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . .67
Table 29.
Power and Ground Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
List of Tables
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Table 30.
Miscellaneous Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Table 31.
Pins with Integrated Resistors (Excluding GPIO/GEVENT Pins) . . . . . . . . . . . . . . . . .80
Table 32.
Standard Straps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
Table 33.
Debug Straps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Table 34.
Power Sequence Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Table 35.
FCH PWR_GOOD and System Clock Timing (Internal Clock Mode Only). . . . . . . . .87
Table 36.
FCH PWR_GOOD and System Clock Timing (External Clock Mode Only) . . . . . . . .88
Table 37.
FCH Voltage Rail Grouping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Table 38.
Power Rail Power-up Sequence Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
Table 39.
ROM Reset Timing Figure for Various Platform Configurations . . . . . . . . . . . . . . . . .94
Table 40.
Reset Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
Table 41.
DC Characteristics of the GPIO Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
Table 42.
DC Characteristics of the PCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
Table 43.
DC Characteristics of the APU Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
Table 44.
DC Characteristics of RSMRST# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
Table 45.
DC Characteristics of PWR_GOOD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
Table 46.
DC Characteristics of the LPC Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
Table 47.
RTC Battery Current Consumption (Preliminary Estimates) . . . . . . . . . . . . . . . . . . . .101
Table 48.
System Clock Input Source Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
Table 49.
System Clock Input Frequency Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
Table 50.
DISP_CLKP/N AC Specifications: (Non-Spread Clock) . . . . . . . . . . . . . . . . . . . . . .103
Table 51.
APU_CLKP/N AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
Table 52.
14MHz/25MHz/48MHz Auxiliary Clock AC Specifications . . . . . . . . . . . . . . . . . . .104
Table 53.
PCI Clock AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
Table 54.
AC Specification of External Reference Clock for 25M_X1 . . . . . . . . . . . . . . . . . . . .105
Table 55.
SPI Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
Table 56.
SPI Serial Clock Timing (Supported frequencies: 16.5, 22, 33 and 66 MHz) . . . . . . .108
Table 57.
Bolton-E4 24.5 mm x 24.5 mm 0.8 mm Pitch 656-FCBGA Physical Dimensions . . .109
Table 58.
Bolton-E4 Thermal Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
Table 59.
Bolton-E4 TDP Values and Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
Table 60.
Recommended Board Solder Reflow Profile - RoHS/Lead-Free Solder . . . . . . . . . . .113
10
List of Tables
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Table 61.
Signals for the Test Controller of Bolton-E4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
Table 62.
Test Mode Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
Table 63.
TEST0 Bit Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
Table 64.
Truth Table for an XOR Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
Table 65.
Connection Order of Bolton-E4 XOR Chain Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
List of Tables
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AMD A77E Fusion Controller Hub Databook
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List of Tables
Rev. 3.01 February 2014
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Revision History
Date
Revision
Change Description
February 2014
3.01
Modified description in the Power and Ground Pin Descriptions table for
VDDBT_RTC_G.
October 2013
3.00
Initial Release
Revision History
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Revision History
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Chapter 1
Introduction
The A77E FCH, code-named “Bolton-E4” is the third generation fusion controller hub (FCH) from
AMD designed to deliver the quality and performance needed for ultimate high end computing,
multitasking, and multimedia functionality on performance embedded platforms. The A77E FCH is
referred to by it's code name throughout this document.
Supporting AMD accelerated processing units (APUs), Bolton-E4 replaces the traditional two-chip
approach with a new, single-chip architecture, reducing power consumption and improving system
performance while reducing the overall chipset footprint. Bolton-E4 provides sixSATA 6Gb/s ports
and four USB 3.0 ports for expanded I/O connectivity.
Chapter 1
Introduction
15
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1.1
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Features of Bolton-E4
Processors Supported
 Supports wake function in S3 and S4
 Supports AMD Accelerated Processor Units
(APUs)
 Supports USB debug port for EHCI controllers
 Supports port disable with individual control
Unified Media Interface (UMI)
 1-, 2-, or 4-lane UMI connecting the FCH with
the APU
SMBus Controller
 Two SMBus controllers – one is multiplexed on
 Automatic detection of lane configuration on
boot-up
 Dynamic lane width up/down configuration on
detecting bandwidth requirement
three (3) pairs of SMBus signals while the other
controller is dedicated for ASF or a Synaptics
InterTouch Touchpad device
 Supports SMBALERT # signal
 Supports transfer rate of 2.5 GT/s (2GB/s) or
5 GT/s (5GB/s) per lane
 Clock speed can be locked at 2.5 GHz for power
Interrupt Controller
 Supports IOAPIC/X-IO APIC mode for 24
saving
channels of interrupts
 Supports 8259 legacy mode for 15 interrupts
PCI Express® 2.0 Controller
 Four-lane PCI Express (PCIe®) 2.0 interface,
supporting up to four general purpose (GPP)
devices. Supported configurations include:
 Supports programmable level/edge triggering on
each channels
 Supports serial interrupt on quiet and
continuous mode
1x4
2x2
DMA Controller
1x2 + 2x1
 Two cascaded 8237 DMA controllers
4x1
 Supports L0s and L1 link power states for power
 Supports LPC DMA
saving
LPC Host Bus Controller
 Supports LPC-based super I/O and flash
USB 3.0/2.0/1.1 Host Controllers
devices
 2 xHCI (v.1.0), 3 OHCI, and 2 EHCI host
controllers to support:
 Three programmable memory windows
4 USB 3.0 ports
 Supports two master/DMA devices
10 USB 2.0 ports
 Supports TPM version 1.1/1.2 devices for
2 dedicated USB 1.1 ports (for internal devices
only)
enhanced security
 Supports SPI devices at speed up to 66MHz
 Supports xHCI 1.0 features + debug port
 Supports a maximum SPI ROM size of 16MB
 Supports OHCI legacy keyboard/mouse
 Supports single, dual, and quad data SPI
16
Introduction
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Timers
SATA Controller
 Supports six third-generation SATA ports with
 8254-compatible timer
 Microsoft® High Precision Event Timer (HPET)
transfer rates up to 6 Gbit/s
 Supports SATA first-generation
 ACPI power management timer
(up to 1.5 Gbit/s) and second-generation (up to
3.0 Gbit/s)-compliant devices
 Watchdog timer
 AMD boot timer
 Complies with SATA 3.0 specification
 Supports three modes of operation:
IDE emulation mode
Real Time Clock (RTC)
AHCI 1.3 mode
 272-byte battery-backed CMOS RAM
 Any of the ports can be configured to a lower
transfer rate of 3.0 or 1.5 Gbit/s for power saving
 Any of the SATA ports can be configured to
support second generation e-SATA port
(compatible with devices running at 3 Gbit/s and
1.5 Gbit/s)
 AHCI Mode supporting the following features:
DIPM (Device Initiated Power Management)
 Hardware-supported century rollover
 Hardware-supported day-light saving feature
 RTC battery monitoring feature
Power Management
 ACPI specification 3.0 compliant power
management schemes
HIPM (Host Initiated Power Management)
 Supports processor C states
Hot Plug detection and notification
 Supports system S0, S3, S4, and S5 states
NCQ (Native Command Queue) mode
 Supports the S5 Plus power saving mode.
FIS Based Switching Mode
 Wakeup events for S3, S4, and S5 generated
by:
Any GEVENT pins that are on the S5 domain
High Definition Audio
Any GPM pins that are on the S5 domain
 Four independent output streams (DMA)
 Multiple channels of audio output per stream
USB (Note: Remote wake from S5 for USB is
not supported by the operating systems’ USB
driver stacks)
 Supports up to 4 codecs
HD modem
 Up to 192kHz sample rate and 32-bit audio
Power Button
 64-bit addressing capability for DMA bus master
Internal RTC wakeup
 Four independent input streams (DMA)
and MSI
SMI Event
 Unified Audio Architecture (UAA) compatible
 HD Audio registers can be located anywhere in
the 64-bit address space
 Supports 3.3V/1.5V dual-voltage interface for
power saving
Chapter 1
Consumer IR
 SMM support: generating SMI by power
management events, bus transaction (IO,
memory, or PCI configuration cycle) trapping,
internal controllers, GPIO, timer, management
message
Introduction
17
AMD A77E Fusion Controller Hub Databook
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 CLKRUN# support for PCI power management
 Low idle power
Rev. 3.01 February 2014
Integrated Clock Generator
 Provides 25 MHz, 14.3 MHz (frequency is
 Supports STPCLK# control
14.318 MHz on average; cycle-to-cycle variation
can be between 14.2857 and 14.8148 MHz),
and 48 MHz clocks
 ALPM (HIPM) on SATA
 DIPM on SATA
 Provides clocks for APU, external graphics,
UMI, and nine general purpose PCIe devices
Integrated Micro-Controller (IMC)
 8051 microcontroller:
VGA Translator
4 Kbytes of data memory
 Provides VGA translation function. Supports a
64 Kbytes base instruction plus expanded
instruction (beyond 64 KB) support
maximum resolution of 1920x1600 at a refresh
rate of 60 Hz.
Thirteen interrupts, 50 interrupt sources, 4
interrupt priority levels
 Auto monitor detection
 Automatic power down for VGA DAC when
 33 MHz operation in S0 state, 16 MHz operation
in system sleep state; option to stop clock when
idle
 JTAG-based In-Circuit Emulator (ICE) or
there is no monitor attached
 Driver can put the VGA DAC into low power
mode when a VGA monitor is attached but
inactive.
debugger
 Host I/O interface
SD Flash Controller
 Four general purpose timers/counters
 Clock speed up to 50 MHz (high-speed mode)
 Hibernation, Watchdog, and RTC timers
 Access to all FCH MMIO resources (e.g. PMIO,
RTC, BIOS_RAM registers)
 Supports both standard (SD) and high-capacity
(SDHC) formats
 Supports 1 and 4-bit modes
 For the SDHC format:
Consumer IR
 Media center infrared with wake from all states
 Two transmitters
 IR receiver and wideband learning receiver
Supports speed classes of up to Class 10
 Fully compatible with Microsoft Windows®
 For the SD format:
Vista® and Windows 7 Media Center
Supports capacities of up to 2 GB
Hardware Monitoring
Miscellaneous
 Fan control: IMC-based APU fan control via SB-
TSI
Supports capacity range of 4 to 32 GB, 4 pins @
50 MHz. Note: With Windows 7 (32 or 64 bit)
and MS Hotfix KB976422, up to 2 TB is
supported.
 Access to ACPI features through:
SMBus
ASFBus
GPIO
18
Introduction
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1.2
Branding and Part Numbers
ASIC NAME
DATE CODE
MADE IN COO
XXXXXX.XX
ZZZ-ZZZZZZZ
Figure 1. Bolton-E4 Branding and Part Number
Notes on branding diagram:
•
Branding can be in laser, ink, or mixed laser-and-ink-marking.
•
AMD logo image may be in hollow/outline form.
•
For the ASIC Name, FCH is used for production parts, while the engineering codename is
used for engineering samples.
•
For the Date Code, ENG designates engineering sample (it does not appear for production
parts).
Figure legends:
ASIC NAME = See table below.
DATE CODE = YYWW (YY = assembly start year, WW = assembly start week)
COO = Country of origin (assembly site)
XXXXXX.XX = Wafer foundry lot number.wafer ID (wafer ID may not appear sometimes)
ZZZ-ZZZZZZZ = AMD part number (see table below)
Chapter 1
Introduction
19
AMD A77E Fusion Controller Hub Databook
Table 1.
Rev. 3.01 February 2014
Bolton-E4 Part Numbers
ASIC Name
FCH
20
53830
ASIC Revision
Date Code
Bolton-E4 Parts
A1
YYWW
Introduction
AMD Part Number
218-0844020-00
Chapter 1
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1.3
Bolton-E4 Block Diagrams
codecs
8
Figure 2. Bolton-E4 Block Diagram
Chapter 1
Introduction
21
AMD A77E Fusion Controller Hub Databook
1.4
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Rev. 3.01 February 2014
Conventions and Notations
The following conventions are used throughout this manual.
1.4.1
Pin Names
Pins are identified by their pin names or ball references. All active-low signals are identified by the
suffix ‘#’ in their names (e.g., GNT0#).
1.4.2
Pin Types
The pins are assigned different codes according to their operational characteristics. These codes are
listed below.
Table 2.
Pin Type Codes
Code
Pin Type
I
Digital Input
O
Digital Output
OD
Open Drain
I/O
Bi-Directional Digital Input or Output
I/OD
M
Digital Input or Open Drain
Multifunctional
PWR
Power
GND
Ground
A-O
Analog Output
A-I
Analog Input
A-I/O
Analog Bi-Directional Input/Output
A-PWR
Analog Power
A-GND
Analog Ground
Other
1.4.3
Pin types not included in any of the categories above
Numeric Representation
Hexadecimal numbers are appended with “h” whenever there is a risk of ambiguity. Other numbers
are in decimal.
Pins of identical functions but different running integers (e.g., “LAD3,” “LAD2,” “LAD3”) are
referred to collectively by specifying their integers in square brackets and with colons (i.e.,
“LAD[3:0]”). A similar short-hand notation is used to indicate bit occupation in a register. For
example, Command[15:10] refers to the bit positions 10 through 15 of the Command register.
22
Introduction
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1.4.4
Register Field
A field of a register is referred to by the format of [Register Name].[Register Field]. For example,
“Commad.Memory Space” is the “Memory Space” field of the register “Command.”
1.4.5
Acronyms and Abbreviations
The following is a list of the acronyms and abbreviations used in this manual.
Table 3.
Acronyms and Abbreviations
Acronym
Full Expression
ACPI
Advanced Configuration and Power Interface
AHCI
Advanced Host Controller Interface
AOAC
Always On Always Connected
APU
Accelerated Processor Unit
BGA
Ball Grid Array
BIOS
Basic Input Output System. Initialization code stored in a ROM or Flash RAM
used to start up a system or expansion card.
DAC
Digital to Analog Converter
DIPM
Device Initiated Interface Power Management
DMA
Direct Memory Access
EHCI
Enhanced Host Controller Interface
EPROM
Erasable Programmable Read Only Memory
FCH
Fusion Controller Hub
GND
Ground
GPIO
General Purpose Input/Output
GPM
General Power Management
HD
High Definition Audio
HIPM
Host Initiated Interface Power Management
HPET
High Precision Event Timer
I2C
Inter-Integrated Circuit
IDE
Integrated Drive Electronics
IMC
Integrated Micro-Controller
IR
ISA
JTAG
LPC
Chapter 1
Infrared
Industry Standard Architecture
Joint Test Access Group. An IEEE standard.
Low Pin Count
Introduction
23
AMD A77E Fusion Controller Hub Databook
Table 3.
NC
No Connect
Native Command Queuing
OHCI
Open Host Controller Interface
PCI
Peripheral Component Interface
PCI Express®
PLL
Phase Locked Loop
POST
Power On Self Test
PD
Pull-down Resistor
PU
Pull-up Resistor
RAID
Redundant Array of Inexpensive Disks
RTC
Real Time Clock
SATA
SCI
Rev. 3.01 February 2014
Acronyms and Abbreviations (Continued)
NCQ
PCIe®
24
53830
Serial ATA
System Controller Interrupt
SGPIO
Serial General Purpose Input/Output
SMBus
System Management Bus
SMI
System Management Interrupt
SPI
Serial Peripheral Interface
TBA
To Be Added (the information is not yet available)
TPM
Trusted Platform Module
UMI
Unified Media Interface
USB
Universal Serial Bus
xHCI
Extensible Host Controller Interface
Introduction
Chapter 1
53830
Rev. 3.01 February 2014
Chapter 2
2.1
AMD A77E Fusion Controller Hub Databook
Functional Description
USB Controllers
Figure 3 is an internal block diagram for Bolton-E4’s USB controllers showing the use of
two xHCI, three OHCI and two EHCI controllers to control four USB 3.0, ten USB 2.0, and two
dedicated USB 1.1 ports.
Chapter 2
Functional Description
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UMI
APU
Unified Media Interface
A-Link
A- Link( PCI BUS0)
OHCI ARBITOR
XHCI B-Link
EHCI B-Link
EHCI B-Link
PCI M/S
XHCI B-Link
OHCI BLink
B-Link
ACPI
controller
PM_event
Device ID
7809h
Vendor ID
1022h
slv
OHCI0
Device 18
Function0
Device ID
7807h
Vendor ID
1022h
slv
slv
slv
Device ID
7808h
Vendor ID
1022h
ROOT HUB
slv
xHCI
Device16
Function0
slv
xHCI
Device16
Function1
Device ID
7814h
7812h
Vendor ID
1022h
Device ID
7814h
7812h
Vendor ID
1022h
INTB
Device ID
7807h
Vendor ID
1022h
ROOT HUB
EHCI
Device19
Function2
INTA
Device ID
7808h
Vendor ID
1022h
INTB
OHCI0
Device19
Function0
INTA
INTC
EHCI
Device 18
Function2
INTB
OHCI
Device 20
Function5
INTA
slv
ROOT HUB ROOT HUB
PHY
FS/ LS
port0
FS/ LS
port1
Port0 Port1 Port2 Port3 Port4
Port5 Port6 Port7 Port8 Port9
Port10 Port11
Controller
OHCI0 ( dev-18 , fun-0)
EHCI ( dev-18 , fun-2)
OHCI0 ( dev-19 , fun-0)
EHCI ( dev-19 , fun-2)
XHCI ( dev-16 , fun-0)
XHCI ( dev-16 , fun-1)
Port12 Port13
Ports mapping
Port 0 - 4
Port 0 - 4
Port 5 - 9
Port 5 - 9
Port 10 - 11
Port 12- 13
Figure 3. USB Controller Block Diagram for Bolton-E4
26
Functional Description
Chapter 2
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AMD A77E Fusion Controller Hub Databook
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2.1.1
USB Power Management
An advanced power management capability interface compliant with PCI Bus Power Management
Interface Specification Revision 1.1 is incorporated into the EHCI and xHCI controllers. This
interface allows the EHCI/xHCI to be placed in various power management states, offering a variety
of power savings for a host system.
Table 4 highlights the EHCI/xHCI support for power management states and features supported for
each of the power management states. An EHCI/xHCI implementation may internally gate-off USB
clocks and suspend the USB transceivers (low power consumption mode) to provide these power
savings.
Table 4.
EHCI/xHCI Support for Power Management States
PCI Power
Management State
State Required / Optional
in Specification
Comments
D0
Required
Supported.
Fully awake backward compatible state. All logic in
full power mode.
D1
Optional
Not supported.
USB Sleep state with EHCI/xHCI bus master
capabilities disabled. All USB ports in suspended
state. All logic in low latency power savings mode
because of low latency returning to D0 state.
D2
Optional
Not supported.
USB Sleep state with EHCI/xHCI bus master
capabilities disabled. All USB ports in suspended
state.
D3hot
Required
Supported.
Deep USB Sleep state with EHCI/xHCI bus master
capabilities disabled. All USB ports in suspended
state.
D3cold
Required
Supported.
Fully asleep backward compatible state. All
downstream devices are either suspended or
disconnected based on the implementation’s capability
to supply downstream port power within the power
budget.
Chapter 2
Functional Description
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The functional and wake-up characteristics for the EHCI/xHCI power states are summarized below.
Table 5.
EHCI/xHCI Power State Summary
Power State
Functional Characteristics
Wake-up Characteristics*
D0
• Fully functional EHCI/xHCI device state • Resume detected on suspended port
• Unmasked interrupts are fully functional • Connect or Disconnect detected on port
• Over Current detected on port
D1
•
•
•
•
EHCI/xHCI preserves PCI configuration
EHCI/xHCI preserves USB configuration
Hardware masks functional interrupts
All ports are disabled or suspended
• Resume detected on suspended port
• Connect or Disconnect detected on port
• Over Current detected on port
D2
•
•
•
•
EHCI/xHCI preserves PCI configuration
EHCI/xHCI preserves USB configuration
Hardware masks functional interrupts
All ports are disabled or suspended
• Resume detected on suspended port
• Connect or Disconnect detected on port
• Over Current detected on port
D3hot
•
•
•
•
EHCI/xHCI preserves PCI configuration
EHCI/xHCI preserves USB configuration
Hardware masks functional interrupts
All ports are disabled or suspended
• Resume detected on suspended port
• Connect or Disconnect detected on port
• Over Current detected on port
D3cold
• PME Context in PCI Configuration space
is preserved
• Wake Context in EHCI/xHCI
MemorySpace is preserved
• All ports are disabled or suspended
• Resume detected on suspended port
• Connect or Disconnect detected on port
• Over Current detected on port
Note: *Associated enables must be set.
28
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2.2
LPC ISA Bridge
2.2.1
LPC Interface Overview
The Low Pin Count (LPC) bus interface is a cost-efficient, low-speed interface designed to support
low bandwidth and legacy devices. The LPC interface essentially eliminates the need of ISA and Xbus in the system. A typical setup of the system with LPC interface is shown in Figure 4. The LPC
host controller contains both LPC and Serial Peripheral Interface (SPI) bridge functions. It connects
to the internal A-Link bus on one side and the LPC and SPI buses on the other side.
A-Link Bus
LPC Bridge
SPI Bridge
LPC Device
Figure 4.
SPI Device
A Typical LPC Bus System
Examples of LPC devices include Super I/O, BIOS RAM, audio, Trusted Platform Module (TPM),
and system management controller. A BIOS ROM can also be populated on the SPI interface. The
FCH can support an LPC or SPI type BIOS ROM. The ROM selection is determined by a strap pin
(refer to Table 32 on page 81) during RSMRST# assertion. In addition to the straps, software can
change the ROM selection through programming in the PMIO registers.
The host controller supports memory and I/O read/write, Direct Memory Access (DMA) read/write,
bus master memory I/O read/write, and TPM read/write. It supports up to two bus masters and seven
DMA channels. A bus master or DMA agent uses the LDRQ pin to assert bus master or DMA
requests. The host controller uses LFRAME# to indicate the start or termination of a cycle. Table 6 on
page 30 shows a list of cycles supported by the host controller, their initiators, data flow directions,
and their PCI counterparts.
Chapter 2
Functional Description
29
AMD A77E Fusion Controller Hub Databook
Table 6.
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LPC Cycle List and Data Direction
Cycle
Size (bytes)
Initiator
Data
Direction
PCI Counterpart
Memory read
1
Host
P-2-Host
MemRead to LPC range
Memory write
1
Host
Host-2-P
MemWrit to LPC range
I/O read
1
Host
P-2-Host
IORead to LPC range
I/O write
1
Host
Host-2-P
IOWrit to LPC range
DMA read
1, 2, 4
Peripheral
Host-2-P
DMA control setup; DMA data fetch
DMA write
1, 2, 4
Peripheral
P-2-Host
DMA control setup; DMA data store
BM Memory read
1, 2, 4
Peripheral
Host-2-P
DMA control setup; DMA data fetch
BM Memory write
1, 2, 4
Peripheral
P-2-Host
DMA control setup; DMA data store
BM I/O read
1, 2, 4
Peripheral
Host-2-P
DMA control setup; I/O data fetch
BM I/O write
1, 2, 4
Peripheral
P-2-Host
DMA control setup; I/O data store
TPM read
1,2,4
Host
P-2-Host
TPM read
TPM write
1,2,4
Host
Host-2-P
TPM write
The host controller has a SERIRQ (Serial IRQ) pin, which is used by peripherals that require interrupt
support. All legacy interrupts are serialized on this pin, decoded by the host controller, and sent to the
interrupt controller for processing. Refer to the Serial IRQ Specification, Version 5.4, for a detailed
description of the Serial IRQ protocol.
30
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2.3
Real Time Clock
The Real Time Clock (RTC) updates the computer’s time and generates interrupts for periodic events
and pre-set alarm. The RTC also makes hardware leap year corrections. The FCH’s RTC includes a
272-byte (256 standard bytes plus 16 additional bytes) CMOS RAM, which is used to store the
configuration of a computer such as the number and type of disk drive, graphics adapter, base
memory, checksum value, etc.
2.3.1
Functional Blocks of RTC
The internal RTC is made of two parts—one part is an analog circuit, powered by a battery (VBAT),
and the other is a digital circuit, powered by the main power (VDD). Figure 5 shows the block
diagram of the internal RTC. The FCH has a hardware-based daylight saving feature, which makes
clock adjustments (spring forward or fall back) at the designated dates/times. Both the date and hour
for the daylight and standard time are fully programmable, allowing for different daylight saving
dates and hours for different parts of the world.
Analog Portion
Powered by
Battery (VBAT)
29 -bit
Ripple
Counter
272 Bytes RAM
Alarm
1Hz
15 -bit
Ripple
Counter
32.768 KHz
Digital Portion
RAM
Controller
Registers
Frequency
Divider
Powered by Main
Power (VDD)
Time
Update
Decode and Interface
To Internal A-Link Bus
Figure 5. Block Diagram of Internal RTC
Chapter 2
Functional Description
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Serial ATA Controller
The integrated Serial ATA controller processes host commands and transfers data between the host
and Serial ATA devices. It supports six independent Serial ATA channels. Each channel has its own
Serial ATA bus and supports one Serial ATA device. The SATA controller supports Serial ATA first,
second, and third generation transfer rates (up to 1.5 Gbit/s, 3.0 Gbit/s, and 6.0 Gbit/s respectively).
Figure 6 on page 33, and Figure 7 on page 35, are diagrams for the SATA block. The SATA
controller can operate in three modes:
•
All six channels configured to SATA AHCI mode.
•
All six channels configured to IDE mode. In this configuration, the SATA controller is configured
into two IDE controllers, with the programming interface of channel 0 to 3 under the first IDE
controller, and that of channel 4 to 5/7 under the second IDE controller.
•
Four channels (channel 0 to 3) configured as SATA AHCI and four channels (channel 4 to 5/7)
configured as IDE mode. In this configuration, the programming interface of channel 4 to 5/7 is
under the IDE controller.
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AHCI Global Control Register & Port Mapping
Port0
Serdes
Interface
Host
Transport
Link
Blink clock
1K-Byte Transmission
FIFO
Asicclk 0
Port0 link clock
PHY
PCI/B-Link Interface
data to be
written
1K-Byte Reception FIFO
Clock
data to
be read
Port1
Asicclk1
Port2
Asicclk2
Port3
Asicclk3
Port4
Asicclk4
Port5
Asicclk5
Figure 6. Block Diagram of the SATA Module of Bolton-E4
Chapter 2
Functional Description
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2.5
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PCI Bridge
The PCI Bridge supports up to three PCI slots. The PCI bridge runs at 33 MHz and can support the
CLKRUN# function with individual clock override (option for not stopping specific PCICLK). In
addition, it has the capability to hide individual PCI devices.
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Functional Description
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2.6
High Definition Audio
The High Definition (HD) audio controller communicates with external HD audio codec(s) over the
HD audio link. The HD audio controller consists of four independent output DMA engines and four
independent input DMA engines that are used to move data between system memory and the external
codec(s). The controller can support up to four audio or modem codecs in any combinations.
2.6.1
HD Audio Codec Connections
Figure 7 shows the HD Audio interface connections to the HD Audio codecs. The FCH can support
up to four HD Audio codecs. Each codec has its own AZ_SDIN (data input) for the HD Audio
interface. Figure 7 shows the connection for a two-codec configuration.
HD CODEC
1
HD CODEC
2
FCH
HD Audio Engine
HD Audio SDIN3
HD Audio SDOUT
HDAudio SYNC/BitCLK/RST#
SDIN0
Figure 7. HD Audio Codec Connections
Chapter 2
Functional Description
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AMD A77E Fusion Controller Hub Databook
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Clock Generation
Bolton-E4 has two clock configurations: (1) external clock mode, and (2) integrated clock mode.
These are shown in Figure 8 and Figure 9 on page 37, respectively.
APU _CLK
Diff, spread
100MHz
DISP_CLK
Diff, Non-spread
100 MHz
SLT _GFX_CLK(diff)
100 MHz
DISP2_CLK(diff)
100MHz
GPP_CLK0(diff)
FCH
GPP_CLK1(diff)
OSCCLK
(50/48/25/24/14MHz)
USB_CLK(diff)
48MHz
25MHz XTAL
PCIE_RCLK(diff)
100MHz
GPP_CLK8 (diff)
PCICLK (x5)
X denotes No Connect,
clocks are provided by the
external clock generator
External
Clock Gen
Figure 8. Bolton-E4 Clock Signals for External Clock Mode
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APU _CLK
Diff, spread
100MHz
DISP_CLK
Diff, Non-spread
100MHz
AMD APU
SIO
DISP2_CLK(diff)
100MHz
LVDS
Translator
SLT_GFX_CLK(diff)
100MHz
Gfx
GPP 0
GPP 1
System
Clock Gen
FCH
SB900
GPP_CLK0(diff)
GPP_CLK1(diff)
48Mhz
OSCCLK
(50/48/25/24/14MHz)
PCIE_RCLK(diff)
100MHz
25MHz XTAL
GPP_CLK8 (diff)
PCICLK (x5)
GPP 8
GPP 9
Figure 9. Bolton-E4 Clock Signals for Internal Clock Mode
The clock mode is selected by a strap pin. If the FCH is in external clock mode, the clock sources
required include a 14.318 MHz source for the timers, a 25MHz clock source for the VGA translator, a
32-KHz crystal for the RTC, a 100 MHz differential clock pair for the PCIe reference clocks, a 48MHz clock source for USB, and a 25 MHz single ended or 100 MHz differential pair clock for SATA.
In addition to the PCIe® clocks, the FCH also uses the 100 MHz clock to generate various internal
clocks, including the PCI 33-MHz clocks.
If integrated clock mode is selected, only a 25 MHz crystal for master reference and a 32 KHz crystal
for the RTC are required. The FCH will then generate all of the system clocks needed, including the
APU clocks, the external graphics clock, the 25 MHz clock for SATA, and the 48 MHz clocks for
USB, and so on.
Chapter 2
Functional Description
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2.8
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SMI/SCI Generation
There are a total of 160 sources of events. The first 64 can be mapped to the 32 standard ACPI
EVENT bits, which can be used to generate SCI or PME. All of the 160 events can be configured to
generate SMI/NMI.
When an event is routed to SMI, an SMI assertion message will be sent by the FCH to the APU. The
SMI status remains active until the EOS bit is set and the status bit is cleared. When the EOS is set, an
SMI de-assertion message will be sent to the APU. If the event is routed to SCI, BIOS can then route
it to any of the legacy interrupts (except IRQ8) or INT21 in the case of IOAPIC.
2.8.1
Event Sources for SCI
Table 7 below shows the 160 sources of SCI events, the first 64 of which can be mapped to the 32
event resources of the ACPI EventStatus. The SCI event mapping are controlled through the SciMap*
registers in SMI_Reg space. And the SCI Event enable/status is accessed through the EventEnable/
EventStatus registers in SMI_reg space. Refer to the AMD Bolton Fusion Controller Hub Register
Reference Guide for more details.
Table 7.
SCI Event Sources and Mapping onto ACPI EventStatus
Event Number
0 ~ 23
38
Event Source
Gevent0 ~ 23 (GEVENT pins)
24
PME from USB device 18
25
PME from USB device 19
26
PME from USB device 20
27
PME from USB device 22
28
PME from GPP device 21, function 0
29
PME from GPP device 21, function 1
30
PME from GPP device 21, function 2
31
PME from GPP device 21, function 3
32
Hot plug event from GPP device 21, function 0
33
Hot plug event from GPP device 21, function 1
34
Hot plug event from GPP device 21, function 2
35
Hot plug event from GPP device 21, function 3
36
PME from HD Audio device
37
SATA Gevent 0
38
SATA Gevent 1
39
PME from Gec
40
IMC Gevent
Functional Description
Chapter 2
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AMD A77E Fusion Controller Hub Databook
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Table 7.
SCI Event Sources and Mapping onto ACPI EventStatus (Continued)
41
Reserved
42
PME from CIR
43
WAKE# pin
44
FanThermal Gevent
45
ASF Master Interrupt event
46
ASF Slave interrupt event
47
SMBUS0 interrupt
48
TWARN event
49
Traffic Monitor Gevent
50
iLLB_event50
51
PwrButton_event
52
ProcHot_event
53
NBHwAssertionMsg
54
NBSciAssertionMsg
55
RAS_event
56
XHC0PME
57
XHC1PME
57: 63
Reserved
64
Reserved
65
Slp_En_Write
66
GecRomSmi
67
SATA_AHCI_Smi
68
NbGppPme
69
NbGppHotPlug
70
RtcIrqEvent
71
ACPI_Timer_Event
72
GBL_RLS
73
BIOS_RLS
74
PWRBTN
75
SmiCmdPort
76
UsiSmi (OHCI legacy support)
77
SerIrqSmi
78
SMBus0Intr
Chapter 2
Functional Description
39
AMD A77E Fusion Controller Hub Databook
Table 7.
40
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Rev. 3.01 February 2014
SCI Event Sources and Mapping onto ACPI EventStatus (Continued)
79
EcSmi
80
xHCErr
81
IntruderAlert
82
VBATLow
83
ProcHot
84
PCI_Serr
85
SB_Gpp0Serr
86
SB_Gpp1Serr
87
SB_Gpp2Serr
88
SB_Gpp3Serr
89
ThermalTrip
90
Emulate64_event90
91
Usb_FLR_event91
92
Sata_FLR_event92
93
Az_FLR_event93
94
Gec_FLR_event94
95
CmosEraseSts_event95
96
IRQ0Trapping_event96
97
IRQ1Trapping_event97
98
IRQ2Trapping_event98
99
IRQ3Trapping_event99
100
IRQ4Trapping_event100
101
IRQ5Trapping_event101
102
IRQ6Trapping_event102
103
IRQ7Trapping_event103
104
IRQ8Trapping_event104
105
IRQ9Trapping_event105
106
IRQ10Trapping_event106
107
IRQ11Trapping_event107
108
IRQ12Trapping_event108
109
IRQ13Trapping_event109
110
IRQ14Trapping_event110
111
IRQ15Trapping_event111
Functional Description
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AMD A77E Fusion Controller Hub Databook
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Table 7.
SCI Event Sources and Mapping onto ACPI EventStatus (Continued)
112
IRQ16Trapping_event112
113
IRQ17Trapping_event113
114
IRQ18Trapping_event114
115
IRQ19Trapping_event115
116
IRQ20Trapping_event116
117
IRQ21Trapping_event117
118
IRQ22Trapping_event118
119
IRQ23Trapping_event119
120
VIn0Sts_event120
121
VIn1Sts_event121
122
VIn2Sts_event122
123
VIn3Sts_event123
124
VIn4Sts_event124
125
VIn5Sts_event125
126
VIn6Sts_event126
127
VIn7Sts_event127
128
Temp0Sts_event128
129
Temp1Sts_event129
130
Temp2Sts_event130
131
Temp3Sts_event131
132
Temp4Sts_event132
133
FanIn0Sts_event133
134
FanIn1Sts_event134
135
FanIn2Sts_event135
136
FanIn3Sts_event136
137
FanIn4Sts_event137
138
Fake0Sts_event138
139
Fake1Sts_event139
140
Fake2Sts_event140
141
CStateMsg_event141
142
ShortTimer_event142
143
LongTimer_event143
144
AbSmiTrap_event144
Chapter 2
Functional Description
41
AMD A77E Fusion Controller Hub Databook
Table 7.
2.8.2
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SCI Event Sources and Mapping onto ACPI EventStatus (Continued)
145
SoftReset_event145
146
PStateChange_event146
147
PStateChange_event147
148
IoTrapping0_event148
149
IoTrapping1_event149
150
IoTrapping2_event150
151
IoTrapping3_event151
152
MemTrapping0_event152
153
MemTrapping1_event153
154
MemTrapping2_event154
155
MemTrapping3_event155
156
CfgTrapping0_event156
157
CfgTrapping1_event157
158
CfgTrapping2_event158
159
CfgTrapping3_event159
SMI Events
Bolton-E4 supports up to 160 sources to generate SMI. The SMI control/status is accessed through
the registers defined in the SMI_Reg space. Refer to the AMD Bolton Fusion Controller Hub Register
Reference Guide, order# 51192 for more details.
2.8.3
SMI/SCI Work Flow
Figure 10 on page 43, shows how the SMI/SCI logic works (SmiSciEn bit set to 1).
42
Functional Description
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One of the 50
Event Sources
Event Triggered?
(SciTrig/edge
triggered)
No
Yes
SmiSciStatus is set
SMI is generated to host
(APU)
BIOS SMI service routine
acknowledges it by writing
1 to SmiSciStatus to clear
it
ACPI Event trigger logic
sees falling edge of
SmiSciStatus
ACPI EventStatus is set
and SCI is generated if
EventEnable is set
Figure 10. SMI/SCI Logic of Bolton-E4
Chapter 2
Functional Description
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AMD A77E Fusion Controller Hub Databook
2.9
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Power Management/ACPI
The Bolton-E4 power management/ACPI logic supports both hardware and message-based C1e,
stutter mode, and S states.
44
Functional Description
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Chapter 3
1
A
0
B
0
C
USB_HSD1P
2
Ballout Assignment
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VSS
0
USB_HSD2N
USB_HSD3N
0
USB_HSD5P
0
USB_HSD7N
0
USB_SS_RX3
N
0
USB_SS_TX3
P
0
USBSS_CALR
N
0
0
0
0
0
0
VSS
0
USB_RCOMP
0
USB_HSD9P
0
VSS
0
USB_SS_TX2
N
0
KSO_15/XDB1/
GPIO224
0
USB_HSD1N
0
USB_HSD2P
USB_HSD3P
0
USB_HSD5N
0
USB_HSD7P
0
USB_SS_RX3
P
0
USB_SS_TX3
N
0
USBSS_CALR
P
0
0
0
VDDPL_33_US
B_S
0
VSS
0
USB_SS_TX2
P
0
KSO_17/XDB3/
GPIO226
D
0
0
E
USB_HSD0P
F
RTCCLK
G
0
H
USB_FSD1P/
GPIO186
0
USB_FSD1N
J
0
IR_LED#/
LLB#/GPIO184
0
K
WAKE#/
GEVENT8#
0
TEMPIN2/
GPIO173
L
0
VIN2/SDATI_1/
GPIO177
M
VIN6/
GBE_STAT3/
GPIO181
N
0
P
VSS
0
USB_HSD9N
0
17
0
0
0
USB_HSD0N
0
VSS
VDDBT_RTC_
G
0
USB_HSD4N
0
USB_HSD8P
0
VSS
0
USB_SS_RX2
P
0
VSS
0
0
INTRUDER_A
LERT#
0
USB_OC3#/
AC_PRES/
TDO/
0
VSS
USB_HSD4P
VSS
USB_HSD8N
VSS
USB_HSD11N
VSS
USB_SS_RX2
N
USB_SS_TX1
P
VSS
VSS
32K_X1
0
32K_X2
0
VSS
VDDAN_33_U
SB_S_1
USBCLK/
14M_25M_48M
_OSC
USB_HSD6N
USB_HSD13N
0
USB_HSD11P
USB_SS_RX1
N
0
USB_SS_TX1
N
VSS
0
0
USB_FSD0N
USB_FSD0P/
GPIO185
S5_CORE_EN
VDDAN_33_U
SB_S_2
USB_HSD6P
USB_HSD13P
0
VSS
USB_SS_RX1
P
0
VSS
USB_SS_TX0
N
0
PWR_BTN#
0
VSS
USB_OC1#/
TDI/
GEVENT13#
VDDAN_33_U
SB_S_3
VSS
VSS
0
USB_HSD12N
VSS
0
USB_SS_RX0
P
USB_SS_TX0
P
0
0
TEMPIN1/
GPIO172
TEMPIN0/
GPIO171
VSS
VDDAN_33_U
SB_S_4
VDDAN_33_U
SB_S_5
USB_HSD12P
0
USB_HSD10P
USB_HSD10N
0
USB_SS_RX0
N
VSS
0
0
NC5
0
VSS
0
0
0
0
0
VSS
VSS
0
VSS
VSS
0
0
VIN1/GPIO176
0
VIN7/
GBE_LED3/
GPIO182
TEMPIN3/
TALERT#/
GPIO174
BLINK/
USB_OC7#/
GEVENT18#
VDDAN_33_H
WM_S
VDDAN_33_U
SB_S_6
VDDAN_33_U
SB_S_7
VDDAN_33_U
SB_S_12
VDDAN_33_U
SB_S_10
VSS
VDDAN_11_S
SUSB_S_2
0
VSS
VDDCR_11_S
SUSB_S_4
VIN0/GPIO175
0
VIN3/
SDATO_1/
GPIO178
0
VSS
PWR_GOOD
VSSAN_HWM
VDDAN_33_U
SB_S_8
VDDAN_33_U
SB_S_9
VSS
VDDAN_33_U
SB_S_11
VSS
VDDAN_11_S
SUSB_S_3
0
VDDCR_11_S
SUSB_S_1
VDDCR_11_S
SUSB_S_2
VIN4/
SLOAD_1/
GPIO179
0
VIN5/SCLK_1/
GPIO180
0
USB_OC2#/
TCK/
GEVENT14#
USB_OC4#/
IR_RX0/
GEVENT16#
0
0
0
0
0
VSS
VDDAN_11_S
SUSB_S_4
VDDAN_11_S
SUSB_S_5
0
VDDAN_11_S
SUSB_S_1
VDDCR_11_S
SUSB_S_3
R
0
RI#/
GEVENT22#
0
VSS
0
VSS
SDA1/
GPIO228
USB_OC6#/
IR_TX1/
GEVENT6#
PME#/
GEVENT3#
THRMTRIP#/
SMBALERT#/
GEVENT2#
VSS
0
0
0
0
0
0
T
USB_OC5#/
IR_TX0/
GEVENT17#
0
SLP_S3#
0
LPC_PD#/
GEVENT5#
SPI_CS1#/
GPIO165
SCL1/
GPIO227
TEST0
TEST1/TMS
VSS
VDDCR_11_U
SB_S_1
VDDCR_11_U
SB_S_2
VDDCR_11_1
0
VSS
VDDCR_11_2
U
0
RSMRST#
0
SYS_RESET#/
GEVENT19#
0
VSS
0
0
0
0
0
VDDAN_11_U
SB_S_1
VDDAN_11_U
SB_S_2
VSS
0
VDDCR_11_4
VSS
V
ROM_RST#/
SPI_WP#/
GPIO161
0
SPI_CLK/
GPIO162
0
SPI_DO/
GPIO163
SPI_DI/
GPIO164
IR_RX1/
GEVENT20#
DDR3_RST#/
GEVENT7#/
VGA_PD
TEST2
GBE_LED2/
GEVENT10#
VSS
VDDIO_33_S_
4
VDDIO_33_S_
5
VDDCR_11_6
0
VSS
VDDCR_11_7
W
0
SLP_S5#
0
VSS
0
VSS
SPI_CS3#/
GBE_STAT1/
GEVENT21#
GBE_LED0/
GPIO183
GBE_PHY_INT
R
GBE_MDIO
VDDIO_33_S_
8
0
0
0
0
0
0
Y
AZ_SDIN3/
GPIO170
0
AZ_SDIN2/
GPIO169
0
AZ_SDIN1/
GPIO168
SPI_HOLD#/
GBE_LED1/
GEVENT9#
0
0
0
0
0
VDDIO_33_S_
6
VDDIO_33_S_
7
VSS
0
VSS
VDDCR_11_9
AA
0
AZ_SDIN0/
GPIO167
0
VDDIO_AZ_S
0
VSS
GBE_PHY_RS
T#
GBE_STAT0/
GEVENT11#
VDDIO_GBE_
S_1
VDDIO_GBE_
S_2
VDDCR_11_G
BE_S_2
VSS
VSS
VSS
0
VSS
VSS
AB
AZ_SDOUT
0
AZ_BITCLK
0
PCIRST#
PCIE_RST2#/
GEVENT4#
GBE_TXCLK
GBE_RXCLK
GBE_TXCTL/
TXEN
VDDIO_33_GB
E_S
VDDCR_11_G
BE_S_1
VDDIO_33_PC
IGP_7
VDDIO_33_PC
IGP_8
VDDIO_33_PC
IGP_9
0
VDDIO_33_PC
IGP_10
VDDIO_33_PC
IGP_1
AC
0
GBE_PHY_PD
0
GBE_COL
0
VSS
0
0
0
0
0
AD24/GPIO24
VDDIO_33_PC
IGP_6
0
AD30/GPIO30
INTG#/GPIO34
0
USB_OC0#/
GEVENT12#/
TRST/
AD
GBE_RXERR
0
GBE_CRS
0
A_RST#
AZ_SYNC
GBE_RXD0
GBE_TXD0
GBE_MDCK
VDDIO_33_PC
IGP_4
0
CBE3#
GNT1#/GPO44
0
AD29/GPIO29
GNT0#
0
AE
0
PCIE_RST#
0
AZ_RST#
0
VSS
GBE_RXD1
GBE_TXD1
VDDIO_33_PC
IGP_3
PAR
0
AD23/GPIO23
AD25/GPIO25
0
VSS
AD31/GPIO31
0
AF
PCICLK1/
GPO36
0
PCICLK0
0
PCICLK2/
GPO37
PCICLK4/
14M_OSC/
GPO39
GBE_RXD2
VSS
GBE_TXD3
TRDY#
0
VSS
AD26/GPIO26
0
REQ2#/
CLK_REQ8#/
GPIO41
VSS
0
AG
0
PCICLK3/
GPO38
0
AD2/GPIO2
0
GBE_TXD2
VDDIO_33_PC
IGP_5
GBE_RXCTL/
RXDV
AD16/GPIO16
FRAME#
0
AD22/GPIO22
REQ1#/
GPIO40
0
REQ0#
NC1
AH
STOP#
0
AD4/GPIO4
0
VSS
0
GBE_RXD3
SERR#
LOCK#
NC2
VSS
SD_WP/
GPIO76
AD27/GPIO27
AD28/GPIO28
SD_DATA2/
GPIO79
FANOUT0/
GPIO52
AJ
AD9/GPIO9
0
AD0/GPIO0
0
AD5/GPIO5
AD13/GPIO13
0
CBE1#
0
AD18/GPIO18
0
SD_CD#/
GPIO75
0
SD_DATA3/
GPIO80
0
FANOUT2/
GPIO54
SD_DATA0/
SDATI_0/
GPIO77
0
AK
0
0
0
0
0
0
AD14/GPIO14
0
DEVSEL#
0
AD20/GPIO20
0
AL
AD6/GPIO6
0
AD11/GPIO11
0
AD1/GPIO1
AD3/GPIO3
0
AD10/GPIO10
0
IRDY#
0
AD19/GPIO19
0
SD_CLK/
SCLK_0/
GPIO73
0
FANIN0/
GPIO56
0
0
FANIN2/
GPIO58
0
SATA_IS4#/
FANOUT3/
GPIO55
0
GNT3#/CLK_
REQ7#/SATA_
IS7#/GPIO46
0
AM
0
0
0
0
0
0
AD12/GPIO12
0
PERR#
0
AD17/GPIO17
0
SD_DATA1/
SDATO_0/
GPIO78
AN
VSS
0
CBE0#
0
AD7/GPIO7
AD8/GPIO8
0
AD15/GPIO15
0
CBE2#
0
AD21/GPIO21
0
SD_CMD/
SLOAD_0/
GPIO74
0
FANIN1/
GPIO57
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
FANOUT1/
GPIO53
0
REQ3#/CLK_
REQ5#/SATA_
IS6#/GPIO42
Figure 11. Bolton-E4 Ballout Assignment (Left)
Chapter 3
Ballout Assignment
45
AMD A77E Fusion Controller Hub Databook
53830
Rev. 3.01 February 2014
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
KSO_12/
GPIO221
0
KSO_5/
GPIO214
0
KSO_3/
GPIO212
0
KSO_16/
XDB2/
0
LAD2
0
NC3
LAD3
0
LFRAME#
0
VSS
0
KSO_9/
GPIO218
0
KSI_5/
GPIO206
0
LPCCLK0
0
LDRQ0#
0
0
0
0
0
0
B
PS2KB_CLK
/GPIO190
0
PS2M_CLK/
GPIO192
0
KSI_6/
GPIO207
0
LPC_SMI#/
GEVENT23#
0
LAD1
ML_VGA_H
PD/GPIO229
0
25M_X1
0
25M_X2
C
PS2KB_DAT
/GPIO189
0
PS2M_DAT/
GPIO191
0
LPCCLK1
0
LAD0
0
0
0
0
0
0
D
E
0
KSO_14/
XDB0/
KSO_13/
GPIO222
0
0
A
KSO_11/
GPIO220
0
KSO_4/
GPIO213
0
KSO_1/
GPIO210
0
EC_PWM0/
EC_TIMER0/
0
KSI_4/
GPIO205
0
APU_PG
0
PROCHOT#
VSS
0
GPP_CLK3N
0
GPP_CLK3P
KSI_7/
GPIO208
VSS
KSO_2/
GPIO211
KSO_0/
GPIO209
KSI_2/
GPIO203
VSS
KSI_3/
GPIO204
VSS
APU_RST#
CLK_CALRN
0
VSS
0
GPP_CLK2N
0
GPP_CLK2P
F
KSO_8/
GPIO217
SDA2/
GPIO194
0
SDA3_LV/
GPIO196
SCL3_LV/
GPIO195
0
VDDXL_33_
S
DMA_ACTIV
E#
LDT_STP#
NC4
PCIE_RCLK
N
0
PCIE_RCLK
P
0
VSS
0
G
SCL2/
GPIO193
0
EC_PWM3/
EC_TIMER3/
EC_PWM1/
EC_TIMER1/
0
VDDPL_33_
SYS
VSSPL_SYS
VDDAN_11_
CLK_1
GPP_CLK0P
GPP_CLK0N
VSS
0
DISP2_CLK
N
0
DISP2_CLK
P
H
0
SPI_CS2#/
GBE_STAT2
EC_PWM2/
EC_TIMER2/
0
VDDPL_11_
SYS_S
VDDAN_11_
CLK_2
14M_25M_4
8M_OSC
GPP_CLK1P
VSS
0
SLT_GFX_C
LKP
0
VSS
0
J
KSI_1/
GPIO202
K
KSO_7/
GPIO216
KSO_6/
GPIO215
KSO_10/
GPIO219
PS2_CLK/
SCL4/
PS2_DAT/
SDA4/
0
KSI_0/
GPIO201
0
VDDAN_11_
CLK_3
VSSXL
GPP_CLK1N
VSS
VSS
SLT_GFX_C
LKN
0
VGA_DAC_
RSET
0
VSSANQ_D
AC
VDDPL_33_
SSUSB_S
VDDIO_33_
S_2
0
VSS
VDDAN_11_
CLK_4
0
0
0
0
0
VSSAN_DA
C
0
VGA_RED
0
VGA_GREE
N
0
L
VDDIO_33_
S_3
0
VDDCR_11_
S_2
VSS
VDDAN_11_
CLK_5
GPP_CLK4P
GPP_CLK4N
VSS
GPP_CLK5N
GPP_CLK5P
VGA_HSYN
C/GPO68
VGA_BLUE
0
LDO_CAP
0
VGA_DDC_
SDA/GPO70
M
VDDIO_33_
S_1
0
VDDCR_11_
S_1
VDDAN_11_
CLK_6
VDDAN_11_
CLK_7
VSS
VSS
GPP_CLK6P
GPP_CLK6N
GPP_CLK8P
VSSIO_DAC
0
VGA_VSYN
C/GPO69
0
VGA_DDC_
SCL/GPO71
0
N
VSS
0
VSS
VSS
VDDAN_11_
CLK_8
0
0
0
0
0
ML_VGA_L3
N
ML_VGA_L3
P
0
VSS
0
VSS
P
0
0
0
0
0
GPP_CLK7P
GPP_CLK7N
VSS
DISP_CLKP
GPP_CLK8N
VSS
0
ML_VGA_L2
N
0
ML_VGA_L2
P
0
R
VSS
0
VDDCR_11_
3
VSSPL_DAC
VDDAN_33_
DAC
APU_CLKN
APU_CLKP
VSS
DISP_CLKN
VSS
ML_VGA_L1
N
ML_VGA_L1
P
0
ML_VGA_L0
P
0
ML_VGA_L0
N
T
0
0
0
0
0
AUXCAL
0
VSS
0
VSS
0
U
VDDCR_11_
5
0
VSS
VSS
VDDPL_33_
ML
VSS
0
VDDCR_11_
8
VDDPL_11_
DAC
VDDPL_33_
DAC
VDDAN_11_
ML_2
VDDAN_11_
ML_3
VDDAN_11_
ML_4
GPP_RX2P
GPP_RX1N
AUX_VGA_
CH_P
AUX_VGA_
CH_N
0
GPP_TX0N
0
GPP_TX0P
V
0
0
0
0
0
GPP_RX3N
GPP_RX3P
VSS
GPP_RX2N
GPP_RX1P
VSS
0
GPP_TX1P
0
GPP_TX1N
0
W
VSS
0
0
0
0
0
UMI_RX3P
UMI_RX3N
0
UMI_RX2N
0
UMI_RX2P
Y
AA
0
VDDAN_11_
SATA_4
VDDAN_11_
PCIE_2
VDDAN_11_
ML_1
VDDAN_11_
SATA_8
0
VDDAN_11_
SATA_7
VDDAN_11_
SATA_1
VDDAN_11_
PCIE_6
GPP_TX3N
GPP_TX3P
VSS
GPP_RX0N
GPP_RX0P
VSS
0
VSS
0
VSS
0
VDDIO_33_
PCIGP_2
0
VDDAN_11_
SATA_9
VDDAN_11_
SATA_2
VDDAN_11_
SATA_3
VDDAN_11_
PCIE_5
VDDAN_11_
PCIE_1
VSS
GPP_TX2P
GPP_TX2N
UMI_RX1P
UMI_RX1N
0
UMI_RX0N
0
UMI_RX0P
AB
VSS
VDDAN_11_
SATA_10
0
VDDAN_11_
SATA_6
VDDAN_11_
SATA_5
0
0
0
0
0
VSS
0
UMI_TX3P
0
UMI_TX3N
0
AC
INTH#/
GPIO35
CLKRUN#
0
GNT2#/
SD_LED/
SATA_ACT#
/GPIO67
0
INTF#/
GPIO33
SERIRQ/
GPIO48
0
VSS
GA20IN/
GEVENT0#
0
INTE#/
GPIO32
WD_PWRG
D
0
KBRST#/
GEVENT1#
0
VSS
VSS
VSS
VDDAN_11_
PCIE_4
CLK_REQ3#
/SATA_IS1#/
SDA0/
GPIO47
VDDAN_11_
PCIE_3
VSS
UMI_TX2P
UMI_TX2N
0
UMI_TX1N
0
UMI_TX1P
AD
LDRQ1#/
CLK_REQ6#
VSS
0
UMI_TX0P
0
UMI_TX0N
0
AE
VDDAN_11_
PCIE_7
SATA_CALR
N
SATA_CALR
P
PCIE_CALR
P
0
PCIE_CALR
N
0
VSS
AF
VDDAN_11_
PCIE_8
VDDPL_33_
SATA
0
VSS
0
VSS
0
AG
AH
SATA_X1
CLK_REQ0#
/SATA_IS3#/
0
SATA_X2
CLK_REQ1#
/FANOUT4/
0
CLK_REQ4#
/SATA_IS0#/
CLK_REQ2#
/FANIN4/
SMARTVOL
T2/
SATA_RX1N
VSS
SATA_TX2N
VSS
SATA_TX3P
VSS
SATA_RX4P
VSS
0
VDDPL_33_
PCIE
0
SATA_TX7N
0
SATA_TX7P
0
SATA_RX1P
0
SATA_TX2P
0
SATA_TX3N
0
SATA_RX4N
0
VSS
VSS
0
SATA_RX7P
0
SATA_RX7N
AJ
0
SATA_TX0P
0
VSS
0
SATA_RX2P
0
VSS
0
SATA_RX5N
0
0
0
0
0
0
AK
VSS
0
SATA_RX0N
0
SATA_TX1N
0
SATA_RX3P
0
SATA_TX4P
0
SATA_TX5N
SATA_TX6P
0
SATA_RX6N
0
SATA_RX6P
AL
SATA_IS5#/
FANIN3/
SPKR/
GPIO66
CLK_REQG
#/GPIO65/
SCL0/
GPIO43
SMARTVOL
T1/
0
SATA_TX0N
0
VSS
0
SATA_RX2N
0
VSS
0
SATA_RX5P
0
0
0
0
0
0
AM
VSS
0
SATA_RX0P
0
SATA_TX1P
0
SATA_RX3N
0
SATA_TX4N
0
VSS
SATA_TX5P
0
SATA_TX6N
0
VSS
AN
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
Figure 12. Bolton-E4 Ballout Assignment (Right)
46
Ballout Assignment
Chapter 3
53830
AMD A77E Fusion Controller Hub Databook
Rev. 3.01 February 2014
Chapter 4
Pin Descriptions
Notes:
For multi-functional pins, please refer to the relevant section for description of a specific function
(e.g., for USB_FSD1P/GPIO186, the USB_FSD1P function is described in Section 4.6 “USB
Interface” on page 51, and the GPIO186 function is described in Section 4.21 “General Purpose I/O
and General Event Pins” on page 67).
4.1
APU Interface
Table 8.
APU Interface Pin Descriptions
Pin name
DMA_ACTIVE#
APU_PG
APU_RST#
LDT_STP#
PROCHOT#
4.2
Table 9.
OD
I
LPC Interface Pin Descriptions
GA20IN/GEVENT0#
KBRST#/
GEVENT1#
LAD[3:0]
LDRQ0#
LDRQ1#/
CLK_REQ6#/
GPIO49
LFRAME#
Chapter 4
VDDIO_33_S
VDDIO_33_S
(0.8V threshold)
Functional Description
DMA_ACTIVE#. See Section 4.14 “Power
Management Interface” on page 57 for description.
APU Power Good
APU Reset. See Section 4.16 “Reset Pins” on
page 60 for description.
Not used. Leave unconnected.
Processor Hot: Similar to TALERT#. When it is
asserted, it can generate SCI or SMI to OS/BIOS
LPC Interface
Pin Name
CLKRUN#
LPCCLK0
Type
Voltage
In/OD VDDIO_33_S
(0.8V threshold)
OD
VDDIO_33_S
OD
VDDIO_33_S
Type
Voltage
I/O VDDIO_33_PCIGP
(5V tolerance)
I
VDDIO_33_PCIGP
(5V tolerance)
I
VDDIO_33_PCIGP
(5V tolerance)
I/O VDDIO_33_S
I
VDDIO_33_S
I/O VDDIO_33_PCIGP
(5V tolerance)
O
VDDIO_33_S
O
VDDIO_33_S
Functional Description
See Section 4.17 “Clock Interface” on page 62 for
description.
A20 Gate Input from SIO / General Event 0
Keyboard reset# / General Event 1
Multiplexed Command / Address/Data [3:0]
Encoded DMA Bus Master Request 0
Encoded DMA Bus Master Request 1 / Clock Request
6 / GPIO 49
LPC Bus Frame. Indicates start of a new cycle or
termination of a broken cycle.
33MHz LPCCLK for LPC device such as flash ROM
Pin Descriptions
47
AMD A77E Fusion Controller Hub Databook
Table 9.
53830
Rev. 3.01 February 2014
LPC Interface Pin Descriptions
Pin Name
LPCCLK1
LPC_SMI#/
GEVENT23#
SERIRQ/GPIO48
Type
Voltage
O
VDDIO_33_S
I
VDDIO_33_S
Functional Description
33MHz LPCCLK for LPC device such as SIO device
LPC SMI / General Event 23
VDDIO_33_PCIGP Serial IRQ / GPIO 48
(5V tolerance)
Note: LPCCLK0 can be assigned to any LPC device. This clock can be active during sleep state during initial
G3->S5 or when IMC is enabled. LPCCLK1 and PCI clock can be used for additional LPC devices that do
not require a clock in S3–S5 states.
4.3
Table 10.
I/O
Unified Media Interface (UMI)
UMI Pin Descriptions
Pin Name
UMI_TX[3:0]P
UMI_TX[3:0]N
UMI_RX[3:0]P
UMI_RX[3:0]N
PCIE_CALRP
Type
Voltage
O
O
I
I
VDDAN_11_
I/O
PCIE
PCIE_CALRN
I/O
4.4
Table 11.
General Purpose PCI Express® Ports Interface
General Purpose PCI Express® Ports Interface Pin Descriptions
Pin Name
GPP_TX[3:0]P
Type
O
GPP_TX[3:0]N
O
GPP_RX[3:0]P
I
GPP_RX[3:0]N
I
48
Functional Description
SCL Lane 3-0 Transmit Positive
SCL Lane 3-0 Transmit Negative
SCL Lane 3-0 Receive Positive
SCL Lane 3-0 Receive Negative
Pad connection to an external resistor to VSS on
board required for TX impedance calibration.
Pad connection to an external resistor to
VDDAN_11_PCIE on board required for RX
impedance calibration.
Voltage
VDDAN_11_
PCIE
Functional Description
General purpose PCIe® ports Lane 3 to 0 Transmit
Positive
General purpose PCIe ports Lane 3 to 0 Transmit
Negative
General purpose PCIe ports Lane 3 to 0 Receive
Positive
General purpose PCIe ports Lane 3 to 0 Receive
Negative
Pin Descriptions
Chapter 4
53830
AMD A77E Fusion Controller Hub Databook
Rev. 3.01 February 2014
4.5
Table 12.
PCI Interface (PCI Host Bus and Internal PCI/PCI
Bridge)
PCI Interface (PCI Host Bus and Internal PCI/PCI Bridge) Pin Description
Pin Name
AD[31:0]/
GPIO[31:0]
CBE[3:0]#
CLKRUN#
DEVSEL#
FRAME#
GNT0#
GNT1#/GPO44
GNT2#/SD_LED/
GPO45
GNT3#/
CLK_REQ7#/
GPIO46
INTH#/GPIO35
INTG#/
GPIO34
INTF#/GPIO33
INTE#/GPIO32
IRDY#
LOCK#
PAR
PCICLK0
Chapter 4
Type
Voltage
I/O VDDIO_33_PCIGP
(5V tolerance)
I/O VDDIO_33_PCIGP
(5V tolerance)
I/O VDDIO_33_PCIGP
(5V tolerance)
I/O VDDIO_33_PCIGP
(5V tolerance)
I/O VDDIO_33_PCIGP
(5V tolerance)
O
VDDIO_33_PCIGP
(5V tolerance)
O
VDDIO_33_PCIGP
(5V tolerance)
Functional Description
PCI Bus Address/Data [31:0] / GPIO[31:0]
Command/Byte Enable[3:0]
See Section 4.17 “Clock Interface” on page 62 for
description.
Device Select. Driven by target to indicate it has
decoded its address as the target of the current access.
Cycle Frame. Driven by the current master to indicate
the beginning and duration of an access.
PCI Bus Grant 0 from the FCH. Indicates to the agent
that access to the bus has been granted.
PCI Bus Grant 1 from the FCH. Indicates to the agent
that access to the bus has been granted. Pin muxed with
GPIO44
O
VDDIO_33_PCIGP PCI Bus Grant 2 from the FCH. Indicates to the agent
(5V tolerance)
that access to the bus has been granted. Pin muxed with
GPIO45
I/O VDDIO_33_PCIGP PCI Bus Grant 3 from the FCH. Indicates to the agent
(5V tolerance)
that access to the bus has been granted. Pin muxed with
GPIO46
I/O VDDIO_33_PCIGP PCI Interrupt H / GPIO 35
(5V tolerance)
I/O VDDIO_33_PCIGP PCI Interrupt G / GPIO 33
(5V tolerance)
I/O VDDIO_33_PCIGP PCI Interrupt F / GPIO 33
(5V tolerance)
I/O VDDIO_33_PCIGP PCI Interrupt E / GPIO 32
(5V tolerance)
I/O VDDIO_33_PCIGP Initiator Ready: Indicates the initiating agent’s ability
(5V tolerance)
to complete the current data phase of the transaction
I/OD VDDIO_33_PCIGP PCI Bus Lock
(5V tolerance)
I/O VDDIO_33_PCIGP PCI Bus Parity
(5V tolerance)
O
VDDIO_33_PCIGP 33 MHz PCI clock 0
(5V tolerance)
Pin Descriptions
49
AMD A77E Fusion Controller Hub Databook
Table 12.
A_RST#
PERR#
REQ0#
REQ1#/GPIO40
REQ2#/
CLK_REQ8#/
GPIO41
REQ3#/
CLK_REQ5#/
GPIO42
SERR#
TRDY#
50
Rev. 3.01 February 2014
PCI Interface (PCI Host Bus and Internal PCI/PCI Bridge) Pin Description
Pin Name
PCICLK[3:1]/
GPO[38:36]
PCICLK4/
14M_OSC/GPO39
PCIRST#
STOP#
53830
Type
Voltage
O
VDDIO_33_PCIGP
(5V tolerance)
O
VDDIO_33_PCIGP
(5V tolerance)
O
VDDIO_33_PCIGP
(5V tolerance)
O
VDDIO_33_S
(5V tolerance)
I/O VDDIO_33_PCIGP
(5V tolerance)
I
VDDIO_33_PCIGP
(5V tolerance)
I
VDDIO_33_PCIGP
(5V tolerance)
I
VDDIO_33_PCIGP
(5V tolerance)
I
Functional Description
33 MHz PCI clock [3:1]
33 MHz PCI clock 4. See Section 4.17 “Clock
Interface” on page 62 for description.
Hardware Reset for PCI Slots. See Section 4.16 “Reset
Pins” on page 60 for description.
PCI Host Bus Reset. See Section 4.16 “Reset Pins” on
page 60 for description.
Parity Error. Reports data parity errors during all PCI
transactions, except in a special cycle.
PCI Request 0 Input. Indicates that the agent desires
use of the bus.
PCI Request 1 Input. Indicates that the agent desires
use of the bus.
Request 2 Input. Indicates that the agent desires use of
the bus
VDDIO_33_PCIGP Request 3 Input. Indicates that the agent desires use of
the bus.
(5V tolerance)
I/OD VDDIO_33_PCIGP System Error. For reporting address parity errors and
data parity errors on the special cycle command, or any
(5V tolerance)
other system error where the result will be catastrophic.
I/O VDDIO_33_PCIGP Stop. Indicates the current target is requesting the
master to stop the current transaction
(5V tolerance)
I/O VDDIO_33_PCIGP Target Ready. Indicates the target agent’s ability to
complete the current data phase of the transaction.
(5V tolerance)
Pin Descriptions
Chapter 4
53830
AMD A77E Fusion Controller Hub Databook
Rev. 3.01 February 2014
4.6
Table 13.
USB Interface
USB Interface Pin Descriptions
Pin Name
USB_SS_TX[3:0]P
USB_SS_TX[3:0]N
USB_SS_RX[3:0]P
USB_SS_RX[3:0]N
USB_HSD[13:0]P
USB_HSD[13:0]N
USB_FSD1P/
GPIO186
USB_FSD0P/
GPIO185
USB_FSD[1:0]N
USBCLK/
14M_25M_48M_O
SC
USB_RCOMP
USB_OC0#/
GEVENT12#/TRST
USB_OC1#/TDI/
GEVENT13#
USB_OC2#/TCK/
GEVENT14#
USB_OC3#/
AC_PRES/TDO/
GEVENT15#
USB_OC4#/
IR_RX0/
GEVENT16#
USB_OC5#/
IR_TX0/
GEVENT17#
USB_OC6#/
IR_TX1/
GEVENT6#
BLINK/
USB_OC7#/
GEVENT18#
USBSS_CALRP
Chapter 4
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Voltage
VDDAN_11_SSUSB
VDDAN_11_SSUSB
VDDAN_11_SSUSB
VDDAN_11_SSUSB
VDDAN_33_USB
VDDAN_33_USB
VDDIO_33_S
Functional Description
USB Super Speed port 3:0 Transmit Positive
USB Super Speed port 3:0 Transmit Negative
USB Super Speed port 3:0 Receive Positive
USB Super Speed port 3:0 Receive Negative
USB Port 13:0 Positive I/O
USB Port 13:0 Negative I/O
USB port 1 (full/low speed) Positive I/O
I/O
VDDIO_33_S
USB port 0 (full/low speed) Positive I/O
I/O
I/O
VDDIO_33_S
VDDPL_33_USB
I
I/O
VDDPL_33_USB
VDDIO_33_S
USB port 1:0 (full/low speed) Negative I/O
See Section 4.16 “Reset Pins” on page 60; Section
4.17 “Clock Interface” on page 62; and Section
4.18 “ATE/JTAG Interface” on page 65
Compensating resistors input.
USB Over Current 0#
I/O
VDDIO_33_S
USB Over Current 1#
I/O
VDDIO_33_S
USB Over Current 2#
I/O
VDDIO_33_S
USB Over Current 3#
I/O
VDDIO_33_S
USB Over Current 4#
I/O
VDDIO_33_S
USB Over Current 5#
I/O
VDDIO_33_S
USB Over Current 6#
I/O
VDDIO_33_S
USB Over Current 7#
VDDAN_11_SSUSB
Pad connection to an external resistor to VSS (close
to USBSS interface) on the motherboard, for TX
impedance calibration
I
Pin Descriptions
51
AMD A77E Fusion Controller Hub Databook
Table 13.
53830
Rev. 3.01 February 2014
USB Interface Pin Descriptions (Continued)
Pin Name
USBSS_CALRN
Type
I
Voltage
VDDAN_11_SSUSB
Functional Description
Pad connection to an external resistor to
VDDAN_11_SSUSB on the motherboard, for RX
impedance calibration
Note:
1. The USB_HSD[13:0]P and USB_HSD[13:0]N signals are used for connecting internal or external USB devices through
the USB Port connectors. These ports are handled by users and are subject directly to ESD events to either the connector,
the device, or to the pins themselves. The USB_HSDP and USB_HSDN signals that may be exposed to the user through an
USB port connection must have ESD protection.
2. The USB_FSD[1:0]P and USB _FSD[1:0]N signals are used only for connecting to internal devices. They support only full
or low, but not high speed devices.
3. The USBCK/14M_25M_48M_OSC pin (G8) as well as the 14M_25M_48M_OSC pin (J26) output a 14.318MHz clock on
the first power up if the internal system clock generator mode strap is selected.
4.7
Table 14.
SD Card Interface
SD Card Interface Pin Descriptions
Pin Name
SD_CLK/SCLK_0/GPIO73
SD_CMD/SLOAD_0/GPIO74
SD_CD#/GPIO75
SD_WP/GPIO76
SD_DATA0/SDATI_0/GPIO77
SD_DATA1/SDATO_0/GPIO78
SD_DATA2/GPIO79
SD_DATA3/GPIO80
GNT2#/SD_LED/GPO45
4.8
Table 15.
Serial ATA Interface
Serial ATA Interface Pin Descriptions
Pin Name
SATA_ACT#/GPIO67
SATA_CALRP
SATA_CALRN
SATA_RX[57:0]N
SATA_RX[57:0]P
52
Type
Voltage
Functional Description
O
SD Clock
O
SD Command
I
SD Card Detect
O
SD Write Protect
I/O VDDIO_33_PCIGP SD Data
I/O
SD Data 1
I/O
SD Data 2
I/O
SD Data 3
O
SD LED
Type
Voltage
Functional Description
OD VDDIO_33_PCIGP SATA Channel Active
I
VDDAN_11_SATA Pad connection to an external resistor to VSS close
to the SATA interface on the motherboard, for TX
impedance calibration
I
VDDAN_11_SATA Pad connection to an external resistor to
VDDAN_11_SATA on the motherboard, for RX
impedance calibration
I
VDDAN_11_SATA SATA Channel[57:0] Receive Negative
I
VDDAN_11_SATA SATA Channel[57:0] Receive Positive
Pin Descriptions
Chapter 4
53830
AMD A77E Fusion Controller Hub Databook
Rev. 3.01 February 2014
Table 15.
Serial ATA Interface Pin Descriptions (Continued)
Pin Name
SATA_TX[57:0]N
SATA_TX[57:0]P
SATA_X1
SATA_X2
CLK_REQ4#/
SATA_IS0#/GPIO64
CLKREQ3#/
SATA_IS1#/GPIO63
SMARTVOLT1/
SATA_IS2#/GPIO50
CLKREQ0#/
SATA_IS3#/GPIO60
SATA_IS4#/
FANOUT3/GPIO55
SATA_IS5#/FANIN3/
GPIO59
REQ3#/CLK_REQ5#/
SATA_IS6#/GPIO42
GNT3#/CLK_REQ7#/
SATA_IS7#/GPIO46
VIN2/SDATI_1/
GPIO177
VIN3/SDATO_1/
GPIO178
VIN4/SLOAD_1/
GPIO179
VIN5/SCLK_1/
GPIO180
SD_CLK/SCLK_0/
GPIO73
SD_CMD/SLOAD_0/
GPIO74
SD_DATA0/
SDATI_0/GPIO77
SD_DATA1/
SDATO_0/GPIO78
Type
Voltage
Functional Description
O
VDDAN_11_SATA SATA Channel[57:0] Transmit Negative
O
VDDAN_11_SATA SATA Channel[57:0] Transmit Positive
I
VDDPL_33_SATA SATA 25MHz crystal clock input (external clock
mode)
O
VDDPL_33_SATA SATA 25MHz crystal clock input (external clock
mode)
I/O VDDIO_33_PCIGP SATA Interlock Switch Port 0 (Input) *
I/O
VDDIO_33_PCIGP
SATA Interlock Switch Port 1 (Input) *
I/O
VDDIO_33_PCIGP
SATA Interlock Switch Port 2 (input) *
I/O
VDDIO_33_PCIGP
SATA Interlock Switch Port 3 (input) *
I/O
VDDIO_33_PCIGP
SATA Interlock Switch Port 4 (input) *
I/O
VDDIO_33_PCIGP
SATA Interlock Switch Port 5 (input) *
I/O
VDDIO_33_PCIGP
SATA Interlock Switch Port 6 (input) *
I/O
VDDIO_33_PCIGP
SATA Interlock Switch Port 7 (input) *
I/O
VDDIO_33_S
SGPIO Data In (set 1) **
I/O
VDDIO_33_S
SGPIO Data Out (set 1) **
I/O
VDDIO_33_S
SGPIO Load (set 1) **
I/O
VDDIO_33_S
SGPIO Clock (set 1) **
I/O
VDDIO_33_PCIGP
SGPIO Clock (set 0) **
I/O
VDDIO_33_PCIGP
SGPIO Load (set 0) **
I/O
VDDIO_33_PCIGP
SGPIO Data In (set 0) **
I/O
VDDIO_33_PCIGP
SGPIO Data Out (set 0) **
Notes:
1. * SATA_ISx#: These are Hot Plug external interlock switches (one for each SATA port). The SATA Hot Plug function support
with AMD drivers does not require the use of these signals. Please refer to the Bolton Motherboard Design Guide on how to
terminate these signals.
2. ** Bolton-E4 supports up to two sets of SGPIO.
Chapter 4
Pin Descriptions
53
AMD A77E Fusion Controller Hub Databook
4.9
Table 16.
HD Audio Interface Pin Descriptions
AZ_RST#
AZ_SDIN[3:0]/
GPIO[170:167]
AZ_SDOUT
AZ_SYNC
Table 17.
Type
Voltage
O
VDDIO_33_S/VDDIO_AZ_S
(1.5V)
O
VDDIO_33_S/VDDIO_AZ_S
(1.5V)
I/O VDDIO_33_S/VDDIO_AZ_S
(1.5V)
O
VDDIO_33_S/VDDIO_AZ_S
(1.5V)
O
VDDIO_33_S/VDDIO_AZ_S
(1.5V)
Functional description
HD Audio Interface Bit Clock
HD Audio Interface Reset
HD Audio Serial Data Input from Codec [3:0]/
GPIO [170:167]
HD Audio Serial Data Output to Codec
HD Audio Sync signal to Codec
Real Time Clock Interface
Real Time Clock Interface
Pin Name
32K_X1
32K_X2
Type
Voltage
I
VDDIO_33_S/
VDDBT_RTC_G
O
VDDIO_33_S/
VDDBT_RTC_G
RTCCLK
INTRUDER_ALER
T#
S5_CORE_EN
I/O
I
VDDIO_33_S
VDDBT_RTC_G
O
VDDIO_33_S
USB_OC3#/
AC_PRES/TDO/
GEVENT15#
WAKE#/
GEVENT8#
IR_LED#/LLB#/
GPIO184
I/O
VDDIO_33_S
I/O
VDDIO_33_S
I/O
VDDIO_33_S
54
Rev. 3.01 February 2014
HD Audio Interface
Pin Name
AZ_BITCLK
4.10
53830
Functional Description
RTC crystal oscillator input 1 (internal RTC). See
Section 4.17 “Clock Interface” on page 62 for
description.
RTC crystal oscillator input 2 (internal RTC). See
Section 4.17 “Clock Interface” on page 62 for
description.
32 kHz output for internal RTC.
Intruder alert sense input
S5 Core Enable. See Section 4.14 “Power
Management Interface” on page 57 for description.
AC Power Present. See Section 4.14 “Power
Management Interface” on page 57 for description.
PCIe® Wake. See Section 4.14 “Power Management
Interface” on page 57 for description.
Low Low Battery. Connected to the battery circuit
signal output that indicates a battery low condition.
When the function is enabled, an assertion of this pin
will prevent the system from waking up by any wake
event .
Pin Descriptions
Chapter 4
53830
AMD A77E Fusion Controller Hub Databook
Rev. 3.01 February 2014
Table 17.
Real Time Clock Interface (Continued)
Pin Name
SLP_S3#
Type
Voltage
O
VDDIO_33_S
SLP_S5#
O
VDDIO_33_S
PWR_BTN#
I
VDDIO_33_S
4.11
Table 18.
Hardware Monitor Interface
Hardware Monitor Interface Pin Descriptions
Pin Name
CLK_REQ1#/
FANOUT4/GPIO61
CLK_REQ2#/
FANIN4/GPIO62
FANIN[2:0]/
GPIO[58:56]
FANOUT[2:0]/
GPIO[54:52]
SATA_IS4#/
FANOUT3/GPIO55
SATA_IS5#/
FANIN3/GPIO59
TEMPIN[2:0]/
GPIO[173:171]
TEMPIN3/
TALERT#/GPIO174
VIN0/GPIO175
VIN1/GPIO176
VIN2/SDATI_1/
GPIO177
VIN3/SDATO_1/
GPIO178
VIN4/SLOAD_1/
GPIO179
VIN5/SCLK_1/
GPIO180
VIN6/GBE_STAT3/
GPIO181
Chapter 4
Functional Description
S3 Sleep Power plane control. See Section 4.14
“Power Management Interface” on page 57 for
description.
S5 Sleep Power plane control. See Section 4.14
“Power Management Interface” on page 57 for
description.
Power Button. See Section 4.14 “Power Management
Interface” on page 57 for description.
Type
Voltage
I/O VDD_IO_33_PCIG
P (5V tolerance)
I/O VDD_IO_33_PCIG
P (5V tolerance)
I/O VDD_IO_33_PCIG
P (5V tolerance)
I/O VDD_IO_33_PCIG
P (5V tolerance)
I/O VDD_IO_33_PCIG
P (5V tolerance)
I/O VDD_IO_33_PCIG
P (5V tolerance)
I/O VDDIO_33_S
Functional Description
Fan PWM Output 4
Fan Input 4
Fan Tachometer Input [2:0]
Fan PWM Output [2:0]
Fan Control Output 3
Fan Input 3
Temperature Monitor Input [2:0] (not supported)
I/O
VDDIO_33_S
I/O
I/O
I/O
VDDIO_33_S
VDDIO_33_S
VDDIO_33_S
Temperature Monitor Input 3 (not supported) /
Temperature has reached cautionary state
Voltage Monitor Input 0 (not supported)
Voltage Monitor Input 1 (not supported)
Voltage Monitor Input 2 (not supported)
I/O
VDDIO_33_S
Voltage Monitor Input 3 (not supported)
I/O
VDDIO_33_S
Voltage Monitor Input 4 (not supported)
I/O
VDDIO_33_S
Voltage Monitor Input 5 (not supported)
I/O
VDDIO_33_S
Voltage Monitor Input 6 (not supported)
Pin Descriptions
55
AMD A77E Fusion Controller Hub Databook
Table 18.
Table 19.
I/O
VDDIO_33_S
Voltage Monitor Input 7 (not supported)
VGA Translator Interface
VGA Translator Interface Pin Descriptions
Pin Name
ML_VGA_L[3:0]P
ML_VGA_L[3:0]N
ML_VGA_HPD/
GPIO229
Type
Voltage
I
VDDAN_11_ML
I
VDDAN_11_ML
I/O* VDDIO_33_S
Functional Description
Translator Input [3:0] Positive
Translator Input [3:0] Negative
VGA Hot Plug Detect
* Programmed by software to output as required, see
Table 28 on page 67, for default I/O state.
AUX Port Calibration
AUX Port Positive
AUX Port Negative
VGA Red Output
AUXCAL
AUX_VGA_CH_P
AUX_VGA_CH_N
VGA_RED
I/O
I/O
I/O
O
VGA_BLUE
VGA_GREEN
VGA_HSYNC/
GPO68
VGA_VSYNC/
GPO69
VGA_DAC_RSET
VGA_DDC_SDA/
GPO70
VGA_DDC_SCL/
GPO71
DDR3_RST#/
GEVENT7#/
VGA_PD
O
O
O
VDDIO_33_PCIGP
VDDIO_33_PCIGP
VDDIO_33_PCIGP
LDO_CAP
(internally- generated
supply)
LDO_CAP
VGA Blue Output
LDO_CAP
VGA Green Output
VDDIO_33_PCIGP VGA Horizontal SYNC
O
VDDIO_33_PCIGP
VGA Veritical SYNC
O
I/O
VDDIO_33_PCIGP
VDDIO_33_PCIGP
(5V tolerance)
VDDIO_33_PCIGP
(5V tolerance)
VDDIO_33_S
DAC Reset
VGA DDC Data
4.13
Rev. 3.01 February 2014
Hardware Monitor Interface Pin Descriptions
VIN7/GBE_LED3/
GPIO182
4.12
53830
I/O
O*
VGA DDC Clock
VGA Power Down. This pin is used to power down
the VGA DAC regulators when no display is
connected.
* Note: Pin type is OD for DDR_RST#, and I/O for
GEVENT7#
SPI ROM Interface
SPI ROM is supported up to 66 MHz. The burst read and fast read cycles are not supported. Refer to
Section 6.5.3.3 “SPI AC Specifications” on page 107 for timing information.
56
Pin Descriptions
Chapter 4
53830
AMD A77E Fusion Controller Hub Databook
Rev. 3.01 February 2014
Table 20.
SPI ROM Interface Pin Descriptions
Pin Name
Type
Voltage
SPI_CS1#/GPIO165
I/O VDDIO_33_S
SPI_CS2#/GBE_STAT2/ I/O VDDIO_33_S
GPIO166
SPI_CS3#/GBE_STAT1/ I/O VDDIO_33_S
GEVENT21#
SPI_CLK/GPIO162
I/O VDDIO_33_S
SPI_DI/GPIO164
I/O VDDIO_33_S
SPI_DO/GPIO163
I/O VDDIO_33_S
SPI_HOLD#/
I/O VDDIO_33_S
GBE_LED1/GEVENT9#
ROM_RST#/SPI_WP#/
I/O VDDIO_33_S
GPIO161
LPC_PD#/GEVENT5#
I/O VDDIO_33_S
4.14
Table 21.
SPI Chip Select3#
SPI Clock
SPI Data In
SPI Data Output
SPI HOLD#. Assert low to hold the SPI
transaction.
ROM reset (LPC flash) or SPI write protect
(active low)
LPC power down (negative logic)
Power Management Interface
Power Management Interface Pin Descriptions
Pin Name
DMA_ACTIVE#
Type
Voltage
In/OD VDDIO_33_S
(0.8V threshold)
PME#/GEVENT3#
I/O
VDDIO_33_S
LPC_SMI#/
GEVENT23#
PWR_BTN#
I/O
VDDIO_33_S
I
VDDIO_33_S
Chapter 4
Functional Description
SPI Chip Select1#
SPI Chip Select2#
Functional Description
DMA active. Bolton-E4 drives the DMA_ACTIVE#
to APU to notify DMA activity. This will cause the
APU to re-establish the SCL link quicker.
LPC/PCI PME# Power management signal for LPC/
PCI interface.
LPC SMI Input
Power Button. The Power Button causes an SMI or
SCI to indicate a system request to go to a sleep state.
If the system is already in a sleep state, this signal will
cause a wake event. If PWRBTN# is pressed for more
than 4 seconds, it will cause an unconditional transition
(power button override) to the S5 state with only the
PWRBTN# available as a wake event. This signal has
an internal pull-up resistor.
Pin Descriptions
57
AMD A77E Fusion Controller Hub Databook
Table 21.
Rev. 3.01 February 2014
Power Management Interface Pin Descriptions (Continued)
Pin Name
PWR_GOOD
RI#/GEVENT22#
S5_CORE_EN
SMARTVOLT2/
SHUTDOWN#/
GPIO51
Type
I
I/O
O
I/O
SLP_S3#
O
SLP_S5#
O
THRMTRIP#/
SMBALERT#/
GEVENT2#
58
53830
I/O
Voltage
VDDIO_33_S
Functional Description
Power good input. Assertion of PWR_GOOD by the
power good circuit on the motherboard indicates that
power supplies to the Bolton-E4 are valid. Assertion
takes place sometime after APU Power Good is
asserted.
Deassertion of PWR_GOOD by the power good
circuit indicates that the power supplies to the chip are
NOT valid. Deassertion takes place sometime after
SLP_S3# or SLP_S5#’s assertion, or after Power
Supply Power Good is deasserted.
VDDIO_33_S
Ring Indicator
VDDIO_33_S
S5 Core Enable.
VDDIO_33_PCIGP System Shutdown.
(5V tolerance)
Assertion will cause the Bolton-E4 to assert SLP_S3#
and SLP_S5# to force system to transition to S5
immediately, without waiting for the STPGNT
message from the APU.
VDDIO_33_S
S3 Sleep Power plane control.
Assertion of SLP_S3# shuts off power to non-critical
components when system transitions to S3, S4, or S5
states.
Deassertion of SLP_S3# turns on power to noncritical components when system transitions from S3,
S4, or S5 back to S0. Deassertion takes place
sometime after a wake-up event has been triggered.
VDDIO_33_S
S5 Sleep Power plane control.
Assertion of SLP_S5# shuts power off to non-critical
components when system transitions to S4 or S5 state.
Deassertion of SLP_S5# turns on power to noncritical components when transitioning from S4/S5
back to S0 state. Deassertion takes place sometime
after a wake-up event is triggered.
VDDIO_33_S
Thermal Trip.
Indicates to Bolton E4 that a thermal trip has
occurred. Its assertion will cause Bolton E4 to
transition the system to S5 immediately, without
waiting for the STPGNT message from the processor.
Note: If Thermtrip function is required, the SMBalert
function can be mapped to any other available Gevent
pin.
Pin Descriptions
Chapter 4
53830
AMD A77E Fusion Controller Hub Databook
Rev. 3.01 February 2014
Table 21.
Power Management Interface Pin Descriptions (Continued)
Pin Name
TEMPIN3/
TALERT#/
GPIO174
Type
I/O
Voltage
VDDIO_33_S
Functional Description
Thermal Alert.
The signal is a thermal alert to the FCH. The FCH can
be programmed to generate an SMI, SCI, or IRQ13
through GPE, or generate an SMI without GPE in
response to the signal’s assertion. See the AMD
Bolton Fusion Controller Hub Register Reference
Guide for details.
USB_OC3#/
AC_PRES/TDO/
GEVENT15#
WAKE#/
GEVENT8#
I/O
VDDIO_33_S
AC Power Present. Used by the FCH to check if AC
power is present.
I/O
VDDIO_33_S
WD_PWRGD
OD
4.15
Table 22.
SMBus Interface
SMBus Interface Pin Descriptions
Pin Name
SCL0/GPIO43
SDA0/GPIO47
SCL1/GPIO227
SDA1/GPIO228
Chapter 4
PCIe Wake. WAKE# signal is required for PCIe
devices. This signal is routed from the PCIe device/slot
to the FCH. Note: the WAKE# is in S5 domain so it is
active when the system is in S5 state. Care must be
taken when plugging in the PCIe devices: the system
should be transitioned into G3 state (S5 Power OFF)
before a PCIe device is installed. Plugging in a PCIe
device when the system is in S5 state may cause the
system to wake up. That is because the WAKE# signal
driven by the PCIe device may transition momentarily
to active state when the device is installed but has not
been initialized to drive the signal in an inactive state.
VDDIO_33_PCIGP The pin is not used by the FCH. Refer to the AMD
Bolton Fusion Controller Hub Motherboard Design
Guide on how to handle the pin.
Type
Voltage
I/O VDDIO_33_PCIGP
(5V tolerance)
I/O VDDIO_33_PCIGP
(5V tolerance)
I/O VDDIO_33_S
I/O
VDDIO_33_S
Functional Description
SMBus Clock 0
SMBus Data 0
SMBus Clock 1. SMBus Clock 1 supports an ASF
interface or a Synaptics InterTouch Touchpad. See
Note 1 below.
SMBus Data 1. SMBus Data 1 supports an ASF
interface or a Synaptics InterTouch Touchpad. See
Note 1 below.
Pin Descriptions
59
AMD A77E Fusion Controller Hub Databook
Table 22.
53830
Rev. 3.01 February 2014
SMBus Interface Pin Descriptions (Continued)
Pin Name
SCL2/GPIO193
SDA2/GPIO194
SCL3_LV/GPIO195
Type
Voltage
I/O VDDIO_33_S
I/O VDDIO_33_S
I/O VDDIO_33_S domain
(0.8V threshold)
I/O VDDIO_33_S domain
(0.8V threshold)
I/O VDDIO_33_S
SDA3_LV/GPIO196
PS2_CLK/SCL4/
GPIO188
PS2_DAT/SDA4/
GPIO187
THRMTRIP#/
SMBALERT#/
GEVENT2#
Functional Description
SMBus Clock 2
SMBus Data 2
SMBus Clock 3 (typically used for TSI)
SMBus Data 3 (typically used for TSI)
SMBus Clock 4
I/O
VDDIO_33_S
SMBus Data 4
I/O
VDDIO_33_S
SMBus Alert#. This signal is used to wake the
system or generate an SMI. If not used for
SMBALERT#, it can be used for thermal trip or as
a GEVENT.
Note: If this pin is used for Thermtrip function, the
SMBalert function can be mapped to any other
available Gevent pin.
Notes:
1. The SDA1 and SCL1 SMBus1 interface is dedicated for ASF devices or a Synaptics InterTouch Touchpad. This SMBus1
interface will not support a connection to both types of devices simultaneously.
2. There are only two SMBus controllers. The SCL1/SDA1 pair is controlled by SMBus controller 1. SCL0/SDA0, SCL2/
SDA2, SCL3/SDA3 and SCL4/SDA4 are multiplexed pins that are all controlled by SMBus controller 0, and only 1 pair of
those pins can be active at any time.
4.16
Table 23.
Reset Pins
Reset Pin Descriptions
Pin Name
A_RST#
AZ_RST#
DDR3_RST#/
GEVENT7#/
VGA_PD
60
Type
Voltage
O VDDIO_33_S
O
OD
VDDIO_33_S/
VDDIO_AZ_S
VDDIO_33_S
Functional Description
PCI Host Bus Reset. Asserted during transition to S3/S4/S5
to reset all devices in the FCH or connected to it, except the
ACPI logic in the FCH.
HD Audio interface Reset.
System Memory Reset
Pin Descriptions
Chapter 4
53830
AMD A77E Fusion Controller Hub Databook
Rev. 3.01 February 2014
Table 23.
Reset Pin Descriptions (Continued)
Pin Name
APU_RST#
PCIE_RST#
Type
Voltage
OD VDDIO_33_S
(0.8V threshold)
O
VDDIO_33_S
PCIE_RST2#/
GEVENT4#
PCIRST#
I/O
VDDIO_33_S
ROM_RST#/
GPIO161
I/O
RSMRST#
SYS_RESET#/
GEVENT19#
Chapter 4
O
VDDIO_33_PCI
GP
(5V tolerance)
VDDIO_33_S
I
VDDIO_33_S
I/O
VDDIO_33_S
Functional Description
APU Reset. Reset signal to the APU. Assertion of
APU_RST# causes the APU to re-initialize its internal states.
Assertion of APU_RST# can occur based on the following:
1) whenever there is a S3 or higher sleep state entry;
2) deassertion of FCH PWR_GOOD;
3) warm reset issued by a software command such as a write
to IO 0xCF9;
4) hardware reset due to assertion of pins such as RSMRST#
or KB_RST# or SYS_RESET#,
5) an internal error (sync flood);
6) expiration of the watchdog timer.
When the above conditions are no longer true, APU_RST#
will deassert after a predetermined period of time (see
Figure 21 Reset Timing Requirements on page 95)
PCIe Reset. Asserted during transition to S3/S4/S5. Same
function as A_RST#.
Additional PCIe reset for GPP.
Hardware Reset for PCI slots. Asserted (a) at power on, (b)
after the system has transitioned into S3/S4/S5, (c) at warm
reset, (d) at software initiated reset
ROM Reset. Early version of system reset, the deassertion of
which is ahead of other system reset signals such as
A_RST#, PCIE_RST#, or PCIRST#. Used for resetting the
system BIOS flash ROM.
Resume Reset from motherboard. Assertion of RSMRST#
resets all FCH registers to their default values. It also causes
all reset signals originating from the FCH (A_RST#,
PCIRST#, PCIE_RST#, APU_RST#, AZ_RST#, FC_RST#,
GBE_PHY_RST#, ROM_RST# and, DDR3_RST#) to be
issued. RSRMT# should be asserted when system power is
being applied for the first time. RSMRST# should be
deasserted sometime after S5 power is up, and should stay
deasserted until system power is removed.
System Reset. Signal coming from the power button circuit
signaling a reset for the system. On receiving the signal, the
FCH asserts all reset signals that originate from the FCH
(A_RST#, PCIRST#, PCIE_RST#, APU_RST#, AZ_RST#,
FC_RST#, ROM_RST#, and DDR3_RST#). it also resets all
FCH registers to their default values.
Pin Descriptions
61
AMD A77E Fusion Controller Hub Databook
4.17
Table 24.
53830
Rev. 3.01 February 2014
Clock Interface
Clock Interface Pin Descriptions
Pin Name
Type
Voltage
Functional Description
25M_X1
I
3.3V
(VDDXL_33_S)
25 MHz crystal clock or external reference clock.
Clock source for FCH internal core PLLs.
25M_X2
O
3.3V
(VDDXL_33_S)
25 MHz crystal clock output.
32K_X1
I
VDDIO_33_S/
VDDBT_RTC_G
RTC crystal oscillator input 1 (internal RTC). Must be
active at all time.
32K_X2
O
VDDIO_33_S/
VDDBT_RTC_G
RTC crystal oscillator input 2 (internal RTC). Must be
active at all time.
14M_25M_48M_OS
C
O
VDDIO_33_S
14MHz / 24MHz / 25MHz / 48MHz /50MHz clock
output.
Note: This pin outputs a 14.318MHz clock on the first
power up if the internal system clock generator mode
strap is selected.
PCICLK0
O
3.3V
(5V tolerance)
33 MHz PCI clock 0
PCICLK1/GPO36
O
3.3V
(5V tolerance)
33 MHz PCI clock 1
PCICLK2/GPO37
O
3.3V
(5V tolerance)
33 MHz PCI clock 2
PCICLK3/GPO38
O
3.3V
(5V tolerance)
33 MHz PCI clock 3
PCICLK4/
14M_OSC/GPO39
O
3.3V
33 MHz PCI Clock 4 / 14.318 MHz clock output.
For external clock generator mode: 33 MHz PCI
clock output.
For internal clock generator mode: 14.318 MHz
clock output for internal clock generator mode.
The function is selected by the pin strap “CLKGEN”
(pin LPCCLK1). Refer to Table 32 on page 81.
CLKRUN#
I/O
3.3V
(5V tolerance)
Clock running is deasserted by the clock provider to
indicate the system is about to shut down the PCI or
LPC clock. When it is driven low by other agents, it
means the agent is requesting the clock provider not to
deactivate the clock.
USBCLK/
14M_25M_48M_OS
C
I/O
VDDIO_33_S
48 MHz clock input used for USB / 14.318 MHz or 25
MHz or 48 MHz output.
62
Pin Descriptions
Chapter 4
53830
AMD A77E Fusion Controller Hub Databook
Rev. 3.01 February 2014
Table 24.
Clock Interface Pin Descriptions (Continued)
Pin Name
Type
Voltage
Functional Description
APU_CLKP
O
VDDAN_11_
CLK
Positive phase of 100 MHz APU reference clock.
Spread capable.
APU_CLKN
O
VDDAN_11_
CLK
Negative phase of 100 MHz APU reference clock.
Spread capable.
GPP_CLK[8:0]P
O
VDDAN_11_
CLK
Positive phase of 100 MHz reference clock for PCIe
device(s). Spread capable.
GPP_CLK[8:0]N
O
VDDAN_11_
CLK
Negative phase of 100 MHz reference clock for PCIe
device(s). Spread capable.
PCIE_RCLKP
I
VDDAN_11_CLK
For external clock generator mode: Positive phase
of 100-MHz reference clock for the FCH. Spread
capable.
For internal clock generator mode: Not used. Left
unconnected.
The function is selected by the pin strap “CLKGEN”
(pin LPCCLK1). Refer to Table 32 on page 81.
PCIE_RCLKN
I
VDDAN_11_CLK
For external clock generator mode: Negative phase
of 100-MHz reference clock for the FCH. Spread
capable.
For internal clock generator mode: Not used. Left
unconnected.
The function is selected by the pin strap “CLKGEN”
(pin LPCCLK1). Refer to Table 32 on page 81.
DISP_CLKP
O
VDDAN_11_CLK
Positive phase of 100-MHz reference clock for APU’s
display engine. Not spread capable.
DISP_CLKN
O
VDDAN_11_CLK
Negative phase of 100-MHz reference clock for
APU’s display engine. Not spread capable.
DISP2_CLKP
O
VDDAN_11_CLK
Positive phase of 100-MHz LVDS translator reference
clock. Not spread capable.
DISP2_CLKN
O
VDDAN_11_CLK
Negative phase of 100-MHz LVDS translator
reference clock. Not spread capable.
SLT_GFX_CLKP
O
VDDAN_11_CLK
Positive phase of 100 MHz reference clock for
external discrete graphics device. Spread capable.
SLT_GFX_CLKN
O
VDDAN_11_CLK
Negative phase of 100 MHz reference clock for
external discrete graphics device. Spread capable.
CLK_REQ0#/
SATA_IS3#/GPIO60
I/O
VDDIO_33_PCIG
P
(5V tolerance)
PCIe® Clock Request 0
Chapter 4
Pin Descriptions
63
AMD A77E Fusion Controller Hub Databook
Table 24.
53830
Rev. 3.01 February 2014
Clock Interface Pin Descriptions (Continued)
Pin Name
Type
Voltage
CLK_REQ1#/
FANOUT4/GPIO61
I/O
VDDIO_33_PCIG
P
(5V tolerance)
PCIe Clock Request 1
CLK_REQ2#/
FANIN4/GPIO62
I/O
VDDIO_33_PCIG
P
(5V tolerance)
PCIe Clock Request 2
CLK_REQ3#/
SATA_IS1#/GPIO63
I/O
VDDIO_33_PCIG
P
(5V tolerance)
PCIe Clock Request 3
CLK_REQ4#/
SATA_IS0#/GPIO64
I/O
VDDIO_33_PCIG
P
(5V tolerance)
PCIe Clock Request 4
REQ3#/
CLK_REQ5#/
GPIO42
I
VDDIO_33_PCIG
P
(5V tolerance)
PCIe Clock Request 5
LDRQ1#/
CLK_REQ6#/
GPIO49
I/O
VDDIO_33_PCIG
P
(5V tolerance)
PCIe Clock Request 6
GNT3#/
CLK_REQ7#/
GPIO46
I/O
VDDIO_33_PCIG
P
(5V tolerance)
PCIe Clock Request 7
REQ2#/
CLK_REQ8#/
GPIO41
I
VDDIO_33_PCIG
P
(5V tolerance)
PCIe Clock Request 8
CLK_REQG#/
GPIO65/OSCIN/
IDLEEXIT#
I
VDDIO_33_PCIG
P
(5V tolerance)
Clock Request by PCIe Graphics / 14.318 MHz clock
input
For external clock generator mode: 14.318 MHz
OSC clock input pin.
For internal clock generator mode: Used as GPIO
or left unconnected.
VDDIO_33_S
32 kHz output for internal RTC.
VDDAN_11_CLK
Pad connection to an external resistor to
VDDAN_11_CLK on the motherboard, for
impedance calibration
RTCCLK
CLK_CALRN
64
I/O
I
Functional Description
Pin Descriptions
Chapter 4
53830
AMD A77E Fusion Controller Hub Databook
Rev. 3.01 February 2014
4.18
ATE/JTAG Interface
Table 25.
ATE/JTAG Interface Pin Descriptions
Pin Name
Type
Voltage
Functional Description
TEST0
I
VDDIO_33_S
ATE Test 0
TEST1/TMS
I
VDDIO_33_S
ATE Test 1/ JTAG TMS
TEST2
I
VDDIO_33_S
ATE Test 2
USB_OC0#/ GEVENT12#/TRST
I/O
VDDIO_33_S
JTAG Reset
USB_OC1#/TDI/GEVENT13#
I/O
VDDIO_33_S
JTAG Data In
USB_OC2#/TCK/GEVENT14#
I/O
VDDIO_33_S
JTAG Clock
USB_OC3#/AC_PRES/TDO/
GEVENT15#
I/O
VDDIO_33_S
JTAG Data Out
4.19
Table 26.
Integrated Micro-Controller (IMC) Interface
Integrated Micro-Controller Interface Pin Descriptions
Pin Name
Type
Voltage
Functional Description
EC_PWM0/
EC_TIMER0/
GPIO197
I/O
VDDIO_33_S
IMC PWM 0
EC_PWM1/
EC_TIMER1/
GPIO198
I/O
VDDIO_33_S
IMC PWM 1
EC_PWM2/
EC_TIMER2/
WOL_EN/
GPIO199
I/O
VDDIO_33_S
IMC PWM 2
EC_PWM3/
EC_TIMER3/
GPIO200
I/O
VDDIO_33_S
IMC PWM 3
Chapter 4
Pin Descriptions
65
AMD A77E Fusion Controller Hub Databook
4.20
53830
Rev. 3.01 February 2014
Consumer Infrared Interface
Table 27.
Consumer Infrared Interface Pin Description
Pin Name
Type
Voltage
Functional Description
USB_OC4#/IR_RX0/
GEVENT16#
I/O
VDDIO_33_S
Infrared Receive 0. Connection to wideband CIR
receiver.
IR_RX1/GEVENT20#
I/O
VDDIO_33_S
Infrared Receive 1. Connection to long-range CIR
receiver.
USB_OC5#/IR_TX0/
GEVENT17#
I/O
VDDIO_33_S
Infrared Transmit 0
USB_OC6#/IR_TX1/
GEVENT6#
I/O
VDDIO_33_S
Infrared Transmit 1
IR_LED#/LLB#/
GPIO184
I/O
VDDIO_33_S
Infrared LED
The following are the possible configurations for CIR
No CIR:
CIR not used
CIR RX with TX0:
One RX pin used with TX0
CIR RX with TX1:
One RX pin used with TX1
CIR RX with TX0 and TX1:
One RX pin used with TX0 and TX1
RX can be RX0 or RX1 except when using wideband CIR, in which case both RX pins need to be used.
66
Pin Descriptions
Chapter 4
53830
AMD A77E Fusion Controller Hub Databook
Rev. 3.01 February 2014
4.21
General Purpose I/O and General Event Pins
The GPIO and GEVENT pins of the FCH are multiplexed with other functions. For information on
how to configure the GPIO pins for the desired functions, see the AMD Bolton Fusion Controller Hub
Register Reference Guide.
Table 28 lists all the GPIO and GEVENT pins on the FCH. The Default I/O State column shows the
direction and the state of the pin after the core power has become stable (VDDCR > ~0.8V). The
integrated resistor column shows the default status of the internal integrated pull-up/pull-down
resistor on the pin after the PCI host bus reset (A_RST#) is deasserted. The integrated resistor can be
enabled/disabled by the system BIOS after boot up.
Table 28.
General Purpose I/O and General Event Pin Descriptions
Pin Name
Type
Level
Default
Muxed
Function
Default I/
O
State
Integrated
Resistor
Functional
Descriptions
General Events
GA20IN/
GEVENT0#
I
VDDIO_33_P null
CIGP
(5V tolerance)
Input, PU
8.2k PU
General Event 0
KBRST#/
GEVENT1#
I
VDDIO_33_P KBRST#
CIGP
(5V tolerance)
Input, PU
8.2k PU
General Event 1
Note: On G3 to S5
transition, the
BIOS will not be
able to program
this pin as
Gevent1#. If the
pin is used as
Gevent1#, the
design should
ensure that the pin
remains in logical
high during the G3
 S5  S0
transition. BIOS
can then program
this pin as
Gevent1# when it
is posting.
THRMTRIP#/
SMBALERT#/
GEVENT2#
I/O
VDDIO_33_S THRM
TRIP#
Input
10K PU
General Event 2
PME#/
GEVENT3#
I/O
VDDIO_33_S null
Input, PU
10K PU
General Event 3
Chapter 4
Pin Descriptions
67
AMD A77E Fusion Controller Hub Databook
Table 28.
53830
Rev. 3.01 February 2014
General Purpose I/O and General Event Pin Descriptions (Continued)
Pin Name
Type
Level
Default
Muxed
Function
Default I/
O
State
Integrated
Resistor
Functional
Descriptions
PCIE_RST2#/
GEVENT4#
I/O
VDDIO_33_S null
Input, PU
10k PU
General Event 4
LPC_PD#/
GEVENT5#
I/O
VDDIO_33_S GEVENT
5#
Input, PU
10k PU
General Event 5
USB_OC6#/
IR_TX1/
GEVENT6#
I/O
VDDIO_33_S null
Input, PU
10k PU
General Event 6
DDR3_RST#/
GEVENT7#/
VGA_PD
I/O
VDDIO_33_S DDR3_
RST#
Output
LOW
10k PU for
General Event 7
GEVENT,
OD for
DDR3_RST#,
push-pull and
no integrated
PU/PD for
VGA_PD
WAKE#/
GEVENT8#
I/O
VDDIO_33_S null
Input, PU
10k PU
General Event 8
SPI_HOLD#/
GBE_LED1/
GEVENT9#
I/O
VDDIO_33_S null
Input, PU
10k PU
General Event 9
GBE_LED2/
GEVENT10#
I/O
VDDIO_33_S null
Input, PU
10k PU
General Event 10
GBE_STAT0/
GEVENT11#
I/O
VDDIO_33_S null
Input, PU
10k PU
General Event 11
USB_OC0#/
GEVENT12#/
TRST
I/O
VDDIO_33_S GEVENT
12#
Input, PU* 10k PU*
USB_OC1#/
TDI/
GEVENT13#
I/O
VDDIO_33_S null
Input, PU* 10k PU*
68
General Event 12
Note: *Integrated PU is
not supported
when the pin is
configured for USB
over current
function.
General Event 13
Note: *Integrated PU is
not supported
when the pin is
configured for USB
over current
function.
Pin Descriptions
Chapter 4
53830
AMD A77E Fusion Controller Hub Databook
Rev. 3.01 February 2014
Table 28.
General Purpose I/O and General Event Pin Descriptions (Continued)
Pin Name
Type
Level
Default
Muxed
Function
Integrated
Resistor
Input, PU* 10k PU*
Functional
Descriptions
USB_OC2#/
TCK/
GEVENT14#
I/O
USB_OC3#/
AC_PRES/
TDO/
GEVENT15#
I/O
USB_OC4#/
IR_RX0/
GEVENT16#
I/O
USB_OC5#/
IR_TX0/
GEVENT17#
I/O
BLINK/
USB_OC7#/
GEVENT18#
I/O
SYS_RESET#/
GEVENT19#
I/O
VDDIO_33_S null
Input, PU
10k PU
General Event 19
IR_RX1/
GEVENT20#
I/O
VDDIO_33_S null
Input, PU
10k PU
General Event 20
SPI_CS3#/
GBE_STAT1/
GEVENT21#
I/O
VDDIO_33_S null
Input, PU
10k PU
General Event 21
Chapter 4
VDDIO_33_S null
Default I/
O
State
General Event 14
Note: *Integrated PU is
not supported
when the pin is
configured for USB
over current
function.
VDDIO_33_S null
Input, PU* 10k PU*
General Event 15
Note: *Integrated PU is
not supported
when the pin is
configured for USB
over current
function.
VDDIO_33_S null
Input, PU* 10k PU*
General Event 16
Note: *Integrated PU is
not supported
when the pin is
configured for USB
over current
function.
VDDIO_33_S null
Input, PU* 10k PU*
General Event 17
Note: * Integrated PU is
not supported
when the pin is
configured for USB
over current
function.
VDDIO_33_S null
Input, PU* 10k PU*
General Event 18
Note: *Integrated PU is
not supported
when the pin is
configured for USB
over current
function.
Pin Descriptions
69
AMD A77E Fusion Controller Hub Databook
Table 28.
53830
Rev. 3.01 February 2014
General Purpose I/O and General Event Pin Descriptions (Continued)
Pin Name
Type
Level
Default
Muxed
Function
Default I/
O
State
Integrated
Resistor
Functional
Descriptions
RI#/
GEVENT22#
I/O
VDDIO_33_S null
Input, PU
10k PU
General Event 22
LPC_SMI#/
GEVENT23#
I/O
VDDIO_33_S null
Input, PU
8.2k PU
General Event 23
S0-domain General Purpose I/O
AD[31:0]/
GPIO[31:0]
I/O
VDDIO_33_P PCI
CIGP
(5V tolerance)
Output
HIGH
-
GPIO [31:0]
INTE#/GPIO32
I/O
VDDIO_33_P PCI
CIGP
(5V tolerance)
Input, PU
8.2k PU
GPIO 32
INTF#/GPIO33
I/O
VDDIO_33_P PCI
CIGP
(5V tolerance)
Input, PU
8.2k PU
GPIO 33
INTG#/GPIO34
I/O
VDDIO_33_P PCI
CIGP
(5V tolerance)
Input, PU
8.2k PU
GPIO 34
INTH#/GPIO35
I/O
VDDIO_33_P PCI
CIGP
(5V tolerance)
Input, PU
8.2k PU
GPIO 35
PCICLK1/
GPO36
O
VDDIO_33_P PCICLK
CIGP
(5V tolerance)
Output
33MHz
-
GPO 36
PCICLK2/
GPO37
O
VDDIO_33_P PCICLK
CIGP
(5V tolerance)
Output
33MHz
-
GPO 37
PCICLK3/
GPO38
O
VDDIO_33_P PCICLK
CIGP
(5V tolerance)
Output
33MHz
-
GPO 38
PCICLK4/
14M_OSC/
GPO39
O
VDDIO_33_P PCICLK
CIGP
(5V tolerance)
Output
-
GPO 39
70
14MHz
(internal
CLKGEN)
or 33MHz
(external
CLKGEN)
Pin Descriptions
Chapter 4
53830
AMD A77E Fusion Controller Hub Databook
Rev. 3.01 February 2014
Table 28.
General Purpose I/O and General Event Pin Descriptions (Continued)
Default I/
O
State
Integrated
Resistor
Functional
Descriptions
Type
REQ1#/GPIO40
I
VDDIO_33_ PCI
PCIGP
(5V tolerance)
Input, PU
15k PU
GPIO 40
REQ2#/
CLK_REQ8#/
GPIO41
I
VDDIO_33_ PCI
PCIGP
(5V tolerance)
Input, PU
15k PU
GPIO 41
REQ3#/
CLK_REQ5#/
GPIO42
I
VDDIO_33_ PCI
PCIGP
(5V tolerance)
Input, PU
15k PU
GPIO 42
SCL0/GPIO43
I/O
VDDIO_33_ null
PCIGP
(5V tolerance)
Input, TriState
-
GPIO 43
GNT1#/GPO44
O
VDDIO_33_ PCI
PCIGP
(5V tolerance)
Output
HIGH
-
GPO 44
GNT2#/
SD_LED/
GPO45
O
VDDIO_33_ PCI
PCIGP
(5V tolerance)
Output
HIGH
-
GPO 45
GNT3#/
CLK_REQ7#/
GPIO46
I/O
VDDIO_33_ null
PCIGP
(5V tolerance)
Input, PU
8.2k PU
GPIO 46
SDA0/GPIO47
I/O
VDDIO_33_ null
PCIGP
(5V tolerance)
Input, TriState
-
GPIO 47
SERIRQ/
GPIO48
I/O
VDDIO_33_ null
PCIGP
(5V tolerance)
Input, PU
8.2k PU
GPIO 48
I
VDDIO_33_ null
PCIGP
(5V tolerance)
Input, PU
8.2k PU
GPIO 49
SMARTVOLT1/
SATA_IS2#/
GPIO50
I/O
VDDIO_33_ null
PCIGP
(5V tolerance)
Input, PU
8.2k PU
GPIO 50
SMARTVOLT2/
SHUTDOWN#/
GPIO51
I/O
VDDIO_33_ null
PCIGP
(5V tolerance)
Input, PU
8.2k PU
GPIO 51
LDRQ1#/
CLK_REQ6#/
GPIO49
Chapter 4
Level
Default
Muxed
Function
Pin Name
Pin Descriptions
71
AMD A77E Fusion Controller Hub Databook
Table 28.
53830
Rev. 3.01 February 2014
General Purpose I/O and General Event Pin Descriptions (Continued)
Pin Name
Type
Level
Default
Muxed
Function
Default I/
O
State
Integrated
Resistor
Functional
Descriptions
FANOUT0/
GPIO52
I/O
VDDIO_33_ null
PCIGP
(5V tolerance)
Input, PU
8.2k PU
GPIO 52
FANOUT1/
GPIO53
I/O
VDDIO_33_ null
PCIGP
(5V tolerance)
Input, PU
8.2k PU
GPIO 53
FANOUT2/
GPIO54
I/O
VDDIO_33_ null
PCIGP
(5V tolerance)
Input, PU
8.2k PU
GPIO 54
SATA_IS4#/
FANOUT3/
GPIO55
I/O
VDDIO_33_ null
PCIGP
(5V tolerance)
Input, PU
8.2k PU
GPIO 55
FANIN[2:0]/
GPIO[58:56]
I/O
VDDIO_33_ null
PCIGP
(5V tolerance)
Input, PU
8.2k PU
GPIO [58:56]
SATA_IS5#/
FANIN3/
GPIO59
I/O
VDDIO_33_ null
PCIGP
(5V tolerance)
Input, PU
8.2k PU
GPIO 59
CLK_REQ0#/
SATA_IS3#/
GPIO60
I/O
VDDIO_33_ null
PCIGP
(5V tolerance)
Input, PU
8.2k PU
GPIO60
CLK_REQ1#/
FANOUT4/
GPIO61
I/O
VDDIO_33_ null
PCIGP
(5V tolerance)
Input, PU
8.2k PU
GPIO 61
CLK_REQ2#/
FANIN4/
GPIO62
I/O
VDDIO_33_ null
PCIGP
(5V tolerance)
Input, PU
8.2k PU
GPIO 62
CLK_REQ3#/
SATA_IS1#/
GPIO63
I/O
VDDIO_33_ null
PCIGP
(5V tolerance)
Input, PU
8.2k PU
GPIO 63
CLK_REQ4#/
SATA_IS0#/
GPIO64
I/O
VDDIO_33_ null
PCIGP
(5V tolerance)
Input, PU
8.2k PU
GPIO 64
CLK_REQG#/
GPIO65/
OSCIN/
IDLEEXIT#
I
VDDIO_33_ null
PCIGP
(5V tolerance)
Input, PU
8.2k PU
GPIO 65
72
Pin Descriptions
Chapter 4
53830
AMD A77E Fusion Controller Hub Databook
Rev. 3.01 February 2014
Table 28.
General Purpose I/O and General Event Pin Descriptions (Continued)
Pin Name
Type
Level
Default
Muxed
Function
Default I/
O
State
Integrated
Resistor
Functional
Descriptions
SPKR/GPIO66
I/O
VDDIO_33_ null
PCIGP
(5V tolerance)
Input, TriState
-
GPIO 66
SATA_ACT#/
GPIO67
OD
VDDIO_33_ null
PCIGP
(5V tolerance)
Input, TriState
-
GPIO 67
VGA_HSYNC/
GPO68
O
VDDIO_33_
PCIGP
VGA_HS
YNC
Tri-State
during
reset then
output low
GPO 68
VGA_VSYNC/
GPO69
O
VDDIO_33_
PCIGP
VGA_VS
YNC
Tri-State
during
reset then
output low
GPO 69
VGA_DDC_SD
A/GPO70
I/O
VDDIO_33_ VGA_DD
PCIGP
C_SDA
(5V tolerance)
Tri-State
-
GPO70
VGA_DDC_SC
L/GPO71
O
VDDIO_33_ VGA_DD
PCIGP
C_SCL
(5V tolerance)
Tri-State
-
GPO 71
SD_CLK/
SCLK_0/
GPIO73
I/O
VDDIO_33_
PCIGP
null
Input, PU
8.2k PU
GPIO 73
SD_CMD/
SLOAD_0/
GPIO74
I/O
VDDIO_33_
PCIGP
null
Input, PU
8.2k PU
GPIO 74
SD_CD#/
GPIO75
I/O
VDDIO_33_
PCIGP
null
Input, PU
8.2k PU
GPIO 75
SD_WP/
GPIO76
I/O
VDDIO_33_
PCIGP
null
Input, PU
8.2k PU
GPIO 76
SD_DATA0/
SDATI_0/
GPIO77
I/O
VDDIO_33_
PCIGP
null
Input, PU
8.2k PU
GPIO 77
SD_DATA1/
SDATO_0/
GPIO78
I/O
VDDIO_33_
PCIGP
null
Input, PU
8.2k PU
GPIO 78
SD_DATA2/
GPIO79
I/O
VDDIO_33_
PCIGP
null
Input, PU
8.2k PU
GPIO 79
Chapter 4
Pin Descriptions
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AMD A77E Fusion Controller Hub Databook
Table 28.
53830
Rev. 3.01 February 2014
General Purpose I/O and General Event Pin Descriptions (Continued)
Pin Name
SD_DATA3/
GPIO80
Type
Level
I/O
VDDIO_33_
PCIGP
Default
Muxed
Function
Default I/
O
State
null
Input, PU
8.2k PU
GPIO 80
Output
LOW
-
GPIO 161
Integrated
Resistor
Functional
Descriptions
S5-Domain General Purpose I/O
ROM_RST#/
SPI_WP#/
GPIO161
I/O
VDDIO_33_S ROM_RS
T#
SPI_CLK/
GPIO162
I/O
VDDIO_33_S null or SPI Input, PD
(strap
dependent)
10k PD
GPIO 162
SPI_DO/
GPIO163
I/O
VDDIO_33_S null or SPI Input, PD
(strap
dependent)
10k PD
GPIO 163
SPI_DI/
GPIO164
I/O
VDDIO_33_S null or SPI Input, PD
(strap
dependent)
10k PD
GPIO 164
SPI_CS1#/
GPIO165
I/O
VDDIO_33_S null or SPI Input, PU
(strap
dependent)
10k PU
GPIO 165
SPI_CS2#/
GBE_STAT2/
GPIO166
I/O
VDDIO_33_S null or SPI Input, PU
(strap
dependent)
10k PU
GPIO 166
AZ_SDIN[3:0]/
GPIO[170:167]
I/O
VDDIO_33_S AZ
/1.5V_S5
Input, PD
50k PD
GPIO [17:167]
TEMPIN[2:0]/
GPIO[173:171]
I/O
VDDIO_33_S null
Input
-
GPIO [173:171]
TEMPIN3/
TALERT#/
GPIO174
I/O
VDDIO_33_S null
Input
-
GPIO 174
VIN[5:0]/
GPIO[180:175]
I/O
VDDIO_33_S null
Input
10k PU/PD
(disabled by
default)
GPIO [180:175]
74
Pin Descriptions
Chapter 4
53830
AMD A77E Fusion Controller Hub Databook
Rev. 3.01 February 2014
Table 28.
General Purpose I/O and General Event Pin Descriptions (Continued)
Pin Name
Type
Level
Default
Muxed
Function
Default I/
O
State
Integrated
Resistor
Functional
Descriptions
VIN6/
GBE_STAT3/
GPIO181
I/O
VDDIO_33_S null
Input
-
GPIO 181
VIN7/
GBE_LED3/
GPIO182
I/O
VDDIO_33_S null
Input
-
GPIO 182
GBE_LED0/
GPIO183
I/O
VDDIO_33_S null
Input
10k PU
GPIO 183
IR_LED#/
LLB#/GPIO184
I/O
VDDIO_33_S null
Input, PU
10k PU
GPIO 184
USB_FSD0P/
GPIO185
I/O
VDDIO_33_S USB
Input, PD
15k PD
GPIO 185
USB_FSD1P/
GPIO186
I/O
VDDIO_33_S USB
Input, PD
15k PD
GPIO 186
PS2_DAT/
SDA4/GPIO187
I/O
VDDIO_33_S null
(5V tolerance)
Input, PU
10k PU
GPIO 187
PS2_CLK/
SCL4/GPIO188
I/O
VDDIO_33_S null
(5V tolerance)
Input, PU
10k PU
GPIO 188
PS2KB_DAT/
GPIO189
I/O
VDDIO_33_S null
(5V tolerance)
Input, PU
10k PU
GPIO 189
PS2KB_CLK/
GPIO190
I/O
VDDIO_33_S null
(5V tolerance)
Input, PU
10k PU
GPIO 190
PS2M_DAT/
GPIO191
I/O
VDDIO_33_S null
(5V tolerance)
Input, PU
10k PU
GPIO 191
PS2M_CLK/
GPIO192
I/O
VDDIO_33_S null
(5V tolerance)
Input, PU
10k PU
GPIO 192
SCL2/GPIO193
I/O
VDDIO_33_S null
(5V tolerance)
Input, TriState
-
GPIO 193
SDA2/GPIO194
I/O
VDDIO_33_S null
(5V tolerance)
Input, TriState
-
GPIO 194
SCL3_LV/
GPIO195
I/O
0.8V
null
threshold,
VDDIO_33_S
domain
Input, TriState
-
GPIO 195
Chapter 4
Pin Descriptions
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AMD A77E Fusion Controller Hub Databook
Table 28.
53830
Rev. 3.01 February 2014
General Purpose I/O and General Event Pin Descriptions (Continued)
Pin Name
Type
Level
Default
Muxed
Function
Default I/
O
State
Integrated
Resistor
Functional
Descriptions
SDA3_LV/
GPIO196
I/O
0.8V
null
threshold,
VDDIO_33_S
domain
Input, TriState
-
GPIO 196
EC_PWM0/
EC_TIMER0/
GPIO197
I/O
VDDIO_33_S null
Input, PU
10k PU
GPIO 197
EC_PWM1/
EC_TIMER1/
GPIO198
I/O
VDDIO_33_S null
Input, PU
10k PU
GPIO 198
EC_PWM2/
EC_TIMER2/
GPIO199
I/O
VDDIO_33_S null
(5V tolerance)
Input, PU
10k PU
GPIO 199
EC_PWM3/
EC_TIMER3/
GPIO200
I/O
VDDIO_33_S null
(5V tolerance)
Input, PU
10k PU
GPIO 200
KSI_[7:0]/
GPIO[208:201]
I/O
VDDIO_33_S null
Input, PU
10k PU
GPIO [208:201]
KSO_[13:0]/
GPIO[222:209]
I/O
VDDIO_33_S null
Input, PU
10k PU
GPIO [222:209]
KSO_14/XDB0/
GPIO223
I/O
VDDIO_33_S null
Input, PU
10k PU
GPIO 223
KSO_15/XDB1/
GPIO224
I/O
VDDIO_33_S null
Input, PU
10k PU
GPIO 224
KSO_16/XDB2/
GPIO225
I/O
VDDIO_33_S null
Input, PU
10k PU
GPIO 225
KSO_17/XDB3/
GPIO226
I/O
VDDIO_33_S null
Input, PU
10k PU
GPIO 226
SCL1/GPIO227
I/O
VDDIO_33_S null
(5V tolerance)
Input, TriState
-
GPIO 227
SDA1/GPIO228
I/O
VDDIO_33_S null
(5V tolerance)
Input, TriState
-
GPIO 228
ML_VGA_HPD
/GPIO229
I/O
VDDIO_33_S HPD
Output
high
-
GPIO 229
76
Pin Descriptions
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AMD A77E Fusion Controller Hub Databook
Rev. 3.01 February 2014
4.22
Power and Ground Pins
For more information on the power domain, grouping, and power-up sequencing for the power rails,
please refer to Section 5.2 “Power Rail Power-up/down Sequence” on page 90.
Table 29.
Power and Ground Pin Descriptions
Signal Name
Voltage
GND
/GND Reference
Note
Description
VDDCR_11_[9:1]
1.1V
VSS
-
Core power
VDDCR_11_S_[2:1]
1.1V
VSS
-
S5 core power
VDDIO_33_S_[8:1]
3.3V
VSS
-
S5 IO power
VDDIO_33_PCIGP[10:1]
3.3V
VSS
-
IO power
VDDIO_AZ_S
1.5V/
3.3V
VSS
-
HD Audio Interface IO power
VDDXL_33_S
3.3V
VSSXL
1
25MHz XTAL IO power
VDDPL_33_SYS
3.3V
VSSPLL_
SYS
2
System clock generator PLLs analog
power
VDDPL_11_SYS_S
1.1V
VSSPL_
SYS
2
System clock generator PLLs analog
power
VDDAN_11_CLK_[8:1]
1.1V
VSS
2
System clock generator analog/output
power
VDDAN_11_ML_[4:1]
1.1V
VSS
-
VGA translator input 1.1V analog power
VDDPL_33_ML
3.3V
VSSPL_
SYS
-
VGA translator input 3.3V analog power
VDDPL_33_PCIE
3.3V
VSS
2
SCL /PCI Express PLL power
VDDAN_11_PCIE_[8:1]
1.1V
VSS
2
SCL / PCI Express analog power
VDDPL_33_SATA
3.3V
VSS
2
SATA PHY PLL power
VDDAN_11_SATA_[10:1]
1.1V
VSS
2
SATA PHY analog/IO power
Chapter 4
Pin Descriptions
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AMD A77E Fusion Controller Hub Databook
Table 29.
53830
Rev. 3.01 February 2014
Power and Ground Pin Descriptions (Continued)
Signal Name
VDDBT_RTC_G
Voltage
GND
/GND Reference
2.5 –
3.6V
BAT
VSS
Note
-
Description
RTC/CMOS backup power. Must be
present at all time.
Notes:
1. If the VBAT voltage falls below 1.65V, the
CMOS CLR status bit will be set.
2. To force CMOS clear status bit to be set
and still maintain the contents of the
CMOS the voltage cannot be lowered past
1.55V.
3. If the foltage falls below 1.3V, then all of
the contents of the RAM and Real Time
Clock is invalid.
4. If the contents of CMOS are not required
to be maintained, then the VBAT input of
the SOC can be grounded momentarily
after the rest of the SOC power rail (S5
and S0) are turned off.
VDDPL_33_USB_S
3.3V
VSS
2, 3, 4 USB PHY PLL analog power
VDDAN_33_USB_S_[12:1]
3.3V
VSS
2, 3, 4 USB PHY analog/IO power
VDDAN_11_USB_S_[2:1]
1.1V
VSS
2, 3, 5 USB PHY DLL analog power
VDDCR_11_USB_S_[2:1]
1.1V
VSS
VDDPL_33_SSUSB_S
3.3V
VSS
2, 3, 4 PLL power for super speed USB
VDDAN_11_SSUSB_S_[5:1]
1.1V
VSS
2, 3, 5 Super speed USB analog power
VDDCR_11_SSUSB_S_[4:1]
1.1V
VSS
3, 5
VDDAN_33_HWM_S
3.3V
VSSAN_H
WM
-
Hardware monitor interface analog/IO
power
VDDAN_33_DAC
3.3V
VSSPL_
DAC
-
DAC 3.3V analog power
VDDPL_33_DAC
3.3V
VSSPL_
DAC
-
DAC 3.3V PLL power
VDDPL_11_DAC
1.1V
VSSPL_
DAC
-
DAC 1.1V PLL power
LDO_CAP
1.8V
VSSPL_
DAC
-
Internally generated 1.8V supply for the
RGB outputs
VSS
GND
-
-
Digital ground (plane)
VSSXL
GND
-
-
25MHz XTAL ground
VSSPL_SYS
GND
-
-
System clock generator PLLs common
ground
78
3, 5
Pin Descriptions
USB PHY core power
Super speed USB core power
Chapter 4
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AMD A77E Fusion Controller Hub Databook
Rev. 3.01 February 2014
Table 29.
Power and Ground Pin Descriptions (Continued)
Signal Name
Voltage
GND
/GND Reference
Note
Description
VSSAN_HWM
GND
-
-
Hardware monitor interface analog ground
VSSIO_DAC
GND
-
-
DAC IO ground
VSSAN_DAC
GND
-
-
DAC analog ground
VSSANQ_DAC
GND
-
-
DAC analog bias ground
VSSPL_DAC
GND
-
-
DAC PLL ground
Notes:
1.
These power rails can be tied to S0-S5 or S0-S3, depending on whether WakeOnLan, USB 3.0
Wakemode is supported. See Table 37.
2. These power rails should be filtered.
3. These power rails can be tied to S0-S5 or S0-S3 power depending on whether wake from S4/S5 is supported or not.
4. VDDPL_33_USB_S and VDDAN_33_USB_S_[12:1]
should be sourced from the same voltage regulator and
have traces routed close together to minimize voltage droop difference.
5. VDDAN_11_USB_S_[2:1] and VDDCR_11_USB_S_[2:1] should be sourced from the same voltage regulator
and have traces routed close together to minimize voltage drop difference.
4.23
Miscellaneous Pins
Table 30.
Miscellaneous Pin Descriptions
Pin Name
NC[x]
Functional Description
No Connect
Note: GbE is not supported. The greyed out pins below are not used and must be connected or not connected as
described.
GBE_COL
No Connect
GBE_CRS
No Connect
GBE_MDCK
No Connect
GBE_MDIO
No Connect
GBE_RXCLK
No Connect
GBE_RXD[3:0]
No Connect
GBE_RXCTL/RXDV
No Connect
GBE_RXERR
No Connect
GBE_TXCLK
No Connect
GBE_TXD[3:0]
No Connect
Chapter 4
Pin Descriptions
79
AMD A77E Fusion Controller Hub Databook
Table 30.
53830
Rev. 3.01 February 2014
Miscellaneous Pin Descriptions (Continued)
GBE_TXCTL/TXEN
No Connect
GBE_PHY_PD
No Connect
GBE_PHY_RST#
No Connect
GBE_PHY_INTR
Not used. Terminate as per the AMD Bolton Fusion Controller
Hub Motherboard Design Guide, order# 51206
VDDIO_GBE_S[2:1]
Not used. Terminate as per the AMD Bolton Fusion Controller
Hub Motherboard Design Guide, order# 51206
VDDIO_33_GBE_S
Not used. Terminate as per the AMD Bolton Fusion Controller
Hub Motherboard Design Guide, order# 51206
VDDCR_11_GBE_S[2:1]
Not used. Terminate as per the AMD Bolton Fusion Controller
Hub Motherboard Design Guide, order# 51206
4.24
Integrated Resistors
Table 31 shows the pins that have an integrated resistor on their pad and the resistor’s nature (pull-up
or pull-down) and value. In general, the integrated resistors are enabled by default, but can be
changed by programming. The table does NOT include information for any GPIO or GEVENT pins,
for which one should refer to Table 28 in Section 4.21 “General Purpose I/O and General Event Pins”
on page 67.
Table 31.
Pins with Integrated Resistors (Excluding GPIO/GEVENT Pins)
Interface
LPC
RTC
80
Pin
Resistor Type/Requirement
LAD[3:0]
10k pull up
LDRQ0#
10k pull up
CLKRUN#
7.5k pull up
DEVSEL#
7.5k pull up
FRAME#
7.5k pull up
IRDY#
7.5k pull up
LOCK#
7.5k pull up
PERR#
7.5k pull up
REQ[3:0]#
15k pull up
SERR#
7.5k pull up
STOP#
7.5k pull up
TRDY#
7.5k pull up
RTCCLK
10k pull up
RSMRST#
10k pull up (cannot be disabled)
Pin Descriptions
Chapter 4
53830
AMD A77E Fusion Controller Hub Databook
Rev. 3.01 February 2014
4.25
Strap Information
Two types of straps are captured on the rising edge of RSMRST# and PWR_GOOD—Type I and
Type II. Type I straps become valid immediately after capture on the rising edge of RSMRST#.
Modules in the S5 power well use this type of straps, which are captured only once when power is
first applied to the chip. All other straps (type II) become valid after PWR_GOOD is asserted in order
to prevent the strap logic that resides in the standby power well from being driven by un-powered
logic. Type II straps are captured every time the system powers up from the S5 state. A transition
from S3 to S0 does not trigger capture.
Straps I
Capture
S5_1.1V
RSMRST#
Don't care
Straps (board)
Straps I
Straps II
VDD
Straps II
Capture
PWRGOOD
Undefined
Straps Type I
Straps Type I
Straps Type II
Straps Type II
Ts
T Parameter
Ts Setup Time for capture
Th Hold Time for capture
Min
0
Max
1310.5
Th
Unit
ns
ns
Figure 13. Straps Capture Timing
Straps are also classified into two groups—standard and debug. Standard straps are required for
selecting different chip options at power-up. Debug straps are used for debugging purposes only and
do not require population for production boards. However, provisions for connecting pull-ups or pulldowns on the debug strap signals should be made if they are not used for normal system operation.
Table 32 and Table 33 show the function of every strap signal in the design. All straps are defined
such that in the most likely scenario of operation, they will be set to the recommended (or safest)
values by default. The values shown in the Description column are the external board strap values,
with 3.3V being a pull up and 0V a pull down.
Chapter 4
Pin Descriptions
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AMD A77E Fusion Controller Hub Databook
Table 32.
Ball Name*
53830
Rev. 3.01 February 2014
Standard Straps
Strap Name
Type
Default
Value
Description
LPCCLK0
ECEnableStrap
I
-
Enable Integrated Micro-Controller
0V – Disable
3.3V – Enable
This strap has to be enabled to support enhanced
hardware monitor features.
EC_PWM2
{ROMTYPE_0 }
I
-
ROMTYPE_0ROM Type
0VSPI ROM
3.3VLPC ROM
RTCCLK
S5 Plus Mode
I
-
Set S5 Plus Mode
0V – Enable
3.3V – Disable
LPCCLK1
CLKGEN
II
-
Defines clock generator.
0V – External clock mode: Use 100 MHz PCIe®
clock as reference clock and generate internal clocks
only.
3.3V – Integrated clock mode: Use 25MHz crystal
clock and generate both internal and external clocks.
PCICLK1
BIF_GEN2_COM
PLIANCE_Strap
II
-
Set PCIe to Gen II mode.
0V – Force PCIe interface at Gen I mode.
3.3V – PCIe interfacce is at Gen II mode.
PCICLK3
DefaultStrapMode
II
-
Default Debug Straps
0V – Disable Debug Straps.
3.3V – Select external Debug Straps (see Table 33).
PCICLK4
CPUClkSel
II
-
APU_CLKP/N and DISP_CLKP/N Clock Selection
0V – Required setting for integrated clock mode.
3.3V – Reserved.
This strap is not used if the strap CLKGEN is
configured for external clock generator mode.
Note: * For clarity’s sake, ball names for strap pins given in this table are truncated to show only the beginning parts. Refer to
the pins lists in Appendix A for the complete ball names.
82
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Table 33.
Ball Name
Debug Straps
Strap Name
Type
Default
Value
Description
AD27
PciPllByp
II
3.3V
(Internal
PU of
15kΩ)
Bypass PCI PLL (used in functional test at tester)
0V– Bypass internal PLL clock.
Use xSPciReqB_1_ as SPCI33 bypass clock.
Use xSPciReqB_2_as A-Link bypass clock.
Use
xSPciGntB_1_as B-Link bypass clock.
Use
xSPciGntB_0_ as B-Link266 bypass clock.
3.3V – Use internal PLL-generated PLL CLK.
AD24
I2CRomEn
II
3.3V
(Internal
PU of
15kΩ)
I2C ROM enable. Load the settings for SCL/PLL/
misc control from I2C ROM.
0V – Getting the value from I2C EPROM.
I2C EPROM ADDRESS set to all zeroes.
Use
REQ3# as SDA.
Use GNT3# as SCL.
3.3V – Disable I2C ROM
AD23
PCI_ROM_
BOOT
II
3.3V
(Internal
PU of
15kΩ)
Booting from PCI memory
0V – Route ROM fetch to PCI bus on the very
first boot. Use ROMTYPE to determine the ROM
type on subsequent boots.
3.3V – Use ROMTYPE straps to determine the
ROM type.
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Pin Descriptions
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Pin Descriptions
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Chapter 4
53830
AMD A77E Fusion Controller Hub Databook
Rev. 3.01 February 2014
Chapter 5
Power Sequence and Timing
This chapter describes the power-on sequences and other timing data for the Bolton-E4 FCH.
5.1
Power-up/down Sequence
Figure 14 on page 85 and Figure 15 on page 86 illustrate respectively the power-up/down sequences
for ACPI S5-to- S0 -to- S5 and S3-to- S0-to-S3 transitions.
Table 34, Table 35, and Table 36 give the timing values.
G3
S5
S0
S5
G3
Wake Event
PWR_BTN#
WAKE#
T13
SLP_S5#/
SLP_S3#
VBAT
VBAT
RTC clock In
(See Note 12)
T2
+3.3V_S5
1.1V_S5
T1
T2B
(See Note 1)
RSMRST#
(See Note 13) T2A
S5 STRAPS
T3
RTCCLK out
PS PWOK
(See Note 9)
S0 power rails
System clocks
(See Note 1)
T13A
T11
(See Note 2)
FCH PWR_GOOD
T8B
T7A
(See Note 2)
T4
T7B
T7
APU_PG
(See Note 6)
S0 STRAPS
T9A
A_RST#
(See Note 5)
KBRST#
PCIRST#
T8A (See Note 4)
T9
T8C
APU_RST#
Figure 14. FCH Power Sequence (S5-to-S0-to-S5)
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S3
S0
S3
Rev. 3.01 February 2014
Wake Event
PWR_BTN#
WAKE#
T13
SLP_S3#
SLP_S5#
GND
VBAT
VBAT
RTC clock
GND
+3.3V_S5
GND
+1.2V_S5
GND
RSMRST#
GND
PS PWOK
(See Note 9)
S0 power rails
System clocks
T11
(See Note 2)
(See Note 1)
T13A
(See Note 2)
T7A
FCH PWR_GOOD
T7B
T7
(See Note 5)
APU_PG
T8B
T9A
A_RST#
KBRST#
T8A (See Note 4)
T9
PCIRST#
T8C
APU_RST#
Figure 15. FCH Power Sequence (S3 to S0 to S3)
Table 34.
Symbol
T1
T2
T2B
86
Power Sequence Timing
Minimum
Maximum
Note 1 of Section 5.1.1
10 ms
–
Description
+3.3V_S5 to +1.1V_S5
+3.3V_S5 to resume reset (RSMRST#)
+1.1V_S5 should ramp up to nominal voltage before resume reset
(RSMRST#) is de-asserted.
(See Description)
T2A
–
50 ms
Resume reset (RSMRST#) rise time (10% to 90%). See Note 11 of
Section 5.1.1.
T3
16 ms
–
RSMRST# de-asserted to start of RTCCLK output from the FCH.
Power Sequence and Timing
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Table 34.
Power Sequence Timing (Continued)
Symbol
T7
T7A
Minimum
Maximum
–
50 ms
T7B
T8A
1 ms
100 ns
T8B
–
0 ns
Note 4 of
Section 5.1.1
–
T8C
T9
T9A
T13
1.0 ms
101 ms
101 ms
–
Note 5 of
Section 5.1.1
2.3 ms
113 ms
113 ms
15 ns
T13A
80 ns
16 ms
–
T14
1 ns
–
T15
5s
–
T16A
T16B
40 µs
4 µs
–
–
Table 35.
Symbol
T7
T11B
Chapter 5
Description
See Table 35 and Table 36 on page 88 .
FCH PWR_GOOD rise time (10% to 90 %). See Note 3 of Section
5.1.1 “Power up Sequence Timing Notes” on page 88.
FCH PWR_GOOD fall time.
A_RST# (PCI host bus reset) to PCIRST#.
KBRST# to FCH PWR_GOOD.
PCIRST# to APU_RST#.
FCH PWR_GOOD to PCIRST#.
FCH PWR_GOOD to A_RST# (T9-T8A).
Wake Event (except PwrButton) to SLP_S3# / SLP_S5# deassertion.
See Note 14 of Section 5.1.1 “Power up Sequence Timing Notes”
on page 88.
Wake Event (PwrButton) to SLP_S3# / SLP_S5# de-assertion.
FCH PWR_GOOD must be de-asserted before VDD (PS PWOK)
drops more than 5% off the nominal value. See Note 9 of Section
5.1.1 “Power up Sequence Timing Notes” on page 88.
FCH PWR_GOOD de-assertion to Resume Reset (RSMRST#)
assertion. See Note 10 of Section 5.1.1 “Power up Sequence Timing
Notes” on page 88.
[Not illustrated] VBAT to +3.3V_S5 to +1.1V_S5. Must be greater
than 5 seconds to allow start time for the internal RTC.
[Not illustrated] APU_STP# assertion to APU_RST# assertion.
[Not illustrated] APU_RST# assertion to SLP_S3# assertion.
FCH PWR_GOOD and System Clock Timing (Internal Clock Mode Only)
Minimum
98 ms
–
Maximum
150 ms
39 ms
Description
FCH PWR_GOOD assertion to APU_PG assertion delay.
[Not illustrated] FCH PWR_GOOD to clock out stable.
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Table 36.
Rev. 3.01 February 2014
FCH PWR_GOOD and System Clock Timing (External Clock Mode Only)
Symbol
T7
Min.
77 ms
Max.
108 ms
T11
–
Note 2 of
Section
5.1.1
5.1.1
53830
Description
FCH PWR_GOOD assertion to APU_PWRGD assertion delay when
using the FCH APU_PG output.
[Not illustrated] Stable system clocks (25MHz, SRC (PCIe), OSC,
48MHz) to FCH PWR_GOOD when using external clock generator.
Power up Sequence Timing Notes
Notes:
1. Refer to Section 5.2 “Power Rail Power-up/down Sequence” on page 90 for the power rail
power-up/down requirements.
2. All system clocks should be stable before the assertion of FCH PWR_GOOD. Refer to the
external clock specification for the timing TSTAB, the time it takes for the external clock chip
to provide stable clocks after valid power is applied.. If the FCH and the external clock chip
share power rails, this parameter needs to be taken into account when considering the FCH
PWR_GOOD assertion timing. Typical value for TSTAB is 1.8 ms. All system clocks should be
stopped after SLP_S3# is asserted when transitioning to sleep states; clock generator
power-down sequencing should be adjusted accordingly to meet this requirement.
3. The FCH will latch the straps after rising edge of FCH PWR_GOOD only once. With debouncing of FCH PWR_GOOD, the latching of strap will occur at approximately ~10ms
after the rising edge of FCH PWR_GOOD.
4. Typical time between A_RST# and PCIRST# is 75 ns. The measurement should be
performed at 10% of both signals. Loading on the motherboard may cause the measurement
at 90% to be more than the specified value.
5. The KBRST# should be de-asserted before FCH PWR_GOOD is de-asserted.
6. Type II Standard and Debug straps will be latched after FCH PWR_GOOD is asserted.
Type I straps are latched on resume reset rising edge.
7. FCH PWR_GOOD Assertion: The FCH PWR_GOOD should be asserted after all S0 power
rails have ramped up to 90% of their nominal value. FCH PWR_GOOD de-assertion: The
FCH will monitor internally the power down events and protect the internal circuit during
the power down event. This includes power down during the S3, S4, and S5 states. During
an unexpected power failure or G3 state, the relationship between the +1.1 V (VDDCR) and
FCH PWR_GOOD should be maintained to protect the internal logic of the FCH.
8. The following figure shows the timing of FCH PWR_GOOD de-asserted to RSMRST# deasserted during a power down sequence. However, this timing only applies to S0-to-G3 state
transition, because G3 state is where both signals are inactivated.
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FCH PWR_GOOD
RSMRST#
T14
S0 to G3
Figure 16. Timing for FCH PWR_GOOD De-asserted to RSMRST# De-asserted
9. When measuring the RSMRST# timing T2A, the loading of the motherboard PCB trace may
cause a slow rise time, which should be taken in account. See Figure 17 below.
3.3V_S5
RSMRST#
T2A
Figure 17.
Measurement for RSMRST# Timing (T2A)
10. The ramp down rate of the 3.3V_S5 rail should not be faster than (-) 8 mV/µS. See Figure 18
on page 90 .
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Ramp down rate should not be
faster than (-) 8 mV/µS
Figure 18.
3.3V_S5 Power-down Sequence Requirement
11. VBAT powers the RTC clock input to the FCH. The RTC clock must be functional before deassertion of RSMRST#; therefore, the VBAT power ramp up time relative to RSMRST# may
need to be controlled. Typical start time is 5 seconds, but the value varies with different
crystals.
12. The maximum time represents the time FCH's internal logic will take to start driving
SLP_S3# / SLP_S5#. The net delay time may be dominated by onboard loading which can
be far greater than the silicon intrinsic delay.
5.2
Power Rail Power-up/down Sequence
The Bolton-E4 FCH power rails can be broadly divided into the following two groups:
•
+ 3.3V and +1.1 V voltage rails that are ON in S0 to S5 states. Rails in this group have the suffix
“_S” at the end of their names.
•
+3.3V and +1.1V voltage rails that are ON in S0 state but turned OFF in S3 to S5 states. Rails in
this group do not have the suffix “_S” at the end of their names.
Table 37 shows how the FCH voltage rails are divided into these two groups. Some of the “_S”
domain voltage rails can be connected to “non-_S” domain voltage rails depending on the feature set
supported, as explained in the “Note” column.
Table 37.
FCH Voltage Rail Grouping
Voltage Rail
VDDIO_33_S
VDDAN_33_USB_S
VDDAN_33_HWM_S
VDDPL_33_USB_S
90
+3.3/1.1V_S5
x
x
x
x
+3.3/1.1V_S0
Note
-.
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Table 37.
FCH Voltage Rail Grouping
Voltage Rail
+3.3/1.1V_S5
+3.3/1.1V_S0
Note
VDDPL_33_SSUSB_S
x
x
VDDPL_33_SSUSB_S should be tied to
+3.3V_S5 rail if USB 3.0 Wake is supported;
otherwise, it can be tied to +3.3V_S0 rail. If
USB 3.0 is not used at all, it can be tied to
GND.
VDDXL_33_S
x
x
VDDXL_33_S should be tied to +3.3V_S5 rail
if USB 3.0 Wake is supported; otherwise, it can
be tied to +3.3V_S0 rail.
VDDIO_33_PCIGP
x
-
VDDPL_33_SYS
x
-
VDDPL_33_PCIE
x
-
VDDPL_33_SATA
x
-
VDDPL_33_DAC
x
VDDPL_33_ML
x
VDDAN_33_DAC
x
VDDPL_33_DAC, VDDPL_33_ML,
VDDAN_33_DAC should be tied to +3.3V_S0
rail if the VGA translator function is supported.
If the VGA translator is not used at all, these
power rails can be tied to GND.
VDDCR_11_S
x
-
VDDCR_11_USB_S
x
-
VDDPL_11_SYS_S
x
x
VDDPL_11_SYS_S should be tied to
+1.1V_S5 rail if USB 3.0 Wake is supported;
otherwise, it can be tied to +1.1V_S0 rail.
VDDCR_11_SSUSB_S
x
x
VDDCR_11_SSUSB_S should be tied to
+1.1V_S5 rail if USB 3.0 Wake is supported;
otherwise, it can be tied to +1.1V_S0 rail. If
USB 3.0 is not used at all, it can be tied to
GND.
VDDCR_11
x
-
VDDAN_11_SATA
x
-
VDDAN_11_PCIE
x
-
VDDAN_11_CLK
x
-
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Table 37.
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FCH Voltage Rail Grouping
Voltage Rail
+3.3/1.1V_S5
VDDAN_11_ML
VDDAN_11_SSUSB_S
x
VDDPL_11_DAC
VDDIO_AZ_S
x
+3.3/1.1V_S0
Note
x
Tie to GND if VGA interface is not enabled.
x
VDDAN_11_SSUSB_S should be tied to
+1.1V_S5 rail if USB 3.0 Wake is supported;
otherwise, it can be tied to +1.1V_S0 rail. If
USB 3.0 is not used at all, it can be tied to
GND.
x
Tie to GND if VGA interface is not enabled.
x
Though the rail’s voltage is 3.3V/1.5V, it
follows the same power-rail power-up/down
requirements for the 3.3V/1.1V rails as
described in this section. It is thus classified
here as belonging to either the 3.3V/1.1V_S5
or the 3.3V/1.1V_S0 rail group with respect to
the power-up/down requirements, according to
the following conditions:
Wake on Ring supported: Tie to +3.3/
1.5V_S5 rail, and treat like a 3.3/1.1V_S5 rail.
Wake on Ring not supported: Tie to +3.3/
1.5V_S0 rail, and treat like a 3.3/1.1V S0 rail.
Within each of the +3.3 /1.1 V_S5 or +3.3 /1.1 V_S0 power rail groups, rails of the same voltage (3.3
V or 1.1 V) should be powered up at the same time. However, there are no required sequencing
relationships between the 3.3-V rails and the 1.1-V rails.
Although there are no power rail sequencing requirements between any specific power rail groups
(except for VBAT—see explanations below), customers can use the power rail power-up sequence
shown in Figure 19 and Table 38 below as a reference. All of the AMD Bolton-E4 reference
platforms are designed to follow that reference power-up sequence.
For power-down sequence, power rails on reference platforms should either be powered-down at the
same time or in the reverse order of the power-up sequence shown below.
The only mandatory requirement for power rail sequencing is that VBAT (VDDBT_RTC_G) must
ramp at least 5 seconds before the S5 rails to allow start time for the external RTC crystal.
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VDDBT_RTC_G
VBAT
+3.3V_S5
T1
VDDIO_33_S, VDDAN_33_USB_S, VDDAN_33_HWM_S, VDDPL_33_USB_S, VDDXL_33_S,
VDDPL_33_SSUSB_S
T2
VDDCR_11_S, VDDCR_11_USB_S, VDDPL_11_SYS_S, VDDCR_11_USB_S,
VDDCR_11_SSUSB_S, VDDAN_11_SSUSB_S
+1.1V_S5
VDDIO_33_PCIGP, VDDPL_33_SYS, VDDPL_33_PCIE, VDDPL_33_SATA,
VDDPL_33_DAC, VDDPL_33_ML, VDDAN_33_DAC
+3.3V_S0
T3
VDDCR_11, VDDAN_11_SATA, VDDAN_11_PCIE,
VDDAN_11_CLK, VDDAN_11_ML, VDDPL_11_DAC
+1.1V_S0
Figure 19. Power Rail Power-up Sequence Requirements
Table 38.
Power Rail Power-up Sequence Requirements
Voltage Difference during Ramping
Symbol
Parameter
T1
VBAT to the S5 rails
T2
+3.3V_S5 rails ramp high
relative to +1.1V_S5 rails
Minimum (V)
Maximum (V)
VDDBT_RTC_G must ramp at
least 5 seconds before the S5 rails.
No restrictions
0
No restrictions*
T3
+3.3V_S0 rails ramp high
0
No restrictions*
relative to +1.1V_S0 rails
*Note: Power rails from the same group are assumed to be generated from the same regulator;
however, they can be generated from different regulators as long as they come up at the same time.
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5.3
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Reset Timings
The FCH controls the system reset signal timings, which are provided in this section. ROMRST#
timing is shown with respect to RSMRST# and A_RST# signals in Figure 20 (a) and (b). ROM_RST
can be generated on the system board using either the RSMRST# or A_RST# signal depending on the
platform configurations, and Table 40 on page 95, indicates the timing figure and label that apply in
each situation.
Table 39.
ROM Reset Timing Figure for Various Platform Configurations
IMC Enabled
ROM Reset Timing Figure
Y
Figure 20 (a)
N
Figure 20 (b)
RSMRST#
A_RST#
ROMRST#
ROMRST#
Tr1
Tr1A
(a)
Figure 20.
(b)
ROM Reset Timing
Figure 21 on page 95 shows the timing of APU_RST#, APU_PG, A_RST#, and PCI_RST# with
respect to the SYS_RST# signal when SYS_RST# is used to force a system reset. SYS_RST# and
RSMRST# signals are input to the FCH and are generated on the system board.
Table 40 on page 95 shows the values of all the timing labels.
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SYS_RST#
APU_RST#
APU_PG
Tr2
Tr3
A_RST#
PCI_RST#
Tr5
Tr4
Figure 21. Reset Timing Requirements
Table 40.
Symbol
Reset Timing Requirements
Min
Typical
Max
48 ms
-
58 ms
A_RST# to ROMRST#
(ROMRST# is generated from A_RST#)
-
-
100 ns
SYS_RESET# assertion to APU_RST# assertion
-
8 ms
-
SYS_RESET# assertion to APU_PG de-assertion
-
8 ms
-
Tr3
SYS_RESET# de-assertion to A-RST# de-assertion
-
230 ms
-
Tr4
SYS_RESET# assertion to A_RST# assertion
-
8.05 ms
-
SYS_RESET# assertion to PCI_RST# assertion
-
8.1 ms
-
SYS_RESET# de-assertion to PCI_RST# de-assertion
-
231 ms
Tr1
Tr1A
Tr2
Tr5
Chapter 5
Parameter
RSMRST# to ROMRST#
(ROMRST# is generated from RSMRST#.)
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KBRST# Timing Requirements
KBRST# rise and fall time requirements are shown in Figure 22 .
tfall
trise
KBRST#
trise = 500ns max (10 - 90 %)
tfall = 500ns max (10 - 90 %)
Figure 22.
96
Timing Requirements for KBRST#
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5.4
Power Button Timing
Figure 23 illustrates various timing values related to the assertion and de-assertion of the power
button.
3.3V_S5 / 1.1V_S5
10 ms min
RSMRST#
10 ms min
PWR_BTN#
16 ms min ( See Note )
200 ns min
SLP_S3# / SLP_S5#
Note: The 16 ms includes requirement for 15 ms
of de-bounce timing . De-bounce logic is internal
to the FCH .
Figure 23. Power Button Timing
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Chapter 6
Electrical Characteristics
Note: Values quoted in this section are preliminary and require further verification.
6.1
Power Rail Specifications
6.1.1
Absolute Ratings
To prevent damage to the ASIC, the voltage applied to each power rail should not exceed 10% of its
nominal voltage, nor should it fall below -0.5V with respect to VSS.
6.1.2
Operating Range
For proper operation of the ASIC, voltages of all power rails should stay within +/- 5% of their
nominal values. Voltages, measured at the ball of the ASIC, must stay within the range of tolerance in
spite of any DC transients or AC noises of frequencies less than 2 MHz.
6.2
DC Characteristics
Table 41.
Symbol
DC Characteristics of the GPIO Pins
Parameter
Minimum
Maximum
Unit
3.0
3.46
V
Condition
VDDQ
I/O power
VIL
Input Low Voltage
-
1.5
V
VIH
Input High Voltage
1.5
-
V
VOL
Output Low Voltage
-
0.4
V
IOL = 8.0 mA (Note 1)
VOH
Output High Voltage
2.4
-
V
IOH = 8.0 mA (Note 1, 2)
ILI
Input Leakage Current
-
10
µA
Only applicable when the
integrated resistors are not
enabled.
CIN
Input Capacitance
-
10
pF
Only applicable when the
integrated resistors are not
enabled.
Notes:
1. For the GEVENT9# and GEVENT10# pads, the IOL and IOH are programmable to values
between 4 and 8 mA.
2. VOH specifications are not applicable to I/OD or OD signals.
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Table 42.
Symbol
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DC Characteristics of the PCI Interface
Parameter
Minimum
Maximum
Unit
3.0
3.46
V
Condition
VDDQ
I/O power
VIL
Input Low Threshold
-
0.3VDD
V
VIH
Input High Threshold
0.3VDD
-
V
VOL
Output Low Voltage
-
0.4
V
IOL = 4.0 mA to 12 .0 mA
VOH*
Output High Voltage
2.4
-
V
IOH = -4.0 mA to 12 mA
ILI
Input Leakage Current
-
10
µA
Only applicable when the
integrated resistors are not
enabled.
CIN
Input Capacitance
-
10
pF
Only applicable when the
integrated resistors are not
enabled.
Note: *VOH specifications are not applicable to I/OD or OD signals.
Table 43.
Symbol
DC Characteristics of the APU Interface
Parameter
Minimum
Maximum
Unit
Condition
-
-
V
OD signal
-
0.4
V
IOL = 8.0 mA
V
OD signal
V
IOL = 8.0 mA
DMA_ACTIVE#
VCPU_IO CPU IO Voltage
VOL
Output Low Voltage
APU_PG, APU_RST#
VDDQ
VOL
Table 44.
Symbol
I/O power
-
Output Low Voltage
0.4
DC Characteristics of RSMRST#
Parameter
Minimum
Maximum
Unit
3.3V_S5
Core standby power
3.0
3.46
V
VIL
Input Low Voltage
-
1.5
V
VIH
Input High Voltage
1.5
-
V
ILI
Input Leakage Current
-
10
µA
CIN
Input Capacitance
-
10
pf
100
Electrical Characteristics
Condition
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Table 45.
Symbol
DC Characteristics of PWR_GOOD
Parameter
Minimum
Maximum
Unit
3.0
3.46
V
VDDQ
I/O power
VIL
Input Low Voltage
-
1.5
V
VIH
Input High Voltage
1.5
-
V
ILI
Input Leakage Current
-
10
µA
CIN
Input Capacitance
-
10
pf
Table 46.
Symbol
Condition
DC Characteristics of the LPC Interface
Parameter
Minimum
Maximum
Unit
3.0
3.46
V
Condition
VDDQ
I/O power
VIL
Input Low Threshold
-
0.3VDD
V
VIH
Input High Threshold
0.3VDD
-
V
VOL
Output Low Voltage
-
0.4
V
IOL = 4.0 mA to 12 .0 mA
VOH
Output High Voltage
2.4
-
V
IOH = -4.0 mA to 12 mA
µA
Only applicable when the
integrated resistors are not
enabled. Not applicable to
LDRQ[1:0]#.
pF
Only applicable when the
integrated resistors are not
enabled. Not applicable to
LDRQ[1:0]#.
ILI
Input Leakage Current
-
-
10
CIN
Input Capacitance
10
6.3
RTC Battery Current Consumption
The RTC battery current consumption is estimated as follows:
Table 47.
RTC Battery Current Consumption (Preliminary Estimates)
Power State
G3 (Off)
S0-S5
Chapter 6
RTC Battery Current
Typical
Maximum
< 3 µA
< 4.5 µA
< 0.2 µA
-
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The RTC battery life is calculated using the rated capacity of the battery and the typical current
numbers. The typical batteries used for the RTC are normally rated for 170 mAh, and the worst case
current consumption for the FCH is 4.5 µA, according to Table 47 on page 101. Thus, the minimum
life of the battery can be calculated as follows:
170,000 µAh / 4.5 µA = 38,000 h ≅ 4.3 years
6.4
States of Power Rails during ACPI S3 to S5 States
Please refer to Section 5.2 “Power Rail Power-up/down Sequence” on page 90.
6.5
System Clock Specifications
6.5.1
System Clock Descriptions
Table 48.
System Clock Input Source Descriptions
Clock Domain
Frequency
25M_X1, 25M_X2
25 MHz
25-MHz Crystal
Master reference clock for the FCH
for internal clock mode
PCIE_RCLKP,
PCIE_RCLKN
100 MHz
Main clock generator
Reference clock for the FCH for
external clock mode.
SATA_X1,
SATA_X2
25 MHz
25-MHz Crystal
For SATA Controllers
32K_X1, 32K_X2
32 KHz
32-KHz Crystal
For RTC
USBCLK
48 MHz
48-MHz OSC or internal USB
48-MHz PLL
For USB Controllers and HD
Audio
6.5.2
Table 49.
102
Source
Usage
System Clock Input Frequency Specifications
System Clock Input Frequency Specifications
Clock
Frequency
25M_X1, 25M_X2
25.000 MHz ± 50 ppm
USBCLK
48.000 MHz ± 100 ppm
SATA_X1, SATA_X2
25.000 MHz ± 50 ppm
Electrical Characteristics
Chapter 6
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AMD A77E Fusion Controller Hub Databook
Rev. 3.01 February 2014
6.5.3
AC Specifications
6.5.3.1
System Clock Output AC Specifications
GPP_CLKP/N, SLT_GFX_CLKP/N, and DISP2_CLKP/N: These clocks are compliant with the
PCI Express® Specification 2.0. Please refer to the PCI Express CEM 2.0 Specification for the clocks’
AC and DC specifications for the clocks.
Table 50.
DISP_CLKP/N AC Specifications: (Non-Spread Clock)
100 MHz Input
Symbol
Parameter
Unit
Minimum Maximum
VIH
VIL
VCROSS
TPERIOD AVG
TCCJITTER
Tdc
Rising Edge Rate
Falling Edge Rate
Table 51.
Differential Input High Voltage
Differential Input Low Voltage
Absolute crossing point voltage
Average Clock Period Accuracy
Cycle to Cycle Jitter
Reference Duty Cycle
Rising Edge Rate
Falling Edge Rate
+150
+250
–300
40
0.6
–4.0
–150
+550
+300
150
60
4.0
–0.6
mV
mV
mV
ppm
ps
%
V/ns
V/ns
APU_CLKP/N AC Specifications
200/100 MHz Output
Symbol
Parameter
Unit
Minimum Maximum
VOH
VOL
VCROSS
Differential Output High Voltage
Differential Output Low Voltage
Absolute crossing point voltage
Variation of VCROSS over all
VCROSS DELTA
rising clock edges
TPERIOD AVG
Average Clock Period Accuracy
Rising Edge Rate Rising Edge Rate
Falling Edge Rate Falling Edge Rate
Cycle to Cycle jitter
TCCJITTER
Duty Cycle
Duty Cycle
Chapter 6
+150
+250
–150
+550
mV
mV
mV
-
+140
mV
–300
0.6
–4.0
40
+300
4.0
–0.6
150
60
ppm
V/ns
V/ns
ps
%
Electrical Characteristics
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AMD A77E Fusion Controller Hub Databook
Table 52.
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Rev. 3.01 February 2014
14MHz/25MHz/48MHz Auxiliary Clock AC Specifications
Value
Symbol
14M
24M
25M
48M
50M
VOL
Parameter
14 MHz Clock
Frequency
24 MHz Clock
Frequency
25 MHz Clock
Frequency
48 MHz Clock
Frequency
50 MHz Clock
Frequency
Output low
voltage
Unit
Note
14.8920
MHz
-
24
TBA
MHz
24.875
25
25.125
MHz
-
47.55
48
48.47
MHz
-
TBA
50
TBA
MHz
-
-
-
0.4
V
IOL=4.0 mA when
highdrive = 0
IOL = 8.0 mA when
highdrive = 1
Minimum
Typical
Maximum
14.2146
14.31818
TBA
VOH
Output high
voltage
2.4
-
-
V
Rising
Slew Rate
Falling
Slew Rate
Tdc
Rising Slew Rate
1.0
-
4.0
V/ns
IOH = -4.0 mA when
highdrive = 0
IOH = 8.0 mA when
highdrive = 1
50pf load
Falling Slew Rate
1.0
-
4.0
V/ns
50pf load
Duty Cycle
40
60
%
Note: In integrated clock mode this pin will output 14.318 MHz clock. The output frequency varies
from cycle to cycle, with an average frequency of 14.318MHz. This clock is available for
customers to use on the system board if it meets the requirements of target device. AMD has
not validated this clock on any specific applications. Since this clock is averaged at 14.318
MHz, AMD does not recommend this clock to be used for devices that use an Internal PLL.
The output will generate 12 MHz on power up until after the FCH PWR_GOOD is asserted.
After the FCH PWR_GOOD assertion, the clock output will be 14MHz. After power up, this
pin can be configured to output a 24-MHz, 25-MHz, 48-MHz, or 50-MHz clock.
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Electrical Characteristics
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Table 53.
PCI Clock AC Specifications
Value
Symbol
Parameter
Unit
Minimum
Tperiod
Clock period
VOL
Note
Typical Maximum
30
-
33.3
MHz
Output low voltage
-
-
0.4
V
IOL = 4.0 mA
VOH
Output high voltage
2.4
-
-
V
IOH = –4.0 mA
Rising Slew Rate
Rising Slew Rate
1.0
-
4.0
V/ns
50pf load
Falling Slew Rate
Falling Slew Rate
1.0
-
4.0
V/ns
50pf load
6.5.3.2
AC Specification of External Reference Clock for 25M_X1
Note: The specification below applies at the input of the 25M_X1 pad only, it does not apply to the
output of the external clock chip.
Table 54.
AC Specification of External Reference Clock for 25M_X1
Symbol
VIH
Vin Max
Parameter
Input High Level
Minimum
Typical
Maximum
Unit
Notes
2.97
--
--
V
1
--
3.3
V
2
Maximum Voltage IN
VIL
Input Low Voltage
0
--
0.33
V
TIP
25MHZ Clock Period
--
40
--
ns
FTOL
Frequency Tolerance
–25
--
25
ppm
DC
Duty Cycle
45
50
55
%
TIR
25MHz Slew Rate (Rise)
1
--
--
V/ns
4, 5
TIF
25MHz Slew Rate (Fall)
1
--
--
V/ns
4, 5
Short Term Peak-to-Peak Jitter
--
--
200
ps
3
25MHz Long Term Jitter Requirement
(10 µs after scope trigger)
--
--
250
ps
TSHORT
TIJLT
Chapter 6
Electrical Characteristics
3
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AMD A77E Fusion Controller Hub Databook
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Rev. 3.01 February 2014
Table 54. AC Specification of External Reference Clock for 25M_X1
Notes:
1. Minimum voltage required to guarantee a High level detection.
2. 25M_X1 input should not exceed Vin Max during normal operation.
3. Time intervals measured at 50% threshold point.
4. Rise Time and Fall Time measurements should be measured at 10%-90% thresholds.
5. For acceptable duty-cycle performance, TIR and TIF should be kept to within 10% of each
other.
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6.5.3.3
SPI AC Specifications
Figure 24 and Figure 25 show the timing requirements for the SPI ROM controller setup.
CS/
SCK
tV
DO
LSB
MSB
Figure 24. SPI Output Timing Diagram
CS/
SCK
DI
tDS tDH
LSB
MSB
Figure 25. SPI Iutput Timing Diagram
Table 55.
SPI Timing Parameters
Symbol
Parameter
tV
Output valid time
tDS
Data in setup
5.5
ns
tDH
Data in hold
0
ns
tV (quad mode)
Output valid time
tDS (quad mode)
Data in setup
6
ns
tDH (quad mode)
Data in hold
0
ns
Chapter 6
Min
Max
Unit
Note
4
ns
@ output load of 10 pf and timing measured
from the falling edge of the clock
6
ns
Timing measured from the falling edge of the
clock
@ output load of 10 pf and timing measured
from thefalling edge of the clock
Timing measured from the falling edge of the
clock
Electrical Characteristics
107
AMD A77E Fusion Controller Hub Databook
Table 56.
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Rev. 3.01 February 2014
SPI Serial Clock Timing (Supported frequencies: 16.5, 22, 33 and 66 MHz)
Minimum
Typical
Maximum
Clock Frequency for READ instructions (fR)
16.34 MHz
16.50 MHz
16.67 MHz
Clock High Time (tCLH)
26.1 ns
30.3 ns
34.5 ns
Clock Low Time (tCLL)
26.1 ns
30.3 ns
34.5 ns
Clock Rise Time (tCLCH)
0.10 V/ns
Clock Fall Time (tCHCL)
0.10 V/ns
Minimum
Typical
Maximum
Clock Frequency for READ instructions (fR)
21.78 MHz
22.00 MHz
22.22 MHz
Clock High Time (tCLH)
12.9 ns
15.0 ns
17.1 ns
Clock Low Time (tCLL)
25.8 ns
30.0 ns
34.2 ns
Clock Rise Time (tCLCH)
0.10 V/ns
Clock Fall Time (tCHCL)
0.10 V/ns
Minimum
Typical
Maximum
Clock Frequency for READ instructions (fR)
32.67 MHz
33.00 MHz
33.33 MHz
Clock High Time (tCLH)
13.0 ns
15.2 ns
17.3 ns
Clock Low Time (tCLL)
13.0 ns
15.2 ns
17.3 ns
Clock Rise Time (tCLCH)
0.10 V/ns
Clock Fall Time (tCHCL)
0.10 V/ns
Min
Typical
Max
Clock Frequency for READ instructions (fR)
65.34 MHz
66.00 MHz
66.66 MHz
Clock High Time (tCLH)
6.5 ns
7.6 ns
8.6 ns
Clock Low Time (tCLL)
6.5 ns
7.6 ns
8.6 ns
Clock Rise Time (tCLCH)
0.10 V/ns
Clock Fall Time (tCHCL)
0.10 V/ns
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Chapter 6
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AMD A77E Fusion Controller Hub Databook
Rev. 3.01 February 2014
Chapter 7
7.1
Package Information
Physical Dimensions
Figure 26. Bolton-E4 24.5 mm x 24.5 mm 0.8 mm Pitch 656-FCBGA Package Outline
Table 57.
Bolton-E4 24.5 mm x 24.5 mm 0.8 mm Pitch 656-FCBGA Physical Dimensions
Reference
Minimum (mm)
Nominal (mm)
Maximum (mm)
c
0.56
0.66
0.76
A
1.77
1.92
2.07
A1
0.30
0.40
0.50
A2
0.81
0.86
0.91
φb
0.40
0.50
0.60
D1
24.35
24.50
24.65
Chapter 7
Package Information
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AMD A77E Fusion Controller Hub Databook
Table 57.
53830
Rev. 3.01 February 2014
Bolton-E4 24.5 mm x 24.5 mm 0.8 mm Pitch 656-FCBGA Physical Dimensions
Reference
Minimum (mm)
Nominal (mm)
Maximum (mm)
D2
-
6.84
-
D3
2.00
-
-
D4
1.00
-
-
E1
24.35
24.50
24.65
E2
-
7.20
-
E3
2.00
-
-
E4
1.00
-
-
F1
-
23.10
-
F2
-
23.10
-
e (min. pitch)
-
0.80
-
ddd
-
-
0.20
7.2
Pressure Specification
To avoid damages to the ASIC (die or solder ball joint cracks) caused by improper mechanical
assembly of the cooling device, follow the recommendations below:
• It is recommended that the maximum load that is evenly applied across the contact area between
the thermal management device and the die do not exceed 6 lbf. Note that a total load of 4-6 lbf is
adequate to secure the thermal management device and achieve the lowest thermal contact
resistance with a temperature drop across the thermal interface material of no more than 3°C.
Also, the surface flatness of the metal spreader should be 0.001 inch/1 inch or better.
•
Pre-test the assembly fixture with a strain gauge to make sure that the flexing of the final
assembled board and the pressure applied around the ASIC package will not exceed 600 microstrains under any circumstances.
•
Ensure that any distortion (bow or twist) of the board after SMT and cooling device assembly is
within industry guidelines (IPC/EIA J-STD-001). For measurement method, refer to the industry
approved technique described in the manual IPC-TM-650, section 2.4.22.
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Package Information
Chapter 7
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7.3
Thermal Information
This section describes some key thermal parameters of Bolton-E4. For a detailed discussion on these
parameters and other thermal design descriptions including package level thermal data and analysis,
please consult the Thermal Design and Analysis Guidelines for the Bolton Fusion Controller Hub,
order# 51209.
Table 58.
Bolton-E4 Thermal Limits
Parameter
Minimum
Nominal
Maximum
Unit
Note
Operating Case
Temperature
0
—
105
°C
1
Absolute Rated Junction
Temperature
—
—
125
°C
2
Storage Temperature
–40
—
60
°C
Ambient Temperature
0
—
45
°C
3
Thermal Design Power
—
See Table 59
—
W
4
Notes:
1. The maximum operating case temperature is the die geometric top-center temperature
measured through proper thermal contact to the back side of the die based on the
methodology given in the document Thermal Design and Analysis Guidelines for the
Bolton Fusion Controller Hub, order# 51209(Chapter 1). This is the temperature at
which the functionality of the chip is qualified.
2. The maximum absolute rated junction temperature is the junction temperature at which
the device can operate without causing damage to the ASIC.
3. The ambient temperature is defined as the temperature of the local intake air to the
thermal management device. The maximum ambient temperature is dependent on the
heat sink's local ambient conditions as well as the chassis' external ambient, and the
value given here is based on the AMD reference Desktop heat sink solution for the FCH.
Refer to Chapter 5 in the Thermal Design and Analysis Guidelines for the Bolton Fusion
Controller Hub, order# 51209, for heat sink and thermal design guidelines. Refer to
Chapter 6 of the above mentioned document for details of ambient conditions.
4. Thermal Design Power (TDP) is defined as the highest power dissipated while running
currently available worst case applications at nominal voltages. The core voltage was
raised to 5% above its nominal value for measuring the ASIC power. Since the core
power of modern ASICs using 65nm and smaller process technology can vary
significantly, parts specifically screened for higher core power were used for TDP
measurement. The TDP is intended only as a design reference, and the value given here
is preliminary.
Chapter 7
Package Information
111
AMD A77E Fusion Controller Hub Databook
Table 59.
53830
Rev. 3.01 February 2014
Bolton-E4 TDP Values and Configurations
Bolton-E4
Clock Gen
Y
SATA
8 x 6Gb/s
RAID
not supported
FIS-Based Switching
Y
HD Audio
Y
x1 PCIe GPP
4 Gen 2
Unified Media Interface
X4 Gen 2
USB 3.0 + 2.0 + 1.1 Ports
4 + 10 +2
APU Fan Control
Y
Consumer IR
Y
SD Controller
Y
VGA DAC
Y
TDP (105 °C)
112
7.8W
Package Information
Chapter 7
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AMD A77E Fusion Controller Hub Databook
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7.4
Reflow Profile
A reference reflow profile is given below. Please note the following when using RoHS/lead-free
solder (SAC105/305/405 Tin-Silver-Cu):
•
The final reflow temperature profile will depend on the type of solder paste and chemistry of flux
used in the SMT process. Modifications to the reference reflow profile may be required in order to
accommodate the requirements of the other components in the application.
•
An oven with 10 heating zones or above is recommended.
•
To ensure that the reflow profile meets the target specification on both sides of the board, a
different profile and oven recipe for the first and second reflow may be required.
•
Mechanical stiffening can be used to minimize board warpage during reflow.
•
It is suggested to decrease temperature cooling rate to minimize board warpage.
•
This reflow profile applies only to RoHS/lead-free (high temperature) soldering process and it
should not be used for eutectic solder packages. Damage may result if this condition is violated.
•
Maximum 3 reflows are allowed on the same part.
Table 60.
Recommended Board Solder Reflow Profile - RoHS/Lead-Free Solder
Profiling Stage
Overall Preheat
Soaking Time
Liquidus
Ramp Rate
Peak
Temperature at peak
within 5°C
Chapter 7
Temperature
Room temp to 220°C
130°C to 170°C
220°C
Ramp up and Cooling
Max. 245°C
Process Range
2 mins to 4 mins
Typical 60 – 80 seconds
Typical 60 – 80 seconds
<2°C / second
235°C ±5 °C
240°C to 245°C
10 – 30 seconds
Package Information
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Figure 27. RoHS/Lead-Free Solder (SAC305/405 Tin-Silver-Copper) Reflow Profile
114
Package Information
Chapter 7
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AMD A77E Fusion Controller Hub Databook
Rev. 3.01 February 2014
Chapter 8
Testability
8.1
XOR Chain Test Mode
8.1.1
Test Control Signals
Table 61 shows the signals used for the integrated test controller of Bolton-E4.
Table 61.
Signals for the Test Controller of Bolton-E4
Signal Name
Description
25M_X1, 25M_X2
25-MHz Reference Clock
TEST0
Test0 input
TEST1
Test1 input
TEST2
Test2 input
Table 62 shows how Test[2:0] are used to select the normal operation, ASIC debug, or test mode.
Table 62.
Test Mode Signals
TEST2
TEST1
TEST0
Test Mode
Description
0
0
0
None
Normal operation
0
0
1
Reserved
Reserved for ASIC debug
0
1
X
Test Mode
EnableTest Mode
1
X
X
Reserved
Reserved for ASIC debug
When TEST2 is low, a low on TEST1 will reset all test logic and allow TEST0 to choose between
normal operation and the reserved debug mode. A high on TEST1 should be followed by a bit
sequence on TEST0 to define the test mode into which Bolton-E4 will enter. A new test mode can be
entered when a new bit sequence is transmitted. In addition to resetting the test controller
asynchronously with TEST1, a bit sequence can also be used to synchronously change the test mode.
Table 63 on page 116 shows the legal bit sequences for TEST0.
Note: Once the Test mode or Test mode and sub test mode is entered, Test2 and Test1 should be kept at
0 and 1 respectively until the requirement for the Test Mode is completed.
Chapter 8
Testability
115
AMD A77E Fusion Controller Hub Databook
Table 63.
53830
Rev. 3.01 February 2014
TEST0 Bit Sequence
TEST0 bit sequence
Test Mode
11111
Look for first 0 to define a new test mode
00000
Reserved
00001
Alt Pull High Test
00010
Pull Outputs High
00011
Pull Outputs Low
00100
Pull Outputs to Z
00101
XOR Test Mode
Figure 28 illustrates the data timing for the test signals with respect to the OSC clock. Any timing
reference referred in this section is assumed to be based on OSC clock running at 25 MHz. The OSC
clock can be slowed down to 1 MHz as long as the bit stream applied on TEST0 pin is also in sync
with this clock. The 25-MHz OSC clock should be disconnected first. For setting any Test 0 bit
sequence, the OSC clock is required only up-to the time the mode set is completed. After this the
clock can be stopped and as long as TEST1 and Test2 pins are set to {1, 0} respectively to maintain
the selected mode to be active. Note that once TEST1 is set to one, TEST0 needs to be asserted to one
for at least 8 clocks before transmitting the test mode bit sequence. The rising of “Internal Test Mode”
in the diagram indicates the time when Huhdson-2 enters into test mode.
Osc
TEST1
TEST0
( TEST0 = 1 ) >
8 Osc clocks
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Internal Test Mode
Figure 28. Test Mode Capturing Sequence Timing
8.1.2
Brief Description of an XOR Chain
A sample of a generic XOR chain is shown in the figure below.
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AMD A77E Fusion Controller Hub Databook
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XOR Start Signal
G
F
A
E
D
C
B
Figure 29.
A Generic XOR Chain
Pin A is assigned to the output direction, and pins B through F are assigned to the input direction.
After all pins from B to F are assigned to logic 0 or 1, a logic change in any one of these pins will
toggle the output pin A.
Table 64 is the truth table for the XOR tree shown in Figure 29. The XOR start signal is assumed to
be logic 1. The start signal is an internal signal to the ASIC and is not part of the XOR tree pins listed
in Table 64.
Once the inputs are set to their respective values, the output pin will reflect the correct value within
200ns. Note: OSC clock is not required to be running after the mode is set and the pads are exercised
in XOR tree function.
Table 64.
Truth Table for an XOR Chain
Test Vector
Number
Input Pin
G
Input Pin
F
Input Pin
E
Input Pin
D
Input Pin
C
1
0
0
0
0
0
0
1
2
1
0
0
0
0
0
0
3
1
1
0
0
0
0
1
4
1
1
1
0
0
0
0
5
1
1
1
1
0
0
1
6
1
1
1
1
1
0
0
7
1
1
1
1
1
1
1
Chapter 8
Testability
Input Pin Output Pin
B
A
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8.2
53830
Rev. 3.01 February 2014
Description of the Bolton-E4 XOR Chain
During XOR chain test mode, most of the chip pads on Bolton-E4 are connected together using XOR
gates as shown in Figure 30. The first input of the chain is connected to a logic level high (internal
connection), and all pads (listed in Table 65) are configured as inputs except for the last pad in the
chain, which is configured as an output. Table 65 lists all pads that are on the Bolton-E4 XOR chain,
as well as and their order of connection. Pads are chained together in the shown order, i.e., pad
number 1 is the first pad on the XOR chain, pad number 2 the second, and so on.
1
( Tie high Internal to Asic)
XOR out
FANOUT0/ GPIO3
pin 1
AD6/ROMA12
pin 2
pin 3
pin N
Frame#
Figure 30.
On-chip XOR Chain Connectivity
Table 65.
Connection Order of Bolton-E4
XOR Chain Pins
XOR# Ball Ref
Pin Name
XOR# Ball Ref
Pin Name
15
B25
LPCCLK0
16
F24
KSI_3/GPIO204
17
E24
KSI_4/GPIO205
18
C24
KSI_6/GPIO207
19
A24
KSO_16/XDB2/GPIO225
20
D23
PS2M_DAT/GPIO191
21
B23
KSI_5/GPIO206
22
K22
KSI_1/GPIO202
23
J22
EC_PWM2/EC_TIMER2/
WOL_EN/GPIO199
24
H22
EC_PWM1/EC_TIMER1/
GPIO198
1
A31
LFRAME#
2
C29
ML_VGA_HPD/GPIO229
3
A29
LAD3
4
E28
PROCHOT#
5
C28
LAD1
6
D27
LAD0
7
B27
LDRQ0#
8
G26
LDT_STP#
9
F26
LDT_RST#
10
E26
LDT_PG
25
G22
SCL3_LV/GPIO195
11
C26
LPC_SMI#/GEVENT23#
26
F22
KSI_2/GPIO203
12
A26
LAD2
27
E22
13
G25
DMA_ACTIVE#
EC_PWM0/EC_TIMER0/
GPIO197
14
D25
LPCCLK1
28
C22
PS2M_CLK/GPIO192
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Testability
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AMD A77E Fusion Controller Hub Databook
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XOR# Ball Ref
Pin Name
29
A22
KSO_3/GPIO212
30
K21
KSI_0/GPIO201
31
J21
SPI_CS2#/GBE_STAT2/
GPIO166
XOR# Ball Ref
Pin Name
60
F5
USB_OC3#/AC_PRES/TDO/
GEVENT15#
61
K1
WAKE#/GEVENT8#
62
J2
IR_LED#/LLB#/GPIO184
32
H21
EC_PWM3/EC_TIMER3/
GPIO200
63
M5
VIN7/GBE_LED3/
GPIO182
33
G21
SDA3_LV/GPIO196
64
P3
VIN5/SCLK_1/GPIO180
34
F21
KSO_0/GPIO209
65
M1
VIN6/GBE_STAT3/GPIO181
35
D21
PS2KB_DAT/GPIO189
66
P1
VIN4/SLOAD_1/GPIO179
36
B21
KSO_9/GPIO218
67
K6
TEMPIN0/GPIO171
37
F20
KSO_2/GPIO211
68
K5
TEMPIN1/GPIO172
38
E20
KSO_1/GPIO210
69
K3
TEMPIN2/GPIO173
39
C20
PS2KB_CLK/GPIO190
70
M6
40
A20
KSO_5/GPIO214
TEMPIN3/TALERT#/
GPIO174
41
K19
PS2_DAT/SDA4/GPIO187
71
J7
USB_OC1#/TDI/GEVENT13#
42
J19
PS2_CLK/SCL4/GPIO188
72
L2
VIN2/SDATI_1/GPIO177
43
H19
SCL2/GPIO193
73
N2
VIN0/GPIO175
44
G19
SDA2/GPIO194
74
M3
VIN1/GPIO176
45
D19
KSO_11/GPIO220
75
N4
VIN3/SDATO_1/GPIO178
46
B19
KSO_14/XDB0/GPIO223
76
M7
47
K18
BLINK/USB_OC7#/
GEVENT18#
KSO_10/GPIO219
77
P5
48
J18
KSO_6/GPIO215
USB_OC2#/TCK/
GEVENT14#
49
H18
KSO_7/GPIO216
78
P6
50
G18
KSO_8/GPIO217
USB_OC4#/IR_RX0/
GEVENT16#
51
F18
KSI_7/GPIO208
79
R2
RI#/GEVENT22#
52
E18
KSO_4/GPIO213
80
R7
SDA1/GPIO228
53
C18
KSO_13/GPIO222
81
R8
54
A18
KSO_12/GPIO221
USB_OC6#/IR_TX1/
GEVENT6#
55
B17
KSO_15/XDB1/GPIO224
82
R9
PME#/GEVENT3#
56
D17
KSO_17/XDB3/GPIO226
83
R10
THRMTRIP#/SMBALERT#/
GEVENT2#
57
H5
USB_FSD0N
84
T1
58
H3
USB_FSD1N
USB_OC5#/IR_TX0/
GEVENT17#
59
J4
PWR_BTN#
85
T5
LPC_PD#/GEVENT5#
Chapter 8
Testability
119
AMD A77E Fusion Controller Hub Databook
XOR# Ball Ref
53830
Rev. 3.01 February 2014
XOR# Ball Ref
Pin Name
Pin Name
86
T7
SCL1/GPIO227
114
Y3
AZ_SDIN2/GPIO169
87
T8
USB_OC0#/ GEVENT12#/
TRST/SPI_TPM_CS#
115
Y5
AZ_SDIN1/GPIO168
116
AA2
AZ_SDIN0/GPIO167
88
T6
SPI_CS1#/GPIO165
117
AB3
AZ_BITCLK
89
V1
ROM_RST#/SPI_WP#/
GPIO161
118
AB1
AZ_SDOUT
90
U4
SYS_RESET#/GEVENT19#
119
AE4
AZ_RST#
91
V3
SPI_CLK/GPIO162
120
AD6
AZ_SYNC
92
V5
SPI_DO/GPIO163
121
AB7
GBE_TXCLK
93
V8
DDR3_RST#/GEVENT7#/
VGA_PD
122
AB8
GBE_RXCLK
123
AB9
GBE_TXCTL/TXEN
94
V7
IR_RX1/GEVENT20#
124
AD7
GBE_RXD0
95
V10
GBE_LED2/
GEVENT10#
125
AD8
GBE_TXD0
126
AE7
GBE_RXD1
96
V6
SPI_DI/GPIO164
127
AE8
GBE_TXD1
97
Y6
SPI_HOLD#/
GBE_LED1/GEVENT9#
128
AF7
GBE_RXD2
129
AF9
GBE_TXD3
98
W8
GBE_LED0/GPIO183
130
AG6
GBE_TXD2
99
W9
GBE_PHY_INTR
131
AG8
GBE_RXCTL/RXDV
100
AC2
GBE_PHY_PD
132
AH7
GBE_RXD3
101
W7
SPI_CS3#/GBE_STAT1/
GEVENT21#
133
AF1
PCICLK1/GPO36
102
AA7
GBE_PHY_RST#
134
AF3
PCICLK0
103
AA8
GBE_STAT0/GEVENT11#
135
AF5
PCICLK2/GPO37
104
W10
GBE_MDIO
136
AF6
PCICLK4/14M_OSC/GPO39
105
AC4
GBE_COL
137
AG2
PCICLK3/GPO38
106
AD1
GBE_RXERR
138
AL1
AD6/GPIO6
107
AD3
GBE_CRS
139
AJ1
AD9/GPIO9
108
AD9
GBE_MDCK
140
AH1
STOP#
109
AE2
PCIE_RST#
141
AN3
CBE0#
110
AD5
A_RST#
142
AL3
AD11/GPIO11
111
AB5
PCIRST#
143
AJ3
AD0/GPIO0
112
AB6
PCIE_RST2#/GEVENT4#
144
AH3
AD4/GPIO4
113
Y1
145
AG4
AD2/GPIO2
146
AN5
AD7/GPIO7
120
AZ_SDIN3/GPIO170
Testability
Chapter 8
53830
AMD A77E Fusion Controller Hub Databook
Rev. 3.01 February 2014
XOR# Ball Ref
Pin Name
XOR# Ball Ref
Pin Name
147
AL5
AD1/GPIO1
180
AD21
GNT2#/SD_LED/GPO45
148
AJ5
AD5/GPIO5
181
AD16
GNT0#
149
AN6
AD8/GPIO8
182
AC16
INTG#/GPIO34
150
AL6
AD3/GPIO3
183
AG13
REQ1#/GPIO40
151
AJ6
AD13/GPIO13
184
AE13
AD25/GPIO25
152
AM7
AD12/GPIO12
185
AF13
AD26/GPIO26
153
AK7
AD14/GPIO14
186
AH13
AD27/GPIO27
154
AN8
AD15/GPIO15
187
AH14
AD28/GPIO28
155
AL8
AD10/GPIO10
188
AD15
AD29/GPIO29
156
AJ8
CBE1#
189
AC15
AD30/GPIO30
157
AH8
SERR#
190
AD19
CLKRUN#
158
AM9
PERR#
191
AF15
REQ2#/CLK_REQ8#/GPIO41
159
AK9
DEVSEL#
192
AE18
INTF#/GPIO33
160
AH9
LOCK#
193
AF18
INTE#/GPIO32
161
AG9
AD16/GPIO16
194
AK17
162
AN10
CBE2#
GNT3#/CLK_REQ7#/
SATA_IS7#/GPIO46
163
AL10
IRDY#
195
AM17
164
AJ10
REQ3#/CLK_REQ5#/
SATA_IS6#/GPIO42
AD18/GPIO18
196
AL16
165
AG10
FANIN2/GPIO58
FRAME#
197
AN16
166
AF10
FANIN1/GPIO57
TRDY#
198
AJ16
167
AE10
FANOUT2/GPIO54
PAR
199
AM15
168
AM11
FANOUT1/GPIO53
AD17/GPIO17
200
AH16
169
AK11
FANOUT0/GPIO52
AD20/GPIO20
201
AK15
170
AN12
FANIN0/GPIO56
AD21/GPIO21
202
AE19
171
AL12
SERIRQ/GPIO48
AD19/GPIO19
203
AD22
172
AG12
SATA_ACT#/GPIO67
AD22/GPIO22
204
AH17
173
AE12
AD23/GPIO23
SATA_IS4#/FANOUT3/
GPIO55
174
AE16
AD31/GPIO31
205
AG18
175
AG15
REQ0#
SATA_IS5#/FANIN3/
GPIO59
176
AD13
GNT1#/GPO44
206
AF25
177
AD12
CBE3#
CLK_REQG#/GPIO65/
OSCIN/IDLEEXIT#
178
AC12
AD24/GPIO24
207
AF19
NB_PWRGD
179
AD18
INTH#/GPIO35
208
AG19
KBRST#/GEVENT1#
Chapter 8
Testability
121
AMD A77E Fusion Controller Hub Databook
XOR# Ball Ref
53830
Pin Name
209
AE22
GA20IN/GEVENT0#
210
AE24
CLK_REQ3#/SATA_IS1#/
GPIO63
211
AG26
SMARTVOLT2/
SHUTDOWN#/GPIO51
212
AG24
CLK_REQ4#/SATA_IS0#/
GPIO64
213
AD25
SDA0/GPIO47
214
AG25
CLK_REQ2#/FANIN4/
GPIO62
215
AG22
CLK_REQ1#/FANOUT4/
GPIO61
216
AF24
SPKR/GPIO66
217
AD26
SCL0/GPIO43
218
AE26
SMARTVOLT1/SATA_IS2#/
GPIO50
219
AF22
CLK_REQ0#/SATA_IS3#/
GPIO60
220
AE27
LDRQ1#/CLK_REQ6#/
GPIO49
221
AH12
SD_WP/GPIO76
222
AN14
SD_CMD/SLOAD_0/
GPIO74
223
AL14
SD_CLK/SCLK_0/
GPIO73
224
AJ12
SD_CD#/GPIO75
225
AJ14
SD_DATA3/GPIO80
226
AK13
SD_DATA0/SDATI_0/
GPIO77
227
AM13
SD_DATA1/SDATO_0/
GPIO78
228
AH15
SD_DATA2/GPIO79
229
N32
VGA_DDC_SCL/GPO71
230
M33
VGA_DDC_SDA/GPO70
231
M28
VGA_HSYNC/GPO68
232
N30
VGA_VSYNC/GPO69
122
Rev. 3.01 February 2014
Testability
Chapter 8
53830
AMD A77E Fusion Controller Hub Databook
Rev. 3.01 February 2014
8.2.1
Unused Pins
The pins that are part of the XOR chain (see Table 65 on page 118) but are not used for testing must
be pulled up or down before the XOR chain is activated. No pins in the XOR chain should be left
floating. All digital or analog pins not included in Table 65 on page 118 are not part of the XOR chain
and can be left floating during an XOR test.
Chapter 8
Testability
123
AMD A77E Fusion Controller Hub Databook
124
53830
Testability
Rev. 3.01 February 2014
Chapter 8
53830
AMD A77E Fusion Controller Hub Databook
Rev. 3.01 February 2014
Appendix A
Pin Listing
This appendix contains pin listings for the Bolton-E4 sorted in two different ways. To go to the listing
of interest, click on the linked cross-references below:
•
“Pin List by Pin Name” on page 126
•
“Pin List by Ball Number” on page 143
Appendix A
Pin Listing
125
AMD A77E Fusion Controller Hub Databook
A.1
53830
Rev. 3.01 February 2014
Pin List by Pin Name
Table A-1 Pin Listing by Pin Name
Pin Name
14M_25M_48M_OSC
25M_X1
25M_X2
32K_X1
32K_X2
A_RST#
AD0/GPIO0
AD1/GPIO1
AD10/GPIO10
AD11/GPIO11
AD12/GPIO12
AD13/GPIO13
AD14/GPIO14
AD15/GPIO15
AD16/GPIO16
AD17/GPIO17
AD18/GPIO18
AD19/GPIO19
AD2/GPIO2
AD20/GPIO20
AD21/GPIO21
AD22/GPIO22
AD23/GPIO23
AD24/GPIO24
AD25/GPIO25
AD26/GPIO26
AD27/GPIO27
AD28/GPIO28
AD29/GPIO29
AD3/GPIO3
AD30/GPIO30
AD31/GPIO31
AD4/GPIO4
AD5/GPIO5
AD6/GPIO6
AD7/GPIO7
AD8/GPIO8
AD9/GPIO9
APU_CLKN
APU_CLKP
APU_PG
126
Pin Listing
Ball #
J26
C31
C33
G2
G4
AD5
AJ3
AL5
AL8
AL3
AM7
AJ6
AK7
AN8
AG9
AM11
AJ10
AL12
AG4
AK11
AN12
AG12
AE12
AC12
AE13
AF13
AH13
AH14
AD15
AL6
AC15
AE16
AH3
AJ5
AL1
AN5
AN6
AJ1
T23
T24
E26
Appendix A
53830
AMD A77E Fusion Controller Hub Databook
Rev. 3.01 February 2014
Pin Name
APU_RST#
AUX_VGA_CH_N
AUX_VGA_CH_P
AUXCAL
AZ_BITCLK
AZ_RST#
AZ_SDIN0/GPIO167
AZ_SDIN1/GPIO168
AZ_SDIN2/GPIO169
AZ_SDIN3/GPIO170
AZ_SDOUT
AZ_SYNC
BLINK/USB_OC7#/
GEVENT18#
CBE0#
CBE1#
CBE2#
CBE3#
CLK_CALRN
CLK_REQ0#/
SATA_IS3#/GPIO60
CLK_REQ1#/
FANOUT4/GPIO61
CLK_REQ2#/FANIN4/
GPIO62
CLK_REQ3#/
SATA_IS1#/GPIO63
CLK_REQ4#/
SATA_IS0#/GPIO64
CLK_REQG#/GPIO65/
OSCIN/IDLEEXIT#
CLKRUN#
DDR3_RST#/
GEVENT7#/VGA_PD
DEVSEL#
DISP_CLKN
DISP_CLKP
DISP2_CLKN
DISP2_CLKP
DMA_ACTIVE#
EC_PWM0/
EC_TIMER0/GPIO197
EC_PWM1/
EC_TIMER1/GPIO198
EC_PWM2/
EC_TIMER2/WOL_EN/
GPIO199
Appendix A
Pin Listing
Ball #
F26
V29
V28
U28
AB3
AE4
AA2
Y5
Y3
Y1
AB1
AD6
M7
AN3
AJ8
AN10
AD12
F27
AF22
AG22
AG25
AE24
AG24
AF25
AD19
V8
AK9
T26
R26
H31
H33
G25
E22
H22
J22
127
AMD A77E Fusion Controller Hub Databook
53830
Pin Name
EC_PWM3/
EC_TIMER3/GPIO200
FANIN0/GPIO56
FANIN1/GPIO57
FANIN2/GPIO58
FANOUT0/GPIO52
FANOUT1/GPIO53
FANOUT2/GPIO54
FRAME#
GA20IN/GEVENT0#
GBE_COL
GBE_CRS
GBE_LED0/GPIO183
GBE_LED2/
GEVENT10#
GBE_MDCK
GBE_MDIO
GBE_PHY_INTR
GBE_PHY_PD
GBE_PHY_RST#
GBE_RXCLK
GBE_RXCTL/RXDV
GBE_RXD0
GBE_RXD1
GBE_RXD2
GBE_RXD3
GBE_RXERR
GBE_STAT0/
GEVENT11#
GBE_TXCLK
GBE_TXCTL/TXEN
GBE_TXD0
GBE_TXD1
GBE_TXD2
GBE_TXD3
GNT0#
GNT1#/GPO44
GNT2#/SD_LED/
GPO45
GNT3#/CLK_REQ7#/
SATA_IS7#/GPIO46
(Note: SATA_IS7#
applies to
GPP_CLK0N
GPP_CLK0P
GPP_CLK1N
GPP_CLK1P
128
Pin Listing
Rev. 3.01 February 2014
Ball #
H21
AK15
AN16
AL16
AH16
AM15
AJ16
AG10
AE22
AC4
AD3
W8
V10
AD9
W10
W9
AC2
AA7
AB8
AG8
AD7
AE7
AF7
AH7
AD1
AA8
AB7
AB9
AD8
AE8
AG6
AF9
AD16
AD13
AD21
AK17
H28
H27
K26
J27
Appendix A
53830
AMD A77E Fusion Controller Hub Databook
Rev. 3.01 February 2014
Pin Name
GPP_CLK2N
GPP_CLK2P
GPP_CLK3N
GPP_CLK3P
GPP_CLK4N
GPP_CLK4P
GPP_CLK5N
GPP_CLK5P
GPP_CLK6N
GPP_CLK6P
GPP_CLK7N
GPP_CLK7P
GPP_CLK8N
GPP_CLK8P
GPP_RX0N
GPP_RX0P
GPP_RX1N
GPP_RX1P
GPP_RX2N
GPP_RX2P
GPP_RX3N
GPP_RX3P
GPP_TX0N
GPP_TX0P
GPP_TX1N
GPP_TX1P
GPP_TX2N
GPP_TX2P
GPP_TX3N
GPP_TX3P
INTE#/GPIO32
INTF#/GPIO33
INTG#/GPIO34
INTH#/GPIO35
INTRUDER_ALERT#
IR_LED#/LLB#/
GPIO184
IR_RX1/GEVENT20#
IRDY#
KBRST#/GEVENT1#
KSI_0/GPIO201
KSI_1/GPIO202
KSI_2/GPIO203
KSI_3/GPIO204
KSI_4/GPIO205
KSI_5/GPIO206
Appendix A
Pin Listing
Ball #
F31
F33
E31
E33
M24
M23
M26
M27
N26
N25
R24
R23
R27
N27
AA26
AA27
V27
W27
W26
V26
W23
W24
V31
V33
W32
W30
AB27
AB26
AA23
AA24
AF18
AE18
AC16
AD18
F3
J2
V7
AL10
AG19
K21
K22
F22
F24
E24
B23
129
AMD A77E Fusion Controller Hub Databook
53830
Pin Name
KSI_6/GPIO207
KSI_7/GPIO208
KSO_0/GPIO209
KSO_1/GPIO210
KSO_10/GPIO219
KSO_11/GPIO220
KSO_12/GPIO221
KSO_13/GPIO222
KSO_14/XDB0/
GPIO223
KSO_15/XDB1/
GPIO224
KSO_16/XDB2/
GPIO225
KSO_17/XDB3/
GPIO226
KSO_2/GPIO211
KSO_3/GPIO212
KSO_4/GPIO213
KSO_5/GPIO214
KSO_6/GPIO215
KSO_7/GPIO216
KSO_8/GPIO217
KSO_9/GPIO218
LAD0
LAD1
LAD2
LAD3
LDO_CAP
LDRQ0#
LDRQ1#/CLK_REQ6#/
GPIO49
LDT_STP#
LFRAME#
LOCK#
LPC_PD#/GEVENT5#
LPC_SMI#/
GEVENT23#
LPCCLK0
LPCCLK1
ML_VGA_HPD/
GPIO229
ML_VGA_L0N
ML_VGA_L0P
ML_VGA_L1N
ML_VGA_L1P
ML_VGA_L2N
130
Pin Listing
Rev. 3.01 February 2014
Ball #
C24
F18
F21
E20
K18
D19
A18
C18
B19
B17
A24
D17
F20
A22
E18
A20
J18
H18
G18
B21
D27
C28
A26
A29
M31
B27
AE27
G26
A31
AH9
T5
C26
B25
D25
C29
T33
T31
T28
T29
R30
Appendix A
53830
AMD A77E Fusion Controller Hub Databook
Rev. 3.01 February 2014
Pin Name
ML_VGA_L2P
ML_VGA_L3N
ML_VGA_L3P
NC1
NC10
NC11
NC12
NC13
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
PAR
PCICLK0
PCICLK1/GPO36
PCICLK2/GPO37
PCICLK3/GPO38
PCICLK4/14M_OSC/
GPO39
PCIE_CALRN
PCIE_CALRP
PCIE_RCLKN
PCIE_RCLKP
PCIE_RST#
PCIE_RST2#/
GEVENT4#
PCIRST#
PERR#
PME#/GEVENT3#
PROCHOT#
PS2_CLK/SCL4/
GPIO188
PS2_DAT/SDA4/
GPIO187
PS2KB_CLK/GPIO190
PS2KB_DAT/GPIO189
PS2M_CLK/GPIO192
PS2M_DAT/GPIO191
PWR_BTN#
PWR_GOOD
REQ0#
REQ1#/GPIO40
Appendix A
Pin Listing
Ball #
R32
P28
P29
AG16
AH33
AH31
AJ33
AJ31
AH10
A28
G27
L4
AL29
AN31
AL31
AL33
AE10
AF3
AF1
AF5
AG2
AF6
AF31
AF29
G28
G30
AE2
AB6
AB5
AM9
R9
E28
J19
K19
C20
D21
C22
D23
J4
N7
AG15
AG13
131
AMD A77E Fusion Controller Hub Databook
53830
Pin Name
REQ2#/CLK_REQ8#/
GPIO41
REQ3#/CLK_REQ5#/
SATA_IS6#/GPIO42
RI#/GEVENT22#
ROM_RST#/SPI_WP#/
GPIO161
RSMRST#
RTCCLK
S5_CORE_EN
SATA_ACT#/GPIO67
SATA_CALRN
SATA_CALRP
SATA_IS4#/FANOUT3/
GPIO55
SATA_IS5#/FANIN3/
GPIO59
SATA_RX0N
SATA_RX0P
SATA_RX1N
SATA_RX1P
SATA_RX2N
SATA_RX2P
SATA_RX3N
SATA_RX3P
SATA_RX4N
SATA_RX4P
SATA_RX5N
SATA_RX5P
SATA_RX6N
SATA_RX6P
SATA_RX7N
SATA_RX7P
SATA_TX0N
SATA_TX0P
SATA_TX1N
SATA_TX1P
SATA_TX2N
SATA_TX2P
SATA_TX3N
SATA_TX3P
SATA_TX4N
SATA_TX4P
SATA_TX5N
SATA_TX5P
SATA_TX6N
SATA_TX6P
132
Pin Listing
Rev. 3.01 February 2014
Ball #
AF15
AM17
R2
V1
U2
F1
H7
AD22
AF27
AF28
AH17
AG18
AL20
AN20
AH20
AJ20
AM23
AK23
AN24
AL24
AJ26
AH26
AK27
AM27
AL31
AL33
AJ33
AJ31
AM19
AK19
AL22
AN22
AH22
AJ22
AJ24
AH24
AN26
AL26
AL28
AN29
AN31
AL29
Appendix A
53830
AMD A77E Fusion Controller Hub Databook
Rev. 3.01 February 2014
Pin Name
SATA_TX7N
SATA_TX7P
SATA_X1
SATA_X2
SCL0/GPIO43
SCL1/GPIO227
SCL2/GPIO193
SCL3_LV/GPIO195
SD_CD#/GPIO75
SD_CLK/SCLK_0/
GPIO73
SD_CMD/SLOAD_0/
GPIO74
SD_DATA0/SDATI_0/
GPIO77
SD_DATA1/SDATO_0/
GPIO78
SD_DATA2/GPIO79
SD_DATA3/GPIO80
SD_WP/GPIO76
SDA0/GPIO47
SDA1/GPIO228
SDA2/GPIO194
SDA3_LV/GPIO196
SERIRQ/GPIO48
SERR#
SLP_S3#
SLP_S5#
SLT_GFX_CLKN
SLT_GFX_CLKP
SMARTVOLT1/
SATA_IS2#/GPIO50
SMARTVOLT2/
SHUTDOWN#/GPIO51
SPI_CLK/GPIO162
SPI_CS1#/GPIO165
SPI_CS2#/
GBE_STAT2/GPIO166
SPI_CS3#/
GBE_STAT1/
GEVENT21#
SPI_DI/GPIO164
SPI_DO/GPIO163
SPI_HOLD#/
GBE_LED1/GEVENT9#
SPKR/GPIO66
STOP#
Appendix A
Pin Listing
Ball #
AH31
AH33
AF21
AG21
AD26
T7
H19
G22
AJ12
AL14
AN14
AK13
AM13
AH15
AJ14
AH12
AD25
R7
G19
G21
AE19
AH8
T3
W2
K29
J30
AE26
AG26
V3
T6
J21
W7
V6
V5
Y6
AF24
AH1
133
AMD A77E Fusion Controller Hub Databook
53830
Pin Name
SYS_RESET#/
GEVENT19#
TEMPIN0/GPIO171
TEMPIN1/GPIO172
TEMPIN2/GPIO173
TEMPIN3/TALERT#/
GPIO174
TEST0
TEST1/TMS
TEST2
THRMTRIP#/
SMBALERT#/
GEVENT2#
TRDY#
UMI_RX0N
UMI_RX0P
UMI_RX1N
UMI_RX1P
UMI_RX2N
UMI_RX2P
UMI_RX3N
UMI_RX3P
UMI_TX0N
UMI_TX0P
UMI_TX1N
UMI_TX1P
UMI_TX2N
UMI_TX2P
UMI_TX3N
UMI_TX3P
USB_FSD0N
USB_FSD0P/GPIO185
USB_FSD1N
USB_FSD1P/GPIO186
USB_HSD0N
USB_HSD0P
USB_HSD10N
USB_HSD10P
USB_HSD11N
USB_HSD11P
USB_HSD12N
USB_HSD12P
USB_HSD13N
USB_HSD13P
USB_HSD1N
USB_HSD1P
134
Pin Listing
Rev. 3.01 February 2014
Ball #
U4
K6
K5
K3
M6
T9
T10
V9
R10
AF10
AB31
AB33
AB29
AB28
Y31
Y33
Y29
Y28
AE32
AE30
AD31
AD33
AD29
AD28
AC32
AC30
H5
H6
H3
H1
E3
E1
K13
K12
F12
G12
J12
K10
G10
H10
C3
C1
Appendix A
53830
AMD A77E Fusion Controller Hub Databook
Rev. 3.01 February 2014
Pin Name
USB_HSD2N
USB_HSD2P
USB_HSD3N
USB_HSD3P
USB_HSD4N
USB_HSD4P
USB_HSD5N
USB_HSD5P
USB_HSD6N
USB_HSD6P
USB_HSD7N
USB_HSD7P
USB_HSD8N
USB_HSD8P
USB_HSD9N
USB_HSD9P
USB_OC0#/
GEVENT12#/TRST
USB_OC1#/TDI/
GEVENT13#
USB_OC2#/TCK/
GEVENT14#
USB_OC3#/AC_PRES/
TDO/GEVENT15#
USB_OC4#/IR_RX0/
GEVENT16#
USB_OC5#/IR_TX0/
GEVENT17#
USB_OC6#/IR_TX1/
GEVENT6#
USB_RCOMP
USB_SS_RX0N
USB_SS_RX0P
USB_SS_RX1N
USB_SS_RX1P
USB_SS_RX2N
USB_SS_RX2P
USB_SS_RX3N
USB_SS_RX3P
USB_SS_TX0N
USB_SS_TX0P
USB_SS_TX1N
USB_SS_TX1P
USB_SS_TX2N
USB_SS_TX2P
USB_SS_TX3N
USB_SS_TX3P
Appendix A
Pin Listing
Ball #
A5
C5
A6
C6
E8
F8
C8
A8
G9
H9
A10
C10
F10
E10
D11
B11
T8
J7
P5
F5
P6
T1
R8
B9
K15
J15
G13
H13
F14
E14
A12
C12
H16
J16
G15
F15
B15
D15
C14
A14
135
AMD A77E Fusion Controller Hub Databook
53830
Pin Name
USBCLK/
14M_25M_48M_OSC
USBSS_CALRN
USBSS_CALRP
VDDAN_11_CLK_1
VDDAN_11_CLK_2
VDDAN_11_CLK_3
VDDAN_11_CLK_4
VDDAN_11_CLK_5
VDDAN_11_CLK_6
VDDAN_11_CLK_7
VDDAN_11_CLK_8
VDDAN_11_ML_1
VDDAN_11_ML_2
VDDAN_11_ML_3
VDDAN_11_ML_4
VDDAN_11_PCIE_1
VDDAN_11_PCIE_2
VDDAN_11_PCIE_3
VDDAN_11_PCIE_4
VDDAN_11_PCIE_5
VDDAN_11_PCIE_6
VDDAN_11_PCIE_7
VDDAN_11_PCIE_8
VDDAN_11_SATA_1
VDDAN_11_SATA_10
VDDAN_11_SATA_2
VDDAN_11_SATA_3
VDDAN_11_SATA_4
VDDAN_11_SATA_5
VDDAN_11_SATA_6
VDDAN_11_SATA_7
VDDAN_11_SATA_8
VDDAN_11_SATA_9
VDDAN_11_SSUSB_S
_1
VDDAN_11_SSUSB_S
_2
VDDAN_11_SSUSB_S
_3
VDDAN_11_SSUSB_S
_4
VDDAN_11_SSUSB_S
_5
VDDAN_11_USB_S_1
VDDAN_11_USB_S_2
VDDAN_33_DAC
136
Pin Listing
Rev. 3.01 February 2014
Ball #
G8
A16
C16
H26
J25
K24
L22
M22
N21
N22
P22
Y22
V23
V24
V25
AB24
Y21
AE25
AD24
AB23
AA22
AF26
AG27
AA21
AC19
AB21
AB22
Y20
AC22
AC21
AA20
AA18
AB20
P16
M14
N14
P13
P14
U12
U13
T22
Appendix A
53830
AMD A77E Fusion Controller Hub Databook
Rev. 3.01 February 2014
Pin Name
VDDAN_33_HWM_S
VDDAN_33_USB_S_1
VDDAN_33_USB_S_10
VDDAN_33_USB_S_11
VDDAN_33_USB_S_12
VDDAN_33_USB_S_2
VDDAN_33_USB_S_3
VDDAN_33_USB_S_4
VDDAN_33_USB_S_5
VDDAN_33_USB_S_6
VDDAN_33_USB_S_7
VDDAN_33_USB_S_8
VDDAN_33_USB_S_9
VDDBT_RTC_G
VDDCR_11_1
VDDCR_11_2
VDDCR_11_3
VDDCR_11_4
VDDCR_11_5
VDDCR_11_6
VDDCR_11_7
VDDCR_11_8
VDDCR_11_9
VDDCR_11_GBE_S_1
VDDCR_11_GBE_S_2
VDDCR_11_S_1
VDDCR_11_S_2
VDDCR_11_SSUSB_S
_1
VDDCR_11_SSUSB_S
_2
VDDCR_11_SSUSB_S
_3
VDDCR_11_SSUSB_S
_4
VDDCR_11_USB_S_1
VDDCR_11_USB_S_2
VDDIO_33_GBE_S
VDDIO_33_PCIGP_1
VDDIO_33_PCIGP_10
VDDIO_33_PCIGP_2
VDDIO_33_PCIGP_3
VDDIO_33_PCIGP_4
VDDIO_33_PCIGP_5
VDDIO_33_PCIGP_6
VDDIO_33_PCIGP_7
Appendix A
Pin Listing
Ball #
M8
G7
M12
N12
M11
H8
J8
K8
K9
M9
M10
N9
N10
E6
T14
T17
T20
U16
U18
V14
V17
V20
Y17
AB11
AA11
N20
M20
N16
N17
P17
M17
T12
T13
AB10
AB17
AB16
AB18
AE9
AD10
AG7
AC13
AB12
137
AMD A77E Fusion Controller Hub Databook
53830
Pin Name
VDDIO_33_PCIGP_8
VDDIO_33_PCIGP_9
VDDIO_33_S_1
VDDIO_33_S_2
VDDIO_33_S_3
VDDIO_33_S_4
VDDIO_33_S_5
VDDIO_33_S_6
VDDIO_33_S_7
VDDIO_33_S_8
VDDIO_AZ_S
VDDIO_GBE_S_1
VDDIO_GBE_S_2
VDDPL_11_DAC
VDDPL_11_SYS_S
VDDPL_33_DAC
VDDPL_33_ML
VDDPL_33_PCIE
VDDPL_33_SATA
VDDPL_33_SSUSB_S
VDDPL_33_SYS
VDDPL_33_USB_S
VDDXL_33_S
VGA_BLUE
VGA_DAC_RSET
VGA_DDC_SCL/
GPO71
VGA_DDC_SDA/
GPO70
VGA_GREEN
VGA_HSYNC/GPO68
VGA_RED
VGA_VSYNC/GPO69
VIN0/GPIO175
VIN1/GPIO176
VIN2/SDATI_1/
GPIO177
VIN3/SDATO_1/
GPIO178
VIN4/SLOAD_1/
GPIO179
VIN5/SCLK_1/GPIO180
VIN6/GBE_STAT3/
GPIO181
VIN7/GBE_LED3/
GPIO182
VSS
138
Pin Listing
Rev. 3.01 February 2014
Ball #
AB13
AB14
N18
L19
M18
V12
V13
Y12
Y13
W11
AA4
AA9
AA10
V21
J24
V22
U22
AH29
AG28
L18
H24
D7
G24
M29
K31
N32
M33
L32
M28
L30
N30
N2
M3
L2
N4
P1
P3
M1
M5
A3
Appendix A
53830
AMD A77E Fusion Controller Hub Databook
Rev. 3.01 February 2014
Pin Name
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Appendix A
Pin Listing
Ball #
A33
AA12
AA13
AA14
AA16
AA17
AA25
AA28
AA30
AA32
AA6
AB25
AC18
AC28
AC6
AD27
AE15
AE21
AE28
AE6
AF12
AF16
AF33
AF8
AG30
AG32
AH11
AH18
AH19
AH21
AH23
AH25
AH27
AH5
AJ18
AJ28
AJ29
AK21
AK25
AL18
AM21
AM25
AN1
AN18
AN28
AN33
139
AMD A77E Fusion Controller Hub Databook
53830
Pin Name
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
140
Pin Listing
Rev. 3.01 February 2014
Ball #
B13
B7
D13
D9
E12
E16
E29
E5
F11
F13
F16
F17
F19
F23
F25
F29
F7
F9
G16
G32
G6
H12
H15
H29
J10
J13
J28
J32
J6
J9
K16
K27
K28
K7
L12
L13
L15
L16
L21
L6
M13
M16
M21
M25
N11
N13
Appendix A
53830
AMD A77E Fusion Controller Hub Databook
Rev. 3.01 February 2014
Pin Name
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSAN_DAC
VSSAN_HWM
VSSANQ_DAC
VSSIO_DAC
VSSPL_DAC
VSSPL_SYS
VSSXL
WAKE#/GEVENT8#
WD_PWRGD
Appendix A
Pin Listing
Ball #
N23
N24
N6
P12
P18
P20
P21
P31
P33
R11
R25
R28
R4
R6
T11
T16
T18
T25
T27
U14
U17
U20
U21
U30
U32
U6
V11
V16
V18
W25
W28
W4
W6
Y14
Y16
Y18
L28
N8
K33
N28
T21
H25
K25
K1
AF19
141
AMD A77E Fusion Controller Hub Databook
142
53830
Pin Listing
Rev. 3.01 February 2014
Appendix A
53830
AMD A77E Fusion Controller Hub Databook
Rev. 3.01 February 2014
A.2
Pin List by Ball Number
Table A-2 Pin List by Ball Number
Ball #
A10
A12
A14
A16
A18
A20
A22
A24
A26
A28
A29
A3
A31
A33
A5
A6
A8
AA10
AA11
AA12
AA13
AA14
AA16
AA17
AA18
AA2
AA20
AA21
AA22
AA23
AA24
AA25
AA26
AA27
AA28
AA30
AA32
AA4
AA6
AA7
Appendix A
Pin Name
USB_HSD7N
USB_SS_RX3N
USB_SS_TX3P
USBSS_CALRN
KSO_12/GPIO221
KSO_5/GPIO214
KSO_3/GPIO212
KSO_16/XDB2/
GPIO225
LAD2
NC3
LAD3
VSS
LFRAME#
VSS
USB_HSD2N
USB_HSD3N
USB_HSD5P
VDDIO_GBE_S_2
VDDCR_11_GBE_S_2
VSS
VSS
VSS
VSS
VSS
VDDAN_11_SATA_8
AZ_SDIN0/GPIO167
VDDAN_11_SATA_7
VDDAN_11_SATA_1
VDDAN_11_PCIE_6
GPP_TX3N
GPP_TX3P
VSS
GPP_RX0N
GPP_RX0P
VSS
VSS
VSS
VDDIO_AZ_S
VSS
GBE_PHY_RST#
Pin Listing
143
AMD A77E Fusion Controller Hub Databook
Ball #
AA8
AA9
AB1
AB10
AB11
AB12
AB13
AB14
AB16
AB17
AB18
AB20
AB21
AB22
AB23
AB24
AB25
AB26
AB27
AB28
AB29
AB3
AB31
AB33
AB5
AB6
AB7
AB8
AB9
AC12
AC13
AC15
AC16
AC18
AC19
AC2
AC21
AC22
AC28
AC30
AC32
AC4
AC6
AD1
144
53830
Rev. 3.01 February 2014
Pin Name
GBE_STAT0/
GEVENT11#
VDDIO_GBE_S_1
AZ_SDOUT
VDDIO_33_GBE_S
VDDCR_11_GBE_S_1
VDDIO_33_PCIGP_7
VDDIO_33_PCIGP_8
VDDIO_33_PCIGP_9
VDDIO_33_PCIGP_10
VDDIO_33_PCIGP_1
VDDIO_33_PCIGP_2
VDDAN_11_SATA_9
VDDAN_11_SATA_2
VDDAN_11_SATA_3
VDDAN_11_PCIE_5
VDDAN_11_PCIE_1
VSS
GPP_TX2P
GPP_TX2N
UMI_RX1P
UMI_RX1N
AZ_BITCLK
UMI_RX0N
UMI_RX0P
PCIRST#
PCIE_RST2#/
GEVENT4#
GBE_TXCLK
GBE_RXCLK
GBE_TXCTL/TXEN
AD24/GPIO24
VDDIO_33_PCIGP_6
AD30/GPIO30
INTG#/GPIO34
VSS
VDDAN_11_SATA_10
GBE_PHY_PD
VDDAN_11_SATA_6
VDDAN_11_SATA_5
VSS
UMI_TX3P
UMI_TX3N
GBE_COL
VSS
GBE_RXERR
Pin Listing
Appendix A
53830
AMD A77E Fusion Controller Hub Databook
Rev. 3.01 February 2014
Ball #
AD10
AD12
AD13
AD15
AD16
AD18
AD19
AD21
AD22
AD24
AD25
AD26
AD27
AD28
AD29
AD3
AD31
AD33
AD5
AD6
AD7
AD8
AD9
AE10
AE12
AE13
AE15
AE16
AE18
AE19
AE2
AE21
AE22
AE24
AE25
AE26
AE27
AE28
AE30
AE32
AE4
AE6
Appendix A
Pin Name
VDDIO_33_PCIGP_4
CBE3#
GNT1#/GPO44
AD29/GPIO29
GNT0#
INTH#/GPIO35
CLKRUN#
GNT2#/SD_LED/
GPO45
SATA_ACT#/GPIO67
VDDAN_11_PCIE_4
SDA0/GPIO47
SCL0/GPIO43
VSS
UMI_TX2P
UMI_TX2N
GBE_CRS
UMI_TX1N
UMI_TX1P
A_RST#
AZ_SYNC
GBE_RXD0
GBE_TXD0
GBE_MDCK
PAR
AD23/GPIO23
AD25/GPIO25
VSS
AD31/GPIO31
INTF#/GPIO33
SERIRQ/GPIO48
PCIE_RST#
VSS
GA20IN/GEVENT0#
CLK_REQ3#/
SATA_IS1#/GPIO63
VDDAN_11_PCIE_3
SMARTVOLT1/
SATA_IS2#/GPIO50
LDRQ1#/CLK_REQ6#/
GPIO49
VSS
UMI_TX0P
UMI_TX0N
AZ_RST#
VSS
Pin Listing
145
AMD A77E Fusion Controller Hub Databook
Ball #
AE7
AE8
AE9
AF1
AF10
AF12
AF13
AF15
AF16
AF18
AF19
AF21
AF22
AF24
AF25
AF26
AF27
AF28
AF29
AF3
AF31
AF33
AF5
AF6
AF7
AF8
AF9
AG10
AG12
AG13
AG15
AG16
AG18
AG19
AG2
AG21
AG22
AG24
AG25
146
53830
Rev. 3.01 February 2014
Pin Name
GBE_RXD1
GBE_TXD1
VDDIO_33_PCIGP_3
PCICLK1/GPO36
TRDY#
VSS
AD26/GPIO26
REQ2#/CLK_REQ8#/
GPIO41
VSS
INTE#/GPIO32
WD_PWRGD
SATA_X1
CLK_REQ0#/
SATA_IS3#/GPIO60
SPKR/GPIO66
CLK_REQG#/GPIO65/
OSCIN/IDLEEXIT#
VDDAN_11_PCIE_7
SATA_CALRN
SATA_CALRP
PCIE_CALRP
PCICLK0
PCIE_CALRN
VSS
PCICLK2/GPO37
PCICLK4/14M_OSC/
GPO39
GBE_RXD2
VSS
GBE_TXD3
FRAME#
AD22/GPIO22
REQ1#/GPIO40
REQ0#
NC1
SATA_IS5#/FANIN3/
GPIO59
KBRST#/GEVENT1#
PCICLK3/GPO38
SATA_X2
CLK_REQ1#/
FANOUT4/GPIO61
CLK_REQ4#/
SATA_IS0#/GPIO64
CLK_REQ2#/FANIN4/
GPIO62
Pin Listing
Appendix A
53830
AMD A77E Fusion Controller Hub Databook
Rev. 3.01 February 2014
Ball #
AG26
AG27
AG28
AG30
AG32
AG4
AG6
AG7
AG8
AG9
AH1
AH10
AH11
AH12
AH13
AH14
AH15
AH16
AH17
AH18
AH19
AH20
AH21
AH22
AH23
AH24
AH25
AH26
AH27
AH29
AH3
AH31
AH31
AH33
AH33
AH5
AH7
AH8
AH9
AJ1
AJ10
AJ12
AJ14
AJ16
Appendix A
Pin Name
SMARTVOLT2/
SHUTDOWN#/GPIO51
VDDAN_11_PCIE_8
VDDPL_33_SATA
VSS
VSS
AD2/GPIO2
GBE_TXD2
VDDIO_33_PCIGP_5
GBE_RXCTL/RXDV
AD16/GPIO16
STOP#
NC2
VSS
SD_WP/GPIO76
AD27/GPIO27
AD28/GPIO28
SD_DATA2/GPIO79
FANOUT0/GPIO52
SATA_IS4#/FANOUT3/
GPIO55
VSS
VSS
SATA_RX1N
VSS
SATA_TX2N
VSS
SATA_TX3P
VSS
SATA_RX4P
VSS
VDDPL_33_PCIE
AD4/GPIO4
NC11 (D3 only)
SATA_TX7N
NC10 (D3 only)
SATA_TX7P
VSS
GBE_RXD3
SERR#
LOCK#
AD9/GPIO9
AD18/GPIO18
SD_CD#/GPIO75
SD_DATA3/GPIO80
FANOUT2/GPIO54
Pin Listing
147
AMD A77E Fusion Controller Hub Databook
Ball #
AJ18
AJ20
AJ22
AJ24
AJ26
AJ28
AJ29
AJ3
AJ31
AJ31
AJ33
AJ33
AJ5
AJ6
AJ8
AK11
AK13
AK15
AK17
AK19
AK21
AK23
AK25
AK27
AK7
AK9
AL1
AL10
AL12
AL14
AL16
AL18
AL20
AL22
AL24
AL26
AL28
AL29
AL29
AL3
AL31
AL31
148
53830
Rev. 3.01 February 2014
Pin Name
VSS
SATA_RX1P
SATA_TX2P
SATA_TX3N
SATA_RX4N
VSS
VSS
AD0/GPIO0
NC13 (D3 only)
SATA_RX7P
NC12 (D3 only)
SATA_RX7N
AD5/GPIO5
AD13/GPIO13
CBE1#
AD20/GPIO20
SD_DATA0/SDATI_0/
GPIO77
FANIN0/GPIO56
GNT3#/CLK_REQ7#/
SATA_IS7#/GPIO46
(Note: SATA_IS7#
applies to
SATA_TX0P
VSS
SATA_RX2P
VSS
SATA_RX5N
AD14/GPIO14
DEVSEL#
AD6/GPIO6
IRDY#
AD19/GPIO19
SD_CLK/SCLK_0/
GPIO73
FANIN2/GPIO58
VSS
SATA_RX0N
SATA_TX1N
SATA_RX3P
SATA_TX4P
SATA_TX5N
NC6 (D3 only)
SATA_TX6P
AD11/GPIO11
NC8 (D3 only)
SATA_RX6N
Pin Listing
Appendix A
53830
AMD A77E Fusion Controller Hub Databook
Rev. 3.01 February 2014
Ball #
AL33
AL33
AL5
AL6
AL8
AM11
AM13
AM15
AM17
AM19
AM21
AM23
AM25
AM27
AM7
AM9
AN1
AN10
AN12
AN14
AN16
AN18
AN20
AN22
AN24
AN26
AN28
AN29
AN3
AN31
AN31
AN33
AN5
AN6
AN8
B11
B13
B15
B17
B19
B21
Appendix A
Pin Name
NC9 (D3 only)
SATA_RX6P (
AD1/GPIO1
AD3/GPIO3
AD10/GPIO10
AD17/GPIO17
SD_DATA1/SDATO_0/
GPIO78
FANOUT1/GPIO53
REQ3#/CLK_REQ5#/
SATA_IS6#/GPIO42
SATA_TX0N
VSS
SATA_RX2N
VSS
SATA_RX5P
AD12/GPIO12
PERR#
VSS
CBE2#
AD21/GPIO21
SD_CMD/SLOAD_0/
GPIO74
FANIN1/GPIO57
VSS
SATA_RX0P
SATA_TX1P
SATA_RX3N
SATA_TX4N
VSS
SATA_TX5P
CBE0#
NC7 (D3 only)
SATA_TX6N
VSS
AD7/GPIO7
AD8/GPIO8
AD15/GPIO15
USB_HSD9P
VSS
USB_SS_TX2N
KSO_15/XDB1/
GPIO224
KSO_14/XDB0/
GPIO223
KSO_9/GPIO218
Pin Listing
149
AMD A77E Fusion Controller Hub Databook
Ball #
B23
B25
B27
B7
B9
C1
C10
C12
C14
C16
C18
C20
C22
C24
C26
C28
C29
C3
C31
C33
C5
C6
C8
D11
D13
D15
D17
D19
D21
D23
D25
D27
D7
D9
E1
E10
E12
E14
E16
E18
E20
E22
150
53830
Rev. 3.01 February 2014
Pin Name
KSI_5/GPIO206
LPCCLK0
LDRQ0#
VSS
USB_RCOMP
USB_HSD1P
USB_HSD7P
USB_SS_RX3P
USB_SS_TX3N
USBSS_CALRP
KSO_13/GPIO222
PS2KB_CLK/GPIO190
PS2M_CLK/GPIO192
KSI_6/GPIO207
LPC_SMI#/
GEVENT23#
LAD1
ML_VGA_HPD/
GPIO229
USB_HSD1N
25M_X1
25M_X2
USB_HSD2P
USB_HSD3P
USB_HSD5N
USB_HSD9N
VSS
USB_SS_TX2P
KSO_17/XDB3/
GPIO226
KSO_11/GPIO220
PS2KB_DAT/GPIO189
PS2M_DAT/GPIO191
LPCCLK1
LAD0
VDDPL_33_USB_S
VSS
USB_HSD0P
USB_HSD8P
VSS
USB_SS_RX2P
VSS
KSO_4/GPIO213
KSO_1/GPIO210
EC_PWM0/
EC_TIMER0/GPIO197
Pin Listing
Appendix A
53830
AMD A77E Fusion Controller Hub Databook
Rev. 3.01 February 2014
Ball #
E24
E26
E28
E29
E3
E31
E33
E5
E6
E8
F1
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
F23
F24
F25
F26
F27
F29
F3
F31
F33
F5
F7
F8
F9
G10
G12
G13
G15
G16
G18
G19
G2
Appendix A
Pin Name
KSI_4/GPIO205
APU_PG
PROCHOT#
VSS
USB_HSD0N
GPP_CLK3N
GPP_CLK3P
VSS
VDDBT_RTC_G
USB_HSD4N
RTCCLK
USB_HSD8N
VSS
USB_HSD11N
VSS
USB_SS_RX2N
USB_SS_TX1P
VSS
VSS
KSI_7/GPIO208
VSS
KSO_2/GPIO211
KSO_0/GPIO209
KSI_2/GPIO203
VSS
KSI_3/GPIO204
VSS
APU_RST#
CLK_CALRN
VSS
INTRUDER_ALERT#
GPP_CLK2N
GPP_CLK2P
USB_OC3#/AC_PRES/
TDO/GEVENT15#
VSS
USB_HSD4P
VSS
USB_HSD13N
USB_HSD11P
USB_SS_RX1N
USB_SS_TX1N
VSS
KSO_8/GPIO217
SDA2/GPIO194
32K_X1
Pin Listing
151
AMD A77E Fusion Controller Hub Databook
Ball #
G21
G22
G24
G25
G26
G27
G28
G30
G32
G4
G6
G7
G8
G9
H1
H10
H12
H13
H15
H16
H18
H19
H21
H22
H24
H25
H26
H27
H28
H29
H3
H31
H33
H5
H6
H7
H8
H9
J10
J12
J13
J15
J16
152
53830
Rev. 3.01 February 2014
Pin Name
SDA3_LV/GPIO196
SCL3_LV/GPIO195
VDDXL_33_S
DMA_ACTIVE#
LDT_STP#
NC4
PCIE_RCLKN
PCIE_RCLKP
VSS
32K_X2
VSS
VDDAN_33_USB_S_1
USBCLK/
14M_25M_48M_OSC
USB_HSD6N
USB_FSD1P/GPIO186
USB_HSD13P
VSS
USB_SS_RX1P
VSS
USB_SS_TX0N
KSO_7/GPIO216
SCL2/GPIO193
EC_PWM3/
EC_TIMER3/GPIO200
EC_PWM1/
EC_TIMER1/GPIO198
VDDPL_33_SYS
VSSPL_SYS
VDDAN_11_CLK_1
GPP_CLK0P
GPP_CLK0N
VSS
USB_FSD1N
DISP2_CLKN
DISP2_CLKP
USB_FSD0N
USB_FSD0P/GPIO185
S5_CORE_EN
VDDAN_33_USB_S_2
USB_HSD6P
VSS
USB_HSD12N
VSS
USB_SS_RX0P
USB_SS_TX0P
Pin Listing
Appendix A
53830
AMD A77E Fusion Controller Hub Databook
Rev. 3.01 February 2014
Ball #
J18
J19
J2
J21
J22
J24
J25
J26
J27
J28
J30
J32
J4
J6
J7
J8
J9
K1
K10
K12
K13
K15
K16
K18
K19
K21
K22
K24
K25
K26
K27
K28
K29
K3
K31
K33
K5
K6
K7
K8
Appendix A
Pin Name
KSO_6/GPIO215
PS2_CLK/SCL4/
GPIO188
IR_LED#/LLB#/
GPIO184
SPI_CS2#/
GBE_STAT2/GPIO166
EC_PWM2/
EC_TIMER2/WOL_EN/
GPIO199
VDDPL_11_SYS_S
VDDAN_11_CLK_2
14M_25M_48M_OSC
GPP_CLK1P
VSS
SLT_GFX_CLKP
VSS
PWR_BTN#
VSS
USB_OC1#/TDI/
GEVENT13#
VDDAN_33_USB_S_3
VSS
WAKE#/GEVENT8#
USB_HSD12P
USB_HSD10P
USB_HSD10N
USB_SS_RX0N
VSS
KSO_10/GPIO219
PS2_DAT/SDA4/
GPIO187
KSI_0/GPIO201
KSI_1/GPIO202
VDDAN_11_CLK_3
VSSXL
GPP_CLK1N
VSS
VSS
SLT_GFX_CLKN
TEMPIN2/GPIO173
VGA_DAC_RSET
VSSANQ_DAC
TEMPIN1/GPIO172
TEMPIN0/GPIO171
VSS
VDDAN_33_USB_S_4
Pin Listing
153
AMD A77E Fusion Controller Hub Databook
Ball #
K9
L12
L13
L15
L16
L18
L19
L2
L21
L22
L28
L30
L32
L4
L6
M1
M10
M11
M12
M13
M14
M16
M17
M18
M20
M21
M22
M23
M24
M25
M26
M27
M28
M29
M3
M31
M33
M5
M6
154
53830
Rev. 3.01 February 2014
Pin Name
VDDAN_33_USB_S_5
VSS
VSS
VSS
VSS
VDDPL_33_SSUSB_S
VDDIO_33_S_2
VIN2/SDATI_1/
GPIO177
VSS
VDDAN_11_CLK_4
VSSAN_DAC
VGA_RED
VGA_GREEN
NC5
VSS
VIN6/GBE_STAT3/
GPIO181
VDDAN_33_USB_S_7
VDDAN_33_USB_S_12
VDDAN_33_USB_S_10
VSS
VDDAN_11_SSUSB_S
_2
VSS
VDDCR_11_SSUSB_S
_4
VDDIO_33_S_3
VDDCR_11_S_2
VSS
VDDAN_11_CLK_5
GPP_CLK4P
GPP_CLK4N
VSS
GPP_CLK5N
GPP_CLK5P
VGA_HSYNC/GPO68
VGA_BLUE
VIN1/GPIO176
LDO_CAP
VGA_DDC_SDA/
GPO70
VIN7/GBE_LED3/
GPIO182
TEMPIN3/TALERT#/
GPIO174
Pin Listing
Appendix A
53830
AMD A77E Fusion Controller Hub Databook
Rev. 3.01 February 2014
Ball #
M7
M8
M9
N10
N11
N12
N13
N14
N16
N17
N18
N2
N20
N21
N22
N23
N24
N25
N26
N27
N28
N30
N32
N4
N6
N7
N8
N9
P1
P12
P13
P14
P16
P17
P18
P20
Appendix A
Pin Name
BLINK/USB_OC7#/
GEVENT18#
VDDAN_33_HWM_S
VDDAN_33_USB_S_6
VDDAN_33_USB_S_9
VSS
VDDAN_33_USB_S_11
VSS
VDDAN_11_SSUSB_S
_3
VDDCR_11_SSUSB_S
_1
VDDCR_11_SSUSB_S
_2
VDDIO_33_S_1
VIN0/GPIO175
VDDCR_11_S_1
VDDAN_11_CLK_6
VDDAN_11_CLK_7
VSS
VSS
GPP_CLK6P
GPP_CLK6N
GPP_CLK8P
VSSIO_DAC
VGA_VSYNC/GPO69
VGA_DDC_SCL/
GPO71
VIN3/SDATO_1/
GPIO178
VSS
PWR_GOOD
VSSAN_HWM
VDDAN_33_USB_S_8
VIN4/SLOAD_1/
GPIO179
VSS
VDDAN_11_SSUSB_S
_4
VDDAN_11_SSUSB_S
_5
VDDAN_11_SSUSB_S
_1
VDDCR_11_SSUSB_S
_3
VSS
VSS
Pin Listing
155
AMD A77E Fusion Controller Hub Databook
Ball #
P21
P22
P28
P29
P3
P31
P33
P5
P6
R10
R11
R2
R23
R24
R25
R26
R27
R28
R30
R32
R4
R6
R7
R8
R9
T1
T10
T11
T12
T13
T14
T16
T17
T18
T20
T21
T22
T23
T24
T25
T26
156
53830
Rev. 3.01 February 2014
Pin Name
VSS
VDDAN_11_CLK_8
ML_VGA_L3N
ML_VGA_L3P
VIN5/SCLK_1/GPIO180
VSS
VSS
USB_OC2#/TCK/
GEVENT14#
USB_OC4#/IR_RX0/
GEVENT16#
THRMTRIP#/
SMBALERT#/
GEVENT2#
VSS
RI#/GEVENT22#
GPP_CLK7P
GPP_CLK7N
VSS
DISP_CLKP
GPP_CLK8N
VSS
ML_VGA_L2N
ML_VGA_L2P
VSS
VSS
SDA1/GPIO228
USB_OC6#/IR_TX1/
GEVENT6#
PME#/GEVENT3#
USB_OC5#/IR_TX0/
GEVENT17#
TEST1/TMS
VSS
VDDCR_11_USB_S_1
VDDCR_11_USB_S_2
VDDCR_11_1
VSS
VDDCR_11_2
VSS
VDDCR_11_3
VSSPL_DAC
VDDAN_33_DAC
APU_CLKN
APU_CLKP
VSS
DISP_CLKN
Pin Listing
Appendix A
53830
AMD A77E Fusion Controller Hub Databook
Rev. 3.01 February 2014
Ball #
T27
T28
T29
T3
T31
T33
T5
T6
T7
T8
T9
U12
U13
U14
U16
U17
U18
U2
U20
U21
U22
U28
U30
U32
U4
U6
V1
V10
V11
V12
V13
V14
V16
V17
V18
V20
V21
V22
V23
V24
V25
V26
Appendix A
Pin Name
VSS
ML_VGA_L1N
ML_VGA_L1P
SLP_S3#
ML_VGA_L0P
ML_VGA_L0N
LPC_PD#/GEVENT5#
SPI_CS1#/GPIO165
SCL1/GPIO227
USB_OC0#/
GEVENT12#/TRST
TEST0
VDDAN_11_USB_S_1
VDDAN_11_USB_S_2
VSS
VDDCR_11_4
VSS
VDDCR_11_5
RSMRST#
VSS
VSS
VDDPL_33_ML
AUXCAL
VSS
VSS
SYS_RESET#/
GEVENT19#
VSS
ROM_RST#/SPI_WP#/
GPIO161
GBE_LED2/
GEVENT10#
VSS
VDDIO_33_S_4
VDDIO_33_S_5
VDDCR_11_6
VSS
VDDCR_11_7
VSS
VDDCR_11_8
VDDPL_11_DAC
VDDPL_33_DAC
VDDAN_11_ML_2
VDDAN_11_ML_3
VDDAN_11_ML_4
GPP_RX2P
Pin Listing
157
AMD A77E Fusion Controller Hub Databook
Ball #
V27
V28
V29
V3
V31
V33
V5
V6
V7
V8
V9
W10
W11
W2
W23
W24
W25
W26
W27
W28
W30
W32
W4
W6
W7
W8
W9
Y1
Y12
Y13
Y14
Y16
Y17
Y18
Y20
Y21
Y22
Y28
Y29
Y3
Y31
Y33
Y5
158
53830
Rev. 3.01 February 2014
Pin Name
GPP_RX1N
AUX_VGA_CH_P
AUX_VGA_CH_N
SPI_CLK/GPIO162
GPP_TX0N
GPP_TX0P
SPI_DO/GPIO163
SPI_DI/GPIO164
IR_RX1/GEVENT20#
DDR3_RST#/
GEVENT7#/VGA_PD
TEST2
GBE_MDIO
VDDIO_33_S_8
SLP_S5#
GPP_RX3N
GPP_RX3P
VSS
GPP_RX2N
GPP_RX1P
VSS
GPP_TX1P
GPP_TX1N
VSS
VSS
SPI_CS3#/
GBE_STAT1/
GEVENT21#
GBE_LED0/GPIO183
GBE_PHY_INTR
AZ_SDIN3/GPIO170
VDDIO_33_S_6
VDDIO_33_S_7
VSS
VSS
VDDCR_11_9
VSS
VDDAN_11_SATA_4
VDDAN_11_PCIE_2
VDDAN_11_ML_1
UMI_RX3P
UMI_RX3N
AZ_SDIN2/GPIO169
UMI_RX2N
UMI_RX2P
AZ_SDIN1/GPIO168
Pin Listing
Appendix A
53830
AMD A77E Fusion Controller Hub Databook
Rev. 3.01 February 2014
Ball #
Y6
Appendix A
Pin Name
SPI_HOLD#/
GBE_LED1/GEVENT9#
Pin Listing
159
AMD A77E Fusion Controller Hub Databook
160
53830
Pin Listing
Rev. 3.01 February 2014
Appendix A