CMP0417AA0-P70I CMOS LPRAM Document Title 256K x 16 bit Super Low Power and Low Voltage Full CMOS RAM Revision History Revision No. History Draft date Remark 0.0 Initial Draft Jul. 04th, 2006 Final 0.1 Corrected timing diagrams and functions (about CS2) Aug. 16th, 2006 Final 0.2 Removed 60ns part Aug. 21st, 2006 Final 0.3 Added Power Up Sequence Sep. 06th, 2006 Final 0.4 Removed VCCQ related information & typo. Dec. 15th, 2006 Final 0.5 Added “RoHS compliant” descriptions Apr. 06th, 2007 Final 1 Revision 0.5 Apr. 2007 CMP0417AA0-P70I CMOS LPRAM 256K x 16 bit Super Low Power and Low Voltage Full CMOS RAM FEATURES • Process Technology : Full CMOS • Organization : 256K x 16 • Power Supply Voltage : 2.7~3.6V • Three state output and TTL Compatible • Package Type : 44-TSOPII (400F) • Automatic power-down when deselected • CMP0417AA0-P70I is RoHS Compliant PRODUCT FAMILY Product Family Power Dissipation Operating Voltage (V) Operating Temperature Speed ICC2 f = 1MHz Min. Typ. Max. CMP0417AA0-P70I ICC1 Industrial (-40~85’C) 2.7 3.0 3.6 70ns f = fmax ISB1 (CMOS Standby Current) Typ. Max. Typ. Max. Typ. Max. 1.5mA 3mA 12mA 20mA 30uA 70uA 1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at Vcc = Vcc (typ) and TA = 25C. 2. T=TSOP, P=TSOP(Pb-Free), W=WAFER PIN DESCRIPTION A4 A3 A2 A1 A0 /CS I/O1 I/O2 I/O3 I/O4 VCC VSS I/O5 I/O6 I/O7 I/O8 /WE A17 A16 A15 A14 A13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 FUNCTIONAL BLOCK DIAGRAM 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 CMP0417AA0-P70I 44-pin TSOPII A5 A6 A7 /OE /UB /LB I/O16 I/O15 I/O14 I/O13 VSS VCC I/O12 I/O11 I/O10 I/O9 NC A8 A9 A10 A11 A12 Clk gen. Precharge circuit. VCC VSS Row Addresses I/O1~I/O8 Row select Data cont Memory array I/O Circuit Column select Data cont I/O9~I/O16 44-Pin TSOP-II : Top View Data cont Name Function Name Function /CS Chip Select Input VCC Core Power /OE Output Enable Input /WE Write Enable Input VSS Ground A0~A17 Address Inputs /UB Upper Byte(I/O9~16) I/O1~I/O16 Data Inputs/Outputs /LB Lower Byte(I/O 1~8) NC No Connection Column Addresses /CS /OE /WE Control Logic /UB /LB 2 Revision 0.5 Apr. 2007 CMP0417AA0-P70I CMOS LPRAM PRODUCT LIST Industrial Temperature Products(-40~85’C) Part Name Function CMP0417AA0-P70I 44-TSOPII, 70ns, VCC=3.0V 1. T=TSOP, P=TSOP(Pb-Free), W=WAFER FUNCTIONAL DESCRIPTION /CS /OE /WE /LB /UB H X1) X1) X1) X1) I/O1-8 I/O9-16 Mode Power High-Z High-Z Deselect/Power-down Standby X1) X1) X1) H H High-Z High-Z Deselect/Power-down Standby H H L X1) High-Z High-Z Output Disabled Active H H X1) L High-Z High-Z Output Disabled Active L H Dout High-Z Lower Byte Read Active L H H L High-Z Dout Upper Byte Read Active L L Dout Dout Word Read Active L L X1) L L H Din High-Z Lower Byte Write Active H L High-Z Din Upper Byte Write Active L L Din Din Word Write Active 1. X means don’t care.(Must be low or high state) ABSOLUTE MAXIMUM RATINGS1) Item Symbol Ratings Unit VIN, VOUT -0.2 to Vcc+0.3V V Voltage on Vcc supply relative to Vss Vcc -0.2 to 3.6 V Power Dissipation PD 1.0 W TSTG -65 to 150 ’C TA -40 to 85 ’C Voltage on any pin relative to Vss Storage temperature Operating Temperature 1 . S t re s s e s gr e a t e r t h a n t h o s e l i st e d u n d e r “A b s olute Maximum Ratings” may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for Industrial periods may affect reliability. RECOMMENDED DC OPERATING CONDITIONS1) CMP0417AA0 Item Symbol Unit Min Max 2.7 3.6 V Supply voltage VCC Ground VSS 0 0 V Input high voltage VIH 0.8VCC VCC+0.22) V Input low voltage VIL -0.23) 0.2VCC V Note : 1.TA=-40 to 85’C, otherwise specified. 2. Overshoot : Vcc+1.0V in case of pulse width≤20ns. 3. Undershoot : -1.0V in case of pulse width≤20ns. 4. Overshoot and undershoot are sampled, not 100% tested. 3 Revision 0.5 Apr. 2007 CMP0417AA0-P70I CAPACITANCE1) CMOS LPRAM (f=1MHz , TA=25’C) Symbol Test Condition Min Max Unit Input capacitance Item CIN VIN=0V - 8 pF Input/Output capacitance CIO VIO=0V - 8 pF 1. Capacitance is sampled, not 100% tested. DC AND OPERATING CHARACTERISTICS Min Typ Max Unit Input leakage current Item Symbol ILI VIN=VSS to VCC Test Conditions -1 - 1 uA Output leakage current ILO /CS=VIH, /OE=VIH or /WE=VIL, VIO=VSS to VCC -1 - 1 uA ICC1 Cycle time=1us, 100%duty, IIO=0mA, /CS≤0.2V, VIN≤0.2V or VIN≥VCC-0.2V - 1.5 3 mA ICC2 Cycle time=Min, IIO=0mA, 100% duty, /CS=VIL, VIN=VIL or VIH - 15 25 mA Output low voltage VOL IOL=0.5mA 0.2VCC V Output high voltage VOH IOH=-0.5mA Standby Current(TTL) ISB /CS=VIH, Other inputs=VIH or VIL - - 0.3 mA Standby Current(CMOS) ISB1 /CS≥VCC-0.2V, Other inputs=0~VCC - - 70 uA Average operating current 0.8VCC 4 V Revision 0.5 Apr. 2007 CMP0417AA0-P70I CMOS LPRAM AC OPERATING CONDITIONS TEST CONDITIONS(Test Load and Input/Output Reference) 1TTL 30pf Input pulse level : 0.2 to VCC-0.2V Input rising and falling time : 5ns Input and output reference voltage : 0.5*VCC Output load(see right) : CL=30pF+1TTL AC CHARACTERISTICS(VCC=2.7V~3.6V, Industrial product : TA=-40 to 85’C) Parameter List 70ns Symbol Units Min Max Read Cycle Time tRC 70 - ns Address Access Time tAA - 70 ns 70 ns Chip Select to Output tCO - Output Enable to Valid Output tOE - 25 ns /UB, /LB Access Time tBA - 70 ns tLZ 10 - ns /UB, /LB Enable to Low-Z Output Chip Select to Low-Z Output tBLZ 10 - ns Output Enable to Low-Z Output tOLZ 5 - ns Read Chip Disable to High- Z Output Write tHZ 0 5 ns /UB, /LB Disable to High- Z Output tBHZ 0 5 ns Output Disable to High- Z Output tOHZ 0 5 ns Output Hold from Address Change tOH 5 - ns Write Cycle Time tWC 70 - ns Chip Select to End of Write tCW 60 - ns Address Set-up Time tAS 0 - ns Address Valid to End of Write tAW 60 - ns /UB, /LB Valid to End of Write tBW 60 - ns Write Pulse Width tWP 50 - ns Write Recovery Time tWR 0 - ns Write to Output High-Z tWHZ 0 5 ns Data to Write Time Overlap tDW 20 - ns Data Hold from Write Time tDH 0 - ns End Write to Output Low-Z tOW 5 - ns tCP 10 - ns /CS High Pulse Width1) 1. /CS High Pulse Width is defined by /CS or (/UB and /LB) because /UB & /LB can make standby mode when /UB=High and /LB=High. 5 Revision 0.5 Apr. 2007 CMP0417AA0-P70I CMOS LPRAM Power Up Sequence 1. Apply Power 2. Maintain stable power for a minimum of 200us with /CS=VIH Standby Mode State machines Power On /CS=VIH Wait min.200us Initial State /CS=VIL, /UB or/and /LB=VIL Active Mode /CS=VIlL /CS=VIH (or/and /UB=/LB=VIH) Standby Mode Standby Mode Characteristics Mode Memory Cell Data Standby Current(uA) Wait Time(us) Standby Valid 70 (ISB1) 0 6 Revision 0.5 Apr. 2007 CMP0417AA0-P70I READ CYCLE (1) CMOS LPRAM (Address controlled,/CS=/OE=VIL, /WE=VIH, /UB or/and /LB=VIL) tRC Address tAA tOH Data Out READ CYCLE (2) Previous Data Valid Data Valid (/WE=VIH) tRC Address tOH tAA tCO /CS tHZ tBA /UB, /LB tBHZ tOE /OE tOLZ Data Out High-Z tOHZ tBLZ tLZ Data Valid 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. 7 Revision 0.5 Apr. 2007 CMP0417AA0-P70I WRITE CYCLE (1) CMOS LPRAM (/WE controlled) tWC Address tCW(2) tWR(4) /CS tAW tBW /UB, /LB tWP(1) /WE tAS(3) tDW Data in tWHZ Data Out WRITE CYCLE (2) tDH Data Valid High-Z High-Z tOW Data Undefined (/CS controlled, /WE=VIH) tWC Address tAS(3) tWR(4) tCW(2) /CS tAW tBW /UB, /LB tWP(1) /WE tDW Data in Data Out WRITE CYCLE (3) tDH Data Valid High-Z High-Z (/UB, /LB controlled) tWC Address tWR(4) tCW(2) /CS tAW tBW /UB, /LB tAS(3) tWP(1) /WE tDW Data in Data Out tDH Data Valid High-Z High-Z 1. A write occurs during the overlap (tWP) of low /CS and /WE. A write begins when /CS goes low and /WE goes low with asserting /UB or /LB for single byte operation or simultaneously asserting /UB and /LB for double byte operation. A write ends at the earliest transition when /CS goes high and WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the /CS going low to end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CS or /WE going high. 8 Revision 0.5 Apr. 2007 CMP0417AA0-P70I CMOS LPRAM PACKAGE DIMENSION Unit : millimeters 44 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400F) 9 Revision 0.5 Apr. 2007