1/4 S T R U C T U R E Silicon Monolithic Integrated Circuit PRODUCT SERIES Strobe Charge Control IC T Y P ＢＤ４２２1NUX E F u n c t i o n s 1. Built-in Low Vth DMOS 45V 2. Adjustable transformer primary-side peak current by RADJ pin 3. Standby mode switching with the START pin. 4. Includes charge complete signal output (FULL) pin. Includes charge voltage detection (VC) pin (can be set externally). 5. Built-in thermal shutdown circuit (TSD). 6. Built-in transformer secondary-side OPEN, SHORT protection. 7. SON 10pin package VSONO10X3020(3.0mm×2.0mm×0.6mm) Built-in under voltage looked out (UVLO). ○ Absolute maximum ratings(Ta=25℃) Parameter VCC pin SW pin VC pin START pin FULL pin IGBT_IN pin Symbol VCC VSW VC START FULL IGBT_IN Limit -0.3 to 7 45 -0.3 to 7 -0.3 to 7 -0.3 to 7 -0.3 to 7 Unit V V V V V V Operating temperature Topr −35 to 85 ℃ Storage temperature range Tstg −55 to 150 ℃ Tjmax 150 ℃ Pd 1540 mW Junction temperature Power dissipation Reduced by 12.32 mW/°C over Ta = 25°C. (When mounted on 74.2 mm 74.2 mm 1.6 mm, glass epoxy) ○ Recommended operating ranges Parameter VCC power supply input voltage range VC pin input voltage range START pin input voltage range IGBT_IN pin input voltage range FULL pin input voltage range Symbol VCC VC VSTART VIGBT_IN VFULL REV. B Limit 2.5 to 5.5 -0.3 to VCC 0 to VCC 0 to VCC 0 to 5.5 Unit V V V V V 2/4 ○ Electrical characteristics (Ta=25℃，VCC=V(START)=3.3 V, V(IGBT_IN)=0V) Limit Parameter Symbol Unit Min. Typ. Max. Conditions [Overall device] VCC circuit current ICC ― 1.5 3 mA Circuit current standby operation ISTB ― ― 1 μA START=0V [Standby control START pin] START pin high voltage VSTH 2 ― ― V START pin low voltage VSTL ― ― 0.6 V ISTART 12 24 36 μA START=3.3V SW=45V Input bias current [Transformer primary-side driver block] SW pin leak current ISWL ― ― 1 μA SW pin peak current IPEAK 0.4 0.5 0.6 A RADJ=100kΩ SW saturation voltage VSAT － 0.2 0.4 V ISW=0.5A RADJ adjustable range RADJ 33 － 100 kΩ Max on time TONMAX 20 40 100 μs Max off time TOFFMAX 10 20 50 μs IVC ― ― 1 μA VFULLTH 0.9875 1 1.0125 V FULL pin ON resistor RFULLL 0.5 1 2 kΩ VC=VCC,FULL=0.5V FULL pin leak current IFULLL － － 1 μA FULL=3.3V UVLO detect voltage VUVLOTH 1.95 2.1 2.25 V UVLO hysteresis VUVLOHYS 120 200 280 mV Output short high current Ioso 90 140 200 mA IGBT_IN=3.3V,START=0V,IGBT_OUT=0V Output short low current Iosi 30 60 90 mA IGBT_IN=3.3V, START=0V,IGBT_OUT=3.3V IGBT_IN input high voltage range1 VIGBTH 2 － － V START=0V IGBT_IN input high voltage range VIGBTL － － 0.6 V START=0V IGBT_IN sink current IIGBT_IN 12 24 36 μA [Charging control block] [Transformer secondary-side detection block] VC pin input current Full charge detection voltage VC=VCC [Protection circuit block] VCC detection [IGBT driver block] IGBT_IN response time Rise Tres_rise1 － 1 2 μs IGBT_IN response time Fall Tres_fall1 － 120 200 ns IGBT_IN response time Rise Tres_rise2 － 15 80 ns IGBT_IN response time Fall Tres_fall2 － 120 200 ns START=0V IGBT_IN→IGBT_OUT response time(rise) START=0V IGBT_IN→IGBT_OUT response time(fall) START=0V IGBT_IN→IGBT_OUT response time(rise) START=3.3V IGBT_IN→IGBT_OUT response time(fall) START=3.3V ◎This product is not designed for normal operation within a radioactive environment REV. B 3/4 ○ Block Diagram Fig.1 ○ Package (UNIT:mm) Block Diagram ○ Pin No. Pin No. 2.0±0.1 B 2 D 1 Pin Name Function 4 2 1 PGND Power GND N 2 IGBT_OUT IGBT driver output 3 GND Ground pin 4 VC 5 VCC VCC supply pin 6 START Standby pin 7 IGBT_IN 8 RADJ primary-side current control pin 9 FULL FULL charge detection flag pin 10 SW Switching pin U □ □ □ □ (0.12) 0.4±0.1 0.64±0.1 +0.03 0.02 -0.02 0.6MAX Lot No. Fig. 2 Marking specification REV. B Secondary–side voltage detection pin nput terminal of trigger signal for starting output of IGBT driver 4/4 ○ Cautions on use 1. Absolute maximum ratings An excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc., can break down the devices, thus making impossible to identify breaking mode, such as a short circuit or an open circuit. If any over rated values will expect to exceed the absolute maximum ratings, consider adding circuit protection devices, such as fuses. 2. GND and PGND potential Ensure a minimum GND and PGND(Except for SW pin and VC pin) pin potential in all operating conditions. In addition, ensure that no pins other than the GND and PGND pin carry a voltage less than or equal to the GND and PGND pin, including during actual transient phenomena. Don’t use VC pin under Absolute Maximum Rating. 3. Thermal design Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions. 4. Protect circuit The IC does not incorporate built-in malfunction protection such as overcurrent protection, short detection, or thermal shutdown circuitry. For this reason, the IC may be damaged if it is shorted or subjected to a load that exceeds the package power. The design of peripheral application circuits should reflect these potential risks. 5. Inter-pin shorts and mounting errors Use caution when positioning the IC for mounting on printed circuit boards. The IC may be damaged if there is any connection error or if positive and ground power supply terminals are reversed. The IC may also be damaged if pins are shorted together or are shorted to other circuit’s power lines. 6. Common impedance The power supply and ground lines must be as short and thick as possible to reduce line impedance. Fluctuating voltage on the power ground line may damage the device. 7. IC Pin Input This is the monolithic IC and has P+ isolation and P substrate for element isolation between each element. By the P layer and N layer of each element, a P-N junction is formed and various parasitic elements are configured. For example, in the case of a resistor and transistor being connected to a pin as shown in Fig.-3; P-N junction operates as a parasitic diode when GND > (Pin A) in the case of the resistor, and when GND > (Pin B) in the case of the transistor (NPN) Also, a parasitic NPN transistor operates by the N layer of another element adjacent to the previous diode in the case of a transistor (NPN) when GND > (Pin B). The parasitic element consequently emerges through the potential relationship because of IC’s structure. The parasitic element pulls interference out of the circuit which may be the cause of malfunction or destruction. Therefore, excessive caution is required to avoid operation of the parasitic element which is caused by applying voltage to an input pin lower than GND (P board), etc. Resistor Transistor (NPN) B E C ～ ～ （Pin A） （Pin B） GND P N N P substrate P N ＋ ＋ P N P P N Ｎ （PinＡ） ＋ ～ ～ P ＋ N Parasitic element P substrate Parasitic element Parasitic Fig.3 El GND t Other adjacent elements REV. B GND Notice Notes No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. 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