High Reliability Series Serial EEPROMs
WL-CSP EEPROM family
I2C BUS
BU9880GUL-W
No.10001EAT19
●Description
2
BU9880GUL-W is a serial EEPROM of I C BUS interface method.
●Features
2
1) Completely conforming to the world standard I C BUS.
All controls available by 2 ports of serial clock (SCL) and serial data (SDA)
2) Other devices than EEPROM can be connected to the same port, saving microcontroller port.
3) 1.7 ~ 5.5V single power source action most suitable for battery use.
4) FAST MODE 400kHz at 1.7 ~ 5.5V
5) Page write mode useful for initial value write at factory shipment.
6) Auto erase and auto end function at data rewrite.
7) Low current consumption
At write operation (5.0V)
: 0.5mA (Typ.)
At read operation (5.0V)
: 0.2mA (Typ.)
At standby operation (5.0V) : 0.1µA (Typ.)
8) Write mistake prevention function
Write (write protect) function added
Write mistake prevention function at low voltage
9) Compact package
10) Data rewrite up to 1,000,000 times
11) Data kept for 40 years
12) Noise filter built in SCL / SDA terminal
13) Shipment data all address FFh
●Page write
Product number
Number of pages
BU9880GUL-W
32Byte
●Absolute maximum ratings (Ta=25℃)
Parameter
Impressed voltage
Permissible dissipation
symbol
Ratings
Unit
VCC
-0.3 ~ 6.5
V
Pd
220
*1
mW
Storage temperature range
Tstg
-65 ~ 125
℃
Action temperature range
Topr
-40 ~ 85
℃
－
-0.3 ~ VCC+1.0 *2
V
Terminal voltage
*1 When using at Ta=25℃or higher, 2.2mW to be reduced per 1℃
*2 The Max value of Terminal Voltage is not over 6.5V.
●Recommended operating conditions
Parameter
Symbol
Ratings
Power source voltage
VCC
1.7 ~ 5.5
Input voltage
VIN
0 ~ VCC
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1/16
Unit
V
2010.11 - Rev.A
Technical Note
BU9880GUL-W
●Memory cell characteristics (Ta=25℃, Vcc=1.7~5.5V)
Limits
Parameter
Number of data rewrite times *1
Data hold years
*1
Unit
Min.
Typ.
Max.
1,000,000
－
－
Times
40
－
－
Years
*1 Not 100% TESTED
●Electrical characteristics (Unless otherwise specified Ta=-40~85℃, VCC=1.7~5.5V)
Limits
Parameter
Symbol
Unit
Min
Typ.
Max.
Condition
"H" Input Voltage1
VIH1
0.7VCC
－
VCC+1.0
V
"L" Input Voltage1
VIL1
－0.3
－
0.3Vcc
V
"L" Output Voltage1
VOL1
－
－
0.4
V
IOL=3.0mA, 2.5V≦VCC≦5.5V(SDA)
"L" Output Voltage2
VOL2
－
－
0.2
V
IOL=0.7mA, 1.7V≦VCC＜2.5V(SDA)
Input Leakage Current
ILI
－1
－
1
µA
VIN=0V ~ VCC
Output Leakage Current
ILO
－1
－
1
µA
VOUT=0V ~ VCC(SDA)
ICC1
－
－
2.0
mA
VCC=5.5V , fSCL =400kHz, tWR=5ms
Byte Write, Page Write
ICC2
－
－
0.5
mA
VCC=5.5V , fSCL =400kHz
Random read, Current read,
Sequential read
ISB
－
－
2.0
µA
VCC=5.5V , SDA・SCL=VCC, WP=GND
Current consumption
at action
Standby Current
○This product is not designed for protection against radioactive rays.
●Action timing characteristics(Unless otherwise specified Ta=-40 ~ 85℃､VCC=1.7 ~ 5.5V)
Parameter
Symbol
Limits
Min.
Typ.
Max.
Unit
SCL Frequency
fSCL
－
－
400
kHz
Data clock "High" time
tHIGH
0.6
－
－
µs
Data clock "Low" time
tLOW
1.2
－
－
µs
tR
－
－
0.3
µs
tF
－
－
0.3
µs
SDA, SCL rise time
SDA, SCL fall time
*1
*1
Start condition hold time
tHD:STA
0.6
－
－
µs
Start condition setup time
tSU:STA
0.6
－
－
µs
Input data hold time
tHD:DAT
0
－
－
ns
Input data setup time
tSU:DAT
100
－
－
ns
tPD
0.1
－
0.9
µs
Output data delay time
Output data hold time
tDH
0.1
－
－
µs
tSU:STO
0.6
－
－
µs
Bus release time before transfer start
tBUF
1.2
－
－
µs
Internal write cycle time
tWR
－
－
5
ms
tI
－
－
0.1
µs
Stop condition data setup time
Noise removal valid period (SDA,SCL terminal)
WP hold time
tHD:WP
0
－
－
ns
WP setup time
tSU:WP
0.1
－
－
µs
WP valid time
tHIGH:WP
1.0
－
－
µs
*1 : Not 100% TESTED
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2/16
2010.11 - Rev.A
Technical Note
BU9880GUL-W
●Sync data input/output timing
tR
tHIGH
tF
SCL
SCL
tSU :DAT
tHD :STA
tLOW
DATA(1)
tHD :DAT
SDA
SDA
(Input)
tPD
tBUF
D1
DATA(n)
D0
ACK
ACK
tWR
tDH
Stop condition
WP
SDA
(Output)
tSU ：WP
○Input read at the rise edge of SCL
○Data output in sync with the fall of SCL
tHD ：
WP
Fig.1-(d) WP timing at write execution
Fig.1-(a) Sync data input / output timing
SCL
tSU :STA
tHD :STA
SCL
tSU :STO
SDA
START BIT
DATA(n)
DATA(1)
SDA
D1
D0
ACK
ACK
tWR
tHIGH:WP
STOP BIT
WP
Fig.1-(b) Start - stop bit timing
○At write execution, in the area from the D0 taken clock rise
of the first DATA(1), to tWR, set WP= 'LOW'.
○By setting WP "HIGH" in the area, write can be cancelled.
When it is set WP = 'HIGH' during tWR, write is forcibly ended,
and data of address under access is not guaranteed, therefore write it
once again.
SCL
SDA
D0
ACK
WRITE DATA(n)
tWR
STOP
CONDITION
Fig.1-(e) WP timing at write cancel
START
CONDITION
Fig.1-(c) Write cycle timing
●Block diagram
A0 1
64Kbit
EEPROM
array
13bit
A1 2
Adddress
decoder
3
Vcc
7
WP
6
SCL
5
SDA
8bit
13bit
START
A2
8
Data
register
Slave - word
address register
STOP
Control circuit
ACK
GND
4
High voltage
generating circuit
Power source
voltage detection
Fig.2 Block
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3/16
diagram
2010.11 - Rev.A
Technical Note
BU9880GUL-W
●Pin assignment and description
C
A2
VSS
A1
B
SDA
A0
A
SCL
1
Fig.3
WP
VCC
2
3
BU9880GUL-W(bottom view)
Land No.
Terminal name
Input / output
Function
C3
A1
Input
Slave address
C2
A2
Input
Slave address
C1
GND
-
B3
A0
Input
B1
SDA
Input / output
A3
Vcc
-
A2
WP
Input
Write protect terminal
A1
SCL
Input
Serial clock input
Reference voltage of all input / output
Slave address
Slave and word address, Serial data input serial data output
Power Supply
●Characteristic data (The following values are Typ. ones.)
6
5
4
3
SPEC
2
1
0.6
L OUTPUT VOLTAGE : VOL(V)
Ta=-40℃
Ta=25℃
Ta=85℃
L INPUT VOLTAGE : VIL(V)
H INPUT VOLTAGE : VIH(V)
6
Ta=-40℃
Ta=25℃
Ta=85℃
5
4
3
2
1
SPEC
0
0
0
1
2
3
4
5
SUPPLY VOLTAGE : Vcc(V)
6
0
1
5
0.4
SPEC
0.2
0
1
2
3
4
5
L OUTPUT CURRENT : IOL(mA)
0.2
0.1
6
Fig.7 'L' output voltage VOL-IOL(Vcc=2.5V)
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1
2
3
4
5
6
7
L OUTPUT CURRENT : IOL(mA)
8
Fig.6 'L' output voltage VOL-IOL(Vcc=1.7V)
1.2
SPEC
1
0.8
0.6
Ta=-40℃
Ta=25℃
Ta=85℃
0.4
0.2
SPEC
1
0.8
0.6
Ta=-40℃
Ta=25℃
Ta=85℃
0.4
0.2
0
0
0
0.3
0
OUTPUT LEAK CURRENT : ILO(uA)
INPUT LEAK CURRENT : ILI(uA)
0.8
Ta=-40℃
Ta=25℃
Ta=85℃
0.4
Ta=-40℃
Ta=25℃
Ta=85℃
0
6
1.2
1
0.6
SPEC
Fig.5 'L' input voltage VIL
(A0,A1,A2,SCL,SDA,WP)
Fig.4 'H' input voltage VIH
(A0,A1,A2,SCL,SDA,WP)
L OUTPUT VOLTAGE : VOL(V)
2
3
4
SUPPLY VOLTAGE : Vcc(V)
0.5
0
1
2
3
4
SUPPLYVOLTAGE : Vcc(V)
5
6
Fig.8 Input leak current ILI
(A0,A1,A2,SCL,WP)
4/16
0
1
2
3
4
5
SUPPLY VOLTAGE : Vcc(V)
6
Fig.9 Output leak current ILO(SDA)
2010.11 - Rev.A
Technical Note
BU9880GUL-W
●Characteristic data (The following values are Typ. ones.)
0.6
2
1.5
Ta=-40℃
Ta=25℃
Ta=85℃
1
0.5
2.5
SPEC
0.5
STANBY CURRENT : ISB(uA)
SPEC
CURRENT CONSUMPTION
AT READING : Icc2(mA)
0.4
Ta=-40℃
Ta=25℃
Ta=85℃
0.3
0.2
0.1
SUPPLY VOLTAGE : Vcc(V)
Fig.10 Current consumption at WRITE operation ICC1
(fscl=400kHz)
Fig.11 Current consumption at READ operation ICC2
(fscl=400kHz)
1
2
3
4
5
0
6
SPEC
100
Ta=-40℃
Ta=25℃
Ta=85℃
10
1
1
6
0
1
2
3
4
5
SUPPLY VOLTAGE : Vcc(V)
4
3
Ta=-40℃
Ta=25℃
Ta=85℃
2
1
6
1
Fig.13 SCL frequency fSCL
2
3
4
5
SUPPLY VOLTAGE : Vcc(V)
1
0
2
3
4
5
SUPPLY VOLTAGE : Vcc(V)
SPEC
0
-50
-100
Ta=-40℃
Ta=25℃
Ta=85℃
-200
1
2
3
4
5
SUPPLY VOLTAGE : Vcc(V)
Ta=-40℃
Ta=25℃
Ta=85℃
SPEC
1
0
0
1
2
3
4
5
SUPPLY VOLTAGE : Vcc(V)
2.9
6
Fig.22 'L' Data output delay time tPD0
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© 2010 ROHM Co., Ltd. All rights reserved.
Ta=-40℃
Ta=25℃
Ta=85℃
1.9
SPEC
0.9
1
2
3
4
5
SUPPLY VOLTAGE : Vcc(V)
100
Ta=-40℃
Ta=25℃
Ta=85℃
-200
1
2
3
4
5
SUPPLY VOLTAGE : Vcc(V)
6
Fig.20 Input Data Setup Time ｔSU: DAT(HIGH)
4
Ta=-40℃
Ta=25℃
Ta=85℃
3
SPEC
2
1
0
0
1
2
3
4
5
SUPPLY VOLTAGE : Vcc(V)
Fig.23 'H' Data output delay time ｔPD1
5/16
Ta=-40℃
Ta=25℃
Ta=85℃
-100
-150
-200
1
2
3
4
5
6
Fig.18 Input Data Hold Time tHD : DAT（HIGH）
SPEC
0
-50
SUPPLY VOLTAGE : Vcc(V)
200
-100
6
SPEC
0
0
300
0
2
3
4
5
SUPPLY VOLTAGE : Vcc（V）
50
6
Fig.17 Start Condition Setup Time tSU : STA
OUTPUT DATA DELAY TIME : tPD(us)
4
2
3.9
6
Fig.19 Input Data Hold Time ｔHD : DAT(LOW）
3
4.9
0
INPUT DATA SET UP TIME : tSU: DAT(ns)
50
0
1
Fig.15 Data clock Low Period tLOW
-0.1
6
Fig.16 Start Condition Hold Time tHD : STA
-150
1
300
200
6
SPEC
100
0
Ta=-40℃
Ta=25℃
Ta=85℃
-100
-200
0
1
2
3
4
5
SUPPLY VOLTAGE : Vcc(V)
6
Fig.21 Input Data setup time tSU : DAT(LOW)
BUS OPEN TIME
BEFORE TRANSMISSION : tBUF(us)
Ta=-40℃
Ta=25℃
Ta=85℃
1
Ta=-40℃
Ta=25℃
Ta=85℃
2
0
INPUT DATA HOLD TIME : tHD: STA(ns)
START CONDITION
SET UP TIME : tSU:STA(uA)
3
0
3
6
5.9
2
SPEC
4
Fig.14 Data clock High Period tHIGH
SPEC
4
6
0
0
5
2
3
4
5
SUPPLY VOLTAGE : Vcc(V)
Fig.12 Stanby operation ISB
0
0
1
5
SPEC
0.1
OUTPUT DATA DELAY TIME : tPD(us)
0.5
ＤＡＴＡ CLK L TIME : tLOW(us)
1000
Ta=-40℃
Ta=25℃
Ta=85℃
1
5
DATA CLK H TIME : tHIGH(uA)
SCL FREQUENCY : fｓｃｌ（ｋHZ）
10000
START CONDITION HOLD TIME : tHD : STA(us)
1.5
0
2
3
4
5
SUPPLY VOLTAGE : Vcc(V)
0
INPUT DATA HOLD TIME : tHD :DAT(ns)
SPEC
2
0
0
INPUT DATA SET UP TIME : tSU : DAT(ns)
CURRENT CONSUMPTION
AT WRITING : Icc1(mA)
2.5
5
Ta=-40℃
Ta=25℃
Ta=85℃
4
3
2
SPEC
1
0
0
1
2
3
4
5
SUPPLY VOLTAGE : Vcc(V)
6
Fig.24 BUS open time before transmission ｔBUF
2010.11 - Rev.A
Technical Note
BU9880GUL-W
●Characteristic data (The following values are Typ. ones.)
SPEC
4
3
2
Ta=-40℃
Ta=25℃
Ta=85℃
1
SPEC
0.8
0.4
0.2
1
2
3
4
5
SUPPLY VOLTAGE : Vcc(V)
0
6
0.5
NOISE REDUCTION
EFFECTIVE TIME : tl(SAD L)(us)
NOISE REDUCTION
EFECTIVE TIME : tl(SDA H)(us)
Ta=-40℃
Ta=25℃
Ta=85℃
0.4
0.3
0.2
SPEC
0.1
0
2
4
SUPPLY VOLATGE : Vcc(V)
6
Fig.28 Noise resuction efecctive time ｔｌ（SDA H）
0.2
SPEC
0.1
0
1
2
3
4
5
SUPPLY VOLTAGE : Vcc(V)
0.5
0.4
0.3
Ta=-40℃
Ta=25℃
Ta=85℃
0.2
SPEC
0.1
6
Fig.27 Noise reduction efective time tl（SCL L）
0.2
SPEC
0.1
0
-0.1
Ta=-40℃
Ta=25℃
Ta=85℃
-0.2
-0.3
-0.4
-0.5
-0.6
0
0
0.3
0
0.6
0.6
0.4
6
Fig.26 Noise reduction efection time tl（SCL H）
Fig.25 Internal writing cycle time ｔWR
WP EFFECTIVE TIME : tHIGH : WP(us)
1
2
3
4
5
SUPPLY VOLTAGE : Vcc(V)
Ta=-40℃
Ta=25℃
Ta=85℃
0.5
0
0
0
Ta=-40℃
Ta=25℃
Ta=85℃
0.6
WP SET UP TIME : tSU : WP(us)
INTERNAL WRITING
CYCLE TIME : tWR(ms)
5
0.6
1
NOISE REDUCTION
EFECTIVE TIME : tl(SCL L)(us)
NOISE REDUCTION
EFECTIVE TIME : tl(SCL H) (us)
6
0
1
2
3
4
5
SUPPLY VOLTAGE : Vcc(V)
6
Fig.29 Noise reduction efective time tl（SDA L）
0
1
2
3
4
5
SUPPLY VOLTAGE : Vcc(V)
6
Fig.30 WP setup time tSU : WP
1.2
SPEC
1
0.8
0.6
0.4
Ta=-40℃
Ta=25℃
Ta=85℃
0.2
0
0
1
2
3
4
5
SUPPLYVOLTAGE : Vcc(V)
6
Fig.31 WP efective time tHIGH : WP
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6/16
2010.11 - Rev.A
Technical Note
BU9880GUL-W
●I2C BUS communication
2
○I C BUS data communication
2
I C BUS data communication starts by start condition input, and ends by stop condition input. Data is always 8bit long,
and acknowledge is always required after each byte.
I2C BUS carries out data transmission with plural devices connected by 2 communication lines of serial data (SDA) and
serial clock (SCL).
Among devices, there are “master” that generates clock and control communication start and end, and “slave” that is
controlled by addresses peculiar to devices.
EEPROM becomes “slave”. And the device that outputs data to bus during data communication is called “transmitter”,
and the device that receives data is called “receiver”.
SDA
1-7
SCL
8
1-7
9
S
START ADDRESS R/W
condition
ACK
8
DATA
9
1-7
ACK
8
9
P
ACK STOP
condition
DATA
Fig.32 Data transfer timing
○Start condition (start bit recognition)
・Before executing each command, start condition (start bit) where SDA goes from 'HIGH' down to 'LOW' when SCL is
'HIGH' is necessary.
・This IC always detects whether SDA and SCL are in start condition (start bit) or not, therefore, unless this condition is
satisfied, any command is executed.
○Stop condition (stop bit recognition)
・Each command can be ended by SDA rising from 'LOW' to 'HIGH' when stop condition (stop bit), namely, SCL is 'HIGH'
○Acknowledge (ACK) signal
・This acknowledge (ACK) signal is a software rule to show whether data transfer has been made normally or not. In
master and slave, the device (µ-COM at slave address input of write command, read command, and this IC at data
output of read command) at the transmitter (sending) side releases the bus after output of 8bit data.
・The device (this IC at slave address input of write command, read command, and µ-COM at data output of read
command) at the receiver (receiving) side sets SDA 'LOW' during 9 clock cycles, and outputs acknowledge signal (ACK
signal) showing that it has received the 8bit data.
・This IC, after recognizing start condition and slave address (8bit), outputs acknowledge signal (ACK signal) 'LOW'.
・Each write action outputs acknowledge signal) (ACK signal) 'LOW', at receiving 8bit data (word address and write data).
・ Each read action outputs 8bit data (read data), and detects acknowledge signal (ACK signal) 'LOW'. When
acknowledge signal (ACK signal) is detected, and stop condition is not sent from the master (µ-COM) side, this IC
continues data output. When acknowledge signal (ACK signal) is not detected, this IC stops data transfer, and
recognizes stop condition (stop bit), and ends read action. And this IC gets in standby status.
○Device addressing
・Output slave address after start condition from master.
・The significant 4 bits of slave address are used for recognizing a device type.
The device code of this IC is fixed to '1010'.
・The most insignificant bit ( R / W --- READ / WRITE ) of slave address is used for designating write or read action,
and is as shown below.
Setting R / W to 0 --- write (setting 0 to word address setting of random read)
Setting R / W to 1 --- read
Type
BU9880GUL-W
Slave address
1
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0
1
0
0
7/16
0
0
R/W
2010.11 - Rev.A
Technical Note
BU9880GUL-W
●Write Command
○Write cycle
・Arbitrary data is written to EEPROM. When to write only 1 byte, byte write normally used, and when to write continuous
data of 2 bytes or more, simultaneous write is possible by page write cycle. The maximum number of write bytes is
specified per device of each capacity.Up to 32 arbitrary bytes can be written.
S
T
A
R
T
SDA
LINE
SLAVE
ADDRESS
W
R
I
T
E
1st WORD
ADDRESS
2nd WORD
ADDRESS
＊ ＊ ＊ WA
12
1 0 1 0 0 0 0
DATA
WA
0
A
C
K
R A
/ C
W K
S
T
O
P
D0
D7
A
C
K
A
C
K
Fig.33 Byte write cycle
S
T
A
R
T
SDA
LINE
SLAVE
ADDRESS
W
R
I
T
E
2nd WORD
ADDRESS(n)
1st WORD
ADDRESS(n)
WA
0
＊ ＊ ＊ WA
1 0 1 0 0 0 0
12
R A
/ C
WK
DATA(n)
D7
A
C
K
A
C
K
S
T
O
P
DATA(n+31)
D0
D0
A
C
K
A
C
K
Fig.34 Page write cycle
・Data is written to the address designated by word address (n-th address).
・By issuing stop bit after 8bit data input, write to memory cell inside starts.
・When internal write is started, command is not accepted for tWR (5ms at maximum).
・By page write cycle, the following can be written in bulk: Up to 32 bytes.
(Refer to "Internal address increment of "Notes on page write cycle" in P9/16.)
・As for page write cycle of BU9880GUL-W , after the significant 7 bits of word address, are designated arbitrarily, by
continuing data input of 2 bytes or more, the address of insignificant 5 bits is incremented internally, and data up to 32
bytes can be written.
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8/16
2010.11 - Rev.A
Technical Note
BU9880GUL-W
○Notes on write cycle continuous input
S
T
A
R
T
SDA
LINE
W
R
I
T
E
SLAVE
ADDRESS
1 0 1 0 A2 A1A0
WORD
ADDRESS(n)
WA
7
R A
/ C
WK
DATA(n)
WA
0
D7
DATA(n+31)
D0
A
C
K
At STOP (stop bit)
write starts.
S
T
O
P
D0
1 0 1 0
A
C
K
A
C
K
Next command
tWR(maximum：5ms)
Command is not accepted
for this period.
Fig.35
○Notes on page write cycle
List of numbers of page write
Product number
Number of pages
BU9880GUL-W
Page write cycle
○Internal address increment
Page write mode
32Byte
WA12 ----0
----0
----0
-----
The above numbers are maximum bytes for respective
types. Any bytes below these can be written.
0
0
0
1
1
0
WA3
0
0
0
1Eh
0
0
0
-------------
WA2
0
0
0
WA1 WA0
0
0
0
1
1
0
Iincrement
---------
WA4
0
0
0
---------
In the case of BU9880GUL-W, 1 page = 32bytes,
but the page write cycle write time is 5ms at maximum
for 32byte bulk write. It does not stand 5ms
at maximum × 32byte = 160ms(Max.).
WA5
0
0
0
1
1
0
1
1
0
0
1
0
1
0
0
Significant bit is fixed.
No digit up
For example, when it is started from address 1Eh,
therefore, increment is made as below,
1Eh→1Fh→00h→01h･･･
* 1Eh･･･16 in hexadecimal, therefore,
00011110 becomes a binary number.
○Write protect (WP) terminal
・Write protect (WP) function
When WP terminal is set Vcc (H level), data rewrite of all address is prohibited. When it is set GND (L level),
data rewrite of all address is enabled. Be sure to connect this terminal to Vcc or GND, or control it to H level or L level.
Do not use it open. At extremely low voltage at power ON/OFF, by setting the WP terminal 'H', mistake write can be
prevented. During tWR, set the WP terminal always to 'L'. If it is set 'H', write is forcibly terminated.
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9/16
2010.11 - Rev.A
Technical Note
BU9880GUL-W
●Read Command
○Read cycle
Data of EEPROM is read. In read cycle, there are random read cycle and current read cycle.
Random read cycle is a command to read data by designating address, and is used generally.
Current read cycle is a command to read data of internal address register without designating address, and is used when
to verify just after write cycle. In both the read cycles, sequential read cycle is available, and the next address data can
be read in succession.
S
T
A
R
T
SDA
LINE
W
R
I
T
E
SLAVE
ADDRESS
2nd WORD
ADDRESS(n)
1st WORD
ADDRESS(n)
WA
0
WA
＊ ＊ ＊ 12
10 10 0 0 0
S
T
A
R
T
R A
/ C
WK
A
C
K
R
E
A
D
SLAVE
ADDRESS
1 0 1 0 A2A1A0
A
C
K
S
T
O
P
DATA(n)
D7
It is necessary to input 'H'
to the last ACK.
D0
R A
/ C
W K
A
C
K
Fig.36 Random read cycle
S
T
A
R
T
SDA
LINE
SLAVE
ADDRESS
R
E
A
D
DATA(n)
1 0 1 0 0 0 0
D7
It is necessary to input 'H'
to the last ACK.
S
T
O
P
D0
A
C
K
R A
/ C
WK
Fig.37 Current read cycle
S
T
A
R
T
SDA
LINE
SLAVE
ADDRESS
R
E
A
D
1 0 1 0 0 0 0
DATA(n+x)
DATA(n)
D7
R A
/ C
W K
S
T
O
P
D0
D7
A
C
K
A
C
K
D0
A
C
K
Fig.38 Sequential read cycle (in the case of current read cycle)
・In random read cycle, data of designated word address can be read.
・When the command just before current read cycle is random read cycle, current read cycle (each including sequential
read cycle), data of incremented last read address (n)-th address, i.e., data of the (n+1)-th address is output.
・When ACK signal 'LOW' after D0 is detected, and stop condition is not sent from master (µ-COM) side, the next address
data can be read in succession.
・Read cycle is ended by stop condition where 'H' is input to ACK signal after D0 and SDA signal is started at SCL signal 'H'.
・When 'H' is not input to ACK signal after D0, sequential read gets in, and the next data is output.
Therefore, read command cycle cannot be ended. When to end read command cycle, be sure input stop condition to
input 'H' to ACK signal after D0, and to start SDA at SCL signal 'H'.
・Sequential read is ended by stop condition where 'H' is input to ACK signal after arbitrary D0 and SDA is started at SCL
signal 'H'.
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10/16
2010.11 - Rev.A
Technical Note
BU9880GUL-W
●Software reset
Software reset is executed when to avoid malfunction after power on, and to reset during command input. Software reset
has several kinds, and 3 kids of them are shown in the figure below. (Refer to Fig.39(a), Fig.39(b), Fig.39(c).) In dummy
clock input area, release the SDA bus ('H' by pull up). In dummy clock area, ACK output and read data '0' (both 'L' level)
may be output from EEPROM, therefore, if 'H' is input forcibly, output may conflict and over current may flow, leading to
instantaneous power failure of system power source or influence upon devices.
Start×2
Dummy clock×14
SCL
1
2
13
Normal command
14
SDA
Normal command
Fig.39-(a) The case of 14 Dummy clock + START + START+ command input
SCL
Start
Dummy clock×9
Start
1
2
8
Normal command
9
SDA
Normal command
Fig.39-(b) The case of START+9 Dummy clock + START + command input
Start×9
SCL
1
2
3
7
8
9
Normal command
SDA
Normal command
Fig.39-(c) START × 9 + command input
* Start command from START input.
●Acknowledge polling
During internal write, all input commands are ignored, therefore ACK is not sent back. During internal automatic write
execution after write cycle input, next command (slave address) is sent, and if the first ACK signal sends back 'L', then it
means end of write action, while if it sends back 'H', it means now in writing. By use of acknowledge polling, next command
can be executed without waiting for tWR = 5ms.
When to write continuously, R / W = 0, when to carry out current read cycle after write, slave address R / W = 1 is sent,
and if ACK signal sends back 'L', then execute word address input and data so forth.
During internal write,
First write command
S
T
A
R
T
Write command
ACK = HIGH is sent back.
S
T
Slave
A
R address
T
S
T
O
P
A
C
K
H
tWR
S
T
A
R
T
A
C
address K
H
Slave
…
Second write command
…
S
T
A
R
T
A
C
address K
H
Slave
S
T
A
R
T
A
C
address K
L
Slave
Word
address
A
C
K
L
Data
A
C
K
L
S
T
O
P
tWR
After completion of internal
write, ACK=LOW is sent back,
so input next word address and
data in succession.
Fig.40 Case to continuously write by acknowledge polling
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11/16
2010.11 - Rev.A
Technical Note
BU9880GUL-W
●WP valid timing (write cancel)
WP is usually fixed to 'H' or 'L', but when WP is used to cancel write cycle and so forth, pay attention to the following WP
valid timing. During write cycle execution, in cancel valid area, by setting WP='H', write cycle can be cancelled. In both byte
write cycle and page write cycle, the area from the first start condition of command to the rise of clock to taken in D0 of
data(in page write cycle, the first byte data) is cancel invalid area.
WP input in this area becomes Don't care. Set the setup time to rise of D0 taken 100ns or more. The area from the rise of
SCL to take in D0 to the end of internal automatic write (tWR) is cancel valid area. And, when it is set WP='H' during tWR,
write is ended forcibly, data of address under access is not guaranteed, therefore, write it once again.(Refer to Fig.41.) After
execution of forced end by WP standby status gets in, so there is no need to wait for tWR (5ms at maximum).
・Rise of D0 taken clock
SCL
SCL
・Rise of SDA
SDA
D1
D0
ACK
SDA
SDA
S
T
A
R
T
ACK
D0
Enlarged view
Enlarged view
A
A
C Word C D7 D6 D5 D4 D3 D2 D1 D0
K address K
address
L
L
Slave
WP cancel invalid area
A
C
K
L
Data
A
C
K
L
WP cancel valid area
S
T
O
P
tWR
Write forced end
WP
Data is not written.
Data not guaranteed
Fig.41 WP valid timing
●Command cancel by start condition and stop condition
During command input, by continuously inputting start condition and stop condition, command can be cancelled. (Refer to
Fig. 42.) However, in ACK output area and during data read, SDA bus may output 'L', and in this case, start condition and
stop condition cannot be input, so reset is not available. Therefore, execute software reset. And when command is
cancelled by start, stop condition, during random read cycle, sequential read cycle, or current read cycle, internal setting
address is not determined, therefore, it is not possible to carry out current read cycle in succession. When to carry out read
cycle in succession, carry out random read cycle.
SCL
SDA
1
0
1
0
Start condition
Stop condition
Fig.42 Case of cancel by start, stop condition during slave address input
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12/16
2010.11 - Rev.A
Technical Note
BU9880GUL-W
●Cautions on microcontroller connection
○Rs
2
In I C BUS, it is recommended that SDA port is of open drain input/output. However, when to use CMOS input / output of
tri state to SDA port, insert a series resistance Rs between the pull up resistance Rpu and the SDA terminal of EEPROM.
This is controls over current that occurs when PMOS of the microcontroller and NMOS of EEPROM are turned ON
simultaneously. Rs also plays the role of protection of SDA terminal against surge. Therefore, even when SDA port is
open drain input/output, Rs can be used.
ACK
SCL
RS
SDA
'H' output of microcontroller
'L' output of EEPROM
Microcontroller
EEPROM
Over current flows to SDA line by 'H'
output of microcontroller and 'L' output
of EEPROM.
Fig.44 Input/output collision timing
Fig.43 I/O circuit diagram
○Maximum value of Rs
The maximum value of Rs is determined by following relations.
(1) SDA rise time to be determined by the capacity (CBUS) of bus line of Rpu and SDA shoulder be tR or below.
And AC timing should be satisfied even when SDA rise time is late.
A to be determined by Rpu and Rs the moment when EEPROM outputs 'L' to SDA bus
(2) The bus electric potential ○
should sufficiently secure the input 'L' level (VIL) of microcontroller including recommended noise margin 0.1Vcc.
(VCC－VOL)×RS
RPU+RS
VCC
A
RPU=10ｋΩ
RS
IOL
VIL
∴ RS ≦
VOL
+ VOL+0.1VCC≦VIL
VIL－VOL－0.1VCC
1.1VCC－VIL
× RPU
Example) When VCC=3V, VIL=0.3VCC, VOL=0.4V, RPU=10kΩ,
from(2),
Bus line
capacity CBUS
RS ≦
EEPROM
Microcontroller
0.3×3－0.4－0.1×3
1.1×3－0.3×3
× 10×103
≦ 0.835［kΩ］
Fig.45 I/O circuit diagram
○Maximum value of Rs
The minimum value of Rs is determined by over current at bus collision. When over current flows, noises in power source
line, and instantaneous power failure of power source may occur. When allowable over current is defined as I, the
following relation must be satisfied. Determine the allowable current in consideration of impedance of power source line
in set and so forth. Set the over current to EEPROM 10mA or below.
RPU=10Ω
'L' output
RS
∴
VCC
RS
≦
I
RS
≧
VCC
I
Over currentⅠ
Example）When VCC=3V, I=10mA
'H' output
Microcontroller
RS
EEPROM
≧
3
10×10-3
Fig.46 I/O circuit diagram
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13/16
2010.11 - Rev.A
Technical Note
BU9880GUL-W
●I2C BUS input / output circuit
○Input (A0, A1, A2, SCL, SDA)
Fig.47 Input pin circuit diagram
○Input/Output (SDA)
Fig.48 Input /output pin circuit diagram
●Notes on power ON
At power on, in IC internal circuit and set, Vcc rises through unstable low voltage area, and IC inside is not completely reset,
and malfunction may occur. To prevent this, functions of POR circuit and LVCC circuit are equipped. To assure the action,
observe the following condition at power on.
1. Set SDA = 'H' and SCL ='L' or 'H'
2. Start power source so as to satisfy the recommended conditions of tR, tOFF, and Vbot for operating POR circuit.
tR
VCC
Recommended conditions of tR, tOFF, Vbot
tOFF
tR
tOFF
Vbot
10ms or below
10ms or higher
0.3V or below
100ms or below
10ms or higher
0.2V or below
Vbot
0
Fig.49 Rise waveform diagram
3. Set SDA and SCL so as not to become 'Hi-Z'.
When the above conditions 1 and 2 cannot be observed, take the following countermeasures.
a) In the case when the above conditions 1 cannot be observed. When SDA becomes 'L' at power on .
→Control SCL and SDA as shown below, to make SCL and SDA, 'H' and 'H'.
VCC
tLOW
SCL
SDA
After Vcc becomes stable
After Vcc becomes stable
tDH
tSU:DAT
Fig.50 When SCL='H' and SDA='L'
tSU:DAT
Fig.51 When SCL='H' and SDA='L'
b) In the case when the above condition 2 cannot be observed.
→After power source becomes stable, execute software reset(P26).
c) In the case when the above conditions 1 and 2 cannot be observed.
→Carry out a), and then carry out b).
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14/16
2010.11 - Rev.A
Technical Note
BU9880GUL-W
●Low voltage malfunction prevention function
LVCC circuit prevents data rewrite action at low power, and prevents wrong write.
At LVCC voltage (Typ. =1.2V) or below, it prevent data rewrite.
●VCC noise countermeasures
○Bypass capacitor
When noise or surge gets in the power source line, malfunction may occur, therefore, for removing these, it is
recommended to attach a by pass capacitor (0.1µF) between IC Vcc and GND. At that moment, attach it as close to IC as
possible. And, it is also recommended to attach a bypass capacitor between board Vcc and GND.
●Notes for use
(1) Described numeric values and data are design representative values, and the values are not guaranteed.
(2) We believe that application circuit examples are recommendable, however, in actual use, confirm characteristics further
sufficiently. In the case of use by changing the fixed number of external parts, make your decision with sufficient margin in
consideration of static characteristics and transition characteristics and fluctuations of external parts and our LSI.
(3) Absolute maximum ratings
If the absolute maximum ratings such as impressed voltage and action temperature range and so forth are exceeded, LSI
may be destructed. Do not impress voltage and temperature exceeding the absolute maximum ratings. In the case of fear
exceeding the absolute maximum ratings, take physical safety countermeasures such as fuses, and see to it that
conditions exceeding the absolute maximum ratings should not be impressed to LSI.
(4) GND electric potential
Set the voltage of GND terminal lowest at any action condition. Make sure that each terminal voltage is lower than that of
GND terminal.
(5) Terminal design
In consideration of permissible loss in actual use condition, carry out heat design with sufficient margin.
(6) Terminal to terminal shortcircuit and wrong packaging
When to package LSI onto a board, pay sufficient attention to LSI direction and displacement. Wrong packaging may
destruct LSI. And in the case of shortcircuit between LSI terminals and terminals and power source, terminal and GND
owing to foreign matter, LSI may be destructed.
(7) Use in a strong electromagnetic field may cause malfunction, therefore, evaluate design sufficiently.
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15/16
2010.11 - Rev.A
Technical Note
BU9880GUL-W
●Ordering part number
B
U
Part No.
9
8
8
0
Part No.
G
U
L
Package
GUL : VCSP50L1
- W
W-CELL
E
2
Packaging and forming specification
E2: Embossed tape and reel
VCSP50L1(BU9880GUL-W)
<Tape and Reel information>
0.55MAX
1.98±0.05
0.1±0.05
1.59±0.05
1PIN MARK
Tape
Embossed carrier tape (heat sealing method)
Quantity
3000pcs
Direction
of feed
S
E2
The direction is the 1pin of product is at the upper left when you hold
( reel on the left hand and you pull out the tape on the right hand
)
(φ0.15)INDEX POST
A
C
B
B
A
1
0.49±0.05
2
P=0.5×2
8-φ0.25±0.05
0.05 A B
0.295±0.05
0.06 S
3
1pin
P=0.5×2
(Unit : mm)
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Reel
16/16
Direction of feed
∗ Order quantity needs to be multiple of the minimum quantity.
2010.11 - Rev.A
Notice
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the
consent of ROHM Co.,Ltd.
The content specified herein is subject to change for improvement without notice.
The content specified herein is for the purpose of introducing ROHM's products (hereinafter
"Products"). If you wish to use any such Product, please be sure to refer to the specifications,
which can be obtained from ROHM upon request.
Examples of application circuits, circuit constants and any other information contained herein
illustrate the standard usage and operations of the Products. The peripheral conditions must
be taken into account when designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specified in this document.
However, should you incur any damage arising from any inaccuracy or misprint of such
information, ROHM shall bear no responsibility for such damage.
The technical information specified herein is intended only to show the typical functions of and
examples of application circuits for the Products. ROHM does not grant you, explicitly or
implicitly, any license to use or exercise intellectual property or other rights held by ROHM and
other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the
use of such technical information.
The Products specified in this document are intended to be used with general-use electronic
equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices).
The Products specified in this document are not designed to be radiation tolerant.
While ROHM always makes efforts to enhance the quality and reliability of its Products, a
Product may fail or malfunction for a variety of reasons.
Please be sure to implement in your equipment using the Products safety measures to guard
against the possibility of physical injury, fire or any other damage caused in the event of the
failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM
shall bear no responsibility whatsoever for your use of any Product outside of the prescribed
scope or not in accordance with the instruction manual.
The Products are not designed or manufactured to be used with any equipment, device or
system which requires an extremely high level of reliability the failure or malfunction of which
may result in a direct threat to human life or create a risk of human injury (such as a medical
instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuelcontroller or other safety device). ROHM shall bear no responsibility in any way for use of any
of the Products for the above special purposes. If a Product is intended to be used for any
such special purpose, please contact a ROHM sales representative before purchasing.
If you intend to export or ship overseas any Product or technology specified herein that may
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More detail product informations and catalogs are available, please contact us.
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R1010A