204Pin DDR3 1600 1.35V SO-DIMM 4GB Based on 512Mx8 AQD-SD3L4GN16-SG Advantech AQD-SD3L4GN16-SG Datasheet Rev. 1.1 2013-09-24 1 204Pin DDR3 1600 1.35V SO-DIMM 4GB Based on 512Mx8 AQD-SD3L4GN16-SG Description Pin Identification Pin Identification AQD-SD3L4GN16-SG is DDR3 Unbuffered SO-DIMM, non-ECC, high-speed, low power memory module that Symbol use 8 pcs of 512Mx8bits DDR3 low voltage SDRAM in A0~A15, BA0~BA2 Address/Bank input FBGA package and a 2048 bits serial EEPROM on a DQ0~DQ63 Data Input / Output. DQS0~DQS7 Data strobes /DQS0~/DQS7 Differential Data strobes CK0, /CK0,CK1, /CK1 Clock Input. (Differential pair) use of system clock. Data I/O transactions are possible CKE0, CKE1 Clock Enable Input. on both edges of DQS. Range of operation frequencies, ODT0, ODT1 On-die termination control line programmable latencies allow the same device to be /CS0, /CS1 DIMM Rank Select Lines. useful for a variety of high bandwidth, high performance /RAS Row Address Strobe /CAS Column Address Strobe /WE Write Enable DM0~DM7 Data masks/high data strobes JEDEC standard 1.35V(1.28V~1.45V) Power supply VDD Voltage power supply JEDEC standard 1.5V(1.425V~1.575V) Power supply VREFDQ/ VREFCA Power Supply for Reference VDDQ=1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V) VDDSPD SPD EEPROM Power Supply 204-pin printed circuit board. AQD-SD3L4GN16-SG is a Dual In-Line Memory Module and is intended for Function mounting into 204-pin edge connector sockets. Synchronous design allows precise cycle control with the memory system applications. Features RoHS compliant products. Clock Freq: 800MHZ for 1600Mb/s/Pin. I2C serial bus address select for SA0~SA2 Programmable CAS Latency: 5, 6, 7, 8, 9, 10, 11 EEPROM Programmable Additive Latency (Posted /CAS): SCL I2C serial bus clock for EEPROM SDA I2C serial bus data for EEPROM VSS Ground /RESET Set DRAMs Known State Burst Length: 4, 8 VTT SDRAM I/O termination supply Bi-directional Differential Data-Strobe NC No Connection 0,CL-2 or CL-1 clock Programmable /CAS Write Latency (CWL) = 8(DDR3-1600) 8 bit pre-fetch Internal calibration through ZQ pin On Die Termination with ODT pin Serial presence detect with EEPROM Asynchronous reset 2 204Pin DDR3 1600 1.35V SO-DIMM 4GB Based on 512Mx8 AQD-SD3L4GN16-SG Dimensions (Unit: millimeter) Note: 1. Tolerances on all dimensions +/-0.15mm unless otherwise specified. 3 204Pin DDR3 1600 1.35V SO-DIMM 4GB Based on 512Mx8 AQD-SD3L4GN16-SG Pin Assignments Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin No Name No Name No Name No Name No Name No 01 VREFDQ 69 DQ27 137 DQS4 02 VSS 70 DQ31 138 03 VSS 71 VSS 139 VSS 04 DQ4 72 VSS 140 05 DQ0 73 CKE0 141 DQ34 06 DQ5 74 CKE1,NC 142 07 DQ1 75 VDD 143 DQ35 08 VSS 76 VDD 144 09 VSS 77 NC 145 VSS 10 /DQS0 78 A15 146 11 DM0 79 BA2 147 DQ40 12 DQS0 80 A14 148 13 VSS 81 VDD 149 DQ41 14 VSS 82 VDD 150 15 DQ2 83 A12 151 VSS 16 DQ6 84 A11 152 17 DQ3 85 A9 153 DM5 18 DQ7 86 A7 154 19 VSS 87 VDD 155 VSS 20 VSS 88 VDD 156 21 DQ8 89 A8 157 DQ42 22 DQ12 90 A6 158 23 DQ9 91 A5 159 DQ43 24 DQ13 92 A4 160 25 VSS 93 VDD 161 VSS 26 VSS 94 VDD 162 27 /DQS1 95 A3 163 DQ48 28 DM1 96 A2 164 29 DQS1 97 A1 165 DQ49 30 /RESET 98 A0 166 31 VSS 99 VDD 167 VSS 32 VSS 100 VDD 168 33 DQ10 101 CK0 169 /DQS6 34 DQ14 102 CK1,NC 170 35 DQ11 103 /CK0 171 DQS6 36 DQ15 104 /CK1,NC 172 37 VSS 105 VDD 173 VSS 38 VSS 106 VDD 174 39 DQ16 107 A10/AP 175 DQ50 40 DQ20 108 BA1 176 41 DQ17 109 BA0 177 DQ51 42 DQ21 110 /RAS 178 43 VSS 111 VDD 179 VSS 44 VSS 112 VDD 180 45 /DQS2 113 /WE 181 DQ56 46 DM2 114 /CS0 182 47 DQS2 115 /CAS 183 DQ57 48 VSS 116 ODT0 184 49 VSS 117 VDD 185 VSS 50 DQ22 118 VDD 186 51 DQ18 119 A13 187 DM7 52 DQ23 120 ODT1,NC 188 53 DQ19 121 /CS1,NC 189 VSS 54 VSS 122 NC 190 55 VSS 123 VDD 191 DQ58 56 DQ28 124 VDD 192 57 DQ24 125 TEST 193 DQ59 58 DQ29 126 VREFCA 194 59 DQ25 127 VSS 195 VSS 60 VSS 128 VSS 196 61 VSS 129 DQ32 197 SA0 62 /DQS3 130 DQ36 198 63 DM3 131 DQ33 199 VDDSPD 64 DQS3 132 DQ37 200 65 VSS 133 VSS 201 SA1 66 VSS 134 VSS 202 67 DQ26 135 /DQS4 203 Vtt 68 DQ30 136 DM4 204 /CS1,ODT1,CKE1：Used for dual-rank SO-DIMMs; NC on single-rank SO-DIMMs. CK1 and /CK1：Used for dual-rank SO-DIMMs; not used on single-rank SO-DIMMs but terminated. 4 Pin Name VSS DQ38 DQ39 VSS DQ44 DQ45 VSS /DQS5 DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS /DQS7 DQS7 VSS DQ62 DQ63 VSS NC SDA SCL Vtt 204Pin DDR3 1600 1.35V SO-DIMM 4GB Based on 512Mx8 AQD-SD3L4GN16-SG Block Diagram 4GB, 512Mx64 Module(1 Rank x8) /S0 /DQS4 DQS4 DQ DM4 32 /DQS0 DQS0 DM0 DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 /DQS1 DQS1 DM1 DQ 8 DQ 9 DQ 10 DQ 11 DQ 12 DQ 13 DQ 14 DQ /DQS2 15 DQ DQS2 16 DM2 DQ 17 DQ 18 DQ 19 DQ 20 DQ 21 DQ 22 /DQS3 DQ DQS3 DQ 23 DM3 24 DQ 25 DQ 26 DQ 27 DQ 28 DQ 29 DQ 30 DQ BA0~BA2 31 A0~A15 CKE0 /RAS /CAS /WE ODT0 CK0 /CK0 DQ 33 DQ 34 DQ 35 DQ 36 DQ 37 DQ 38 /DQS5 DQ DQS5 DQ 39 DM5 40 D /C DQS/DQS M S I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D0 D /C DQS/DQS M S I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ 41 DQ 42 DQ 43 DQ 44 DQ 45 DQ 46 /DQS6 DQ DQS6 47 48 DM6 DQ 49 DQ 50 DQ 51 DQ 52 DQ 53 DQ 54 /DQS7 DQ DQS7 DQ 55 DM7 56 DQ 57 DQ 58 DQ 59 DQ 60 DQ 61 DQ EEPRO 62 DQ M 63 D1 D /C DQS/DQS M S I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D2 D /C DQS/DQS M S I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D3 BA0–BA2: SDRAMs D0–D7 A0-A15: SDRAMs D0–D7 CKE: SDRAMs D0–D7 /RAS: SDRAMs D0–D7 /CAS: SDRAMs D0–D7 /WE: SDRAMs D0–D7 ODT: SDRAMs D0–D7 CK: SDRAMs D0–D7 /CK: SDRAMs D0–D7 SC L D /C DQS/DQS M S I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D4 D /C DQS/DQS M S I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D5 D /C DQS/DQS M S I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D6 D /C DQS/DQS M S I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 WP A0 A1 A2 SA0SA1SA2 NOTE: D7 VDDSP D SD VDD/VDDQ VREFD A QVS VREFC S A EEPRO M D0~D7 D0~D7 D0~D7 D0~D7 1. DQ-to-I/O wiring is shown as recommended but may be 2. changed. DQ,DQS,/DQS,ODT,DM,CKE,/S relationships must be 3. maintained as shown. DQ,DM,DQS,/DQS resistors: Refer to associated topology diagram. This technical information is based on industry standard data and tests believed to be reliable. However, Advantech makes no warranties, either expressed or implied, as to its accuracy and assume no liability in connection with the use of this product. Advantech reserves the right to make changes in specifications at any time without prior notice. 5 204Pin DDR3 1600 1.35V SO-DIMM 4GB Based on 512Mx8 AQD-SD3L4GN16-SG Operating Temperature Condition Parameter Symbol Rating Unit Operating Temperature TOPER 0 to 85 C Note: Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard. Note 1,2 Absolute Maximum DC Ratings Parameter Symbol Value Unit Note Voltage on VDD relative to Vss VDD -0.4 ~ 1.975 V 1 Voltage on VDDQ pin relative to Vss VDDQ -0.4 ~ 1.975 V 1 Voltage on any pin relative to Vss VIN, VOUT -0.4 ~ 1.975 V 1 Storage temperature TSTG -55~+100 C 1,2 1. Stress greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the Note: device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard. AC & DC Operating Conditions Recommended DC operating conditions Rating Parameter Symbol Voltage Unit Notes Min Typ. Max 1.35V 1.283 1.35 1.45 V 1.5V 1.425 1.5 1.575 1.35V 1.283 1.35 1.45 V Supply voltage for Output VDDQ 1.5V 1.425 1.5 1.575 I/O Reference Voltage (DQ) VREFDQ(DC) 1.35V 0.49*VDDQ 0.50*VDDQ 0.51*VDDQ V I/O Reference Voltage (CMD/ADD) VREFCA(DC) 1.5V 0.49*VDDQ 0.50*VDDQ 0.51*VDDQ V 1.35V VREF+0.160 V AC Input Logic High VIH(AC) 1.5V VREF+0.175 1.35V VREF-0.160 V AC Input Logic Low VIL(AC) 1.5V VREF-0.175 1.35V VREF+0.09 VDD V DC Input Logic High VIH(DC) 1.5V VREF+0.1 VDD 1.35V VSS VREF-0.09 V DC Input Logic Low VIL(DC) 1.5V VSS VREF-0.1 Note: 1. Under all conditions VDDQ must be less than or equal to VDD. 2. VDDQ tracks with VDD, AC parameters are measured with VDD and VDDQ tied together. 3. Peak to peak AC noise on VREF may not allow deviate from VREF(DC) by more than +/-1% VDD. Supply voltage VDD 6 1, 2 1, 2 3 3 204Pin DDR3 1600 1.35V SO-DIMM 4GB Based on 512Mx8 AQD-SD3L4GN16-SG IDD Specification parameters Definition( IDD values are for full operating range of Voltage and Temperature) 4GB, 512Mx64 Module(1 Rank x8) Parameter Operating One bank Active-Precharge current; tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD); CKE is HIGH, /CS is HIGH between valid commands;Address bus inputs are SWITCHING; Data bus inputs are SWITCHING Symbol DDR3 1600 CL11 Unit IDD0 675 mA IDD1 768 mA IDD2P 296 mA IDD2Q 376 mA IDD2N 400 mA IDD3P 504 mA IDD3N 496 mA IDD4R 1553 mA IDD4W 1390 mA IDD5 1819 mA IDD6 176 mA IDD7 2413 mA Operating One bank Active-read-Precharge current; IOUT = 0mA; BL = 8, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD = tRCD(IDD); CKE is HIGH, /CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W Precharge power-down current; All banks idle; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge quiet standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, /CS is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, /CS is HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Active power - down current; All banks open; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Active standby current; All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, /CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, /CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W Operating burst write current; All banks open, Continuous burst writes; BL = 8, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, /CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING IDD4R Burst refresh current; tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, /CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Self refresh current; CK and /CK at 0V; CKE ≒ 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 8, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), Trc = tRC(IDD), tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS is HIGH between valid commands;Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R; Note: 1.Module IDD was calculated on the specific brand DRAM(4xnm) component IDD and can be differently measured according to DQ loading capacitor. 7 204Pin DDR3 1600 1.35V SO-DIMM 4GB Based on 512Mx8 AQD-SD3L4GN16-SG Timing Parameters & Specifications Speed Parameter DDR3 1600 Unit Symbol Min Max Average Clock Period tCK 1.25 <1.5 ns CK high-level width tCH 0.47 0.53 tCK CK low-level width tCL 0.47 0.53 tCK tDQSQ - 100 ps tQH 0.38 - tCK tLZ(DQ) -450 225 ps tHZ(DQ) - 225 tDS 10 - tDH 45 tDIPW 360 - ps tRPRE 0.9 - tCK DQS, /DQS to DQ skew, per group, per access DQ output hold time from DQS, /DQS DQ low-impedance time from CK, /CK DQ high-impedance time from CK, /CK Data setup time to DQS, /DQS reference to Vih(ac)Vil(ac) levels Data hold time to DQS, /DQS reference to Vih(ac)Vil(ac) levels DQ and DM input pulse width for each input ps ps ps DQS, /DQS Read preamble DQS, /DQS differential Read postamble DQS, /DQS Write preamble tRPST 0.3 - tCK tWPRE 0.9 - tCK DQS, /DQS Write postamble tWPST 0.3 - tCK tLZ(DQS) -450 225 ps - 225 ps 0.45 0.55 tCK 0.45 0.55 tCK -0.27 +0.27 tCK 0.18 - tCK 0.18 - tCK Max (4tck, 7.5ns) - DQS, /DQS low-impedance time DQS, /DQS high-impedance time tHZ(DQS) DQS, /DQS differential input low pulse tDQSL width DQS, /DQS differential input high tDQSH pulse width DQS, /DQS rising edge to CK, /CK tDQSS rising edge DQS, /DQS falling edge setup time to tDSS CK, /CK rising edge DQS, /DQS falling edge hold time to tDSH CK, /CK rising edge Delay from start of Internal write tWTR transaction to Internal read command Write recovery time tWR 15 - ns Mode register set command cycle time tMRD 4 - tCK /CAS to /CAS command delay tCCD 4 - nCK 8 204Pin DDR3 1600 1.35V SO-DIMM 4GB Based on 512Mx8 AQD-SD3L4GN16-SG Auto precharge write recovery + precharge time Active to active command period for 1KB page size Speed Parameter Active to active command period for 2KB page size Four Activate Window for 1KB page size Four Activate Window for 2KB page size products tDAL tRRD tWR+tRP/tck Max (4tck, 6ns) nCK - DDR3 1600 Unit Min Max (4tck, 7.5ns) Max tFAW 30 - ns tFAW 40 - ns Power-up and RESET calibration time tZQinitl 512 - tCK Normal operation Full calibration time tZQoper 256 - tCK tZQcs 64 - tCK tXS Max (5tCK, tRFC+10ns) - tXSDLL tDLL(min) - Normal operation short calibration time Exit self refresh to commands not requiring a locked DLL Exit self refresh to commands requiring a locked DLL Internal read to precharge command delay Minimum CKE low width for Self refresh entry to exit timing Exit power down with DLL to any valid command: Exit Precharge Power Down with DLL CKE minimum pulse width (high and low pulse width) Asynchronous RTT turn-on delay (Power-Down mode) Asynchronous RTT turn-off delay (Power-Down mode) ODT turn-on ODT turn-off Symbol ns tRRD Max tRTP (4tck, 7.5ns) tCKESR tCK(min)+1tCK Max tXP (3tCK, 6ns) - tCK - tCKE Max (3tCK, 5ns) tAONPD 2 8.5 ns tAOFPD 2 8.5 ns tAON -225 225 ps tAOF 0.3 0.7 tCK 9 204Pin DDR3 1600 1.35V SO-DIMM 4GB Based on 512Mx8 AQD-SD3L4GN16-SG SERIAL PRESENCE DETECT SPECIFICATION AQD-CSD3L4G16N-SG Serial Presence Detect Byte No. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32-59 Function Described Standard Specification CRC:0-116Byte Number of SPD Bytes written / SPD device size / CRC SPD Byte use: 176Byte coverage during module production SPD Byte total: 256Byte SPD Revision Version 1.0 Key Byte / DRAM Device Type DDR3 SDRAM Key Byte / Module Type SODIMM SDRAM Density and Banks 4Gb 8banks SDRAM Addressing ROW:16, Column:10 Module Nominal Voltage, VDD 1.35V and 1.5V Module Organization 1Rank / x8 Module Memory Bus Width Non ECC, 64bit Fine Timebase Dividend and Divisor 2.5ps Medium Timebase Dividend 0.125ns Medium Timebase Divisor 0.125ns SDRAM Minimum Cycle Time (tCKmin) 1.25ns Reserved CAS Latencies Supported, Least Significant Byte 5, 6, 7, 8, 9,10,11 CAS Latencies Supported, Most Significant Byte Minimum CAS Latency Time (tAAmin) 13.125ns Minimum Write Recovery Time (tWRmin) 15ns Minimum /RAS to /CAS Delay Time (tRCDmin) 13.125ns Minimum Row Active to Row Active Delay Time 6ns (tRRDmin) Minimum Row Precharge Time (tRPmin) 13.125ns Upper Nibble for tRAS and tRC Minmum Active to Precharge Time (tRASmin) 35ns Minmum Active to Active/Refresh Time (tRCmin) 48.125ns Minmum Refresh Recovery Time (tRFCmin), Least 260ns Significant Byte Minmum Refresh Recovery Time (tRFCmin), Most 260ns Significant Byte Minmum Internal Write to Read Command Delay Time 7.5ns (tWTmin) Minimum Internal Read to Precharge Command Delay 7.5ns Time (tRTPmin) Upper Nibble for tFAW 30ns Minmum Four Active Window Delay Time (tFAWmin) 30ns DLL off Mode, SDRAM Optional Features RZQ/6, RZQ/7 SDRAM Thermal and Refresh Options No ODTs, No ASR Reserved 10 Vendor Part 92 10 0B 03 04 21 02 01 03 52 01 08 0A 00 FE 00 69 78 69 30 69 11 18 81 20 08 3C 3C 00 F0 83 01 00 204Pin DDR3 1600 1.35V SO-DIMM 4GB Based on 512Mx8 AQD-SD3L4GN16-SG 60 61 62 63 64-116 117 118 119 120-121 122-125 126-127 Module Nominal Height Module Max Thickness Reference Raw Card Used Address Mapping from Edge Connector to DRAM Reserved Module Manufacturer ID Code, Least Significant Byte Module Manufacturer ID Code, Most Significant Byte Module Manufacturing Location Module Manufacturing Date Module Serial Number Cyclical Redundancy Code 30mm Planar Double Sides R/C B Standard Transcend Transcend Taipei - 0F 11 21 00 00 01 4F 54 00 00 4A, 3E 41 51 44 2D 53 128-145 Module Part Number AQD-SD3L4GN16-SG 33 4C 34 47 4E 31 36 2D 53 47 20 146-147 148-149 150-175 176-255 Revision Code DRAM Manufacturer ID Code Manufacturer Specific Data Open for customer use By Manufacturer By Manufacturer Undefined 11 44 00 Variable Variable 00 20