32-BIT MICROCONTROLLER
FM4 Family
Analog Macro Part
PERIPHERAL MANUAL
For the information for microcontroller supports, see the following web site.
http://www.spansion.com/support/microcontrollers/
Publication Number FM4_MN709-00003
CONFIDENTIAL
Revision 4.0
Issue Date May 27, 2015
P E R I P H E R A L
2
CONFIDENTIAL
M A N U A L
FM4_MN709-00003-4v0-E, May 27, 2015
P E R I P H E R A L
M A N U A L
Preface
Thank you for your continued use of Cypress products.
Read this manual and "Data Sheet" thoroughly before using products in this family.
Purpose of This Manual and Intended Readers
This manual explains the functions and operations of this family and describes how it is used. The manual is
intended for engineers engaged in the actual development of products using this family.
For the descriptions on Analog macro, Timer, and Communication Macro, see the respective separate
peripheral manual.
Note:
−
This manual explains the configuration and operation of the peripheral functions, but does not cover
the specifics of each device in the series.
Users should refer to the respective data sheets of devices for device-specific details.
Trademark
ARM and Cortex are the registered trademarks of ARM Limited in the EU and other countries.
The company names and brand names herein are the trademarks or registered trademarks of their
respective owners.
Sample Programs and Development Environment
Cypress offers sample programs free of charge for using the peripheral functions of the FM4 family. Cypress
also makes available descriptions of the development environment required for this family. Feel free to use
them to verify the operational specifications and usage of this Cypress microcontroller.
Microcontroller Support Information:
http://www.spansion.com/support/microcontrollers/
Note:
−
Note that the sample programs are subject to change without notice. Since they are offered as a
way to demonstrate standard operations and usage, evaluate them sufficiently before running them
on your system.
Cypress assumes no responsibility for any damage that may occur as a result of using a sample
program.
Overall Organization of This Manual
Peripheral Manual Timer part has 2 chapters and Appendixes as shown below.
CHAPTER 1-1: A/D Converter
CHAPTER 1-2: 10-bit A/D Converter
CHAPTER 1-3: A/D Timer Trigger Selection
CHAPTER 2: 12-bit D/A Converter
Appendixes
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Related Manuals
The manuals related to this family are listed below. See the manual appropriate to the applicable conditions.
The contents of these manuals are subject to change without notice. Contact us to check the latest versions
available.
Peripheral Manual
FM4 Family Peripheral Manual (MN709-00001)
Called Peripheral Manual hereafter
FM4 Family Peripheral Manual Timer Part (MN709-00002)
Called Timer Part hereafter
FM4 Family Peripheral Manual Analog Macro Part (this manual)
Called Analog Macro Part hereafter
FM4 Family Peripheral Manual Communication Macro Part (MN709-00004)
Called Communication Macro Part hereafter
FM4 Family Peripheral Manual GDC Part (MN709-00014)
Called GDC Part hereafter
Data Sheet
For details about device-specific, electrical characteristics, package dimensions, ordering information etc.,
see the following document.
32-bit Microcontroller FM4 Family Data Sheet
Note:
−
The data sheets for each series are provided.
See the appropriate data sheet for the series that you are using.
CPU Programming Manual
For details about ARM Cortex-M4F core, see the following documents that can be obtained from
http://www.arm.com/.
Cortex-M4 Technical Reference Manual
ARMv7-M Architecture Application Level Reference Manual
Flash Programming Manual
For details about the functions and operations of the built-in flash memory, see the following document.
FM4 Family Flash Programming Manual
Note:
−
4
CONFIDENTIAL
Flash programming manuals for each series are provided.
See the appropriate flash programming manual for the series that you are using.
FM4_MN709-00003-4v0-E, May 27, 2015
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How to Use This Manual
Finding a Function
The following methods can be used to search for the explanation of a desired function in this manual:
Search from the table of the contents
The table of the contents lists the manual contents in the order of description.
Search from the register
The address where each register is located is not described in the text. To verify the address of a
register, see A. Register Map in Appendixes.
About the Chapters
Basically, this manual explains 1 peripheral function per chapter.
Terminology
This manual uses the following terminology.
Term
Explanation
Word
Indicates access in units of 32 bits.
Half word
Indicates access in units of 16 bits.
Byte
Indicates access in units of 8 bits.
Notations
The notations in bit configuration of the register explanation of this manual are written as follows.
− bit:
bit number
− Field:
bit field name
− Attribute:
Attributes for read and write of each bit
−
R:
−
W:
−
R/W:
−
-:
− Initial value:
Read only
Write only
−
−
−
0:
1:
Initial value is 0
Initial value is 1
X:
Initial value is undefined
Readable/Writable
Undefined
Initial value of the register after reset
The multiple bits are written as follows in this manual.
Example : bit7:0 indicates the bits from bit7 to bit0
The values such as for addresses are written as follows in this manual.
− Hexadecimal number:
0x is attached in the beginning of a value as a prefix
(example : 0xFFFF)
− Binary number:
− Decimal number :
May 27, 2015, FM4_MN709-00003-4v0-E
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0b is attached in the beginning of a value as a prefix
(example: 0b1111)
Written using numbers only (example : 1000)
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The Target Products in This Manual
In this manual, the products are classified into the following groups and are described follows.
For the descriptions such as TYPE1-M4, see the relevant items of the target product in the list below.
Table 1 TYPE1-M4 Product List
Flash memory size
Description in
this manual
1024 Kbytes
768 Kbytes
512 Kbytes
MB9BF567M
MB9BF566M
MB9BF567N
MB9BF566N
MB9BF567R
MB9BF566R
MB9BF468M
MB9BF467M
MB9BF466M
MB9BF468N
MB9BF467N
MB9BF466N
MB9BF568M
MB9BF568N
MB9BF568R
MB9BF568RF
TYPE1-M4
MB9BF468R
MB9BF467R
MB9BF466R
MB9BF368M
MB9BF367M
MB9BF366M
MB9BF368N
MB9BF367N
MB9BF366N
MB9BF368R
MB9BF367R
MB9BF366R
MB9BF168M
MB9BF167M
MB9BF166M
MB9BF168N
MB9BF167N
MB9BF166N
MB9BF168R
MB9BF167R
MB9BF166R
Table 2 TYPE2-M4 Product list
Flash memory size
Description in
this manual
TYPE2-M4
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CONFIDENTIAL
512 Kbytes
384 Kbytes
256 Kbytes
MB9BF566K
MB9BF565K
MB9BF564K
MB9BF566L
MB9BF565L
MB9BF564L
MB9BF466K
MB9BF465K
MB9BF464K
MB9BF466L
MB9BF465L
MB9BF464L
MB9BF366K
MB9BF365K
MB9BF364K
MB9BF366L
MB9BF365L
MB9BF364L
MB9BF166K
MB9BF165K
MB9BF164K
MB9BF166L
MB9BF165L
MB9BF164L
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Table 3 TYPE3-M4 Product List
Flash memory size
Description
in this
2 Mbytes
manual
1.5 Mbytes
1 Mbytes
S6E2CC9 L0AGL20
S6E2CC8 LHAGL20
S6E2CCA L0AGL20
S6E2CCA LHAGL20
S6E2CCAJ0AGV20
S6E2CCAJHAGV20
S6E2CCAJ0AGB10
S6E2CCAJHAGB10
S6E2CCAH0AGV20
S6E2CCAHHAGV20
S6E2CCAJGAGV20
S6E2CCAJGAGB10
S6E2CC9 LHAGL20
S6E2CC8J0AGV20
S6E2CC9J0AGV20
S6E2CC8JHAGV20
S6E2CC9JHAGV20
S6E2CC8J0AGB10
S6E2CC9J0AGB10
S6E2CC8JHAGB10
S6E2CC9JHAGB10
S6E2CC8H0AGV20
S6E2CC9H0AGV20
S6E2CC8HHAGV20
S6E2CC9HHAGV20
S6E2CC8JGAGB10
-
S6E2CC8JFAGB10
S6E2C5A L0AGL20
S6E2C59 L0AGL20
S6E2C58 L0AGL20
S6E2C5AJ0AGV20
S6E2C59J0AGV20
S6E2C58J0AGV20
S6E2C5AJ0AGB10
S6E2C59J0AGB10
S6E2C58J0AGB10
S6E2C5AH0AGV20
S6E2C59H0AGV20
S6E2C58H0AGV20
S6E2C4A L0AGL20
S6E2C49 L0AGL20
S6E2C48 L0AGL20
S6E2C4AJ0AGV20
S6E2C49J0AGV20
S6E2C48J0AGV20
S6E2C4AJ0AGB10
S6E2C49J0AGB10
S6E2C48J0AGB10
S6E2C4AH0AGV20
S6E2C49H0AGV20
S6E2C48H0AGV20
S6E2C3A L0AGL20
S6E2C39 L0AGL20
S6E2C38 L0AGL20
S6E2C3AJ0AGV20
S6E2C39J0AGV20
S6E2C38J0AGV20
S6E2C3AJ0AGB10
S6E2C39J0AGB10
S6E2C38J0AGB10
S6E2C3AH0AGV20
S6E2C39H0AGV20
S6E2C38H0AGV20
S6E2C2A L0AGL20
S6E2C29 L0AGL20
S6E2C28L0AGL20
S6E2C2A LHAGL20
S6E2C29 LHAGL20
S6E2C28LHAGL20
S6E2C2AJ0AGV20
S6E2C29J0AGV20
S6E2C28J0AGV20
S6E2C2AJHAGV20
S6E2C29JHAGV20
S6E2C28JHAGV20
S6E2C2AJ0AGB10
S6E2C29J0AGB10
S6E2C28J0AGB10
S6E2C2AJHAGB10
S6E2C29JHAGB10
S6E2C28JHAGB10
S6E2C2AH0AGV20
S6E2C29H0AGV20
S6E2C28H0AGV20
S6E2C2AHHAGV20
S6E2C29HHAGV20
S6E2C28HHAGV20
-
-
-
-
S6E2C1AL0AGL20
S6E2C19L0AGL20
S6E2C18L0AGL20
S6E2C10H2AGV20
S6E2C1AJ0AGV20
S6E2C19J0AGV20
S6E2C18J0AGV20
S6E2C10J2AGV20
S6E2C1AJ0AGB10
S6E2C19J0AGB10
S6E2C18J0AGB10
S6E2C10J2AGB10
S6E2C1AH0AGV20
S6E2C19H0AGV20
S6E2C18H0AGV20
S6E2C10L2AGL20
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SRAM size
256 Kbytes
S6E2CC8 L0AGL20
S6E2CCAJFAGB10
TYPE3-M4
No-Flash
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Table 4 TYPE4-M4 Product List
Flash memory size
Description in this
manual
384 Kbytes
VRAM 512 Kbytes
VRAM 512 Kbytes
+
VFLASH 2 Mbytes
S6E2D35G0AGB30
S6E2D35G0AGV20
S6E2D35G0AGE20
S6E2D35GJAMV20
S6E2D35J0AGV20
S6E2D55G0AGB30
S6E2D55G0AGV20
S6E2D55G0AGE20
S6E2D55GJAMV20
S6E2D55J0AGV20
TYPE4-M4
S6E2DF5G0AGB30
S6E2DF5G0AGV20
S6E2DF5G0AGE20
S6E2DF5GJAMV20
S6E2DF5J0AGV20
S6E2DH5G0AGB30
S6E2DH5G0AGV20
S6E2DH5G0AGE20
S6E2DH5GJAMV20
S6E2DH5J0AGV20
8
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Table 5 TYPE5-M4 Product List
Flash memory size
Description in
this manual
TYPE5-M4
1 Mbytes
512 Kbytes
S6E2GM8JHAGV20
S6E2GM6JHAGV20
S6E2GM8J0AGV20
S6E2GM6J0AGV20
S6E2GM8HHAGV20
S6E2GM6HHAGV20
S6E2GM8H0AGV20
S6E2GM6H0AGV20
S6E2GK8JHAGV20
S6E2GK6JHAGV20
S6E2GK8J0AGV20
S6E2GK6J0AGV20
S6E2GK8HHAGV20
S6E2GK6HHAGV20
S6E2GK8H0AGV20
S6E2GK6H0AGV20
S6E2GH8J0AGV20
S6E2GH6J0AGV20
S6E2GH8H0AGV20
S6E2GH6H0AGV20
S6E2G28JHAGV20
S6E2G28J0AGV20
S6E2G28HHAGV20
S6E2G28H0AGV20
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CONFIDENTIAL
S6E2G26JHAGV20
S6E2G26J0AGV20
S6E2G26H0AGV20
S6E2G38J0AGV20
S6E2G36J0AGV20
S6E2G38H0AGV20
S6E2G36H0AGV20
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Table 6 TYPE6-M4 Product List
Flash memory size
Description in
this manual
TYPE6-M4
10
CONFIDENTIAL
512 Kbytes
256 Kbytes
S6E2HG6G0AGV20
S6E2HG4G0AGV20
S6E2HG6F0AGV20
S6E2HG4F0AGV20
S6E2HG6E0AGV20
S6E2HG4E0AGV20
S6E2HG6G0AGB10
S6E2HG4G0AGB10
S6E2HE6G0AGV20
S6E2HE4G0AGV20
S6E2HE6F0AGV20
S6E2HE4F0AGV20
S6E2HE6E0AGV20
S6E2HE4E0AGV20
S6E2HE6G0AGB10
S6E2HE4G0AGB10
S6E2H46G0AGV20
S6E2H44G0AGV20
S6E2H46F0AGV20
S6E2H44F0AGV20
S6E2H46E0AGV20
S6E2H44E0AGV20
S6E2H46G0AGB10
S6E2H44G0AGB10
S6E2H16G0AGV20
S6E2H14G0AGV20
S6E2H16F0AGV20
S6E2H14F0AGV20
S6E2H16E0AGV20
S6E2H14E0AGV20
S6E2H16G0AGB10
S6E2H14G0AGB10
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Table of Contents
CHAPTER 1-1: A/D Converter ..................................................................................................................... 15
1. Configuration..................................................................................................................................... 16
2. Functions and Operations ................................................................................................................. 18
3. Usage Precautions............................................................................................................................ 19
CHAPTER 1-2: 12-bit A/D Converter .......................................................................................................... 21
1. Overview ........................................................................................................................................... 22
2. Configuration..................................................................................................................................... 23
3. Explanation of Operations ................................................................................................................. 24
3.1. Enabling Operations of the A/D Converter ............................................................................ 25
3.2. A/D Conversion Operation .................................................................................................... 26
3.2.1. Scan Conversion Operation .................................................................................... 27
3.2.2. Priority Conversion Operation ................................................................................. 29
3.2.3. Priority Levels and State Transitions ....................................................................... 30
3.3. FIFO Operations ................................................................................................................... 32
3.3.1. FIFO Operations in Scan Conversion ...................................................................... 33
3.3.2. Interrupts in Scan Conversion ................................................................................. 34
3.3.3. FIFO Operations in Priority Conversion ................................................................... 36
3.3.4. Interrupts in Priority Conversion .............................................................................. 37
3.3.5. Validity of FIFO Data ............................................................................................... 38
3.3.6. Bit placement Selection for FIFO Data Registers .................................................... 39
3.4. A/D Comparison Function ..................................................................................................... 40
3.5. Range Comparison Function ................................................................................................ 41
3.6. Starting DMA ........................................................................................................................ 45
4. Setup procedure Examples ............................................................................................................... 46
4.1. A/D Operation Enable Setup Procedure Example ................................................................ 47
4.2. Scan Conversion Setup Procedure Example ........................................................................ 48
4.3. Priority Conversion Setup Procedure Example ..................................................................... 49
4.4. Range Comparison Function Setting Example ..................................................................... 50
4.5. Setting Conversion Time....................................................................................................... 52
5. Registers ........................................................................................................................................... 53
5.1. A/D Control Register (ADCR) ............................................................................................... 54
5.2. A/D Status Register (ADSR) ................................................................................................. 56
5.3. Scan Conversion Control Register (SCCR) .......................................................................... 58
5.4. Scan Conversion FIFO Stage Count Setup Register (SFNS) ............................................... 60
5.5. Scan Conversion FIFO Data Register (SCFD) ..................................................................... 61
5.6. Scan Conversion Input Selection Register (SCIS) ................................................................ 63
5.7. Priority Conversion Control Register (PCCR) ....................................................................... 64
5.8. Priority Conversion FIFO Stage Count Setup Register (PFNS) ............................................ 66
5.9. Priority Conversion FIFO Data Register (PCFD) .................................................................. 67
5.10. Priority Conversion Input Selection Register (PCIS) ........................................................... 69
5.11. A/D Comparison Value Setup Register (CMPD) ................................................................. 70
5.12. A/D Comparison Control Register (CMPCR) ...................................................................... 71
5.13. Sampling Time Selection Register (ADSS) ......................................................................... 72
5.14. Sampling Time Setup Register (ADST) .............................................................................. 73
5.15. Frequency Division Ratio Setup Register (ADCT) .............................................................. 75
5.16. A/D Operation Enable Setup Register (ADCEN)................................................................. 76
5.17. Upper Limit Setup Register (WCMPDH) ............................................................................. 77
5.18. Range Comparison Control Register (WCMPCR) .............................................................. 78
5.19. Lower Limit Threshold Setup Register (WCMPDL) ............................................................. 80
5.20. Range Comparison Channel Select Register (WCMPSR) .................................................. 81
5.21. Range Comparison Threshold Excess Flag Register (WCMRCOT) ................................... 82
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5.22. Range Comparison Flag Register (WCMRCIF) .................................................................. 83
CHAPTER 1-3: A/D Timer Trigger Selection .............................................................................................. 85
1. Overview ........................................................................................................................................... 86
2. Registers ........................................................................................................................................... 87
2.1. Scan Conversion Timer Trigger Selection Register (SCTSL) ............................................... 88
2.2. Priority Conversion Timer Trigger Selection Register (PRTSL) ............................................ 89
CHAPTER 1-4: A/D Converter Offset Caribration...................................................................................... 91
1. Overview ........................................................................................................................................... 92
2. Configuration Block Diagram ............................................................................................................ 93
3. Operation .......................................................................................................................................... 94
3.1. Operation of A/D Converter Offset Calibration ...................................................................... 94
3.1.1. Setting the Value for Offset Calibration.................................................................... 94
3.1.2. A/D Converter Offset Calibration ............................................................................. 95
3.1.3. A/D Converter Offset Calibration Setting Example .................................................. 98
3.1.4. Calculation of Offset Calibration Value .................................................................... 98
4. Setting Procedure Example .............................................................................................................. 99
5. Register List .................................................................................................................................... 101
5.1. Calibration Setting Register (CALSR) ................................................................................. 102
6. Usage Precautions.......................................................................................................................... 103
CHAPTER 2: 12-bit D/A Converter............................................................................................................ 105
1. Overview ......................................................................................................................................... 106
2. Configuration................................................................................................................................... 107
3. Operations ...................................................................................................................................... 108
4. Example of Setting Procedure ........................................................................................................ 110
5. Registers ......................................................................................................................................... 111
5.1. D/A Control Register (DACR) ............................................................................................. 112
5.2. D/A Data Register (DADR) ................................................................................................. 113
Appendixes ................................................................................................................................................ 115
A. Register Map .................................................................................................................................. 116
1. Register Map................................................................................................................................... 118
1.1. FLASH_IF ........................................................................................................................... 119
1.1.1. TYPE1-M4, TYPE2-M4 products ............................................................................ 119
1.1.2. TYPE3-M4 product ................................................................................................ 120
1.1.3. TYPE4-M4, TYPE5-M4, TYPE6-M4 products ....................................................... 121
1.2. Unique ID ............................................................................................................................ 122
1.3. ECC Capture Address ........................................................................................................ 122
1.4. Clock/Reset ........................................................................................................................ 123
1.4.1. TYPE1-M4, TYPE2-M4 products ........................................................................... 123
1.4.2. TYPE3-M4, TYPE4-M4, TYPE5-M4, TYPE6-M4 products .................................... 125
1.5. HW WDT............................................................................................................................. 127
1.6. SW WDT ............................................................................................................................. 127
1.7. Dual_Timer ......................................................................................................................... 128
1.8. MFT .................................................................................................................................... 129
1.8.1. TYPE1-M4, TYPE2-M4 products ........................................................................... 129
1.8.2. TYPE3-M4, TYPE4-M4, TYPE5-M4, TYPE6-M4 products .................................... 132
1.9. PPG .................................................................................................................................... 135
1.10. Base Timer ....................................................................................................................... 138
1.11. IO Selector for Base Timer ............................................................................................... 139
1.12. QPRC ............................................................................................................................... 140
1.12.1. TYPE1-M4, TYPE2-M4, TYPE6-M4 products ..................................................... 140
1.12.2. TYPE3-M4, TYPE4-M4, TYPE5-M4 products ..................................................... 141
1.13. QPRC NF .......................................................................................................................... 142
1.14. A/DC ................................................................................................................................. 143
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1.15. CR Trim ............................................................................................................................ 144
1.16. EXTI .................................................................................................................................. 145
1.16.1. TYPE1-M4, TYPE2-M4, TYPE3-M4, TYPE4-M4 products .................................. 145
1.16.2. TYPE5-M4, TYPE6-M4 products ......................................................................... 145
1.17. INT-Req. READ ................................................................................................................ 146
1.17.1. TYPE1-M4, TYPE2-M4, TYPE6-M4 products ..................................................... 146
1.17.2. TYPE3-M4, TYPE5-M4 product .......................................................................... 152
1.17.3. TYPE4-M4 product .............................................................................................. 159
1.18. D/AC ................................................................................................................................. 166
1.19. HDMI-CEC ........................................................................................................................ 167
1.20. GPIO ................................................................................................................................. 168
1.20.1. TYPE1-M4, TYPE2-M4, TYPE6-M4 products ..................................................... 168
1.20.2. TYPE3-M4 product .............................................................................................. 175
1.20.3. TYPE4-M4 product .............................................................................................. 184
1.20.4. TYPE5-M4 product .............................................................................................. 192
1.21. LVD ................................................................................................................................... 201
1.22. DS_Mode .......................................................................................................................... 201
1.23. USB Clock ........................................................................................................................ 202
1.24. CAN_Prescaler ................................................................................................................. 203
1.25. MFS .................................................................................................................................. 203
1.26. CRC .................................................................................................................................. 205
1.27. Watch Counter .................................................................................................................. 205
1.28. RTC .................................................................................................................................. 206
1.28.1. TYPE1-M4, TYPE2-M4, TYPE3-M4, TYPE6-M4 products .................................. 206
1.28.2. TYPE4-M4 product .............................................................................................. 209
1.28.3. TYPE5-M4 product .............................................................................................. 213
1.29. Low-speed CR Prescaler .................................................................................................. 214
1.30. Peripheral Clock Gating .................................................................................................... 215
1.30.1. TYPE1-M1, TYPE2-M4 products ......................................................................... 215
1.30.2. TYPE3-M4, TYPE4-M4 products ......................................................................... 215
1.30.3. TYPE5-M4, TYPE6-M4 products ......................................................................... 216
1.31. Smart Card Interface......................................................................................................... 217
1.32. MFSI2S ............................................................................................................................. 218
1.33. I2S Prescaler .................................................................................................................... 219
1.33.1. TYPE1-M4, TYPE2-M4, TYPE3-M4 products ..................................................... 219
1.33.2. TYPE4-M4 product .............................................................................................. 220
1.34. GDC_Prescaler ................................................................................................................. 221
1.35. EXT-Bus I/F ...................................................................................................................... 222
1.35.1. TYPE1-M4 product .............................................................................................. 222
1.35.2. TYPE3-M4, TYPE4-M4, TYPE5-M4, TYPE6-M4 products .................................. 225
1.36. USB .................................................................................................................................. 228
1.37. DMAC ............................................................................................................................... 230
1.38. DSTC ................................................................................................................................ 232
1.39. CAN .................................................................................................................................. 234
1.40. Ethernet-MAC ................................................................................................................... 236
1.41. Ethernet-Control................................................................................................................ 236
1.42. I2S .................................................................................................................................... 237
1.43. SD-Card ............................................................................................................................ 237
1.44. CAN FD ............................................................................................................................ 238
1.45. Programmable-CRC ......................................................................................................... 241
1.46. WorkFlash_IF.................................................................................................................... 241
1.47. High-Speed Quad SPI Controller ...................................................................................... 242
1.47.1. TYPE1-M4, TYPE2-M4, TYPE3-M4 products ..................................................... 242
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P E R I P H E R A L
M A N U A L
1.47.2. TYPE4-M4 product .............................................................................................. 245
1.48. HyperBus Interface ........................................................................................................... 248
1.49. GDC Sub System Controller ............................................................................................. 249
1.50. GDC Sub System SDRAM Controller ............................................................................... 252
B List of Notes..................................................................................................................................... 253
1. Notes When High-speed CR is Used for the Master Clock ............................................................. 254
Major Changes ........................................................................................................................................... 256
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CHAPTER 1-1: A/D Converter
This chapter explains the functions and operations of the A/D converter.
1. Configuration
2. Functions and Operations
3. Usage Precautions
CODE: 9BFADCTOP_FM4-E01.0
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CHAPTER 1-1: A/D Converter
1. Configuration
P E R I P H E R A L
1.
M A N U A L
Configuration
The A/D converter converts analog input voltage from an external pin to a digital value.
A/D Converter Configuration
The maximum 3 units of A/D converters with 12-bit resolution have been installed.
Any channel can be selected to any unit from the maximum 32 channels of analog input.
The following triggers can be selected as an activation trigger for A/D conversion.
− Priority conversion activation trigger
Trigger input from an external pin
Timer trigger input (base timer or multifunction timer)
Software activation
− Scan conversion activation trigger
Timer trigger input (base timer or multifunction timer)
Software activation
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CHAPTER 1-1: A/D Converter
1. Configuration
P E R I P H E R A L
M A N U A L
Figure 1-1 shows a block diagram of the A/D converter with the related circuits.
Figure 1-1 Block Diagram of the A/D Converter with the Related Circuits
SE L
ADC0 scan activation in multifunction timer unit 0
ADC0 scan activation in multifunction timer unit 1
ADC0 scan activation in multifunction timer unit 2
Scan conversion
timer activation
Base timer ch.0 to ch.13 output(14 triggers)
SE L
ADC0 priority activation in multifunction timer unit 0
ADC0 priority activation in multifunction timer unit 1
ADC0 priority activation in multifunction timer unit 2
Priority
coversion
timer activation
ADC
unit 1
Base timer ch.0 to ch.13 output(14 triggers)
Priority coversion
external trigger activation
S EL
ADC1 scan activation in multifunction timer unit 0
ADC1 scan activation in multifunction timer unit 1
ADC1 scan activation in multifunction timer unit 2
Analog signal
external input pin
Scan conversion
timer activation
AN00
Base timer ch.0 to ch.13 output(14 triggers)
AN01
A/D activation trigger
extrenal pin
S EL
ADC1 priority activation in multifunction timer unit 0
ADC1 priority activation in multifunction timer unit 1
ADC1 priority activation in multifunction timer unit 2
Priority
coversion
timer activation
ADC
unit 1
Base timer ch.0 to ch.13 output(14 triggers)
A na log Se lect or
AN02
AN03
AN04
ADTG_0
ADTG_2
I/O port
selection circuit
ADTG_1
Priority coversion
external trigger activation
AN31
ADTG_8
S EL
ADC2 scan activation in multifunction timer unit 0
ADC2 scan activation in multifunction timer unit 1
ADC2 scan activation in multifunction timer unit 2
Scan conversion
timer activation
Base timer ch.0 to ch.13 output(14 triggers)
S EL
ADC2 priority activation in multifunction timer unit 0
ADC2 priority activation in multifunction timer unit 1
ADC2 priority activation in multifunction timer unit 2
Priority
coversion
timer activation
ADC
unit 1
Base timer ch.0 to ch.13 output(14 triggers)
P riority con version
external trigger activation
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CHAPTER 1-1: A/D Converter
2. Functions and Operations
P E R I P H E R A L
2.
M A N U A L
Functions and Operations
See descriptions of the following related chapters for functions and operations of the A/D converter.
12-bit A/D Converter Operation
See the chapter of 12-bit A/D Converter for conversion operations of 12-bit A/D converter.
12-bit A/D Timer Trigger Select Operation
See the chapter of A/D Timer Trigger Selection for operations of 12-bit A/D converter timer trigger selection.
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CHAPTER 1-1: A/D Converter
3. Usage Precautions
P E R I P H E R A L
3.
M A N U A L
Usage Precautions
This section shows the notes.
Notes on 12-bit A/D Converter
Simultaneous A/D conversion of multiple channels is possible on the products that have multiple A/D
converters.
Do not select the same input channel with the multiple units.
Some channels of an analog input cannot be used for certain products. Do not change the selection
registers (SCIS0, SCIS1, SCIS2, and SCIS3) and the sampling time selection registers (ADSS0, ADSS1,
ADSS2, and ADSS3) for the channels which cannot be used from their initial values.
In this family, P1A[2:0] of the priority conversion input selection register (PCIS) should be selected for an
analog input channel during priority conversion. Always write 0 to ESCE bit of the priority conversion
control register (PCCR) of the 12-bit A/D converter.
DMA transfer using the A/D interrupt request generation of this family supports only DMA transfer using
generation of a scan conversion interrupt request. DMA transfer using a priority conversion interrupt
request is not supported.
Product specifications and Number of channels mounted
The number of analog inputs mounted and the number of base timer channels used for AD Startup trigger
are different by products.
For details, see Product Configuration in Data Sheet of the product used.
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CHAPTER 1-1: A/D Converter
3. Usage Precautions
P E R I P H E R A L
20
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M A N U A L
FM4_MN709-00003-4v0-E, May 27, 2015
CHAPTER 1-2: 12-bit A/D Converter
This chapter explains the functions and operations of the 12-bit A/D converter.
1. Overview
2. Configuration
3. Explanation of Operations
4. Setup procedure Examples
5. Registers
CODE: 9xFBAD12M3_FM4-E01.0
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CHAPTER 1-2: 12-bit A/D Converter
2. Configuration
P E R I P H E R A L
1.
M A N U A L
Overview
The 12-bit A/D converter is a function that converts analog input voltages into 12-bit digital values using a
type of the RC Successive Approximation Register.
Features of the 12-bit A/D Converter
12-bit resolution
Converter using a type of RC Successive Approximation Register with sample and hold circuits
Two sampling times selectable for each input channel
Scan conversion operation:
− Multiple analog inputs can be selected from multiple channels.
− Start factors are software and timers.
− Repeat mode is available.
Priority conversion operation:
Even during scan operation, if a start factor of priority conversion occurs, it is possible to interrupt the
ongoing scan conversion and perform conversion with high priority (There are two priority levels: 1
and 2. Priority level 1 is higher than priority level 2.).
Start factors are software and timers (priority level 2), and external triggers (priority level 1).
FIFO function:
− Sixteen FIFO stages for scan conversion and four FIFO stages for priority conversion are
incorporated.
− An interrupt is generated when data is written in the specified count of FIFO stages.
Changeable A/D conversion data placement (selectable between shift to the MSB side and shift to LSB
side)
The A/D conversion result comparison function is available.
Range comparison function
− Upper and lower limits can be specified
− Either detection of within the range or without the range can be set.
− With the continuous detection, the noise can be removed. The continuous detection time can be
specified from 0 to 7.
− For the detection of without the range, over the upper limit or below the lower limit can be specified.
There are five interrupt factors as follows:
1.
2.
3.
4.
5.
Scan conversion FIFO stage count interrupt
Priority conversion FIFO stage count interrupt
FIFO overrun interrupt (for both scan and priority conversion processes)
A/D conversion result comparison interrupt
Range comparison interrupt
DMA transfer triggered by an interrupt request.
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CHAPTER 1-2: 12-bit A/D Converter
2. Configuration
P E R I P H E R A L
2.
M A N U A L
Configuration
This section provides the configuration of the 12-bit A/D converter.
12-bit A/D Converter Block Diagram
Figure 2-1 12-bit A/D Converter Block Diagram
Scan conversion FIFO,
16 stages
Priority conversion FIFO,
4 stages
D/A converter
Buffer
A/D converter
Sample
&
hold
X
Peripheral buses
M P
Analog input n
Analog input n-1
.
.
.
.
Analog input 3
Analog input 2
Analog input 1
Analog input 0
Control unit
Comparator
Channel & status control unit
Timer trigger
External trigger pin
A/D conversion result
comparison interrupt
FIFO overrun interrupt
Scan FIFO interrupt
Priority FIFO interrupt
Range comparison interrupt
Input Impedance
The sampling circuit of the A/D converter is shown as an equivalent circuit in Figure 2-2. See the "Electrical
Characteristics" in "Data Sheet" to make sure that the external impedance, Rext should be selected not to
exceed the sampling time.
Figure 2-2 Input Impedance Equivalent Circuit Diagram
LSI
Rext
ANx
Rin
Analog SW
Analog
signal
source
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Cin
ADC
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CHAPTER 1-2: 12-bit A/D Converter
3. Explanation of Operations
P E R I P H E R A L
3.
M A N U A L
Explanation of Operations
This section explains the operations of the 12-bit A/D converter.
3.1. Enabling Operations of the A/D Converter
3.2. A/D Conversion Operation
3.3. FIFO Operations
3.4. A/D Comparison Function
3.5. Range Comparison Function
3.6. Starting DMA
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CHAPTER 1-2: 12-bit A/D Converter
3. Explanation of Operations
P E R I P H E R A L
3.1
M A N U A L
Enabling Operations of the A/D Converter
This section explains enabling operations of the A/D converter.
The A/D converter must be in the operation enable state prior to A/D conversion. Writing "1" to the ENBL bit
of the A/D Operation Enable Setup Register (ADCEN) turns the A/D converter from the operation stop state
to the operation enable state after the period of operation enable state transitions. On the other hand, writing
"0" to the ENBL bit of the ADCEN register turns the A/D converter immediately to the operation stop state.
A/D conversion can be performed only in the operation enable state. An A/D conversion request in the
operation stop state is ignored. If the A/D converter enters the operation stop state during A/D conversion,
A/D conversion stops immediately.
Reading the READY bit of the ADCEN register allows you to check whether the A/D converter is in the
operation enable state or not.
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CHAPTER 1-2: 12-bit A/D Converter
3. Explanation of Operations
P E R I P H E R A L
3.2
M A N U A L
A/D Conversion Operation
The A/D converter can perform two types of conversion processes: scan conversion and priority conversion.
3.2.1. Scan Conversion Operation
3.2.2. Priority Conversion Operation
3.2.3. Priority Levels and State Transitions
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CHAPTER 1-2: 12-bit A/D Converter
3. Explanation of Operations
P E R I P H E R A L
3.2.1
M A N U A L
Scan Conversion Operation
This section explains the scan conversion operation.
The input channels are selected in the Scan Conversion Input Selection Register (SCIS). By setting the
corresponding bit in the SCIS to 1, any necessary channel can be selected from among multiple analog
input channels.
The A/D converter can be started by software or a timer. To start the converter by software, set the SSTR bit
in the Scan Conversion Control Register (SCCR) to 1. Then conversion starts. To start the converter by
timers, set the SHEN bit in the SCCR register to 1 to enable timer start. Conversion starts when the timer's
rising edge is detected. When conversion starts, the SCS bit in the ADSR register is set to 1. When the
conversion is completed, the SCS bit is reset to 0.
When the SSTR bit in the SCCR register is set to 1 again during A/D conversion or the timer's rising edge is
detected again while timer start is enabled, the ongoing conversion operation is immediately stopped and
initialized and the A/D conversion is performed again (the operation is restarted).
The available scan conversion modes are as follows:
1. One-shot mode for a single channel
This mode is selected when only one analog priority conversion is specified for scan conversion and
RPT = 0 in the SCCR register. When the selected priority conversion is completed, the operation
stops.
Figure 3-1 Stop of Operation in One-shot Mode for a Single Channel
(SCIS3 = 0x00, SCIS2 = 0x00, SCIS1 = 0x00, SCIS0 = 0x08)
RPT
SSTR
Conversion
channel
Stop
ch.3
Stop
2. Continuous mode for a single channel
This mode is selected when only one analog priority conversion process is specified for scan
conversion and RPT = 1 in the SCCR register. When the selected priority conversion is completed,
the same priority conversion is started again. To stop A/D conversion, set RPT bit to 0. The operation
stops when the ongoing A/D conversion is completed.
Figure 3-2 Stop of Operation in Continuous Mode for a Single Channel
(SCIS3 = 0x00, SCIS2 = 0x00, SCIS1 = 0x00, SCIS0 = 0x08)
RPT
SSTR
Conversion
channel
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Stop
ch.3 ch.3
ch.3
ch.3 ch.3 ch.3
Stop
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CHAPTER 1-2: 12-bit A/D Converter
3. Explanation of Operations
P E R I P H E R A L
M A N U A L
3. One-shot mode for multiple channels
This mode is selected when multiple analog channels are specified for scan conversion and RPT = 0
in the SCCR register. When the conversion starts, the existence of each channel is automatically
checked. While the channels are switched from one to another, A/D conversion is started and the
conversion result is written to FIFO when the conversion is completed. The conversion channels are
selected in descending order of channel number (starting from ch.0). Channels not selected in the
SCIS register are skipped and the conversion operation targets the next selected channel. When the
A/D conversion of the last one of the selected channels is completed, the A/D conversion is stopped.
Figure 3-3 Stop of Operation in One-shot Mode for Multiple Channels
(SCIS3 = 0x00, SCIS2 = 0x01, SCIS1 = 0x01, SCIS0 = 0x11)
RPT
SSTR
Conversion
channel
Stop
ch.0 ch.4 ch.8 ch.16
Stop
4. Continuous mode for multiple channels
This mode is selected when multiple analog channels are specified for scan conversion and RPT = 1
in the SCCR register. When the conversion starts, the existence of each channel is automatically
checked. While the channels are switched from one to another, A/D conversion is started and the
conversion result is written to FIFO when the conversion is completed. The conversion channels are
selected in descending order of channel number (starting from ch.0). Channels not selected in the
SCIS register are skipped and the conversion operation targets the next selected channel. When the
A/D conversion of the last one of the selected channels is completed, the conversion operation
starts again from ch.0. To end A/D conversion, clear the RPT bit to 0. The operation stops when the
A/D conversion of the last one of the selected channels is completed.
Figure 3-4 Stop of Operation in Continuous Mode for Multiple Channels
(SCIS3 = 0x00, SCIS2 = 0x01, SCIS1 = 0x01, SCIS0 = 0x11)
RPT
SSTR
Conversion
channel
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Stop
ch.0 ch.4 ch.8 ch.16 ch.0 ch.4 ch.8 ch.16
Stop
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CHAPTER 1-2: 12-bit A/D Converter
3. Explanation of Operations
P E R I P H E R A L
3.2.2
M A N U A L
Priority Conversion Operation
This section explains the priority conversion operation.
This mode is used to give priority to a specific conversion process. Even when scan conversion is in
progress, if priority conversion is started, the scan conversion is interrupted immediately and the priority
conversion is performed. When the priority conversion is completed, the scan operation restarts from the
channel where it was interrupted. If conversion with higher priority (priority level 1) is started while the
conversion with lower priority (priority level 2) is performed, the priority level 2 conversion is interrupted
immediately and the priority level 1 conversion is performed. When the priority level 1 conversion is
completed, the priority level 2 conversion is restarted.
Two levels of priority are given to priority conversion. Priority level 1 is the highest and priority level 2 is the
second. Trigger start by an external pin is assigned as the start factor at priority level 1 and software/timer
start is assigned as that at priority level 2.
− The input channels are selected in the Priority Conversion Input Selection register (PCIS).
The procedure for selecting channels at priority level 1 differs depending on the ESCE bit in the
Priority Conversion Control Register (PCCR).
When ESCE = 0:
The P1A[2:0] bits in the PCIS register are used. Only one of the eight
channels, ch.0 to ch.7, can be selected.
When ESCE = 1:
The setting of the P1A[2:0] bits in the PCIS register is ignored. Only one of
the eight channels, ch.0 to ch.7, can be selected with input from the external pin (ECS[2:0]).
Example: ECS[2:0] =
000 -> ch.0
=
010 -> ch.2
=
111 -> ch.7
− The P2A[4:0] bits in the PCIS register are used for selecting the channel at priority level 2. Only one of
the multiple input channels can be selected.
The start factor of A/D conversion differs depending on the priority level.
− Priority level 1 (highest priority) conversion can be started by a falling edge of external trigger input.
To enable external trigger start, set the PEEN bit in the PCCR register to 1.
− Priority level 2 conversion can be started by software or a timer.
To start conversion by software, set the PSTR bit in the PCCR register to 1. To start conversion by a
timer, set the PHEN bit in the PCCR register to 1 to enable timer start. Conversion starts when the
timer's rising edge is detected. When conversion starts, the PCS bit in the ADSR register is set to 1.
When the conversion is completed, the PCS bit is reset to 0.
In priority conversion mode, the conversion cannot be restarted. In addition, start factors at the same priority
level are ignored.
(A timer start factor is ignored during software-started operation.)
If a priority level 1 start factor (external trigger) occurs during conversion started by a priority level 2
start factor (software or timer), the PCNS bit in the A/D Status Register (ADSR) is set to 1 and the
priority level 2 conversion is interrupted immediately. When the priority level 1 conversion is
completed, PCNS is reset to 0 and the interrupted priority level 2 conversion is restarted. If a priority
level 2 start factor occurs during priority level 1 conversion, the priority level 2 start factor is reserved
(retained) and PCNS bit is set to 1. When the priority level 1 conversion is completed, PCNS bit is
reset to 0 and the priority level 2 conversion is started.
Priority conversion can only be performed in one-shot mode for a single channel.
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CHAPTER 1-2: 12-bit A/D Converter
3. Explanation of Operations
P E R I P H E R A L
3.2.3
M A N U A L
Priority Levels and State Transitions
This section explains priority levels and state transitions.
Priority Levels
Table 3-1 Priority Levels for the A/D Converter
Priority level
Conversion type
1
Priority level 1 conversion
2
Priority level 2 conversion
Start factor
- Input from external trigger pin (at falling edge)
- Software (when the priority conversion start bit (PSTR) of priority
conversion control register (PCCR) is set to 1)
- Trigger input from timer (at rising edge)
- Software (when the scan conversion start bit (SSTR) of scan
3
Scan conversion
conversion control register (SCCR)is set to 1)
- Trigger input from timer (at rising edge)
When a startup by priority conversion occurs during scan conversion
The scan conversion operation is interrupted and priority conversion operation is performed. When
the priority conversion operation is completed, the scan conversion is restarted from the channel
where it was interrupted.
When a startup at priority level 1 occurs during conversion at priority level 2
The priority level 2 conversion is interrupted and the operation by the startup at priority level 1 is
performed. When the priority level 1 operation is completed, the priority level 2 conversion is
restarted automatically.
When a startup at priority level 2 occurs during conversion at priority level 1
The start factor at priority level 2 is retained. When the priority level 1 conversion is completed, the
priority level 2 conversion is started automatically.
When a startup of scan conversion occurs during priority level 1 conversion
The start factor of the scan conversion is retained. When the priority level 1 conversion is completed,
the scan conversion operation is started automatically.
When a startup of scan conversion occurs during priority level 2 conversion
The start factor of the scan conversion is retained. When the priority level 2 conversion is completed,
the scan conversion operation is started automatically.
While priority conversion is performed, start factor at the same priority level are masked (the operation is
not restarted).
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CHAPTER 1-2: 12-bit A/D Converter
3. Explanation of Operations
P E R I P H E R A L
M A N U A L
State Transitions
Figure 3-5 12-bit A/D Converter State Transitions
000
Standby for A/D conversion
Scan conversion
request
Scan conversion
completed
001
Scan conversion
is in progress.
Priority conversion
request
Priority conversion
completed
Priority conversion
request
010
Priority conversion
is in progress.
Scan conversion
request
011
Priority conversion
completed
Priority level 1
conversion
completed
Priority conversion is in
progress.
Scan conversion is
pending.
Priority level 1
conversion
completed
Priority
conversion
request
Priority
conversion
request
110
Priority level 1 conversion is in
progress.
Priority level 2 conversion is
pending.
Scan conversion
request
111
Priority level 1 conversion is in
progress.
Priority level 2 conversion is pending.
Scan conversion is pending.
The operation states can be read from the PCNS, PCS, and SCS bits of the ADSR register.
Table 3-2 Correspondence between Bits and Operation States
PCNS
PCS
SCS
0
0
0
Standby for A/D conversion.
0
0
1
Scan A/D conversion is in progress.
0
1
0
Priority A/D conversion (priority level 1 or 2) is in progress.
0
1
1
1
1
0
1
1
1
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Explanation of states
Priority A/D conversion (priority level 1 or 2) is in progress. Scan conversion is
pending.
Priority A/D conversion (priority level 1) is in progress. Priority conversion (priority
level 2) is pending.
Priority A/D conversion (priority level 1) is in progress. Scan conversion and priority
conversion (priority level 2) are pending.
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CHAPTER 1-2: 12-bit A/D Converter
3. Explanation of Operations
P E R I P H E R A L
3.3
M A N U A L
FIFO Operations
The A/D converter has 16 FIFO stages for scan conversion and 4 FIFO stages for priority conversion. When
conversion data is written in the specified count of FIFO stages, an interrupt is generated to the CPU.
3.3.1. FIFO Operations in Scan Conversion
3.3.2. Interrupts in Scan Conversion
3.3.3. FIFO Operations in Priority Conversion
3.3.4. Interrupts in Priority Conversion
3.3.5. Validity of FIFO Data
3.3.6. Bit placement Selection for FIFO Data Registers
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CHAPTER 1-2: 12-bit A/D Converter
3. Explanation of Operations
P E R I P H E R A L
3.3.1
M A N U A L
FIFO Operations in Scan Conversion
This section explains FIFO operations in scan conversion.
Sixteen FIFO stages are incorporated for writing scan conversion data. After reset, they are in empty state
and the SEMP bit in the Scan Conversion Control Register (SCCR) is set to 1. When A/D conversion of one
channel is completed, the conversion result, start factor, and conversion channel are written in the first FIFO
stage. This resets SEMP bit to 0. The conversion result, start factor, and conversion channel for the next
channel are written sequentially in the second FIFO stage.
When such data is written in all of the 16 stages, the SFUL bit is set to 1 to indicate that FIFO is in full state.
If conversion is performed and an attempt is made to write data in FIFO when FIFO is in full state, the SOVR
bit is set to 1 and the data is discarded (cannot overwrite the existing data).
To clear the data in FIFO, set the SFCLR bit in the Scan Conversion Control register to 1. FIFO goes to the
empty state and the SEMP bit is set to 1.
Data in FIFO can be read sequentially by reading the Scan Conversion FIFO Data Register (SCFD). To
perform a byte (8 bits) access to this register, read the most significant byte (bit31:24) to shift FIFO (reading
the other bytes (bit23:16, bit15:8, bit7:0) does not shift FIFO). To perform a half word (16 bits) access to this
register, read the most significant half word (bit31:16) to shift FIFO (reading the other byte (bit15:0) does not
shift FIFO). Performing a word (32 bits) access to this register shifts FIFO.
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CHAPTER 1-2: 12-bit A/D Converter
3. Explanation of Operations
P E R I P H E R A L
3.3.2
M A N U A L
Interrupts in Scan Conversion
This section explains interrupts in scan conversion.
Figure 3-6 FIFO Interrupt Settings and FIFO Operations
Valid FIFO
stage count
N=5(6stages)
FIFO stage
count setting
N=3(4stages)
Flag clear
FIFO interrupt
request
Flag clear
FIFO readout
A/D conversion
Stop
1 2 3 4 5 6
Stop
1 2 3 4 5 6
Stop
1
Stop
When conversion data for the number of FIFO stages (N + 1) set in SFS[3:0] in the Scan Conversion FIFO
Stage Count Setup Register (SFNS) is written in FIFO, the interrupt request bit (SCIF) in the A/D Control
Register (ADCR) is set to 1. If the interrupt enable bit (SCIE) is set to 1, an interrupt request is generated to
the CPU.
The following explains FIFO stage count interrupt methods for each scan conversion mode.
1. One-shot mode for a single channel
To generate an interrupt after the completion of one conversion process for the specified channel,
set SFS[3:0] = 0x0. When conversion data is written in the first FIFO stage, SCIF bit is set to 1.
Note:
−
If SFS[3:0] bits are set to 0x1 or more (two stages or more), interrupts are not generated until
conversion data is written into FIFO by the specified stage count.
2. Continuous mode for a single channel
To generate an interrupt after the completion of one conversion process for the specified channel,
set SFS[3:0] = 0x0. When conversion data is written in the first FIFO stage, SCIF bit is set to 1.
To generate an interrupt at the completion of a number of times of conversion of the specified
channel, set SFS[3:0] bits to 0x1 or more (two stages or more). For example, set SFS[3:0] = 0x3 to
generate an interrupt after four repeats.
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CHAPTER 1-2: 12-bit A/D Converter
3. Explanation of Operations
P E R I P H E R A L
M A N U A L
3. One-shot mode for multiple channels
To generate an interrupt after the completion of conversion of the multiple specified channels, set the
FIFO stage count according to the number of channels. If eight channels are selected, set the FIFO
stage count by setting SFS[3:0] = 0x7. When the conversion of the last one of the selected channels
is completed, SCIF bit is set to 1.
An interrupt can be generated at any timing before scan completion by setting SFS[3:0] bits to a
value less than the number of selected channels.
4. Continuous mode for multiple channels
To generate an interrupt after the completion of the first scan of the multiple specified channels, set
the FIFO stage count according to the number of channels. If eight channels are selected, set the
FIFO stage count by setting SFS[3:0] = 0x7. When the conversion of the last one of the selected
channels is completed, SCIF bit is set to 1.
To generate an interrupt after the completion of the second scan, set the FIFO stage count to twice
the number of selected channels. For example, when four channels are selected, set the FIFO stage
count to 8 (SFS[3:0] = 0x7). An interrupt is generated when the second scan is completed.
Because the FIFO stage count can be set to any value, an interrupt can be generated at any desired
timing.
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CHAPTER 1-2: 12-bit A/D Converter
3. Explanation of Operations
P E R I P H E R A L
3.3.3
M A N U A L
FIFO Operations in Priority Conversion
This section explains FIFO operations in priority conversion.
Four FIFO stages are incorporated for writing priority conversion data. After reset, they are in empty state
and the PEMP bit in the Priority Conversion Control Register is set to 1. When one A/D conversion process
is completed, the conversion result, start factor, and conversion channels are written in the first FIFO stage.
This resets SEMP bit to 0. The conversion result and conversion channels for the subsequent conversion
processes are written in the corresponding FIFO stages.
When such data is written in all of the 4 stages, the PFUL bit is set to 1 to indicate that FIFO is in full state. If
conversion is performed and an attempt is made to write data in FIFO when FIFO is in full state, the POVR
bit is set to 1 and the data is discarded (cannot overwrite the existing data).
To clear the data in FIFO, set the PFCLR bit in the Priority Conversion Control Register (PCCR) to "1". FIFO
goes to the empty state and the PEMP bit is set to 1.
Data in FIFO can be read sequentially by reading the Priority Conversion FIFO Data Register (PCFD). To
perform byte (8 bits) access to this register, read the most significant byte (bit31:24) to shift FIFO (reading
the other bytes (bit23:16, bit15:8, bit7:0) does not shift FIFO). To perform a half word (16 bits) access to this
register, read the most significant half word (bit31:16) to shift FIFO (reading the other byte (bit15:0) does not
shift FIFO). Performing a word (32 bits) access to this register shifts FIFO.
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CHAPTER 1-2: 12-bit A/D Converter
3. Explanation of Operations
P E R I P H E R A L
3.3.4
M A N U A L
Interrupts in Priority Conversion
This section explains interrupts in priority conversion.
When conversion data for the number of FIFO stages (N + 1) set in PFS[1:0] in the Priority Conversion FIFO
Stage Count Setup Register (PFNS) is written in FIFO, the interrupt request bit (PCIF) in the A/D Control
Register (ADCR) is set to 1. If the interrupt enable bit (PCIE) is set to "1", an interrupt request is generated to
the CPU.
The following explains FIFO stage count interrupt methods in priority conversion.
To generate an interrupt after the completion of one conversion process for the specified channel,
set PFS[1:0] = 0x0. When conversion data is written in the first FIFO stage, PCIF bit is set to 1.
Note:
−
If PFS[1:0] bits are set to 0x1 or more (two stages or more), interrupts are not generated until
conversion data is written into FIFO by the specified stage count.
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CHAPTER 1-2: 12-bit A/D Converter
3. Explanation of Operations
P E R I P H E R A L
3.3.5
M A N U A L
Validity of FIFO Data
This section explains a restriction on reading FIFO data registers.
The bit12 of the Scan Conversion FIFO Data Register (SCFD) and Priority Conversion FIFO Data Register
(PCFD) comes with the INVL (A/D conversion result disable) bit which indicates data validity. During reading
FIFO data registers, the INVL bit is cleared to 0 if data is valid while the INVL bit is set to 1 if data is invalid.
For word (32 bits) reading, data validity can be checked by the INVL bit.
For half word (16 bits) reading which does not use interrupts or empty bits (SEMP, PEMP), always start
reading from the least significant 16 bits including the INVL bit. If the INVL bit is 1 at this time, reading the
most significant 16 bits is prohibited. The most significant 16 bits must be read only when the INVL bit is 0.
For byte (8 bits) reading which does not use interrupts or empty bits (SEMP, PEMP), always start reading
from bit15:8 including the INVL bit. If the INVL bit is 1 at this time, reading bit31:24, bit23:16, or bit7:0 is
prohibited. They must be read only when the INVL bit is 0.
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CHAPTER 1-2: 12-bit A/D Converter
3. Explanation of Operations
P E R I P H E R A L
3.3.6
M A N U A L
Bit placement Selection for FIFO Data Registers
This section explains bit placement selection for FIFO data registers.
The A/D converter can change the bit placement for the conversion results in the Scan Conversion FIFO
Data Register (SCFD) and Priority Conversion FIFO Data Register (PCFD) with the FDAS bit in the A/D
Status Register (ADSR) (Figure 3-7).
Setting the FDAS bit to 1 places 12-bit A/D conversion results (SD11 to SD0, PD11 to PD0) on the LSB side
(bit27:16) when a FIFO data register is read. Placement of the least significant 16 bits of a FIFO data
register does not change.
FIFO is shifted, regardless of the set value of the FDAS bit, by reading bit31:24 (for a byte access), bit31:16
(for a half word access), or bit31:0 (for a word access) of a FIFO data register.
Figure 3-7 FIFO Data Register Bit Placement
SCFD register
When FDAS=0
31
30
SD11
SD10
29
28
27
26
25
24
SD9 SD8 SD7 SD6 SD5 SD4
23
22
21
20
19
SD3 SD2 SD1 SD0
18
17
16
Reserved
When FDAS=1
31
30
29
28
27
26
0
0
0
0
SD11
SD10
29
28
27
26
25
24
SD9 SD8
23
22
21
20
19
18
17
16
SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0
PCFD register
When FDAS=0
31
30
PD11
PD10
25
24
PD9 PD8 PD7 PD6 PD5 PD4
23
22
21
20
19
PD3 PD2 PD1 PD0
18
17
16
Reserved
When FDAS=1
31
30
29
28
27
26
0
0
0
0
PD11
PD10
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25
24
PD9 PD8
23
22
21
20
19
18
17
16
PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
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CHAPTER 1-2: 12-bit A/D Converter
3. Explanation of Operations
P E R I P H E R A L
3.4
M A N U A L
A/D Comparison Function
The A/D comparison function compares A/D conversion results and generates interrupts.
To use the comparison function, set the CMPEN bit in the A/D Comparison Control Register (bit7 in the
CMPCR register) to 1.
The values set in the A/D Comparison Value Setup Register (CMPD) are compared with the most significant
10 bits (bit11:2) of the A/D conversion result. If the comparison result satisfies the conditions set in the A/D
Comparison Control Register (CMPCR), the A/D comparison interrupt bit (CMPIF) in the ADCR register is
set to 1. If the interrupt enable bit (CMPIE) is 1, an interrupt is generated to the CPU.
Note:
−
Two bits (bit1:0) on the LSB side are not compared.
Because the result of A/D conversion, regardless of scan or priority, is compared before it is written to FIFO,
comparison is possible when FIFO is full.
If CMD1 bit is set to 1 (to generate an interrupt when the result is equal to or more than the CMPD set value),
CMPIF is set to 1 when the conversion result is equal to the value in the A/D Comparison Value Setup
Register (CMPD).
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CHAPTER 1-2: 12-bit A/D Converter
3. Explanation of Operations
P E R I P H E R A L
3.5
M A N U A L
Range Comparison Function
The range comparison function is a function to determine whether the conversion result of the A/D converter
is within or outside the specified range and generate an interrupt.
To start the range comparison function, write 1 to the range comparison enabling setting (RCOE) of Range
Comparison Control Register (WCMPCR).
The upper 10 bits (bit11:2) of the A/D conversion result is compared with the upper threshold setting register
(WCMPDH) and the lower threshold setting register (WCMPDL).
Note:
−
The comparison with two bits (bit1, bit0) on LSB side is not executed.
When the within-range /outside-range confirmation select (RCOIRS) of Range Comparison Control Register
is 1, the A/D conversion result is confirmed to be outside of the specified range.
Table 3-3 shows the detection conditions of the range comparison and Figure 3-8 shows the operation of the
range comparison.
Table 3-3 Range Comparison Conditions
Outside-Range
Range Comparison Result
Outside range (beyond upper limit threshold)
A/D data bit > upper limit threshold setting register
Within-Range
Confirmation
Confirmation
(RCOIRS="0")
(RCOIRS="1")
Remarks
Detected
Not Undetected
Figure 3-8：2,6
Not detected
Detected
Figure 3-8：1,4,5
Detected
Not detected
Figure 3-8：3
Within Range
A/D data bit ≥ lower limit threshold setting register
And,
A/D data bit upper limit threshold setting register
Outside range (below lower limit threshold)
A/D data bit < lower limit threshold setting register
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CHAPTER 1-2: 12-bit A/D Converter
3. Explanation of Operations
P E R I P H E R A L
M A N U A L
Figure 3-8 Range Comparison Operation
Voltage
↑
6.
Outside range
A/D conversion result
（Beyond upper
limit threshold）
2.
Upper limit threshold
setting register 0
(ADRCUT0)
4.
1.
Within range
5.
Lower limit threshold
setting register 0
(ADRCLT0)
Outside range
（Below lower limit
threshold）
3.
→Time
The Continuous detection function detects the range comparison continuously, and removes the noise etc.
When the range comparison is continuously detected for the times specified in continuous detection count
specification and state setting (RCOCD) of the range comparison control register (WCMPCR), the range
comparison flag register (RCINT) is set to 1. When the range comparison interrupt enable bit (RCOIE) is set
to "1", the interrupt is generated for CPU.
When the range comparison result is found to be undetected even one time in the continuous detection, the
continuous detection measurement is cleared to 0 times, and restarts the measurement.
For the continuous detection conditions, see Table 3-4.
Table 3-4 Continuous Detection Conditions
Items
Descriptions
Continuous detection
The detection is always operated whenever the continuous comparison execution
measurement operation
enable setting (RCOE) is set to "1".
−
With the continuous detection count specification (RCOCD), the detection count
can be selected from 1 to 7 times.
Continuous detection count
Clear conditions
−
With the continuous detection count status display (RCOCD), the state of the
detection count can be confirmed.
−
When the range comparison execution enable setting (RCOE) is set to "0".
−
When the result is undetected with the range comparison result.
When the result is detected with the range comparison result.
Increment condition
However, when the detection count reaches the continuous detection count
specification (RCOCD), the detection is stopped at the continuous detection count
specification value
Note:
−
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When the confirmation of outside-range (WCMPCR.RCOIRS) is 0, the continuous detection
measurement is not cleared to 0 times, and continues the continuous detection even if the range
comparison result is changed from the state of the upper limit threshold excess to the state of below
lower limit threshold.
To initialize the state of the continuous detection count of the range comparison result, disable the
range comparison while A/D conversion is not required, and then enable the range comparison
again.
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CHAPTER 1-2: 12-bit A/D Converter
3. Explanation of Operations
P E R I P H E R A L
M A N U A L
When the confirmation of outside-range of the range comparison (RCOIRS) is "0",the state of the upper limit
threshold excess or the state of below lower limit threshold can be confirmed with the range comparison
threshold excess flag bit (RCOOF).
For the judgment conditions of the Range Comparison Threshold Excess Flag, see Table 3-5.
Table 3-5 Range Comparison Threshold Excess Flag, Judgment Conditions
Range Comparison Threshold Excess Flag Bit(RCOOF)
Range Comparison Result
Outside-range confirmed
Within-range confirmed
(RCOIRS="0")
(RCOIRS="1")
"1"
Prior value held
Outside range (beyond upper limit threshold)
A/D data bit > upper limit threshold setting register
Within Range
A/D data bit ≥ lower limit threshold setting register
Prior value held
And,
Prior value held
A/D data bit upper limit threshold setting register
Outside range (below lower limit threshold)
"0"
A/D data bit < lower limit threshold setting register
Prior value held
Moreover, the range comparison threshold excess flag bit (RCOOF) holds the content set in itself while the
comparison interrupt factor flag (RCINT) is set to 1.
For the operation example of the range comparison function, see Figure 3-9.
Figure 3-9 Range Comparison Function Operation Example
[Range comparison Information]
Continuous detection count setting(ADRCCS[n].RCOTS1,RCOTS0="00B")
Outside-range confirmation(ADRCCS[n].RCOIRS="0")
Voltage
↑
A/D conversion result
Outside range
（Beyond upper limit
threshold）
2.
8.
Upper limit setting register 0
(ADRCUT0)
3.
7.
Within range
4.
Outside range
（Below lower limit
threshold）
Lower limit threshold setting register 0
(ADRCLT0)
5.
→Time
Continuous detection
count specification
"011"
(ADRCCS[n].RCOCD2～0)
Range comparison
execution enable bit
1.
11.
(ADRCCS[n].RCOE)
Continuous detection
count state
2.
3.
"001"
"000"
"010"
4.
"000"
5.
"001"
"010"
7.
"011"
8.
"000"
"001"
11.
"010" "011" "000"
(ADRCCS[n].RCOCD2～0)
5.
Range comparison
interrupt factor flag
6.
9.
6.
9.
10.
(ADRCIF.RCINT[n])
Interrupt factor flag clear
(ADRCIF.RCINT[n]="0"writor)
Threshold excess flag
(ADRCOT.RCOOF[n])
2.
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3.
4.
5.
6.
8.
invalid
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CHAPTER 1-2: 12-bit A/D Converter
3. Explanation of Operations
P E R I P H E R A L
M A N U A L
The explanation of range comparison function operation in Figure 3-9 is as follows:
1. When the range comparison execution disable setting (RCOE) is 0, the continuous detection count state
(RCOCD) is initialized to 000.
When the range comparison execution disable setting (RCOE) is set to 1, the range comparison operation
is started.
2. When the range comparison result exceeds the upper limit threshold , the continuous count detection
state (RCOCD) begins to increment.
Moreover, the threshold excess flag notifies the upper limit threshold excess (RCOOF=1).
3. Before the continuous detection count specification value (RCOCD) becomes 011, the range comparison
result is found to be within the range. So, the continuous detection count state (RCOCD) is initialized to be
000.
Furthermore, the threshold excess flag (RCOOF) holds the prior value.
4. Because the range comparison result is below the lower limit threshold, the continuous count detection
state (RCOCD) executes the increment.
And, the threshold excess flag notifies that the result is below the lower limit threshold (RCOOF=0).
5. As the range comparison result reaches continuously the continuous detection count specification value
(RCOCD =011), the range comparison interrupt factor flag (RCINT) is set to be 1.
Moreover, the threshold excess flag (RCOOF) sets the threshold excess state where the range
comparison interrupt factor flag is set (RCINT=1) and holds the state until the range comparison interrupt
factor flag is cleared (RCINT=0).
6. The set operation by the state of the continuous detection is given priority when the state of the range
comparison interrupt factor flag clear (RCINT=0) and the state of the continuous detection compete. The
range comparison interrupt factor flag is set (RCINT=1) and the threshold excess flag (RCOOF) set to the
threshold excess state again.
7. When the range comparison result is within the range, even in the state of the range comparison interrupt
factor flag set (RCINT=1), the state of the continuous detection frequency is initialized (RCOCD =000).
8. Even in the range comparison interrupt factor flag set state (RCINT=1), the range comparison result
increments the continuous count detection (RCOCD2) by the upper limit threshold excess.
However, in the range comparison interruption factor flag set state (RCINT=1), the threshold excess flag
(RCOOF) holds the prior value.
9. The range comparison interrupt factor flag is cleared (RCINT=0) because of the range comparison
interrupt factor flag clear (RCINT=0).
Moreover, the hold state of the limit excess flag (RCOOF) is also released.
10. Because the range comparison result continuously reached the continuous detection count specification
value (RCOCD =011), the range comparison interrupt factor flag (RCINT) is set to 1.
Moreover, the threshold excess flag (RCOOF) is set to the threshold excess state when the range
comparison interrupt factor flag is set (RCINT=1) and its state is held until the range comparison interrupt
factor flag is cleared (RCINT=0).
11. When the range comparison operation is disabled (RCOE=0), the continuous detection count state
(RCOCD) is initialized to 000.
Moreover, neither the range comparison interrupt factor flag (RCINT) nor the threshold excess flag
(RCOOF) are cleared because the range comparison operation is disabled (RCOE=0).
However, because the range comparisons of the A/D conversion results are implemented before A/D
conversion result is written to FIFO regardless of the scanning conversion and the priority conversion, the
range comparison can be executed even when FIFO is in the FULL state.
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CHAPTER 1-2: 12-bit A/D Converter
4. Setup procedure Examples
P E R I P H E R A L
3.6
M A N U A L
Starting DMA
This section explains the DMA transfer processing for FIFO data of A/D converter.
Data stored in FIFO of A/D converter can be transferred with the hardware activated DMA transfer using
interrupt signals. The required settings and operations are as follows.
This product is compatible with DMA transfers of scan convert FIFO data by DMAC, and scan convert FIFO
data and prior convert FIFO data by DSTC.
・The interrupt signal from the A/D converter is connected to the interrupt controller in the initial state.
According to the select register setting for DMA transfer requests of interrupt controller and the DREQENB
register setting of DSTC, connect the scan convert interrupt signal and prior convert interrupt signal to
DMAC/DSTC. Enables interrupts from the A/D converter. (ADCR:SCIE=1, ADCR:PCIE=1)
・Set 0 for the FIFO stage count when the interrupts from the A/D converter are generated (the interrupt
request will be generated when the conversion result is stored in the first FIFO stage ).
・For DMAC/DSTC side, specify the transfer source addresses for the scan convert FIFO data register
(SCFD) and prior conversion FIFO data register (PCFD). In case of DMAC, select the hardware demand
transfer for transfer mode. In case of DSTC, select DES0.MODE=1 for transfer mode. For number of transfer,
specify the number of data stored in FIFO.
Figure 3-10 shows a timing chart of DMA transfer operations.
After A/D conversion is started, the converted data will be stored in FIFO. Interrupt requests from the A/D
converter are generated. By DMAC/DSTC, reading the FIFO data register and writing to the destination are
performed, and data transfer is performed. The generated interrupt signals are cleared from the
DMAC/DSTC side. (▼mark in this figure) Clearing the interrupt flag (ADCR:SCIF, ADCR:PCIF) from CPU is
not required. After transfer operation is completed for the times specified in DMAC/DSTC, the transfer
completion notification from DMAC/DSTC can be received.
If DMAC/DSTC processes transfer requests other than those of the A/D converter, note that the start of DMA
transfer may get delayed as shown from ▽ to △ in the figure.
Figure 3-10 DMA transfer Operation
A/D start
A/D conversion
Stop
1
2
Stop
3
▼
1
2
3
Stop
1
▼
2
3
Stop
▼
FIFO interrupt request
（DMA start request）
▽
△
FIFO readout
（DMA transfer）
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CHAPTER 1-2: 12-bit A/D Converter
4. Setup procedure Examples
P E R I P H E R A L
4.
M A N U A L
Setup procedure Examples
This section provides examples of setup procedures for the 12-bit A/D converter.
4.1. A/D Operation Enable Setup Procedure Example
4.2. Scan Conversion Setup Procedure Example
4.3. Priority Conversion Setup Procedure Example
4.4. Range Comparison Function Setting Example
4.5. Setting Conversion Time
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CHAPTER 1-2: 12-bit A/D Converter
4. Setup procedure Examples
P E R I P H E R A L
4.1
M A N U A L
A/D Operation Enable Setup Procedure Example
This section provides an A/D operation enable setup procedure example.
Set the period of operation enable state transitions
Poll the operation enable state
Figure 4-1 A/D Operation Enable Setup Procedure Example
Start
Set A/D operation enable
(set ADCEN:CYCLSL(*), write ADCEN:ENBL="1")
Check operation enable
state ADCEN:READY="1"?
No
Yes
End
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CHAPTER 1-2: 12-bit A/D Converter
4. Setup procedure Examples
P E R I P H E R A L
4.2
M A N U A L
Scan Conversion Setup Procedure Example
This section provides a scan conversion setup procedure example.
Scan conversion by software startup
Set A/D conversion channels to ch.1 and ch.3
Set different sampling times for ch.1 and ch.3
Set the clock division ratio
Read the least significant 16 bits of FIFO data and check data validity by the INVL bit
After checking that data is valid, read the most significant 16 bits of FIFO data
Figure 4-2 Scan Conversion Setup Procedure Example
Start
Initial settings
- Set A/D conversion channels (set SCIS0 to ch.1, ch.3)
- Set sampling times(set ADST0, ADST1, ADSS)
- Set the division ratio (set ADCT:CT)
- Set FIFO data placement (write ADSR:FDAS="1")
- No comparison function used (write CMPCR:CMPEN="0")
- No interrupt used (write ADCR:SCIE="0")
- Clear FIFO (write SCCR:SFCLR="1")
- Set a conversion mode (write SCCR:RPT="0")
- Start the A/D software (write SCCR:SSTR="1")
Read the least significant 16 bits of FIFO data (the
SCFD register)
Check data validity
SCFD:INVL="0"?
No
Yes
Read the most significant 16 bits of FIFO data (the SCFD
register) (read the A/D conversion results of ch.1)
Read the least significant 16 bits of FIFO data (the
SCFD register)
Check data validity
SCFD:INVL="0"?
No
Yes
Read the most significant 16 bits of FIFO data (the SCFD
register) (read the A/D conversion results of ch.3)
End
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CHAPTER 1-2: 12-bit A/D Converter
4. Setup procedure Examples
P E R I P H E R A L
4.3
M A N U A L
Priority Conversion Setup Procedure Example
This section provides a priority conversion setup procedure example.
Priority conversion at priority level 2 by timer start
Conversion channels are ch.1 and ch.3
Set different sampling times for ch.1 and ch.3
Set the clock division ratio
Read 32 bits of FIFO data by using an interrupt
Read FIFO by the specified stage count
Figure 4-3 Priority Conversion Setup Procedure Example
Start
Initial setting
- Set A/D conversion channels (set PCIS:P2A)
- Set sampling times (set ADST0, ADST1, ADSS)
- Set the division ratio(set ADCT:CT)
- Set FIFO stage count (set PFNS:PFS)
- Set FIFO data placement (write ADSR:FDAS="1")
- No comparison function used (write CMPCR:CMPEN="0")
- Use a priority conversion interrupt (write ADCR:PCIE="1")
- Clear FIFO (write PCCR:SFCLR="1")
- Start the A/D timer (write PCCR:PHEN="1")
Wait for an interrupt
An interrupt is generated
Read 32 bits of FIFO data (the PCFD register) (repeat
this by the specified FIFO stage count)
Clear a priority conversion interrupt request (write
ADCR:PCIF="0")
End
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CHAPTER 1-2: 12-bit A/D Converter
4. Setup procedure Examples
P E R I P H E R A L
4.4
M A N U A L
Range Comparison Function Setting Example
This section shows the example of range comparison function setting procedures.
Figure 4-4 Example of Comparison Function Setting Procedures
Setting Start
Initial setting
・Upper limit threshold register setting(WCMPDH:CMHD Setting)
・Lower limit threshold register setting(WCMPDL:CMLD Setting)
・Range comparison channel select register setting(WCMPSR:WCMD, WCMPSR:WCCH
setting)
Continuous detection count setting (WCMPCR:RCOCD Setting)
Within-range/OutSide-range select setting (WCMPCR:RCOIRS Setting)
Range comparison interrupt request enable (WCMPCR:RCOIE Setting)
Range comparison execution enable (WCMPCR:RCOE Setting)
A/D conversion execution
Wait for interrupt
Interrupt occurrence
Flag register (WCMRCIF:RCINT)Clear
End
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CHAPTER 1-2: 12-bit A/D Converter
4. Setup procedure Examples
P E R I P H E R A L
M A N U A L
Example of Conversion Time Calculation (when HCLK = 20 MHz (50 ns cycle))
(1) Sampling time
−
When ST04 to ST00 = 2, STX02, STX01, and STX00 = 000 (multiplied by 1), and CT7 to CT0=0
(Compare clock division ratio: 2)
−
Sampling time = 50 ns × 2 {(2+1) × 1 + 3} = 600 ns
When ST14 to ST10 = 19, STX12, STX11, and STX10 = 001 (multiplied by 4), and CT7 to CT0=0
(Compare clock division ratio: 2)
Sampling time = 50 ns × 2 {(19 + 1) × 4 + 3} = 8300 ns
(2) Comparison time
− When CT7 to CT0 = 0 (Clock division ratio: 2)
Compare clock cycle = 50 ns × 2 = 100 ns
Comparison time = 100 ns × 14 = 1400 ns
(3) Conversion time
− By adding (1) and (2) together:
Conversion time for channels specified with the ADST0 register = 2000 ns
Conversion time for channels specified with the ADST1 register = 9700 ns
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CHAPTER 1-2: 12-bit A/D Converter
5. Registers
P E R I P H E R A L
4.5
M A N U A L
Setting Conversion Time
The conversion time of the A/D converter is "sampling time" + "comparison time". Two sampling time
settings can be applied to each channel. This section explains how to set and calculate the conversion time.
Example of Setting the Sampling Time
A sampling time is set in each of Sampling Time Setup Registers 0 and 1 (ADST0 and ADST1). Using
Sampling Time Selection Registers (ADSS3 to ADSS0), whether Sampling Time Setup Registers 0 or 1 is
used to provide the value can be selected for each channel. This allows you to set different sampling times
for channels with different external impedances.
Sampling time = Base clock (HCLK) cycle× Clock division ratio × {(ST set value + 1) × STX setting multiplier
+ 3}
Notes:
−
−
For setting the sampling time, refer to the "Electrical Characteristics" in the "Data Sheet" to make
sure that an appropriate time should be selected in accordance with an external impedance of an
input channel, an analog power supply voltage (AVCC), and a base clock (HCLK) cycle.
When STXx2, STXx1, and STXx0 = 000 (STx4 to STx0 set values multiplied by 1) are set, set STx4
to STx0 to "2" or more ("1" or less must not be set).
Example of Setting the Comparison Time
The comparison time is set in the Comparison Time Setup Register (ADCT).
Comparison time = Compare clock cycle × 14
Compare clock cycle = Base clock (HCLK) cycle × Clock division ratio
Notes:
52
CONFIDENTIAL
−
For setting the compare clock cycle, refer to the "Electrical Characteristics" in the "Data Sheet" to
make sure that an appropriate time should be selected in accordance with an analog power supply
voltage (AVCC) and a base clock (HCLK) cycle.
−
If the sampling time or compare clock cycle fails to meet the electrical characteristics of the A/D
converter, the A/D conversion accuracy may be degraded.
FM4_MN709-00003-4v0-E, May 27, 2015
CHAPTER 1-2: 12-bit A/D Converter
5. Registers
P E R I P H E R A L
5.
M A N U A L
Registers
This section explains the configuration and functions of the registers used for the 12-bit A/D converter.
Table 5-1 List of Registers for the 12-bit A/D Converter
Abbreviation
Reference
ADCR
A/D Control Register
5.1
ADSR
A/D Status Register
5.2
SCCR
Scan Conversion Control Register
5.3
SFNS
Scan Conversion FIFO Stage Count Setup Register
5.4
SCFD
Scan Conversion FIFO Data Register
5.5
SCIS
Scan Conversion Input Selection Register
5.6
PCCR
Priority Conversion Control Register
5.7
PFNS
Priority Conversion FIFO Stage Count Setup Register
5.8
PCFD
Priority Conversion FIFO Data Register
5.9
PCIS
Priority Conversion Input Selection Register
5.10
CMPD
A/D Comparison Value Setup Register
5.11
CMPCR
A/D Comparison Control Register
5.12
ADSS
Sampling Time Selection Register
5.13
ADST
Sampling Time Setup Register
5.14
ADCT
Comparison Time Setup Register
5.15
ADCEN
A/D Operation Enable Setup Register
5.16
WCMPDH
Upper Limit Threshold Setting Register
5.17
WCMPCR
Range Comparison Control Register
5.18
WCMPDL
Lower Limit Threshold Setting Register
5.19
WCMPSR
Range Comparison Channel Select Register
5.20
WCMRCOT
Range Comparison Threshold Excess Flag Register
5.21
WCMRCIF
Range Comparison Flag Register
5.22
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Register name
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CHAPTER 1-2: 12-bit A/D Converter
5. Registers
P E R I P H E R A L
5.1
M A N U A L
A/D Control Register (ADCR)
The A/D Control Register (ADCR) performs interrupt flag display and interrupt enable control.
bit
15
14
13
12
11
10
9
8
Field
SCIF
PCIF
CMPIF
Reserved
SCIE
PCIE
CMPIE
OVRIE
Attribute
R/W
R/W
R/W
-
R/W
R/W
R/W
R/W
Initial value
0
0
0
X
0
0
0
0
[bit15] SCIF: Scan conversion interrupt request bit
When conversion values are written up to the stage count specified in the Scan Conversion FIFO Stage
Count Setup Register (SFNS), this bit is set to 1. The read value of Read-Modify-Write operation is 1
regardless of the bit value.
Description
bit
Read
Write
0
Conversion result is not stored.
Clears this bit.
1
Conversion result is stored.
No effect.
[bit14] PCIF: Priority conversion interrupt request bit
When conversion values are written up to the stage specified in the Priority Conversion FIFO Stage Count
Setup Register (PFNS), this bit is set to 1. The read value of Read-Modify-Write operation is 1 regardless of
the bit value.
Description
bit
Read
Write
0
Conversion result is not stored.
Clears this bit.
1
Conversion result is stored.
No effect.
[bit13] CMPIF: Conversion result comparison interrupt request bit
When the condition set in the A/D Comparison Value Setup Register (CMPD) or A/D Comparison Control
Register (CMPCR) is satisfied during the operation of the A/D conversion result comparison function, this bit
is set to 1. The read value of Read-Modify-Write operation is 1 regardless of the bit value.
Description
bit
Read
Write
0
Specified condition is not satisfied.
Clears this bit.
1
Specified condition is satisfied.
No effect.
[bit12] Reserved: Reserved bit
Writing has no effect on operation.
The read value is undefined.
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CONFIDENTIAL
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CHAPTER 1-2: 12-bit A/D Converter
5. Registers
P E R I P H E R A L
M A N U A L
[bit11] SCIE: Scan conversion interrupt enable bit
This bit controls the interrupt request of SCIF. When the SCIE bit is enabled, and the SCIF bit is set, an
interrupt request to the CPU is generated.
bit
Description
0
Interrupt request disable
1
Interrupt request enable
[bit10] PCIE: Priority conversion interrupt enable bit
This bit controls the interrupt request of PCIF. When the PCIE bit is enabled, and the PCIF bit is set, an
interrupt request to the CPU is generated.
bit
Description
0
Interrupt request disable
1
Interrupt request enable
[bit9] CMPIE: Conversion result comparison interrupt enable bit
This bit controls the interrupt request of CMPIF. When the CMPIE bit is enabled, and the CMPIF bit is set, an
interrupt request to the CPU is generated.
bit
Description
0
Interrupt request disable
1
Interrupt request enable
[bit8] OVRIE: FIFO overrun interrupt enable bit
This bit controls the interrupt request of the SOVR bit in the SCCR register or the POVR bit in the PCCR
register. When the OVRIE bit is enabled, and the SOVR or POVR bit is set, an interrupt request to the CPU
is generated.
bit
0
Interrupt request disable
1
Interrupt request enable
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Description
55
CHAPTER 1-2: 12-bit A/D Converter
5. Registers
P E R I P H E R A L
5.2
M A N U A L
A/D Status Register (ADSR)
The A/D Status Register (ADSR) displays scan and priority conversion statuses.
bit
7
6
Field
ADSTP
FDAS
Attribute
R/W
Initial value
0
5
2
1
0
Reserved
4
3
PCNS
PCS
SCS
R/W
-
R
R
R
0
XXX
0
0
0
[bit7] ADSTP: A/D conversion forced stop bit
Setting the ADSTP bit to 1 stops the A/D conversion operation forcibly (both scan and priority conversion
operations are stopped). Forced stop of A/D conversion initializes the PCNS, PCS, and SCS bits in the
ADSR register to 0. However, other register bits are not reset.
bit
0
1
Description
Read
The value is always "0".
Write
No effect.
Stops the conversion operation forcibly.
[bit6] FDAS: FIFO data placement selection bit
Setting the FDAS bit to 1 shifts the Scan Conversion FIFO Data Register (SCFD) and Priority Conversion
FIFO Data Register (PCFD) conversion result values by 4 bits to the LSB side, placing them in bit27:16. The
position of the lower 16-bit of the FIFO data register does not change.
bit
Description
0
Places conversion result on the MSB side.
1
Places conversion result on the LSB side.
[bit5:3] Reserved: Reserved bits
Writing has no effect on operation.
The read value is undefined.
[bit2] PCNS: Priority conversion pending flag
This flag indicates that conversion at priority level 2 (software/timer) is pending. This flag is set when priority
conversion at priority level 2 (software/timer) is started while priority conversion at priority level 1 (external
trigger start) is performed or when conversion at priority level 1 is started while priority conversion at priority
level 2 is performed. Writing is ignored.
bit
56
CONFIDENTIAL
Description
0
Priority level 2 conversion is not pending.
1
Priority level 2 conversion is pending.
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CHAPTER 1-2: 12-bit A/D Converter
5. Registers
P E R I P H E R A L
M A N U A L
[bit1] PCS: Priority conversion status flag
This flag indicates that priority A/D conversion is in progress. This flag is set while priority conversion at
priority level 1 or 2 is performed. Writing is ignored.
bit
Description
0
Priority conversion is stopped.
1
Priority conversion is in progress.
[bit0] SCS: Scan conversion status flag
This flag indicates that scan A/D conversion is in progress. Writing is ignored.
bit
0
Scan conversion is stopped.
1
Scan conversion is in progress.
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Description
57
CHAPTER 1-2: 12-bit A/D Converter
5. Registers
P E R I P H E R A L
5.3
M A N U A L
Scan Conversion Control Register (SCCR)
The Scan Conversion Control Register (SCCR) controls the scan conversion mode.
bit
15
14
13
12
11
10
9
8
Field
SEMP
SFUL
SOVR
SFCLR
Reserved
RPT
SHEN
SSTR
Attribute
R
R
R/W
R/W
-
R/W
R/W
R/W
Initial value
1
0
0
0
X
0
0
0
[bit15] SEMP: Scan conversion FIFO empty bit
This bit is set when FIFO goes to the empty state. When conversion data is written in the Scan Conversion
FIFO Data Register (SCFD), this bit is set to 0. Writing is ignored.
bit
Description
0
Data remains in FIFO.
1
FIFO is empty.
[bit14] SFUL: Scan conversion FIFO full bit
This bit is set when FIFO goes to full state. When SFCLR is set to 1 or the Scan Conversion FIFO Data
Register (SCFD) is read, this bit is set to 0. Writing is ignored.
bit
Description
0
Data can be input to FIFO.
1
FIFO is full.
[bit13] SOVR: Scan conversion overrun flag
This bit is set when an attempt to write data to a full FIFO is made (conversion data in a full FIFO is not
overwritten). The read value of Read-Modify-Write operation is 1 regardless of the bit value. When the
OVRIE bit in the ADCR register is 1 and the SOVR bit is 1, an interrupt is generated to the CPU.
bit
Description
Read
Write
0
No overrun has occurred.
Clears this bit.
1
Overrun has occurred.
No effect.
[bit12] SFCLR: Scan conversion FIFO clear bit
Setting this bit to 1 clears the scan conversion FIFO. FIFO becomes empty and the SEMP bit is set to 1.
bit
0
1
58
CONFIDENTIAL
Description
Read
The value is always "0".
Write
No effect.
Clears FIFO.
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CHAPTER 1-2: 12-bit A/D Converter
5. Registers
P E R I P H E R A L
M A N U A L
[bit11] Reserved: Reserved bit
Writing has no effect on operation.
The read value is undefined.
[bit10] RPT: Scan conversion repeat bit
Setting this bit to 1 places the converter in the repeat mode. When the conversion of all analog input
channels selected in the Scan Conversion Input Selection Register (SCIS) is completed, the conversion is
started again.
Setting the RPT bit to 0 ends the repeat conversion. The operation stops when the conversion of the analog
input channels selected in the SCIS bit is completed.
Setting the RPT bit to 1 must be performed while scan conversion is stopped (ADSR: SCS= 0). (Setting the
SSTR bit to 1 may be performed simultaneously with setting the RPT bit to 1.)
bit
Description
0
Single conversion mode
1
Repeat conversion mode
Note:
−
The repeat transfer cannot be stooped immediately even when PRT bit is set to 0.
Writing data to FIFO will be continued until the transfer is stopped.
Note that FIFO data and Status bits (FIFO full bit etc.) continue to change until the transfer is
stopped.
[bit9] SHEN: Scan conversion timer start enable bit
Set this bit to 1 to start scan conversion using a rising edge from a timer. Software startup (SSTR = 1) is valid
even when this bit is set to 1.
bit
Description
0
Timer start disable
1
Timer start enable
[bit8] SSTR: Scan conversion start bit
Setting this bit to 1 starts A/D conversion. Setting this bit to 1 again during conversion stops the ongoing
conversion immediately and restarts the conversion.
bit
Description
Read
0
1
Write
No effect.
The value is always "0".
Starts conversion or restarts the conversion
(during conversion).
Note:
−
If a startup by a timer occurs simultaneously with the setting of the SSTR bit to 1, the setting of the
SSTR bit to 1 takes preference and the startup by the timer is ignored.
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CHAPTER 1-2: 12-bit A/D Converter
5. Registers
P E R I P H E R A L
5.4
M A N U A L
Scan Conversion FIFO Stage Count Setup Register (SFNS)
The Scan Conversion FIFO Stage Count Setup Register (SFNS) sets up the generation of interrupt requests
in scan conversion. When the specified count of FIFO stages store A/D conversion data, the interrupt
request bit (SCIF) is set.
bit
7
6
5
4
3
2
1
Field
Reserved
SFS[3:0]
Attribute
-
R/W
Initial value
XXXX
0000
0
[bit7:4] Reserved: Reserved bits
Writing has no effect on operation.
The read value is undefined.
[bit3:0] SFS[3:0]: Scan conversion FIFO stage count setting bits
When A/D conversion data for the FIFO stage count (N + 1) set in SFS[3:0] bits are written, the interrupt
request flag (SCIF) is set to 1.
bit3:0
0000
Generates an interrupt request when conversion result is stored in the first FIFO stage.
0001
Generates an interrupt request when conversion result is stored in the second FIFO stage.
0010
Generates an interrupt request when conversion result is stored in the third FIFO stage.
...
60
CONFIDENTIAL
Description
...
1101
Generates an interrupt request when conversion result is stored in the 14th FIFO stage.
1110
Generates an interrupt request when conversion result is stored in the 15th FIFO stage.
1111
Generates an interrupt request when conversion result is stored in the 16th FIFO stage.
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CHAPTER 1-2: 12-bit A/D Converter
5. Registers
P E R I P H E R A L
5.5
M A N U A L
Scan Conversion FIFO Data Register (SCFD)
The Scan Conversion FIFO Data Register (SCFD) consists of 16 FIFO stages and stores analog conversion
results. Data can be retrieved sequentially by reading the register.
bit
31
30
29
28
27
26
25
24
23
22
21
20
Field
SD
SD
SD
SD
SD
SD
SD
SD
SD
SD
SD
SD
11
10
9
8
7
6
5
4
3
2
1
0
19
18
17
Reserved
Attribute
R
R
Initial value
0xXXX
XXXX
bit
15
14
13
10
9
8
RS
RS
12
11
Field
Reserved
INV
Reserved
Attribute
R
R
R
R
R
R
Initial value
XXX
X
XX
XX
XXX
XXXXX
L
1
7
6
Reserved
0
5
16
4
3
2
1
0
SC
SC
SC
SC
SC
4
3
2
1
0
[bit31:20] SD11 to SD0: Scan conversion result
The result of 12-bit scan A/D conversion is written.
[bit19:13] Reserved: Reserved bits
The read value is undefined.
[bit12] INVL : A/D conversion result disable bit
This bit is set when this register value is invalid.
bit
Description
0
This register value is valid
1
This register value is invalid
[bit11:10] Reserved: Reserved bits
The read value is undefined.
[bit9:8] RS1, RS0: Scan conversion start factor
The start factor of the scan conversion corresponding to this register value is shown.
bit9:8
Description
01
Software start
10
Timer start
[bit7:5] Reserved: Reserved bits
The read value is undefined.
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CHAPTER 1-2: 12-bit A/D Converter
5. Registers
P E R I P H E R A L
M A N U A L
[bit4:0] SC4 to SC0: Conversion input channel bits
The analog input channels corresponding to the conversion result written in SD11 to SD0 are written.
Settings for channels not defined in the product specifications are not written. See the specified number of
the analog input channels in the Data Sheet of each product.
bit4:0
Description
00000
ch.0
00001
ch.1
00010
ch.2
...
...
11101
ch.29
11110
ch.30
11111
ch.31
Notes:
−
62
CONFIDENTIAL
−
This register has different bit configurations depending on the FDAS bit setting in the A/D Status
Register (ADSR). When the FDAS bit is 1, see 3.3.6 Bit placement Selection for FIFO Data
Registers.
To perform a byte access to this register, read the most significant byte (bit31:24) to shift the FIFO
data. Reading the other bytes (bit23:16, bit15:8, bit7:0) does not shift FIFO. To perform a half byte
access to this register, read the most significant half byte (bit 31:16) to shift the FIFO data. Reading
the other byte (bit15:0) does not shift FIFO. Performing a word access to this register shifts FIFO.
−
If software and a timer are started simultaneously, 0b11 may be read from the RS[1:0] bits.
FM4_MN709-00003-4v0-E, May 27, 2015
CHAPTER 1-2: 12-bit A/D Converter
5. Registers
P E R I P H E R A L
5.6
M A N U A L
Scan Conversion Input Selection Register (SCIS)
The Scan Conversion Input Selection Register (SCIS) is used to select analog input channels for which scan
conversion is performed. Any channels can be selected from multiple analog inputs. The selected channels
are converted in ascending order of channel number.
SCIS3 (most significant byte: AN31 to AN24) and SCIS2 (least significant byte: AN23 to
AN16)
bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Field
AN
AN
AN
AN
AN
AN
AN
AN
AN
AN
AN
AN
AN
AN
AN
AN
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Attribute
R/W
Initial value
0x00
[bit15:0] AN31 to AN16: Analog input selection bits
When these bits are set to 1, the corresponding channels are selected for analog conversion.
SCIS1 (most significant byte: AN15 to AN8) and SCIS0 (least significant byte: AN7 to AN0)
bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Field
AN
AN
AN
AN
AN
AN
AN
AN
AN
AN
AN
AN
AN
AN
AN
AN
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Attribute
R/W
Initial value
0x00
[bit15:0] AN15 to AN0: Analog input selection bits
When these bits are set to 1, the corresponding channels are selected for analog conversion.
Notes:
−
−
It is not allowed to change the channels during A/D conversion. Be sure to set SCIS3 to SCIS0 while
the A/D conversion is stopped. A/D conversion is not period of waiting start factors. It is allowed to
change the channel during no start factors period.
It is not possible to set 1 in the bit corresponding to a channel that is not defined in the product
specifications. See the specified number of the analog input channels in the Data Sheet of each
product.
Example of Scan Conversion Order
The selected channels are converted in ascending order of channel number.
Example : When the AN1, AN3, AN5, and AN23 bits are set to 1, the analog conversion
proceeds from ch.1, ch.3, ch.5, and to ch.23.
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CHAPTER 1-2: 12-bit A/D Converter
5. Registers
P E R I P H E R A L
5.7
M A N U A L
Priority Conversion Control Register (PCCR)
The Priority Conversion Control Register (PCCR) controls the priority conversion mode.
Priority conversion can be performed even while scan conversion is being performed.
In addition, different priority levels (two levels) can be given to priority conversion processes.
bit
15
14
13
12
11
10
9
8
Field
PEMP
PFUL
POVR
PFCLR
ESCE
PEEN
PHEN
PSTR
Attribute
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
1
0
0
0
0
0
0
0
[bit15] PEMP: Priority conversion FIFO empty bit
This bit is set when FIFO goes to the empty state. When conversion data is written in the Priority Conversion
FIFO Data Register (PCFD), this bit is set to "0". Writing is ignored.
bit
Description
0
Data remains in FIFO.
1
FIFO is empty.
[bit14] PFUL: Priority conversion FIFO full bit
This bit is set when FIFO goes to full state. When PFCLR bit is set to "1" or the Priority Conversion FIFO
Data Register (PCFD) is read, this bit is set to 0. Writing is ignored.
bit
Description
0
Data can be input to FIFO.
1
FIFO is full.
[bit13] POVR: Priority conversion overrun flag
This bit is set when an attempt to write data to a full FIFO is made (conversion data in a full FIFO is not
overwritten). The read value of Read-Modify-Write operation is 1 regardless of the bit value. When the
OVRIE bit in the ADCR register is 1, an interrupt is generated to the CPU if the POVR bit is 1.
bit
Description
Read
Write
0
No overrun has occurred.
Clears this bit.
1
Overrun has occurred.
No effect on operation.
[bit12] PFCLR: Priority conversion FIFO clear bit
Setting this bit to 1 clears the priority conversion FIFO. FIFO becomes empty and the PEMP bit is set to 1.
bit
0
1
64
CONFIDENTIAL
Description
Read
The value is always "0".
Write
No effect on operation
Clears FIFO.
FM4_MN709-00003-4v0-E, May 27, 2015
CHAPTER 1-2: 12-bit A/D Converter
5. Registers
P E R I P H E R A L
M A N U A L
[bit11] ESCE: External trigger analog input selection bit
This bit selects whether the external trigger analog input is selected with the P1A[2:0] bits in the Priority
Conversion Input Selection Register (PCIS) or the external input pin ECS[2:0] bits.
bit
Description
0
The external trigger analog inputs are selected with P1A[2:0].
1
The external trigger analog inputs are selected with an external input.
Notes:
−
−
It is not allowed to change the setting of the ESCE bit during A/D conversion. To change the setting,
make sure the A/D conversion is stopped. A/D conversion is not period of waiting start factors. It is
allowed to change the setting of the ESCE bit during no start factors period.
If channel selection with external pins ECS[2:0] cannot be used due to the product specifications, be
sure to set the ESCE bit to 0.
[bit10] PEEN: Priority conversion external start enable bit
Set this bit to 1 to start priority conversion using a falling edge of an external trigger pin input. Conversion
started with an external trigger has priority level 1 (highest priority).
bit
Description
0
External trigger start disable
1
External trigger start enable
[bit9] PHEN: Priority conversion timer start enable bit
Set this bit to 1 to start priority conversion using a rising edge from a timer. Software startup (PSTR = 1) is
valid even when this bit is set to 1. Conversion started with an external trigger has priority level 2
(lower priority than level 1).
bit
Description
0
Timer start disable
1
Timer start enable
[bit8] PSTR: Priority conversion start bit
Setting this bit to 1 starts A/D conversion. Conversion started with this bit has priority level 2 (lower than
priority level 1). It is not possible to restart the conversion started with this bit.
bit
0
1
May 27, 2015, FM4_MN709-00003-4v0-E
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Description
Read
The value is always "0".
Write
No effect on operation
Starts priority conversion.
65
CHAPTER 1-2: 12-bit A/D Converter
5. Registers
P E R I P H E R A L
5.8
M A N U A L
Priority Conversion FIFO Stage Count Setup Register (PFNS)
The Priority Conversion FIFO Stage Count Setup Register (PFNS) sets up the generation of interrupt
requests in priority conversion. When the specified count of FIFO stages store A/D conversion data, the
interrupt request bit (PCIF) is set.
bit
7
6
5
4
3
2
1
0
Field
Reserved
TEST[1:0]
Reserved
PFS[1:0]
Attribute
-
R
-
R/W
Initial value
XX
XX
XX
00
[bit7:6] Reserved: Reserved bits
Writing has no effect on operation.
The read value is undefined.
[bit5:4] TEST[1:0]: Test bits
Write
Has no effect on operation.
Read
The value is undefined.
[bit3:2] Reserved: Reserved bits
Writing has no effect on operation.
The read value is undefined.
[bit1:0] PFS[1:0]: Priority conversion FIFO stage count setting bits
When A/D conversion data for the FIFO stage count (N + 1) set in PFS[1:0] is written, the interrupt request
flag (PCIF) is set to 1.
bit1:0
66
CONFIDENTIAL
Description
00
Generates an interrupt request when conversion result is stored in the first FIFO stage.
01
Generates an interrupt request when conversion result is stored in the second FIFO stage.
10
Generates an interrupt request when conversion result is stored in the third FIFO stage.
11
Generates an interrupt request when conversion result is stored in the fourth FIFO stage.
FM4_MN709-00003-4v0-E, May 27, 2015
CHAPTER 1-2: 12-bit A/D Converter
5. Registers
P E R I P H E R A L
5.9
M A N U A L
Priority Conversion FIFO Data Register (PCFD)
The Priority Conversion FIFO Data Register (PCFD) consists of four FIFO stages and stores analog
conversion results. Data can be retrieved sequentially by reading the register.
bit
31
30
29
28
27
26
25
24
23
22
21
20
Field
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
11
10
9
8
7
6
5
4
3
2
1
0
19
18
17
Reserved
Attribute
R
R
Initial value
0xXXX
XXXX
bit
15
14
13
12
7
11
10
9
8
Field
Reserved
INV
Rese
RS
RS
RS
6
L
rved
2
1
0
Attribute
R
R
R
R
R
R
Initial value
XXX
X
X
XXX
XXX
XXXXX
Reserved
5
16
4
3
2
1
0
PC
PC
PC
PC
PC
4
3
2
1
0
[bit31:20] PD11 to PD0: Priority conversion result
The result of 12-bit priority A/D conversion is written.
[bit19:13] Reserved: Reserved bits
The read value is undefined.
[bit12] INVL: A/D conversion result disable bit
This bit is set when this register value is invalid.
bit
Description
0
This register value is valid
1
This register value is invalid
[bit11] Reserved: Reserved bit
The read value is undefined.
[bit10:8] RS2 to RS0: Scan conversion start factor
The start factor of the priority conversion corresponding to this register value is shown.
bit10:8
Software start (priority level 2)
010
Timer start (priority level 2)
100
External trigger (priority level 1)
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CONFIDENTIAL
Description
001
67
CHAPTER 1-2: 12-bit A/D Converter
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M A N U A L
[bit7:5] Reserved: Reserved bits
The read value is undefined.
[bit4:0] PC4 to PC0: Conversion input channel bits
The analog input channels corresponding to the conversion result written in PD11 to PD0 are written.
Settings for channels not defined in the product specifications are not written. See the specified number of
the analog input channels in the "Data Sheet" of each product.
bit4:0
Description
00000
ch.0
00001
ch.1
00010
ch.2
...
...
11101
ch.29
11110
ch.30
11111
ch.31
Notes:
−
−
−
−
68
CONFIDENTIAL
This register has different bit configurations depending on the FDAS bit setting in the A/D Status
Register (ADSR). When the FDAS bit is 1, see 3.3.6 Bit placement Selection for FIFO Data
Registers.
To perform a byte access to this register, read the most significant byte (bit31:24) to shift the FIFO
data. Reading the other bytes (bit23:16, bit15:8, bit7:0) does not shift FIFO. To perform a half word
access to this register, read the most significant half word (bit31:16) to shift FIFO. Reading the other
byte (bit15:0) does not shift FIFO. Performing a word access to this register shifts FIFO.
If software and a timer are started simultaneously, 0b011 may be read from the RS[2:0] bits.
Conversion started with an external trigger can be performed only when the analog input channel is
between ch.0 to ch.7.
FM4_MN709-00003-4v0-E, May 27, 2015
CHAPTER 1-2: 12-bit A/D Converter
5. Registers
P E R I P H E R A L
M A N U A L
5.10 Priority Conversion Input Selection Register (PCIS)
The Priority Conversion Input Selection Register (PCIS) is used to select the analog input channels for
which priority conversion is performed. For software or timer start at priority level 2, only one channel can be
selected from multiple analog input channels. For external trigger start at priority level 1, one channel can be
selected from eight channels (ch.0 to ch.7).
bit
7
6
Field
5
4
3
2
1
P2A[4:0]
P1A[2:0]
Attribute
R/W
R/W
Initial value
00000
000
0
[bit7:3] P2A[4:0]: Priority level 2 analog input selection
This bit specifies the analog input channel for a start at priority level 2 (software/timer). It can be selected
from all channels. It is not possible to set the channel that is not defined in the product specifications. See
the specified number of the analog input channels in the "Data Sheet" of each product.
bit7:3
Description
00000
ch.0
00001
ch.1
00010
ch.2
...
...
11101
ch.29
11110
ch.30
11111
ch.31
[bit2:0] P1A[2:0]: Priority level 1 analog input selection
This bit specifies the analog input channel for a start at priority level 1 (external trigger). It can be selected
from eight channels (ch.0 to ch.7).
bit2:0
Description
000
ch.0
001
ch.1
010
ch.2
...
...
101
ch.5
110
ch.6
111
ch.7
Note:
−
It is not allowed to change the channel during A/D conversion. Be sure to write a value to P1A or
P2A when the A/D conversion is stopped. A/D conversion is not period of waiting start factors. It is
allowed to change the channel during no start factors period.
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CHAPTER 1-2: 12-bit A/D Converter
5. Registers
P E R I P H E R A L
M A N U A L
5.11 A/D Comparison Value Setup Register (CMPD)
The A/D Comparison Value Setup Register (CMPD) sets the value to be compared with the A/D conversion
result. When the conditions set in both this register and the A/D Comparison Control Register (CMPCR) are
satisfied, the conversion result comparison interrupt request bit (CMPIF) in the A/D Control Register (ADCR)
is set.
bit
31
30
29
28
27
26
25
24
Field
CMAD11
CMAD10
CMAD9
CMAD8
CMAD7
CMAD6
CMAD5
CMAD4
Attribute
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
bit
23
22
21
20
19
18
17
16
Field
CMAD3
CMAD2
Attribute
R/W
R/W
Reserved
-
Initial value
0
0
XXXXXX
[bit31:22] CMAD11 to CMAD2: A/D conversion compare value setting bits
These bits set the value to be compared with the A/D conversion result.
The most significant 10 bits (bit11:2) of the A/D conversion result are compared with the value in this register
(CMAD11 to CMAD2). The least significant two bits (bit1:0) of the A/D conversion result are not compared.
[bit21:16] Reserved: Reserved bits
The read value is undefined.
70
CONFIDENTIAL
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CHAPTER 1-2: 12-bit A/D Converter
5. Registers
P E R I P H E R A L
M A N U A L
5.12 A/D Comparison Control Register (CMPCR)
The A/D Comparison Control Register (CMPCR) controls the A/D comparison function. When the converted
value is compared with the value in the A/D Comparison Value Setup Register (CMPD) and the comparison
condition in this register is satisfied, the conversion result comparison interrupt request bit (CMPIF) in the
A/D Control Register (ADCR) is set.
bit
7
6
5
Field
CMPEN
CMD1
CMD0
4
3
2
Attribute
R/W
R/W
R/W
R/W
Initial value
0
0
0
00000
1
0
CCH[4:0]
[bit7] CMPEN: Conversion result comparison function operation enable bit
This bit enables the operation of the A/D comparison function.
bit
Description
0
Stops the comparison function operation.
1
Enables the comparison function operation.
[bit6] CMD1: Comparison mode 1
This bit sets the condition for generating a conversion interrupt request.
bit
0
1
Description
Generates an interrupt request when the most significant 10 bits (bit11:2) of the A/D
conversion result is smaller than the CMPD set value.
Generates an interrupt request when the most significant 10 bits (bit11:2) of the A/D
conversion result is equal to or greater than the CMPD set value.
[bit5] CMD0: Comparison mode 0
This bit selects the comparison target. When this bit is 1, the setting of CCH[4:0] is invalid.
bit
Description
0
Compares the conversion result of the channel set in CCH[4:0].
1
Compares the conversion results of all channels.
[bit4:0] CCH[4:0]: Comparison target analog input channel
This bit sets the analog channel to be compared. When the CMD0 bit is 1, setting of this bit is invalid. It is not
possible to set the channel that is not defined in the product specifications. See the specified number of the
analog input channels in the "Data Sheet" of each product.
bit4:0
ch.0
00001
ch.1
00010
ch.2
...
...
11101
ch.29
11110
ch.30
11111
ch.31
May 27, 2015, FM4_MN709-00003-4v0-E
CONFIDENTIAL
Description
00000
71
CHAPTER 1-2: 12-bit A/D Converter
5. Registers
P E R I P H E R A L
M A N U A L
5.13 Sampling Time Selection Register (ADSS)
The Sampling Time Selection Register (ADSS3 to ADSS0) allows you to set the sampling time for each bit.
Which of the sampling times set in Sampling Time Setup Registers 0 and 1 (ADST0 and ADST1) is used is
specified in this register.
ADSS3 (most significant byte: TS31 to TS24) and ADSS2 (least significant byte: TS23 to
TS16)
bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Field
TS3
TS3
TS2
TS2
TS2
TS2
TS2
TS2
TS2
TS2
TS2
TS2
TS1
TS1
TS1
TS1
1
0
9
8
7
6
5
4
3
2
1
0
9
8
7
6
Attribute
R/W
Initial value
0x0000
[bit15:0] TS31 to TS16: Sampling time selection bits
Set the sampling time specified in the Sampling Time Setup Register (ADST) for the corresponding channel.
Setting 0 specifies the time set in ADST0 and setting 1 specifies the time set in ADST1. TS31 to TS16
correspond respectively to ch.31 to ch.16.
ADSS1 (most significant byte: TS15 to TS8) and ADSS0 (least significant byte: TS7 to TS0)
bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Field
TS1
TS1
TS1
TS1
TS1
TS1
TS9
TS8
TS7
TS6
TS5
TS4
TS3
TS2
TS1
TS0
5
4
3
2
1
0
Attribute
R/W
Initial value
0x0000
[bit15:0] TS15 to TS0: Sampling time selection bits
Set the sampling time specified in the Sampling Time Setup Register (ADST) for the corresponding channel.
Setting 0 specifies the time set in ADST0 and setting "1" specifies the time set in ADST1. TS15 to TS0
correspond respectively to ch.15 to ch.0.
Notes:
−
−
72
CONFIDENTIAL
It is not allowed to write to the ADSS register during A/D conversion. A/D conversion is not period of
waiting start factors. It is allowed to write to the ADSS register during no start factors period.
It is not possible to set 1 in the bit corresponding to a channel that is not defined in the product
specifications. See the specified number of the analog input channels in the "Data Sheet" of each
product.
FM4_MN709-00003-4v0-E, May 27, 2015
CHAPTER 1-2: 12-bit A/D Converter
5. Registers
P E R I P H E R A L
M A N U A L
5.14 Sampling Time Setup Register (ADST)
Sampling Time Setup Registers 0 and 1 (ADST0 and ADST1) set the sampling times for A/D conversion.
ADST0 and ADST1 are provided for setting two sampling times, and which one is used is selected in the
Sampling Time Selection Register (ADSS3 to ADSS0).
ADST0 (most significant byte)
bit
15
14
13
12
11
10
9
8
Field
STX02
STX01
STX00
ST04
ST03
ST02
ST01
ST00
Attribute
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
1
0
0
0
0
[bit15:13] STX02 to STX00: Sampling time N times setting bits
These bits multiply the sampling time set values in the ST04 to ST00 bits by N.
bit15
bit14
bit13
0
0
0
Set value × 1 (Initial value)
Description
0
0
1
Set value × 4
0
1
0
Set value × 8
0
1
1
Set value × 16
1
0
0
Set value × 32
1
0
1
Set value × 64
1
1
0
Set value × 128
1
1
1
Set value × 256
[bit12:8] ST04 to ST00: Sampling time setting bits
These bit set the sampling time for A/D conversion.
Sampling time = HCLK cycle × Clock division ratio {(ST set value + 1) × STX setting multiplier + 3}
Example : When ST04 to ST00 = 9, STX02, STX01, and STX00 = 001 (multiplied by 4),
CT7 to CT0=0x00 (Clock frequency division ratio: 2), and HCLK = 20 MHz (50 ns),
Sampling time = 50 ns × 2 {(9 + 1) × 4 + 3} = 4300ns
Notes:
−
−
−
It is not allowed to write to the ADST0 register during A/D conversion. A/D conversion is not period
of waiting start factors. It is allowed to write to the ADST0 register during no start factors period.
For setting the sampling time, refer to the "Electrical Characteristics" in the "Data Sheet" to make
sure that an appropriate time should be selected in accordance with an external impedance of an
input channel, an analog power supply voltage (AVCC), and a base clock (HCLK) cycle.
When STX02, STX01, and STX00 = 000 (ST04 to ST00 set values multiplied by 1) are set, set ST04
to ST00 to 2 or more (1 or less must not be set).
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CHAPTER 1-2: 12-bit A/D Converter
5. Registers
P E R I P H E R A L
M A N U A L
ADST1 (least significant byte)
bit
7
6
5
4
3
2
1
0
Field
STX12
STX11
STX10
ST14
ST13
ST12
ST11
ST10
Attribute
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
1
0
0
0
0
[bit7:5] STX12 to STX10: Sampling time N times setting bits
These bits multiply the sampling time set values in the ST14 to ST10 bits by N.
bit7
bit6
bit5
0
0
0
Set value × 1(initial value)
Description
0
0
1
Set value × 4
0
1
0
Set value × 8
0
1
1
Set value × 16
1
0
0
Set value × 32
1
0
1
Set value × 64
1
1
0
Set value × 128
1
1
1
Set value × 256
[bit4:0] ST14 to ST10: Sampling time setting bits
These bit set the sampling time for A/D conversion.
Sampling time = HCLK cycle × Clock division ratio {(ST set value + 1) × STX setting multiplier + 3}
Example : When ST14 to ST10 = 9, STX12, STX11, and STX10 = 001 (multiplied by 4),
CT7 to CT0=0x00 (Clock frequency division ratio: 2), and HCLK = 20 MHz (50 ns),
Sampling time = 50 ns × {(9 + 1) × 4 + 3} = 4300ns
Notes:
−
−
−
74
CONFIDENTIAL
It is not allowed to write to the ADST1 register during A/D conversion. A/D conversion is not period
of waiting start factors. It is allowed to write to the ADST1 register during no start factors period.
For setting the sampling time, refer to the Electrical Characteristics in the Data Sheet to make sure
that an appropriate time should be selected in accordance with an external impedance of an input
channel, an analog power supply voltage (AVCC), and a base clock (HCLK) cycle.
When STX12, STX11, and STX10 = 000 (ST14 to ST10 set values multiplied by 1) are set, set ST14
to ST10 to 2 or more (1 or less must not be set).
FM4_MN709-00003-4v0-E, May 27, 2015
CHAPTER 1-2: 12-bit A/D Converter
5. Registers
P E R I P H E R A L
M A N U A L
5.15 Frequency Division Ratio Setup Register (ADCT)
The Frequency Division Ratio Setup Register (ADCT) sets the clock frequency division ratio, which is part
of the A/D conversion time.
bit
7
6
5
4
3
2
1
0
Field
CT7
CT6
CT5
CT4
CT3
CT2
CT1
CT0
Attribute
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
1
1
1
[bit7:0] CT7 to CT0: Frequency division ratio setting bits
These bits set the division ratio of the HCLK frequency for generating the clock of A/D conversion.
The frequency division ratio setting is common in Sampling Setup Registers 0 and 1 (ADST0/1).
bit7:0
Description
0x80
Frequency division ratio 1
0x00
Frequency division ratio 2
0x01
Frequency division ratio 3
0x02
Frequency division ratio 4
...
0X07
...
...
Frequency division ratio 9 (Initial value)
...
0x3C
Frequency division ratio 62
0x3D
Frequency division ratio 63
0x3E
Frequency division ratio 64
0x3F
Frequency division ratio 65
Compare clock cycle = Base clock (HCLK) cycle × Frequency division ratio
Comparison time = Compare clock cycle × 14
Example : When the CT[7:0] set value = 0 (Compare frequency division ratio: 2) and
HCLK = 20 MHz (50 ns),
Compare clock cycle = 50 ns × 2 = 100 ns
Comparison time = 100 ns × 14 = 1400 ns
Notes:
−
−
−
Setting 0x40 to 0x7F to bit7:0 is not allowed.
It is not allowed to write to the clock division setting register (ADCT) during A/D conversion. A/D
conversion is not period of waiting start factors. It is allowed to write to the clock division setting
register (ADCT) during no start factors period.
Only when the base clock prescaler register (BSC_PSR) of clock generator is set to 0x0, A/D
conversion can be performed in frequency division ratio at 1.
For setting the compare clock cycle, refer to the Electrical Characteristics in the Data Sheet to make
sure that an appropriate time should be selected in accordance with an analog power supply voltage
(AVCC) and a base clock (HCLK) cycle.
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CHAPTER 1-2: 12-bit A/D Converter
5. Registers
P E R I P H E R A L
M A N U A L
5.16 A/D Operation Enable Setup Register (ADCEN)
The A/D Operation Enable Setup Register (ADCEN) is used to turn the 12-bit A/D converter to the operation
enable state.
bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Field
ENBLTIME[15:8]
Reserved
READY
ENBL
Attribute
R/W
R
R
R/W
Initial value
0xFF
000000
0
0
[bit15:8] ENABLETIME[15:8]: Operation enable state transition cycle selection bits
These bits select the cycle count of operation enable state transition period.
Operation enable state transition period= Base clock (HCLK) cycle (ENABLETIME setting value 4 + 1)
Example) When ENBLTIME[15:8] = 0xFF, and HCLK = 20MHz (50ns),
Operation enable state transition period = 50 ns (2554 + 1) = 51050 ns
[bit7:2] Reserved: Reserved bits
The read value is undefined.
[bit1] READY: A/D operation enable state bit
This bit indicates whether the A/D converter is in the operation enable state or in the operation stop state.
A/D conversion can be performed only in the operation enable state.
An A/D conversion request in the operation stop state is ignored.
If the A/D converter enters the operation stop state during A/D conversion, A/D conversion stops
immediately.
bit
Description
0
Operation stop state
1
Operation enable state
[bit0] ENBL: A/D operation enable bit
This bit enables the operation of the A/D converter.
Writing 1 to the ENBL bit turns the A/D converter to the operation enable state after the period of operation
enable state transitions. On the other hand, writing 0 to this bit turns the A/D converter to the operation stop
state.
bit
Description
0
Stops operation
1
Enables operation
Note:
−
76
CONFIDENTIAL
For setting the period of operation enable state transition, refer to the Electrical Characteristics in
the Data Sheet to make sure that an appropriate time should be selected in accordance with an
analog power supply voltage (AVCC) and a base clock (HCLK) cycle.
It is not allowed to rewrite ENBLTIME[15:8] during the period between writing 1 to ENBL bit and
setting READY bit to 1.
When setting the CPU to the timer mode, the stop mode, RTC mode, deep standby STOP mode,
and deep standby RTC mode, set the ENBL bit to 0 and turn the A/D converter to the operation stop
state.
FM4_MN709-00003-4v0-E, May 27, 2015
CHAPTER 1-2: 12-bit A/D Converter
5. Registers
P E R I P H E R A L
M A N U A L
5.17 Upper Limit Setup Register (WCMPDH)
The Upper Limit Setup Register (WCMPDH) is used to set the upper limit used for the range comparison.
bit
31
30
29
28
27
26
25
24
Field
CMHD11
CMHD10
CMHD9
CMHD8
CMHD7
CMHD6
CMHD5
CMHD4
Attribute
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
21
20
19
18
17
16
bit
23
22
Field
CMHD3
CMHD2
Reserved
Attribute
R/W
R/W
R
Initial value
0
0
000000
[bit32:22] CMHD11 to CMHD2: Upper limit bits
These bits specify the upper limit threshold used for range comparison.
bit31:22
Description
Upper limit
[bit21:16] Reserved: Reserved bits
When writing, always write 0.
When reading, 0 is always read.
Note:
−
When the range comparison function enabled, the most significant 10 bits (bit11:2) of the A/D
conversion result is compared with this register (CMHD). The comparison with the least significant 2
bits (bit1:0) of the A/D conversion result is not executed.
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CHAPTER 1-2: 12-bit A/D Converter
5. Registers
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M A N U A L
5.18 Range Comparison Control Register (WCMPCR)
The range comparison control register (WCMPCR) is used for the confirmation of continuous detection
specification count and its state, the selection of within-range or out-of-range confirmation, the confirmation
of upper limit excess or lower limit excess in the out-of-range area, and enabling and disabling of range
comparison interrupt.
bit
7
6
5
4
3
2
Field
RCOCD2
RCOCD1
RCOCD0
RCOIRS
RCOIE
RCOE
1
0
Attribute
R/W
R/W
R/W
R/W
R/W
R/W
R
Initial value
0
0
1
0
0
0
00
Reserved
[bit7:5] RCOCD2 to RCOCD0: Continuous detection specification count/state indication
bits
These bits indicate continuous detection specification count and continuous detection time state of range
comparison result.
Description
bit7:5
000
At reading except in RMW accessing
At reading or at writing in RMW
accessing
Continuous detection state: 0 times
Setting prohibited
001
Continuous detection state: 1 time
Specified continuous detection time: 1
010
Continuous detection state: 2 times
Specified continuous detection time: 2
011
Continuous detection state: 3 times
Specified continuous detection time: 3
100
Continuous detection state: 4 times
Specified continuous detection time: 4
101
Continuous detection state: 5 times
Specified continuous detection time: 5
110
Continuous detection state: 6 times
Specified continuous detection time: 6
111
Continuous detection state: 7 times
Specified continuous detection time: 7
When the range comparison result count reaches the continuous detection specification count, the range
comparison interrupt factor flag bit (RCINT) of the corresponding start channel is set to 1. And the
continuous detection state is stopped at the continuous detection specification count.
At reading other the read-modify-write (RMW) access, the continuous detection state is read out.
At reading other the read-modify-write (RMW) access, the written value (the continuous detection
specification count) is read out.
Notes:
−
−
78
CONFIDENTIAL
Do not change the continuous detection specification count bit and state indication bit (RCOCD)
while the range comparison operation is enabled (RCOE=1).
Do not set 000 to the continuous detection specification count bit and state indication bit (RCOCD).
FM4_MN709-00003-4v0-E, May 27, 2015
CHAPTER 1-2: 12-bit A/D Converter
5. Registers
P E R I P H E R A L
M A N U A L
[bit4] RCOIRS: Selection bit of within-range and out-of- range confirmation
bit
Description
0
Confirmation of out-of-range
1
Confirmation of within-range
The A/D conversion result (scan conversion or priority conversion) selects the range comparison
conditions of out-of- range or within-range for upper limit threshold bit (CMHD) and lower limit threshold bit
(CMLD) selected by the upper/lower limit threshold selection bit (RCOTS).
The range comparison condition at the out-of-range confirmation (RCOIRS=0) is as follows:
A/D conversion result (scan conversion or priority conversion) > upper limit threshold bit (CMHD)
Or, A/D conversion result (scan conversion or priority conversion) < lower limit threshold bit (CMLD)
The range comparison condition at the within-range confirmation (RCOIRS=1) is as follows:
A/D conversion result (scan conversion or priority conversion) upper limit threshold bit (CMHD)
And, A/D conversion result (scan conversion or priority conversion) ≥ lower limit threshold bit
(CMLD)
At the range comparison detection for the out-of-range range confirmations (RCOIRS="0"), the upper limit
threshold excess or below the lower limit threshold can be confirmed by threshold excess flag bit
(RCOOF).
[bit3] RCOIE: Range comparison interrupt request enable bit
bit
Description
0
Range comparison interrupt disabled
1
Range comparison interrupt enabled
When the range comparison interrupt factor flag bit (RCINT) of the corresponding startup channel is set to
1 and when the range comparison interrupt request is enabled (RCOIE=1), the interrupt request is
generated.
[bit2] RCOE: Range comparison execution enable bit
Selects A/D comparison function and range comparison function.
bit
Description
0
Range comparison execution disabled
1
Range comparison execution enabled
When the range comparison execution enable bit (RCOE) is 0, the range comparison execution is disabled.
Moreover, the continuous detection count sate is initialized to 000.
When the range comparison execution enable bit (RCOE) is 1, the range comparison execution is enabled.
[bit1:0] Reserved: Reserved bits
When writing, always write 0.
When reading, 0 is always read.
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CHAPTER 1-2: 12-bit A/D Converter
5. Registers
P E R I P H E R A L
M A N U A L
5.19 Lower Limit Threshold Setup Register (WCMPDL)
The lower limit threshold setup register (WCMPDL) is used to set the lower limit threshold for the range
comparison.
bit
31
30
29
28
27
26
25
24
Field
CMLD11
CMLD10
CMLD9
CMLD8
CMLD7
CMLD6
CMLD5
CMLD4
Attribute
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
21
20
19
18
17
16
bit
23
22
Field
CMLD3
CMLD2
Reserved
Attribute
R/W
R/W
R
Initial value
0
0
000000
[bit32:22] CMLD11 to CMLD2: Lower limit threshold bits
Set the lower limit threshold used for the range comparison.
bit
Description
Lower limit threshold
[bit21:16] Reserved: Reserved bits
When writing, always write 0.
When reading, 0 is always read.
Note:
−
80
CONFIDENTIAL
When the range comparison execution is enabled, the most significant 10 bits (bit11:2) of the A/D
conversion result is compared with this register (CMLD). The comparison with the least significant 2
bits (bit1:0) of the A/D conversion result is not executed.
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CHAPTER 1-2: 12-bit A/D Converter
5. Registers
P E R I P H E R A L
M A N U A L
5.20 Range Comparison Channel Select Register (WCMPSR)
The range comparison channel select register (WCMPSR) is used to set the channel for the range
comparison.
bit
7
6
5
4
3
2
Field
Reserved
WCMD
Attribute
R
R/W
R/W
Initial value
00
0
00000
1
0
WCCH[4:0]
[bit7:6] Reserved: Reserved bits
When writing, always write 0.
When reading, 0 is always read.
[bit5] WCMD: Comparison mode select bit
bit
Description
0
Compares the conversion result of the channel set with WCCH[4:0] bits.
1
Compares the conversion results of all channels.
Selects the target for the range comparison. When this bit is 1, the setting of WCCH[4:0] bits becomes
invalid.
[bit4:0] WCCH[4:0]: Comparison target analog input channel
bit
Description
00000
Ch.0
00001
Ch.1
00010
Ch.2
---
---
11101
Ch.29
11110
Ch.30
11111
Ch.31
Selects the target analog input channel for comparison. When WCMD bit is 1, the setting of these bits is
invalid. It is not possible to set the channel that is not defined in the product specifications. See the specified
number of the analog input channels in the Data Sheet of the product used.
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CHAPTER 1-2: 12-bit A/D Converter
5. Registers
P E R I P H E R A L
M A N U A L
5.21 Range Comparison Threshold Excess Flag Register (WCMRCOT)
The range comparison threshold excess flag register (WCMCOT) is used to indicate that the comparison
result is beyond the upper limit threshold or below the lower limit threshold in the out-of-range confirmation
setting.
bit
31
30
29
28
Field
Reserved
Attribute
R
Initial value
0x00
bit
23
22
21
20
Field
Attribute
R
0x00
15
14
13
12
Field
Reserved
Attribute
R
Initial value
0x00
bit
26
25
24
19
18
17
16
11
10
9
8
3
2
1
Reserved
Initial value
bit
27
7
6
5
Field
4
0
Reserved
RCOOF
Attribute
R
R/W
Initial value
0000000
0
[bit31:1] Reserved: Reserved bits
When writing, always write 0.
When reading, 0 is always read.
[bit0] RCOOF: Threshold excess flag bit
bit
Description
0
Below the lower limit threshold (A/D data Lower limit threshold bit)
1
Beyond the upper limit threshold (A/D data Upper limit threshold bit)
For the confirmation of outside-range (RCOIRS=0), this bit indicates that the range comparison result is
greater than the upper limit threshold setting register (RCOOF=1), or the result is smaller than the lower
limit threshold (RCOOF=0).
For the confirmation of outside-range (RCOIRS=0), when the range comparison result is confirmed to be
within the range, the threshold excess flag bit holds the prior value.
When the range comparison interrupt factor flag bit (RCINT) of the corresponding startup channel is set to
be 1, the threshold excess flag bit (RCOOF) is not updated and holds the prior value, even if the range
comparison result is confirmed to be outside the range for the confirmation of outside-range (RCOIRS=0).
For the confirmation of within-range (RCOIRS=1), the threshold excess flag bit has no meaning (the bit
holds the prior value.)
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CHAPTER 1-2: 12-bit A/D Converter
5. Registers
P E R I P H E R A L
M A N U A L
5.22 Range Comparison Flag Register (WCMRCIF)
The range comparison flag register (WCMRCIF) indicates the interrupt factor due to the continuous
detection of the range comparison result.
bit
31
30
29
28
Field
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
Reserved
Attribute
R
Initial value
0x00
bit
23
22
21
20
Field
Reserved
Attribute
R
Initial value
0x00
bit
15
14
13
12
Field
Reserved
Attribute
R
Initial value
0x00
Bit
7
6
5
Field
4
0
Reserved
RCINT
Attribute
R
R/W
Initial value
0000000
0
[bit31:1] Reserved: Reserved bits
When writing, always write 0.
When reading, 0 is always read.
[bit0] RCINT: Range comparison interrupt factor flag bit
bit
0
Description
Read
Range comparison interrupt factor clear
state
Write
Bit clear
State where the interrupt factor is generated
1
due to the continuous detection of range
No change and no influence to others.
comparison results
The RCINT bit is set to 1 by the continuous detection of the range comparison results of the corresponding
startup channel.
When RCINT bit and range comparison interrupt request permission (RCOIE) of the corresponding startup
channel are 1, the range comparison interrupt request is generated.
At writing, the RCINT bit is cleared by 0, the bit is not changed by 1 and has no influence to others.
Notes:
−
−
At read-modify-write access (RMW), 1 is read.
When the software clear (writing RCINT=0) and hardware set occurs simultaneously, the hardware
set has a priority.
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CHAPTER 1-2: 12-bit A/D Converter
5. Registers
P E R I P H E R A L
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M A N U A L
FM4_MN709-00003-4v0-E, May 27, 2015
CHAPTER 1-3: A/D Timer Trigger Selection
This chapter explains the functions and operations to select a timer trigger of the A/D
converter.
1. Overview
2. Registers
CODE: 9BFBATSB_FM4-E01.0
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CHAPTER 1-3: A/D Timer Trigger Selection
2. Registers
P E R I P H E R A L
1.
M A N U A L
Overview
This section explains the operations to select a timer trigger of the A/D converter.
Selecting a Timer Trigger of the A/D Converter
The A/D converter can be started by the factors shown in Table 1-1.
Table 1-1 A/D Converter Start Factor
Conversion type
Priority level 1 conversion
Start factor
−
Input from an external trigger pin (at falling edge)
−
Software (when the Priority Conversion Start Bit(PSTR ) of Priority Conversion
Priority level 2 conversion
Control Register (PCCR) is set to 1)
−
Trigger input from timer (at rising edge)
−
Software (when the Scan Conversion Start Bit (SSTR) of SCAN Conversion
Scan conversion
Control Register (SCCR) is set to 1)
−
Trigger input from timer (at rising edge)
The A/D converter can be started with two types of timers: base timer and multifunction timer.
A timer start factor can be selected using the Scan Conversion Timer Trigger Selection Register (SCTSL) or
Priority Conversion Timer Trigger Selection Register (PRTSL). The A/D converter starts A/D conversion if a
rising edge of the selected timer is detected while timer starting is enabled.
The multiple A/D converters can use same start factor.
For details on the operations of the 12-bit A/D converter, see 3. Explanation of operations in the 12-bit A/D
Converter.
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CHAPTER 1-3: A/D Timer Trigger Selection
2. Registers
P E R I P H E R A L
2.
M A N U A L
Registers
This section explains the configuration and functions of the registers used to select an A/D timer trigger.
List of Timer Trigger Selection Registers for A/D Converter
Abbreviation
Reference
SCTSL
Scan Conversion Timer Trigger Selection Register
2.1
PRTSL
Priority Conversion Timer Trigger Selection Register
2.2
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Register name
87
CHAPTER 1-3: A/D Timer Trigger Selection
2. Registers
P E R I P H E R A L
2.1
M A N U A L
Scan Conversion Timer Trigger Selection Register (SCTSL)
The Scan Conversion Timer Trigger Selection Register (SCTSL) is used to select a timer trigger when
performing scan conversion.
bit
15
14
13
12
11
10
9
Field
Reserved
Attribute
R
R/W
Initial value
XXXX
0000
8
SCTSL[3:0]
[bit15:12] Reserved: Reserved bits
The read values are undefined.
Writing has no effect in operation.
[bit11:8] SCTSL[3:0]: Scan conversion timer trigger selection bits
bit11:8
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CONFIDENTIAL
Description
0000
No selected trigger (Input is fixed to 0.)
0001
Starts scan conversion with the multifunction timer.
0010
Base timer ch.0
0011
Base timer ch.1
0100
Base timer ch.2
0101
Base timer ch.3
0110
Base timer ch.4
0111
Base timer ch.5
1000
Base timer ch.6
1001
Base timer ch.7
1010
Base timer ch.8
1011
Base timer ch.9
1100
Base timer ch.10
1101
Base timer ch.11
1110
Base timer ch.12
1111
Base timer ch.13
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CHAPTER 1-3: A/D Timer Trigger Selection
2. Registers
P E R I P H E R A L
2.2
M A N U A L
Priority Conversion Timer Trigger Selection Register (PRTSL)
The Priority Conversion Timer Trigger Selection Register (PRTSL) is used to select a timer trigger when
performing priority conversion.
bit
7
6
5
4
3
2
1
Field
Reserved
Attribute
R
R/W
Initial value
XXXX
0000
0
PRTSL[3:0]
[bit7:4] Reserved: Reserved bits
The read values are undefined.
Writing has no effect in operation.
[bit3:0] PRTSL[3:0]: Priority conversion timer trigger selection bits
bit3:0
No selected trigger (Input is fixed to 0.)
0001
Starts priority conversion with the multifunction timer.
0010
Base timer ch.0
0011
Base timer ch.1
0100
Base timer ch.2
0101
Base timer ch.3
0110
Base timer ch.4
0111
Base timer ch.5
1000
Base timer ch.6
1001
Base timer ch.7
1010
Base timer ch.8
1011
Base timer ch.9
1100
Base timer ch.10
1101
Base timer ch.11
1110
Base timer ch.12
1111
Base timer ch.13
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Description
0000
89
CHAPTER 1-3: A/D Timer Trigger Selection
2. Registers
P E R I P H E R A L
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M A N U A L
FM4_MN709-00003-4v0-E, May 27, 2015
CHAPTER 1-4: A/D Converter Offset Calibration
This chapter describes the offset calibration for the A/D converter.
1.
2.
3.
4.
5.
6.
Overview
Configuration Block Diagram
Operation
Setting Procedure Example
Register List
Usage Precautions
Control code:
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CHAPTER 1-4: A/D Converter Offset Calibration
1. Overview
P E R I P H E R A L
1.
M A N U A L
Overview
The A/D converter in this device has an offset error due to process variation.
Offset correction of the A/D converter is performed for correcting the zero-transition voltage and full scale
transition voltage. This enables the elimination of intermediate code error for minimizing the overall error.
Figure 1-1 Overall Error before Correction
Output Code
Ideal characteristics
Actual characteristics
4095
Overall error
2047
0
AVRL
Vinp
1/2
AVRH
AVRH
Figure 1-2 Overall Error after Correction
Output Code
Ideal characteristics
Actual characteristics
4095
Overall error
2047
Overall error is reduced by
minimizing the error in
intermediate codes
0
AVRL
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Vinp
1/2
AVRH
AVRH
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CHAPTER 1-4: A/D Converter Offset Calibration
2. Configuration Block Diagram
P E R I P H E R A L
2.
M A N U A L
Configuration Block Diagram
The block diagram of the A/D converter offset calibration is shown in Figure 2-1.
Figure 2-1 Block Diagram of A/D Converter Offset Calibration
APB-Bus
キャリブレーション設定レジスタ
Calibration setting register
キャリブレーション許可ビット
Calibration
enable bit
オフセット設定ビット
offset
setting bit
AVRH
AVRL
AN01
.
.
.
Analog Selector
AN00
A/D
convertor
A/Dコンバータ
unit
Unit
AN30
AN31
Setting the calibration setting register connects AVRH and AVRL to the A/D converter, enabling A/D
conversion.
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CHAPTER 1-4: A/D Converter Offset Calibration
3. Operation
P E R I P H E R A L
3.
M A N U A L
Operation
This section describes the operation of the offset calibration for the A/D converter.
3.1 Operation of A/D Converter Offset Calibration
3.1.1
Setting the Value for Offset Calibration
An offset calibration value can be written to the offset calibration value setting bit (OFST) in the calibration
setting register (CALSR) to correct the offset error of the A/D converter due to process variation.
Figure 3-1 shows the change in characteristics when offset calibration is performed.
Figure 3-1 Offset Characteristics
Output Code
OFST[7:0] = 00000001
4095
OFST[7:0] = 01111111
OFST[7:0] = 10000001
-31.75LSB
-0.25LSB
OFST[7:0] = 00000000
+31.75LSB
0
AVRL
Vinp
AVRH
In offset calibration, the OFST bit can be set to 0x7F to enable -31.75LSB correction, and the OFSET bit can
be set to 0x81 to enable correction up to +31.75LSB. The 0.25LSB characteristics can be shifted per 1-bit
correction of the OFST bit.
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CHAPTER 1-4: A/D Converter Offset Calibration
3. Operation
P E R I P H E R A L
3.1.2
M A N U A L
A/D Converter Offset Calibration
Following three steps must be completed to perform offset calibration for the A/D converter.
A/D conversion of the analog reference voltage value AVRH
A/D conversion of the analog reference voltage value AVRL
Calculation of offset calibration value
The detailed setting steps are provided starting from section 3.1.2.
An A/D conversion must be performed for the analog reference voltage value before performing offset
calibration for the A/D converter. For this purpose, an A/D conversion of the analog reference voltage value
(AVRH/AVRL) is provided.
In A/D conversion of AVRH/AVRL, maximum offset correction is performed to obtain the code for
AVRH/AVRL.
Output Code
Ideal
characteristics
Actual characteristics when the offsets are
changed to the maximum and minimum values
Actual characteristics
before correction
409
5
(1) Conversion of AVRH
(2) Conversion of
AVRL
0
AVRL
Vinp
AVRH
(1) For details on the AVRH conversion method, see 3.1.2.1 AVRH Conversion Method.
(2) For details on the AVRL conversion method, see 3.1.2.2 AVRL Conversion Method.
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3. Operation
P E R I P H E R A L
M A N U A L
Next, connect the AVRH conversion result and AVRL conversion result with a line, and find the difference
between the ideal line and the intermediate code. The difference from the ideal line indicates the code
amount for which calibration is required.
Output Code
Ideal
characteristics
Line connecting
AVRL/AVRH
Actual characteristics when the offsets are
changed to the maximum and minimum values
4095
AVRH conversion result
(4) Performing offset
correction for minimizing
the overall error
2047
(3) Obtaining the difference
from the ideal characteristics
AVRL conversion
result
0
AVRL
Vinp
AVRH
For details on (3) and (4), see 3.1.3 Calculation of Offset Calibration Value.
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CHAPTER 1-4: A/D Converter Offset Calibration
3. Operation
P E R I P H E R A L
M A N U A L
The intermediate code difference required for calibration is minimized for reducing the overall error.
Output Code
Ideal
characteristics
Characteristics
before correction
Characteristics after correction
4095
Minimizing the intermediate code
difference for reducing the overall error
2047
0
Vinp
AVRL
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AVRH
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CHAPTER 1-4: A/D Converter Offset Calibration
3. Operation
P E R I P H E R A L
M A N U A L
3.1.3
A/D Converter Offset Calibration Setting Example
3.1.3.1 AVRH conversion method
1.
Only the bit that corresponds to AN0 of the scan conversion input selection register (SCIS) is set to 1,
and all other bits are set to 0.
2.
The CALEN bit in the calibration setting register (CALSR) is set to 1, and the OFST bit is set to 0x81.
3.
Scan conversion of the A/D converter is performed, and the conversion results are fetched from the
scan conversion FIFO data register (SCFD) after the conversion is completed.
3.1.3.2
3.1.4
AVRL conversion method
1.
Only the bit that corresponds to AN1 of the scan conversion input selection register (SCIS) only is set
to 1, and all other bits are all set to 0.
2.
The CALEN bit of the calibration setting register (CALSR) is set to 1, and the OFST bit is set to 0x7F.
3.
Scan conversion of the A/D converter is performed, and the conversion results are fetched from the
scan conversion FIFO data register (SCFD) after the conversion is completed.
Calculation of Offset Calibration Value
The calculation method for data that is written to the offset calibration value setting bit (OFST) in the
calibration setting register (CALSR) is shown below.
The formula below is used to calculate the difference of intermediate code between the actual
characteristics and ideal characteristics based on the AVRH/AVRL voltage conversion values.
OFT_CAL = 2047.5 - (OFT_VRH + OFT_VRL) / 2
* OFT_VRH: A/D conversion value of AVRH
OFT_VRL: A/D conversion value of AVRL
The offset calibration value (OFST) is calculated from the OFT_CAL calculation value, and it is written to the
offset calibration value setting bit (OFST). The register value required for offset can be found by setting to
four times the OFT_CAL value.
OFST = OFT_CAL * 4
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CHAPTER 1-4: A/D Converter Offset Calibration
4. Setting Procedure Example
P E R I P H E R A L
4.
M A N U A L
Setting Procedure Example
This section provides an example of the setting procedure for the offset calibration function for the A/D
converter.
Figure 4-1 Example of AVRH A/D Conversion Setting Procedure
Start
Initial setting
･Sampling time setting (ADST0, ADST1, and ADSS are set)
･Clock frequency division ratio setting (ADCT is set)
･FIFO data layout setting (ADSR:FDAS=”1” Write)
･A/D conversion function is not used (CMPCR:CMPEN=”0” Write)
･Interrupt is not used (ADCR:SCIE=”0” Write)
Analog reference voltage (AVRH) is set to the analog input channel
･Scan conversion input selection register setting
(SCIS3=SCIS2=SCIS1=”0x00” Write, SCIS0=”0x01” Write)
･Setting of calibration setting register (CALSR)
(CALEN="1" Write, OFST=”0x81” Write)
･FIFO clear (SCCR:SFCLR="1" Write)
･Conversion mode setting (SCCR:RPT=”0” Write)
･A/D software start (SCCR:SSTR=”1” Write)
Read the lower 16 bits of SCFD register
Data enable/disable
determination
SCFD:INVL="0"?
No
Yes
Read the upper 16 bits of SCFD register
(AVRH A/D conversion result reading)
END
Note
−
The A/D conversion of AVRH/AVRL can be performed at the fastest speed setting provided in
"Electrical Characteristics" of the Data Sheet for your product.
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CHAPTER 1-4: A/D Converter Offset Calibration
4. Setting Procedure Example
P E R I P H E R A L
M A N U A L
Figure 4-2 Example of AVRL A/D Conversion Setting Procedure
Start
Initial setting
･Sampling time setting (ADST0, ADST1, and ADSS are set)
･Clock frequency division ratio setting (ADCT is set)
･FIFO data layout setting (ADSR:FDAS=”1” Write)
･A/D conversion function is not used (CMPCR:CMPEN=”0” Write)
･Interrupt not used (ADCR:SCIE= ”0” Write)
Analog reference voltage (AVRL) is set to the analog input channel
･Scan conversion input selection register setting
(SCIS3=SCIS2=SCIS1=”0x00” Write, SCIS0=”0x02” Write)
･Setting of calibration setting register (CALSR)
(CALEN="1" Write, OFST=”0x7F” Write)
･FIFO clear (SCCR:SFCLR="1" Write)
･Conversion mode setting (SCCR:RPT=”0” Write)
･A/D software start (SCCR:SSTR=”1” Write)
Read the lower 16 bits of SCFD register
Data enable/disable
determination
SCFD:INVL=“0”？
No
Yes
Read the upper 16 bits of SCFD register
(AVRL A/D conversion result reading)
END
Note
−
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The A/D conversion of AVRH/AVRL can be performed at the fastest speed setting provided in
Electrical Characteristics of the Data Sheet for your product.
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CHAPTER 1-4: A/D Converter Offset Calibration
5. Register List
P E R I P H E R A L
5.
M A N U A L
Register List
This section describes the registers for the offset calibration function of the A/D converter.
Register abbreviation
CALSR
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Register name
Calibration setting register
Refer to
5.1
101
CHAPTER 1-4: A/D Converter Offset Calibration
5. Register List
P E R I P H E R A L
5.1
M A N U A L
Calibration Setting Register (CALSR)
The calibration setting register (CALSR) is used to set whether calibration (offset calibration) is allowed and
to set the offset calibration value.
Bit
31
9
8
7
0
Field
Reserved
CLBEN
Attribute
-
R/W
OFST
R/W
Default value
-
0
0x00
[bit31:9] Reserved: Reservation bit
A value read out always be 0.
Write a value of 0.
[bit8] CLBEN: Calibration permission bit
This bit determines whether the calibration operation of the A/D converter is permitted.
Bit
Description
0
Calibration operation stop (default value)
1
Calibration operation permitted
[bit7:0] OFST: Offset calibration value setting bit
This bit sets the offset calibration value of the A/D converter.
Bit
Writing
Reading
Description
This bit sets the offset calibration value of the A/D converter.
The value that was set is read out.
The default value is 0x00.
The OFST bit can be changed to set the calibration values shown below.
OFST
Correction value
0x7F
-31.75 LSB
:
:
0x01
-0.25 LSB
0x00
0 LSB
0xFF
+0.25 LSB
:
:
0x81
+31.75 LSB
0x80
Setting prohibited
Notes
−
−
102
CONFIDENTIAL
Overwriting of this register is prohibited during A/D conversion.
When set to calibration operation permitted (CLBEN=1), conversion operations other than scan
conversion are prohibited.
FM4_MN709-00003-4v0-E, May 27, 2015
CHAPTER 1-4: A/D Converter Offset Calibration
6. Usage Precautions
P E R I P H E R A L
6.
M A N U A L
Usage Precautions
This section provides the usage precautions of the offset calibration for the A/D converter.
Overwriting of the calibration setting register (CALSR) is prohibited during A/D conversion.
When the calibration operation is permitted (CALEN=1 for the calibration setting register (CALSR)), all
conversion operations other than scan conversion are prohibited.
Before performing the calibration operation, stop the conversion operations for units other than the unit
performing calibration. Simultaneous calibration of multiple units is prohibited.
During A/D conversion of AVRH and AVRL, do not restart scan conversion by setting SSTR of the scan
conversion control register (SCCR) to 1.
If A/D conversion is performed for a channel other than AVRH and AVRL, be sure to always set the offset
calibration value setting bit (CLBEN) of the calibration setting register (CALSR) to 0.
If measurement error occurred due to the measurement environment, perform conversion of AVRH/AVRL
multiple times, and then use the average value to perform offset calibration.
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103
CHAPTER 1-4: A/D Converter Offset Calibration
6. Usage Precautions
P E R I P H E R A L
104
CONFIDENTIAL
M A N U A L
FM4_MN709-00003-4v0-E, May 27, 2015
CHAPTER 2: 12-bit D/A Converter
This chapter explains the functions and operations of the 12-bit D/A converter.
1. Overview
2. Configuration
3. Operations
4. Example of Setting Procedure
5. Registers
CODE:
May 27, 2015, FM4_MN709-00003-4v0-E
CONFIDENTIAL
9xFBDA12M3_FM4-E01.0
105
CHAPTER 2: 12-bit D/A Converter
2. Configuration
P E R I P H E R A L
1.
M A N U A L
Overview
The 12-bit D/A converter converts a 12-bit digital value into an analog value.
Features of the 12-bit D/A Converter
12-bit resolution (Maximum: 2 units)
− 12-bit mode / 10-bit mode can be selected.
R-2R method
The 12-bit D/A converter stops operating in the following low power consumption modes.
− RTC mode
− Stop mode
− Deep standby RTC mode
− Deep standby Stop mode
106
CONFIDENTIAL
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CHAPTER 2: 12-bit D/A Converter
3. Operations
P E R I P H E R A L
2.
M A N U A L
Configuration
This section shows the configuration of the 12-bit D/A converter.
12-bit D/A Converter Block Diagram
Figure 2-1 12-bit D/A Converter Block Diagram
Peripheral bus
D/A converter
operation enable bit
D/A Data Register
Digital input
Stop
RTC mode
STOP mode
Deep standby RTC mode
Deep standby STOP mode
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D/A converter
Analog output
DAx
AVCC
AVSS
107
CHAPTER 2: 12-bit D/A Converter
3. Operations
P E R I P H E R A L
3.
M A N U A L
Operations
This section explains the operations of the 12-bit D/A converter.
Set the 12-bit D/A converter to operation enable state before performing D/A conversion. When 1 is written
to the DAE bit in the D/A Control Register (DACR), the 12-bit D/A converter transits from operation stop state
to operation enable state. When 0 is written to the DAE bit in the D/A Control Register (DACR), the 12-bit
D/A converter transits to operation stop state immediately.
D/A conversion can be executed only in the operation enable state. D/A conversion is prohibited in the
operation stop state.
It can be checked whether the 12-bit D/A converter is in the operation enable state by reading the DRDY bit
in the D/A Control Register (DACR).
If a value is written to the D/A Data Register (DADR) in the operation enable state, the 12-bit D/A converter
converts the digital value written into an analog value and outputs the analog value from the DAx pin. In this
situation, the direction of the I/O port is input, input to the I/O port is blocked, and the I/O port is disconnected
from the pull-up resistor.
In certain low power consumption modes, regardless of the setting of the DAE bit, the operation of the 12-bit
D/A converter stops.
If the DAE bit in the D/A Control Register (DACR) is 1 when the 12-bit D/A converter returns from a low
power consumption mode, the 12-bit D/A converter transits from the operation stop state to the operation
enable state after the operation enable state transition period has elapsed.
Table 3-1 shows the operation state of the 12-bit D/A converter.
Table 3-1 Operation State of the 12-bit D/A Converter
Operation mode
DRDY
12-bit D/A converter operation
RTC mode
STOP mode
Deep standby RTC mode
-
Stopped
0
Stopped
1
Enabled
Deep standby STOP mode
Modes other than the above
In 12-bit mode, the voltage that can be output when the operation of the 12-bit D/A converter is enabled
ranges from 0.0 V to 4095/4096×AVCC (AVCC: voltage of AVCC pin). Table 3-2 shows the relation between
the D/A Data Register (DADR) and the ideal output voltage.
Table 3-2 Relation between DA[11:0] and Analog Output Value in 12-bit Mode
DA[11:0]
108
CONFIDENTIAL
Ideal output voltage
000000000000
0 / 4096 × AVCC
000000000001
1 / 4096 × AVCC
000000000010
2 / 4096 × AVCC
...
...
111111111101
4093 / 4096 × AVCC
111111111110
4094 / 4096 × AVCC
111111111111
4095 / 4096 × AVCC
FM4_MN709-00003-4v0-E, May 27, 2015
CHAPTER 2: 12-bit D/A Converter
4. Example of Setting Procedure
P E R I P H E R A L
M A N U A L
In 10-bit mode, the voltage that can be output when the operation of the 12-bit D/A converter is enabled
ranges from 0.0 V to 1023/1024×AVCC (AVCC: voltage of AVCC pin). Table 3-3 shows the ideal output
voltages with the 10-bit mode data allocation selection bit (DDAS) in the D/A Data Register (DADR) set to 0,
and Table 3-4 shows the ideal output voltages with the 10-bit mode data allocation selection bit (DDAS) in
the D/A Data Register (DADR) set to 1.
Table 3-3 Relation between DA[11:0] of DDAS=0 and Analog Output Value
DA[11:0]
Ideal output voltage
000000000000
0 / 1024 × AVCC
000000000100
1 / 1024 × AVCC
000000001000
2 / 1024 × AVCC
...
...
111111110100
1021 / 1024 × AVCC
111111111000
1022 / 1024 × AVCC
111111111100
1023 / 1024 × AVCC
Table 3-4 Relation between DA[11:0] of DDAS=1 and Analog Output Value
DA[11:0]
Ideal output voltage
000000000000
0 / 1024 × AVCC
000000000001
1 / 1024 × AVCC
000000000010
2 / 1024 × AVCC
...
...
001111111101
1021 / 1024 × AVCC
001111111110
1022 / 1024 × AVCC
001111111111
1023 / 1024 × AVCC
When the 12-bit D/A converter stops operating, its output is Hi-Z.
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109
CHAPTER 2: 12-bit D/A Converter
5. Registers
P E R I P H E R A L
4.
M A N U A L
Example of Setting Procedure
This section provides an example of procedure for setting the 12-bit D/A converter.
Below is the setting procedure for making the 12-bit D/A converter operate and output a conversion result to
the DAx pin.
1. Set the operation mode using DAC10 and DDAS in the D/A Control Register (DACR), and set the DAE bit
to 1.
2. Wait until the DRDY bit in the D/A Control Register (DACR) becomes 1.
3. Write to the D/A Data Register (DADR) the digital value to be converted into an analog value.
After the above settings have been completed, an analog value is output from the DAx pin.
Notes:
−
110
CONFIDENTIAL
After DAE in the D/A Control Register (DACR) has been set to 1, the output of the DAx pin is
indeterminate until a digital value is written to the D/A Data Register (DADR).
FM4_MN709-00003-4v0-E, May 27, 2015
CHAPTER 2: 12-bit D/A Converter
5. Registers
P E R I P H E R A L
5.
M A N U A L
Registers
This section explains the configuration and functions of registers used in the 12-bit D/A converter.
List of 12-bit D/A Converter Registers
Abbreviation
Reference
DACR
D/A Control Register
5.1
DADR
D/A Data Register
5.2
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Register name
111
CHAPTER 2: 12-bit D/A Converter
5. Registers
P E R I P H E R A L
5.1
M A N U A L
D/A Control Register (DACR)
The D/A Control Register (DACR) controls the operation of the 12-bit D/A converter.
bit
23
21
20
Reserved
DDAS
DAC10
Attribute
-
R/W
Initial value
XX
0
Field
22
19
17
16
Reserved
18
DRDY
DAE
R/W
-
R
R/W
0
XX
0
0
[bit23:22] Reserved: Reserved bits
The read value is indeterminate.
Writing a value to a reserved bit has no effect on operation.
[bit21] DDAS: 10-bit mode data allocation selection bit
In 10-bit mode, DDAS selects the conversion target bits in the D/A Data Register (DADR).
In 12-bit mode, regardless of the setting of this bit, DA[11:0] in the D/A Data Register (DADR) are selected
as the conversion target bits.
bit
Description
0
DA[11:2] in the D/A Data Register (DADR)
1
DA[9:0] in the D/A Data Register (DADR)
[bit20] DAC10: 10-bit mode
DAC switches the operation mode of the 12-bit D/A converter between 10-bit mode and 12-bit mode.
bit
Description
0
12-bit mode
1
10-bit mode
[bit19:18] Reserved: Reserved bits
The read value is indeterminate.
Writing a value to a reserved bit has no effect on operation.
[bit17] DRDY: D/A converter operation enable state bit
bit
Description
0
Operation stop state
1
Operation enable state
[bit16] DAE: D/A converter operating enable bit
bit
112
CONFIDENTIAL
Description
0
Stops the operation of the D/A converter.
1
Enables the operation of the D/A converter.
FM4_MN709-00003-4v0-E, May 27, 2015
CHAPTER 2: 12-bit D/A Converter
5. Registers
P E R I P H E R A L
5.2
M A N U A L
D/A Data Register (DADR)
The D/A Data Register sets the digital value to be converted into analog signal.
bit
15
14
Field
13
12
11
10
Reserved
Attribute
-
R/W
Initial value
XXXX
XXXX
bit
7
6
9
8
1
0
DA[11:8]
5
4
3
Field
DA[7:0]
Attribute
R/W
Initial value
0xXX
2
[bit15:12] Reserved: Reserved bits
The read value is indeterminate.
Writing a value to a reserved bit has no effect on operation.
[bit11:0] DA[11:0]: D/A Data Register
The 12-bit D/A converter executes D/A conversion immediately after a value has been written to DA[11:0].
In 10-bit mode, write 0 to an unused bit.
See Table 3-2 for the relation between the setting of this register and the output voltage.
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CHAPTER 2: 12-bit D/A Converter
5. Registers
P E R I P H E R A L
114
CONFIDENTIAL
M A N U A L
FM4_MN709-00003-4v0-E, May 27, 2015
Appendixes
This chapter shows the register map, list of notes, limitations and product type list.
A. Register Map
B. List of Notes
CODE: 9BFAPPENDIXES-E03.0
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115
A. Register Map
This chapter shows the register map.
1. Register Map
1.1 FLASH_IF
1.2 Unique ID
1.3 ECC Capture Address
1.4 Clock/Reset
1.5 HW WDT
1.6 SW WDT
1.7 Dual_Timer
1.8 MFT
1.9 PPG
1.10 Base Timer
1.11 IO Selector for Base Timer
1.12 QPRC
1.13 QPRC NF
1.14 A/DC
1.15 CR Trim
1.16 EXTI
1.17 INT-Req. READ
1.18 D/AC
1.19 HDMI-CEC
1.20 GPIO
1.21 LVD
1.22 DS_Mode
1.23 USB Clock
1.24 CAN_Prescaler
1.25 MFS
1.26 CRC
1.27 Watch Counter
1.28 RTC
1.29 Low-speed CR Prescaler
1.30 Peripheral Clock Gating
1.31 Smart Card Interface
1.32 MFSI2S
1.33 I2S Prescaler
1.34 GDC_Prescaler
1.35 EXT-Bus I/F
1.36 USB
1.37 DMAC
1.38 DSTC
1.39 CAN
1.40 Ethernet-MAC
116
CONFIDENTIAL
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A. Register Map
1. Register Map
P E R I P H E R A L
1.41
1.42
1.43
1.44
1.45
1.46
1.47
1.48
1.49
1.50
M A N U A L
Ethernet-Control
I2S
SD-Card
CAN FD
Programmable-CRC
WorkFlash_IF
High-Speed Quad SPI Controller
HyperBus Interface
GDC Sub System Controller
GDC Sub System SDRAM Controller
CODE: 9BFREGMAP_FM4-J01.0
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A. Register Map
1. Register Map
P E R I P H E R A L
1.
M A N U A L
Register Map
Register map is shown on the table every module/function.
[How to read the each table]
Module/function name and its base address
Clock/Reset
Base_Address : 0x4001_0000
Base_Address
Register
+ Address
+3
0x000
+2
-
0x004
+1
-
-
+0
SCM_CTL[B,H,W]
-
-
00000-0SCM_STR[B,H,W]
-
00000-0-
STB_CTL[B,H,W]
0x008
00000000 00000000 -------- ---0--00
0x00C
-
RST_STR[B,H,W]
-
-------0 00000-01
Initial value after reset
- : Reserved area
* : Test register area
"1"
:
Initial value is 1
"0"
:
Initial value is 0
"X"
:
Initial value is undefined
"-"
:
Reserved bit
Register name
Access unit
(B: byte, H: half word, W: word)
Rightmost register address (For word-length access, the "+0" column of the register is
the LSB of the data.)
Notes:
−
−
−
−
−
−
−
118
CONFIDENTIAL
The register table is represented in the little-endian.
When performing a data access, the addresses should be as below according to the access size.
Word access:
Address should be multiples of 4 (least significant 2 bits should be 0x00)
Half word access:
Address should be multiples of 2 (least significant bit should be 0x0)
Byte access:
Do not access the test register area.
Do not access the area that is not written in the register table.
FM4_MN709-00003-4v0-E, May 27, 2015
A. Register Map
1. Register Map
P E R I P H E R A L
1.1
M A N U A L
FLASH_IF
1.1.1
TYPE1-M4, TYPE2-M4 products
FLASH_IF Base_Address : 0x4000_0000
Register
Base_Address
+ Address
+3
+2
0x000
FASZR[B,H,W]
0x004
FRWTR[B,H,W]
0x008
FSTR[B,H,W]
0x00C
*
0x010
FSYNDN[B,H,W]
0x014
FBFCR[B,H,W]
0x018 - 0x01C
-
-
0x020
FISR[B,H,W]
0x028
FICLR[B,H,W]
-
-
-
-
0x100
0x104 - 0x1FC
+0
-
-
-
-
-
-
FICR[B,H,W]
0x024
0x02C - 0x0FC
+1
CRTRMM[B,H,W]
Note:
−
For details of Flash I/F registers, see Flash Programming Manual of the product used.
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119
A. Register Map
1. Register Map
P E R I P H E R A L
1.1.2
M A N U A L
TYPE3-M4 product
FLASH_IF Base_Address : 0x4000_0000
Register
Base_Address
+ Address
+3
+2
0x000
FASZR[B,H,W]
0x004
FRWTR[B,H,W]
0x008
FSTR[B,H,W]
0x00C
*
0x010
FSYNDN[B,H,W]
0x014
FBFCR[B,H,W]
0x018 - 0x01C
-
-
0x020
FICR[B,H,W]
0x024
FISR[B,H,W]
0x028
0x02C
-
-
-
-
FGPDM1[B,H,W]
0x114
FGPDM2[B,H,W]
0x118
FGPDM3[B,H,W]
0x11C
-
-
-
-
-
-
-
-
+1
+0
-
-
Register
+3
+2
0x400
DFASZR[B,H,W]
0x404
DFRWTR[B,H,W]
0x408
0x40C - 0x4FC
-
FGPDM4[B,H,W]
-
Base_Address
+ Address
-
CRTRMM[B,H,W]
0x110
0x120 - 0x1FC
-
DFCTRLR[W]
0x100
0x104 - 0x10C
+0
FICLR[B,H,W]
-
0x030
0x034 - 0x0FC
+1
DFSTR[B,H,W]
-
-
Note:
−
120
CONFIDENTIAL
For details of Flash I/F registers, see Flash Programming Manual of the product used.
FM4_MN709-00003-4v0-E, May 27, 2015
A. Register Map
1. Register Map
P E R I P H E R A L
1.1.3
M A N U A L
TYPE4-M4, TYPE5-M4, TYPE6-M4 products
FLASH_IF Base_Address : 0x4000_0000
Register
Base_Address
+ Address
+3
+2
0x000
FASZR[B,H,W]
0x004
FRWTR[B,H,W]
0x008
FSTR[B,H,W]
0x00C
*
0x010
FSYNDN[B,H,W]
0x014
FBFCR[B,H,W]
0x018 - 0x01C
-
-
0x020
FICR[B,H,W]
0x024
FISR[B,H,W]
0x028
0x02C - 0x0FC
+0
-
-
-
-
-
-
FICLR[B,H,W]
-
-
0x100
0x104 - 0x10C
+1
CRTRMM[B,H,W]
-
-
0x110
FGPDM1[B,H,W]
0x114
FGPDM2[B,H,W]
0x118
FGPDM3[B,H,W]
0x11C
FGPDM4[B,H,W]
0x120 - 0x1FC
-
Note:
−
For details of Flash I/F registers, see Flash Programming Manual of the product used.
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121
A. Register Map
1. Register Map
P E R I P H E R A L
1.2
M A N U A L
Unique ID
Unique ID Base_Address : 0x4000_0200
Register
Base_Address
+ Address
+3
+0
XXXXXXXX XXXXXXXX XXXXXXXX XXXX---UIDR1[W]
0x004
1.3
+1
UIDR0[W]
0x000
0x008 - 0xDFC
+2
-------- -------- ---XXXXX XXXXXXXX
-
-
-
-
+1
+0
ECC Capture Address
ECC Capture Address
Base_Address : 0x4000_0300
Register
Base_Address
+ Address
+3
FERRAD[W]
0x000
0x004 - 0xFFC
122
CONFIDENTIAL
+2
-------- -XXXXXXX XXXXXXXX XXXXXXXX
-
-
-
-
FM4_MN709-00003-4v0-E, May 27, 2015
A. Register Map
1. Register Map
P E R I P H E R A L
M A N U A L
1.4 Clock/Reset
1.4.1
TYPE1-M4, TYPE2-M4 products
Clock/Reset
Base_Address : 0x4001_0000
Register
Base_Address
+ Address
0x000
0x004
+3
-
+1
-
-
-
00000-0SCM_STR[W]
-
00000-0-
00000000 00000000 -------- ---0-000
RST_STR[W]
0x00C
-
-
0x010
-
-
-
0x014
-
-
-
0x018
-
-
-
0x01C
-
-
-
-------0 0000--01
0x020
-
-
-
0x024 – 0x027
-
-
-
0x028
-
-
-
0x02C – 0x02F
-
-
-
0x030
-
-
-
0x034
-
-
-
0x038
-
-
-
0x03C
-
-
-
0x040
-
-
0x044
-
-
0x048
-
-
0x04C
-
-
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+0
SCM_CTL[W]
STB_CTL[W]
0x008
CONFIDENTIAL
+2
BSC_PSR[W]
-----000
APBC0_PSR[W]
------00
APBC1_PSR[W]
1--0--00
APBC2_PSR[W]
1--0--00
SWC_PSR[W]
------00
TTC_PSR[W]
------00
CSW_TMR[W]
00000000
PSW_TMR[W]
---0-000
PLL_CTL1[W]
00000000
PLL_CTL2[W]
--000000
CSV_CTL[W]
-111--00 ------11
-
CSV_STR[W]
------00
FCSWH_CTL[W]
11111111 11111111
FCSWL_CTL[W]
00000000 00000000
123
A. Register Map
1. Register Map
P E R I P H E R A L
Register
Base_Address
124
CONFIDENTIAL
M A N U A L
+ Address
+3
+2
0x050
-
-
0x054
-
-
-
0x058
-
-
-
0x05C - 0x05F
-
-
-
+1
+0
FCSWD_CTL[W]
00000000 00000000
0x060
-
-
-
0x064
-
-
-
0x068
-
-
-
0x06C – 0xFFC
-
-
-
DBWDT_CTL[W]
0-0----*
INT_ENR[W]
--0--000
INT_STR[W]
--0–000
INT_CLR[W]
--0--000
-
FM4_MN709-00003-4v0-E, May 27, 2015
A. Register Map
1. Register Map
P E R I P H E R A L
1.4.2
M A N U A L
TYPE3-M4, TYPE4-M4, TYPE5-M4, TYPE6-M4 products
Clock/Reset
Base_Address : 0x4001_0000
Register
Base_Address
+ Address
0x000
0x004
+3
-
-
+1
-
-
-
00000-0SCM_STR[W]
-
00000-0-
00000000 00000000 -------- ---0-000
RST_STR[W]
0x00C
-
-
0x010
-
-
-
0x014
-
-
-
0x018
-
-
-
0x01C
-
-
-
-------0 0000--01
0x020
-
-
-
0x024 – 0x027
-
-
-
0x028
-
-
-
0x02C – 0x02F
-
-
-
0x030
-
-
-
0x034
-
-
-
0x038
-
-
-
0x03C
-
-
-
0x040
-
-
0x044
-
-
0x048
-
-
0x04C
-
-
May 27, 2015, FM4_MN709-00003-4v0-E
+0
SCM_CTL[W]
STB_CTL[W]
0x008
CONFIDENTIAL
+2
BSC_PSR[W]
-----000
APBC0_PSR[W]
------00
APBC1_PSR[W]
1--0--00
APBC2_PSR[W]
1--0--00
SWC_PSR[W]
------00
TTC_PSR[W]
------00
CSW_TMR[W]
00000000
PSW_TMR[W]
---0-000
PLL_CTL1[W]
00000000
PLL_CTL2[W]
--000000
CSV_CTL[W]
-111--00 ------11
-
CSV_STR[W]
------00
FCSWH_CTL[W]
11111111 11111111
FCSWL_CTL[W]
00000000 00000000
125
A. Register Map
1. Register Map
P E R I P H E R A L
Register
Base_Address
+ Address
+3
+2
0x050
-
-
0x054
-
-
-
0x058
-
-
-
0x05C - 0x05F
-
-
-
+0
FCSWD_CTL[W]
00000000 00000000
-
-
-
0x064
-
-
-
0x068
-
-
-
0x06C – 0x070
-
-
0x078 – 0xFFC
CONFIDENTIAL
+1
0x060
-
DBWDT_CTL[W]
0-0----*
INT_ENR[W]
--0--000
INT_STR[W]
--0–000
INT_CLR[W]
--0--000
-
PLLCG_CTL[W]
0x074
126
M A N U A L
-------- 11111111 00000000 00----00
-
-
-
-
FM4_MN709-00003-4v0-E, May 27, 2015
A. Register Map
1. Register Map
P E R I P H E R A L
1.5
M A N U A L
HW WDT
HW WDT Base_Address : 0x4001_1000
Register
Base_Address
+ Address
+3
+2
0x000
WDG_VLR[W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0x008
-
-
-
0x00C
-
-
-
0x010
-
-
-
-
-
0x014
0x018 – 0xBFC
WDG_CTL[W]
------11
WDG_ICL[W]
XXXXXXXX
WDG_RIS[W]
-------0
*
-
-
WDG_LCK[W]
0xC00
0xC04 – 0xFFC
+0
00000000 00000000 11111111 11111111
0x004
1.6
+1
WDG_LDR[W]
00000000 00000000 00000000 00000001
-
-
-
-
+1
+0
SW WDT
SW WDT Base_Address : 0x4001_2000
Register
Base_Address
+ Address
+3
WdogLoad[W]
0x000
11111111 11111111 11111111 11111111
WdogValue[W]
0x004
0x008
11111111 11111111 11111111 11111111
-
-
-
-
-
-
-
-
0x01C – 0xBFC
-
-
-
May 27, 2015, FM4_MN709-00003-4v0-E
-------0
WdogSPMC[W]
-------0
-
00000000 00000000 00000000 00000000
-
-
0xF00 - 0xF04
0xFE0 - 0xFFC
WdogRIS[W]
WdogLock[W]
0xC00
0xF08 - 0xFDF
---00000
*
0x018
0xC04 - 0xDFC
WdogControl[W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0x014
CONFIDENTIAL
WdogIntClr[W]
0x00C
0x010
+2
-
-
-
-
*
-
*
127
A. Register Map
1. Register Map
P E R I P H E R A L
1.7
M A N U A L
Dual_Timer
Dual_Timer
Base_Address : 0x4001_5000
Register
Base_Address
+ Address
+3
Timer1Value[W]
11111111 11111111 11111111 11111111
Timer1Control[W]
0x008
-------- -------- -------- 00100000
Timer1IntClr[W]
0x00C
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Timer1RIS[W]
0x010
-------- -------- -------- -------0
Timer1MIS[W]
0x014
-------- -------- -------- -------0
Timer1BGLoad[W]
0x018
00000000 00000000 00000000 00000000
Timer2Load[W]
0x020
00000000 00000000 00000000 00000000
Timer2Value[W]
0x024
11111111 11111111 11111111 11111111
Timer2Control[W]
0x028
-------- -------- -------- 00100000
Timer2IntClr[W]
0x02C
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Timer2RIS[W]
0x030
-------- -------- -------- -------0
Timer2MIS[W]
0x034
-------- -------- -------- -------0
Timer2BGLoad[W]
0x038
CONFIDENTIAL
+0
00000000 00000000 00000000 00000000
0x004
128
+1
Timer1Load[W]
0x000
0x040 - 0xFFC
+2
00000000 00000000 00000000 00000000
-
-
-
-
FM4_MN709-00003-4v0-E, May 27, 2015
A. Register Map
1. Register Map
P E R I P H E R A L
M A N U A L
1.8 MFT
1.8.1
TYPE1-M4, TYPE2-M4 products
MFT unit0 Base_Address : 0x4002_0000
MFT unit1 Base_Address : 0x4002_1000
MFT unit2 Base_Address : 0x4002_2000
Register
Base_Address
+ Address
+3
+0
-
-
-
-
-
-
-
-
-
-
-
-
OCSD10[B,H,W]
OCSB10[B,H,W]
OCSA10[B,H,W]
00000000
00000000
00000000
OCSD32[B,H,W]
OCSB32[B,H,W]
OCSA32[B,H,W]
00000000
00000000
00000000
OCSD54[B,H,W]
OCSB54[B,H,W]
OCSA54[B,H,W]
00000000
00000000
00000000 00000000
OCCP1[H,W]
0x104
00000000 00000000
OCCP2[H,W]
0x108
00000000 00000000
OCCP3[H,W]
0x10C
00000000 00000000
OCCP4[H,W]
0x110
00000000 00000000
OCCP5[H,W]
0x114
00000000 00000000
0x118
-
0x11C
-
00000000
0x124
-
-
0x128
-
-
0x130
0x13C
0x140
0x144
0x148
0x14C
May 27, 2015, FM4_MN709-00003-4v0-E
--000000
-
OCSE0[B,H,W]
00000000 00000000
00000000 00000000 00000000 00000000
-
OCSE2[B,H,W]
-
00000000 00000000
OCSE3[B,H,W]
0x134
0x138
OCSC[B,H,W]
OCSE1[B,H,W]
0x12C
CONFIDENTIAL
+1
OCCP0[H,W]
0x100
0x120
+2
00000000 00000000 00000000 00000000
-
OCSE4[B,H,W]
-
00000000 00000000
OCSE5[B,H,W]
00000000 00000000 00000000 00000000
TCCP0[H,W]
11111111 11111111
TCDT0[H,W]
00000000 00000000
-
-
-
-
TCSC0[H,W]
TCSA0[B,H,W]
00000000 00000000
00000000 01000000
TCCP1[H,W]
11111111 11111111
-
129
A. Register Map
1. Register Map
P E R I P H E R A L
M A N U A L
Register
Base_Address
+ Address
+3
+2
TCDT1[H,W]
0x150
00000000 00000000
0x154
-
-
TCSC1[H,W]
TCSA1[B,H,W]
00000000 01000000
11111111 11111111
TCDT2[H,W]
0x15C
+0
00000000 00000000
TCCP2[H,W]
0x158
+1
00000000 00000000
-
-
-
-
TCSC2[H,W]
0x160
TCSA2[B,H,W]
00000000 00000000
00000000 01000000
TCAL[W]
00000000 00000000 11111111 11111111 *1
0x164
-
-
-
- *2
OCFS32[B,H,W]
OCFS10[B,H,W]
*1 MFT unit0
*2 MFT unit1,unit2
0x168
-
0x16C
-
0x170
-
00000000
00000000
00000000
ICFS32[B,H,W]
ICFS10[B,H,W]
00000000
00000000
ACFS54[B,H,W]
ACFS32[B,H,W]
ACFS10[B,H,W]
00000000
00000000
00000000
-
-
-
-
-
-
-
-
ICSB10[B,H,W]
ICSA10[B,H,W]
-
ICCP0[H,W]
0x174
00000000 00000000
ICCP1[H,W]
0x178
00000000 00000000
ICCP2[H,W]
0x17C
00000000 00000000
ICCP3[H,W]
0x180
0x184
OCFS54[B,H,W]
00000000 00000000
-
-
0x188
0x18C
0x190
0x194
0x198
0x19C
130
CONFIDENTIAL
WFTF10[H,W]
00000000 00000000
------00
00000000
ICSB32[B,H,W]
ICSA32[B,H,W]
------00
00000000
-
-
WFTB10[H,W]
WFTA10[H,W]
00000000 00000000
00000000 00000000
WFTF32[H,W]
00000000 00000000
-
-
WFTB32[H,W]
WFTA32[H,W]
00000000 00000000
00000000 00000000
WFTF54[H,W]
00000000 00000000
-
-
FM4_MN709-00003-4v0-E, May 27, 2015
A. Register Map
1. Register Map
P E R I P H E R A L
M A N U A L
Register
Base_Address
+ Address
+3
0x1A0
WFTA54[H,W]
00000000 00000000
-
0x1A8
-
-
0x1AC
-
-
0x1B0
-
-
0x1B4
-
ACMP0[H,W]
00000000 00000000
ACMP1[H,W]
00000000 00000000
ACMP2[H,W]
0x1C0
00000000 00000000
ACMP3[H,W]
0x1C4
00000000 00000000
ACMP4[H,W]
0x1C8
00000000 00000000
ACMP5[H,W]
0x1CC
0x1D0
00000000 00000000
-
WFSA10[B,H,W]
--000000 000000
WFSA32[B,H,W]
--000000 000000
WFSA54[B,H,W]
--000000 000000
WFIR[H,W]
00000000 00000000
NZCL[H,W]
00000000 00000000
-
-
-
-
-
-
-
-
-
-
-
ACSA[B,H,W]
-
0x1D4
-
-
0x1D8
-
-
0x1DC
-
-
0x1E0
-
-
0x1E4
-
-
0x1E8
-
-
0x1EC-0xFFC
-
-
May 27, 2015, FM4_MN709-00003-4v0-E
+0
WFTB54[H,W]
-
0x1BC
+1
00000000 00000000
0x1A4
0x1B8
CONFIDENTIAL
+2
00000000 00000000
ACSD0[B,H,W]
ACSC0[B,H,W]
00000000
00000000
ACSD1[B,H,W]
ACSC1[B,H,W]
00000000
00000000
ACSD2[B,H,W]
ACSC2[B,H,W]
00000000
00000000
ACSD3[B,H,W]
ACSC3[B,H,W]
00000000
00000000
ACSD4[B,H,W]
ACSC4[B,H,W]
00000000
00000000
ACSD5[B,H,W]
ACSC5[B,H,W]
00000000
00000000
-
-
131
A. Register Map
1. Register Map
P E R I P H E R A L
1.8.2
TYPE3-M4, TYPE4-M4, TYPE5-M4, TYPE6-M4 products
MFT unit0
Base_Address : 0x4002_0000
MFT unit1
Base_Address : 0x4002_1000
MFT unit2
Base_Address : 0x4002_2000
Register
Base_Address
+ Address
+3
00000000 00000000
OCCP1[H,W]
0x104
00000000 00000000
OCCP2[H,W]
0x108
00000000 00000000
OCCP3[H,W]
0x10C
00000000 00000000
OCCP4[H,W]
0x110
00000000 00000000
OCCP5[H,W]
0x114
00000000 00000000
0x118
0x11C
0x120
-
-
-
-
-
-
-
OCSA32[B,H,W]
OCSD32[B,H,W]
OCSB32[B,H,W]
00000000
00000000
OCSD54[B,H,W]
OCSB54[B,H,W]
OCSA54[B,H,W]
00000000
00000000
OCSC[B,H,W]
--000000
-
OCSE0[B,H,W]
00000000 00000000
OCSE1[B,H,W]
00000000 00000000 00000000 00000000
-
OCSE2[B,H,W]
-
00000000 00000000
OCSE3[B,H,W]
0x134
0x14C
-
--000000 00000000
-
0x148
-
00000000
-
0x144
-
OCSA10[B,H,W]
0x128
0x140
-
00000000
-
0x13C
-
OCSB10[B,H,W]
-
0x138
+0
OCSD10[B,H,W]
0x124
0x130
+1
--000000 00000000
--000000 00000000
0x12C
CONFIDENTIAL
+2
OCCP0[H,W]
0x100
132
M A N U A L
00000000 00000000 00000000 00000000
-
OCSE4[B,H,W]
-
00000000 00000000
OCSE5[B,H,W]
00000000 00000000 00000000 00000000
TCCP0[H,W]
11111111 11111111
TCDT0[H,W]
00000000 00000000
-
-
-
-
TCSC0[H,W]
TCSA0[B,H,W]
00000000 00000000
00000000 01000000
TCCP1[H,W]
11111111 11111111
-
-
FM4_MN709-00003-4v0-E, May 27, 2015
A. Register Map
1. Register Map
P E R I P H E R A L
M A N U A L
Register
Base_Address
+ Address
+3
+2
TCDT1[H,W]
0x150
00000000 00000000
0x154
-
-
TCSC1[H,W]
TCSA1[B,H,W]
00000000 01000000
11111111 11111111
TCDT2[H,W]
0x15C
+0
00000000 00000000
TCCP2[H,W]
0x158
+1
00000000 00000000
-
-
-
-
TCSC2[H,W]
0x160
TCSA2[B,H,W]
00000000 00000000
00000000 01000000
TCAL[W]
00000000 00000000 11111111 11111111 *1
0x164
-
-
-
- *2
OCFS32[B,H,W]
OCFS10[B,H,W]
*1 MFT unit0
*2 MFT unit1,unit2
0x168
-
0x16C
-
0x170
-
00000000
00000000
00000000
ICFS32[B,H,W]
ICFS10[B,H,W]
00000000
00000000
ACFS54[B,H,W]
ACFS32[B,H,W]
ACFS10[B,H,W]
00000000
00000000
00000000
-
-
-
-
-
-
-
-
ICSB10[B,H,W]
ICSA10[B,H,W]
-
ICCP0[H,W]
0x174
00000000 00000000
ICCP1[H,W]
0x178
00000000 00000000
ICCP2[H,W]
0x17C
00000000 00000000
ICCP3[H,W]
0x180
0x184
OCFS54[B,H,W]
00000000 00000000
-
-
0x188
0x18C
0x190
0x194
0x198
0x19C
May 27, 2015, FM4_MN709-00003-4v0-E
CONFIDENTIAL
WFTF10[H,W]
00000000 00000000
------00
00000000
ICSB32[B,H,W]
ICSA32[B,H,W]
------00
00000000
-
-
WFTB10[H,W]
WFTA10[H,W]
00000000 00000000
00000000 00000000
WFTF32[H,W]
00000000 00000000
-
-
WFTB32[H,W]
WFTA32[H,W]
00000000 00000000
00000000 00000000
WFTF54[H,W]
00000000 00000000
-
-
133
A. Register Map
1. Register Map
P E R I P H E R A L
M A N U A L
Register
Base_Address
+ Address
+3
0x1A0
0x1A8
-
-
0x1AC
-
-
0x1B0
-
-
0x1B4
-
ACMP0[H,W]
00000000 00000000
ACMP1[H,W]
00000000 00000000
ACMP2[H,W]
00000000 00000000
ACMP3[H,W]
0x1C4
00000000 00000000
ACMP4[H,W]
0x1C8
00000000 00000000
ACMP5[H,W]
0x1CC
0x1D0
CONFIDENTIAL
WFTA54[H,W]
00000000 00000000
-
0x1C0
00000000 00000000
-
0x1D4
-
0x1D8
-
0x1DC
-
0x1E0
-
0x1E4
-
0x1E8
-
+0
WFTB54[H,W]
-
0x1BC
+1
00000000 00000000
0x1A4
0x1B8
134
+2
WFSA10[B,H,W]
--000000 000000
WFSA32[B,H,W]
--000000 000000
WFSA54[B,H,W]
--000000 000000
WFIR[H,W]
00000000 00000000
NZCL[H,W]
00000000 00000000
-
-
-
-
-
-
-
-
-
-
-
ACSA[B,H,W]
-
00000000 00000000
ACMC0[B,H,W]
ACSD0[B,H,W]
ACSC0[B,H,W]
00--0000
00000000
00000000
ACMC1[B,H,W]
ACSD1[B,H,W]
ACSC1[B,H,W]
00--0000
00000000
00000000
ACMC2[B,H,W]
ACSD2[B,H,W]
ACSC2[B,H,W]
00--0000
00000000
00000000
ACMC3[B,H,W]
ACSD3[B,H,W]
ACSC3[B,H,W]
00--0000
00000000
00000000
ACMC4[B,H,W]
ACSD4[B,H,W]
ACSC4[B,H,W]
00--0000
00000000
00000000
ACMC5[B,H,W]
ACSD5[B,H,W]
ACSC5[B,H,W]
00--0000
00000000
0x1EC
-
-
-
0x1F0-0xFFC
-
-
-
00000000
TCSD[B,H,W]
------00
-
FM4_MN709-00003-4v0-E, May 27, 2015
A. Register Map
1. Register Map
P E R I P H E R A L
1.9
M A N U A L
PPG
PPG
Base_Address : 0x4002_4000
Register
Base_Address
+ Address
+2
0x000
-
-
0x004
-
-
0x008
-
-
0x00C
-
-
+1
+0
TTCR0 [B,H,W]
-
11110000
-
*
COMP0 [B,H,W]
-
00000000
COMP2 [B,H,W]
-
00000000
COMP4 [B,H,W]
0x010
-
-
0x014
-
-
-
0x018 - 0x01C
-
-
-
0x020
-
-
0x024
-
-
0x028
-
-
0x02C
-
-
0x030
-
-
0x034
-
-
-
0x038 - 0x03C
-
-
-
0x040
-
-
0x044
-
-
0x048
-
-
0x04C
-
-
0x050
-
-
0x054
-
-
-
0x058 - 0x0FC
-
-
-
0x100
-
-
0x104
-
-
0x108 - 0x13C
-
-
May 27, 2015, FM4_MN709-00003-4v0-E
CONFIDENTIAL
+3
-
00000000
COMP6 [B,H,W]
00000000
-
TTCR1 [B,H,W]
-
11110000
-
*
COMP1 [B,H,W]
-
00000000
COMP3 [B,H,W]
-
00000000
COMP5 [B,H,W]
-
00000000
COMP7 [B,H,W]
00000000
-
TTCR2 [B,H,W]
-
11110000
-
*
COMP8 [B,H,W]
-
00000000
COMP10 [B,H,W]
-
00000000
COMP12 [B,H,W]
-
00000000
COMP14 [B,H,W]
00000000
TRG0 [B,H,W]
00000000 00000000
REVC0 [B,H,W]
00000000 00000000
-
-
135
A. Register Map
1. Register Map
P E R I P H E R A L
Register
Base_Address
+ Address
+3
+2
0x140
-
-
0x144
-
-
0x148 - 0x1FC
-
-
0x200
-
0x208
-
-
0x20C
-
-
0x210
-
-
-
-
0x218
-
-
0x21C - 0x23C
-
-
0x240
-
-
0x244
-
-
-
-
0x24C
-
-
0x250
-
-
+1
+0
TRG1 [B,H,W]
-------- 00000000
REVC1 [B,H,W]
-------- 00000000
-
-
PPGC0 [B,H,W]
PPGC1 [B,H,W]
00000000
00000000
PPGC2 [B,H,W]
PPGC3 [B,H,W]
00000000
00000000
PRLH0 [B,H,W]
PRLL0 [B,H,W]
XXXXXXXX
XXXXXXXX
PRLH1 [B,H,W]
PRLL1 [B,H,W]
XXXXXXXX
XXXXXXXX
PRLH2 [B,H,W]
PRLL2 [B,H,W]
XXXXXXXX
XXXXXXXX
PRLH3 [B,H,W]
PRLL3 [B,H,W]
XXXXXXXX
-
XXXXXXXX
GATEC0 [B,H,W]
--00---00
-
-
PPGC4 [B,H,W]
PPGC5 [B,H,W]
00000000
00000000
PPGC6 [B,H,W]
PPGC7 [B,H,W]
00000000
00000000
PRLH4 [B,H,W]
PRLL4 [B.H.W]
XXXXXXXX
XXXXXXXX
PRLH5 [B,H,W]
PRLL5 [B,H,W]
XXXXXXXX
XXXXXXXX
PRLH6 [B,H,W]
PRLL6 [B,H,W]
XXXXXXXX
XXXXXXXX
PRLH7 [B,H,W]
PRLL7 [B,H,W]
XXXXXXXX
XXXXXXXX
0x254
-
-
0x258
-
-
-
0x25C - 0x27C
-
-
-
-
0x280
-
-
PPGC8 [B,H,W]
PPGC9 [B,H,W]
0x284
-
-
0x288
-
-
0x28C
-
-
0x290
CONFIDENTIAL
-
-
0x248
136
-
0x204
0x214
M A N U A L
-
-
GATEC4 [B,H,W]
------00
00000000
00000000
PPGC10 [B,H,W]
PPGC11 [B,H,W]
00000000
00000000
PRLH8 [B,H,W]
PRLL8 [B,H,W]
XXXXXXXX
XXXXXXXX
PRLH9 [B,H,W]
PRLL9 [B,H,W]
XXXXXXXX
XXXXXXXX
PRLH10 [B,H,W]
PRLL10 [B,H,W]
XXXXXXXX
XXXXXXXX
PRLH11 [B,H,W]
PRLL11 [B,H,W]
XXXXXXXX
XXXXXXXX
0x294
-
-
0x298
-
-
-
0x29C - 0x2BC
-
-
-
GATEC8 [B,H,W]
--00--00
-
FM4_MN709-00003-4v0-E, May 27, 2015
A. Register Map
1. Register Map
P E R I P H E R A L
M A N U A L
Register
Base_Address
+ Address
+3
+2
0x2C0
-
-
0x2C4
-
-
0x2C8
-
-
0x2CC
0x2D0
-
-
0x2D4
-
-
0x2D8
-
-
0x2DC - 0x2FC
-
-
0x300
-
-
0x304
-
-
0x308
-
-
0x30C
-
-
0x310
-
-
0x314
-
-
+0
PPGC12 [B,H,W]
PPGC13 [B,H,W]
00000000
00000000
PPGC14 [B,H,W]
PPGC15 [B,H,W]
00000000
00000000
PRLH12 [B,H,W]
PRLL12 [B,H,W]
XXXXXXXX
XXXXXXXX
PRLH13 [B,H,W]
PRLL13 [B,H,W]
XXXXXXXX
XXXXXXXX
PRLH14 [B,H,W]
PRLL14 [B,H,W]
XXXXXXXX
XXXXXXXX
PRLH15 [B,H,W]
PRLL15 [B,H,W]
XXXXXXXX
XXXXXXXX
-
GATEC12 [B,H,W]
------00
-
-
PPGC16 [B,H,W]
PPGC17 [B,H,W]
00000000
00000000
PPGC18 [B,H,W]
PPGC19 [B,H,W]
00000000
00000000
PRLH16 [B,H,W]
PRLL16 [B,H,W]
XXXXXXXX
XXXXXXXX
PRLH17 [B,H,W]
PRLL17 [B,H,W]
XXXXXXXX
XXXXXXXX
PRLH18 [B,H,W]
PRLL18 [B,H,W]
XXXXXXXX
XXXXXXXX
PRLH19 [B,H,W]
PRLL19 [B,H,W]
XXXXXXXX
XXXXXXXX
GATEC16 [B,H,W]
0x318
-
-
-
0x31C - 0x33C
-
-
-
-
0x340
-
-
PPGC20 [B,H,W]
PPGC21 [B,H,W]
0x344
0x348
-
-
--00---00
00000000
00000000
PPGC22 [B,H,W]
PPGC23 [B,H,W]
00000000
00000000
PRLH20 [B,H,W]
PRLL20 [B.H.W]
XXXXXXXX
XXXXXXXX
PRLH21 [B,H,W]
PRLL21 [B,H,W]
XXXXXXXX
XXXXXXXX
PRLH22 [B,H,W]
PRLL22 [B,H,W]
XXXXXXXX
XXXXXXXX
PRLH23 [B,H,W]
PRLL23 [B,H,W]
XXXXXXXX
XXXXXXXX
0x34C
-
-
0x350
-
-
0x354
-
-
0x358
-
-
-
0x35C - 0x37C
-
-
-
-
0x380
-
-
-
-
0x384 - 0xFFC
-
-
-
-
May 27, 2015, FM4_MN709-00003-4v0-E
CONFIDENTIAL
-
+1
GATEC20 [B,H,W]
------00
137
A. Register Map
1. Register Map
P E R I P H E R A L
M A N U A L
1.10 Base Timer
Base Timer ch.0
Base Address : 0x4002_5000
Base Timer ch.1
Base Address : 0x4002_5040
Base Timer ch.2
Base Address : 0x4002_5080
Base Timer ch.3
Base Address : 0x4002_50C0
Base Timer ch.4
Base Address : 0x4002_5200
Base Timer ch.5
Base Address : 0x4002_5240
Base Timer ch.6
Base Address : 0x4002_5280
Base Timer ch.7
Base Address : 0x4002_52C0
Base Timer ch.8
Base Address : 0x4002_5400
Base Timer ch.9
Base Address : 0x4002_5440
Base Timer ch.10 Base Address : 0x4002_5480
Base Timer ch.11
Base Address : 0x4002_54C0
Base Timer ch.12 Base Address : 0x4002_5600
Base Timer ch.13 Base Address : 0x4002_5640
Base Timer ch.14 Base Address : 0x4002_5680
Base Timer ch.15 Base Address : 0x4002_56C0
Register
Base_Address
138
CONFIDENTIAL
+ Address
+3
+2
0x000
-
-
0x004
-
-
0x008
-
-
0x00C
-
-
0x010
-
-
0x014 - 0x03C
-
-
+1
+0
PCSR/PRLL [H,W]
XXXXXXXX XXXXXXXX
PDUT/PRLH/DTBF [H,W]
XXXXXXXX XXXXXXXX
TMR [H,W]
00000000 00000000
TMCR [B,H,W]
-0000000 00000000
TMCR2 [B,H,W]
STC [B,H,W]
0------0
0000-000
-
-
FM4_MN709-00003-4v0-E, May 27, 2015
A. Register Map
1. Register Map
P E R I P H E R A L
M A N U A L
1.11 IO Selector for Base Timer
IO Selector for ch.0-ch.3 (Base Timer)
Base Address : 0x4002_5100
Register
Base_Address
+ Address
+3
+2
0x000
-
-
0x004 - 0x0FC
-
-
+1
+0
BTSEL0123 [B,H,W]
-
00000000
-
-
IO Selector for ch.4-ch.7(Base Timer) Base Address : 0x4002_5300
Register
Base_Address
+ Address
+3
+2
0x000
-
-
0x004 - 0x0FC
-
-
IO Selector for ch.8-ch.11(Base Timer)
+0
BTSEL4567 [B,H,W]
-
00000000
-
-
Base Address : 0x4002_5500
Register
Base_Address
+ Address
+3
+2
0x000
-
-
0x004 - 0x0FC
-
-
IO Selector for ch.12-ch.15(Base Timer)
+1
+0
BTSEL89AB [B,H,W]
-
00000000
-
-
Base Address : 0x4002_5700
Register
Base_Address
+ Address
+3
+2
0x000
-
-
0x004 - 0x0FC
-
-
Software-based Simulation Startup(Base Timer)
+1
+0
BTSELCDEF [B,H,W]
-
00000000
-
-
Base Address : 0x4002_5F00
Register
Base_Address
+ Address
+3
+2
+1
+0
0x000 - 0x0FB
-
-
-
-
0x0FC
-
-
May 27, 2015, FM4_MN709-00003-4v0-E
CONFIDENTIAL
+1
BTSSSR [B,H,W]
XXXXXXXX XXXXXXXX
139
A. Register Map
1. Register Map
P E R I P H E R A L
M A N U A L
1.12 QPRC
1.12.1 TYPE1-M4, TYPE2-M4, TYPE6-M4 products
QPRC ch.0
Base Address : 0x4002_6000
QPRC ch.1
Base Address : 0x4002_6040
QPRC ch.2
Base Address : 0x4002_6080
QPRC ch.3
Base Address : 0x4002_60C0
Register
Base_Address
+ Address
+3
+2
0x0000
-
-
0x0004
-
-
0x0008
-
-
0x000C
-
-
0x0010
-
-
0x0014
-
-
0x0018
-
-
0x001C
-
-
-
-
0x0020 0x003B
0x003C
140
CONFIDENTIAL
+1
+0
QPCR [H,W]
00000000 00000000
QRCR [H,W]
00000000 00000000
QPCCR [H,W]
00000000 00000000
QPRCR [H,W]
00000000 00000000
QMPR [H,W]
11111111 11111111
QICRH [B,H,W]
QICRL [B,H,W]
--000000
00000000
QCRH [B,H,W]
QCRL [B,H,W]
00000000
00000000
QECR [B,H,W]
-------- -----000
-
-
QPCRR[B,H,W]
QRCRR[B,H,W]
00000000 00000000
00000000 00000000
FM4_MN709-00003-4v0-E, May 27, 2015
A. Register Map
1. Register Map
P E R I P H E R A L
1.12.2
M A N U A L
TYPE3-M4, TYPE4-M4, TYPE5-M4 products
QPRC ch.0
Base Address : 0x4002_6000
QPRC ch.1
Base Address : 0x4002_6040
QPRC ch.2
Base Address : 0x4002_6080
QPRC ch.3
Base Address : 0x4002_60C0
Register
Base_Address
+ Address
+3
+2
0x0000
-
-
0x0004
-
-
0x0008
-
-
0x000C
-
-
0x0010
-
-
0x0014
-
0x0018
-
-
0x001C
-
-
-
-
0x0020 0x003B
0x003C
May 27, 2015, FM4_MN709-00003-4v0-E
CONFIDENTIAL
-
+1
+0
QPCR [H,W]
00000000 00000000
QRCR [H,W]
00000000 00000000
QPCCR [H,W]
00000000 00000000
QPRCR [H,W]
00000000 00000000
QMPR [H,W]
11111111 11111111
QICRH [B,H,W]
QICRL [B,H,W]
--000000
00000000
QCRH [B,H,W]
QCRL [B,H,W]
00000000
00000000
QECR [B,H,W]
-------- ----0000
-
-
QPCRR[B,H,W]
QRCRR[B,H,W]
00000000 00000000
00000000 00000000
141
A. Register Map
1. Register Map
P E R I P H E R A L
M A N U A L
1.13 QPRC NF
QPRC ch.0 NF
Base Address : 0x4002_6100
QPRC ch.1 NF
Base Address : 0x4002_6110
QPRC ch.2 NF
Base Address : 0x4002_6120
QPRC ch.3 NF
Base Address : 0x4002_6130
Register
Base_Address
142
CONFIDENTIAL
+ Address
+3
+2
+1
0x0000
-
-
-
0x0004
-
-
-
0x0008
-
-
-
0x000C
-
-
-
+0
NFCTLA[B,H,W]
--00-000
NFCTLB[B,H,W]
--00-000
NFCTLZ[B,H,W]
--00-000
-
FM4_MN709-00003-4v0-E, May 27, 2015
A. Register Map
1. Register Map
P E R I P H E R A L
M A N U A L
1.14 A/DC
12bit A/DC unit0
Base_Address : 0x4002_7000
12bit A/DC unit1
Base_Address : 0x4002_7100
12bit A/DC unit2
Base_Address : 0x4002_7200
Register
Base_Address
+ Address
+3
+2
0x000
-
-
0x004
-
-
0x008
-
-
-
-
-
-
0x018
-
-
-
SCCR[B,H,W]
SFNS[B,H,W]
1000-000
----0000
SCIS3[B,H,W]
00000000
00000000
SCIS0[B,H,W]
00000000
00000000
PCCR[B,H,W]
PFNS[B,H,W]
10000000
--XX--00
CMPD[B,H,W]
-
-
0x030
-
-
0x034
-
-
0x038
-
-
00000000
ADSS2[B,H,W]
00000000
00000000
ADSS1[B,H,W]
ADSS0[B,H,W]
00000000
00000000
ADST0[B,H,W]
ADST1[B,H,W]
00010000
00010000
ADCT[B,H,W]
-
00000111
SCTSL[B,H,W]
PRTSL[B,H,W]
----0000
----0000
ADCEN[B,H,W]
-
11111111 ------00
CALSR[B,H,W]
-------- -------- -------0 00000000
-
-
-
0x048
-
-
-
-
0x050
May 27, 2015, FM4_MN709-00003-4v0-E
CMPCR[B,H,W]
ADSS3[B,H,W]
0x044
0x040 - 0x0FC
00000000
-
-
PCIS[B,H,W]
-
00000000 00------
0x02C
0x04C
SCIS2[B,H,W]
SCIS1[B,H,W]
-
0x040
CONFIDENTIAL
*
XXXXXXXX XXXX---- ---X-XXX ---XXXXX
0x024
0x03C
00---000
-
PCFD[B,H,W]
0x01C
0x028
000-0000
XXXXXXXX XXXX---- ---X--XX ---XXXXX
0x014
0x020
+0
ADSR[B,H,W]
SCFD[B,H,W]
0x00C
0x010
+1
ADCR[B,H,W]
-
-
WCMRCOT[B,H,W]
00000000
WCMRCIF[B,H,W]
00000000
WCMPSR[B,H,W]
WCMPCR[B,H,W]
00000000
00100000
WCMPDH[B,H,W]
WCMPDL[B,H,W]
00000000 00000000
00000000 00000000
-
-
143
A. Register Map
1. Register Map
P E R I P H E R A L
M A N U A L
1.15 CR Trim
CR Trim
Base_Address : 0x4002_E000
Register
Base_Address
+ Address
0x000
+3
-
-
-
0x008
-
-
0x010 - 0x0FC
CONFIDENTIAL
+1
-
0x004
+0
MCR_PSR[B,H,W]
-
-----001
MCR_FTRM[B,H,W]
------01 11101111
-
MCR_TTRM[B,H,W]
---10000
MCR_RLR[W]
0x00C
144
+2
00000000 00000000 00000000 00000001
-
-
-
-
FM4_MN709-00003-4v0-E, May 27, 2015
A. Register Map
1. Register Map
P E R I P H E R A L
M A N U A L
1.16 EXTI
1.16.1 TYPE1-M4, TYPE2-M4, TYPE3-M4, TYPE4-M4 products
EXTI
Base_Address : 0x4003_0000
Register
Base_Address
+ Address
+3
+2
0x000
EIRR[B,H,W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
EICL[B,H,W]
0x008
11111111 11111111 11111111 11111111
ELVR[B,H,W]
0x00C
00000000 00000000 00000000 00000000
ELVR1[B,H,W]
0x010
00000000 00000000 00000000 00000000
NMIRR[B,H,W]
0x014
-
-
-
0x018
-
-
-
0x01C
-
-
-
-
0x020 - 0x0FC
-
-
-
-
+1
+0
-------0
NMICL[B,H,W]
-------1
TYPE5-M4, TYPE6-M4 products
EXTI
Base_Address : 0x4003_0000
Register
Base_Address
+ Address
+3
+2
ENIR[B,H,W]
0x000
00000000 00000000 00000000 00000000
EIRR[B,H,W]
0x004
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
EICL[B,H,W]
0x008
11111111 11111111 11111111 11111111
ELVR[B,H,W]
0x00C
00000000 00000000 00000000 00000000
ELVR1[B,H,W]
0x010
00000000 00000000 00000000 00000000
0x014
-
-
-
0x018
-
-
-
0x020 - 0x0FC
May 27, 2015, FM4_MN709-00003-4v0-E
NMIRR[B,H,W]
-------0
NMICL[B,H,W]
-------1
ELVR2[B,H,W]
0x01C
CONFIDENTIAL
+0
00000000 00000000 00000000 00000000
0x004
1.16.2
+1
ENIR[B,H,W]
00000000 00000000 00000000 00000000
-
-
-
-
145
A. Register Map
1. Register Map
P E R I P H E R A L
M A N U A L
1.17 INT-Req. READ
1.17.1 TYPE1-M4, TYPE2-M4, TYPE6-M4 products
INT-Req. READ
Base_Address : 0x4003_1000
Register
Base_Address
+ Address
+3
+2
0x000
ODDPKS[B]
0x010
-
-
-
0x014
-
-
-
-
0x018
-
*
-
*
0x01C – 0x10C
-
-
-
-
-------- 00000000 -------- 00000000
IRQ004SEL[B,H,W]
0x114
-------- 00000000 -------- 00000000
IRQ005SEL[B,H,W]
0x118
-------- 00000000 -------- 00000000
IRQ006SEL[B,H,W]
0x11C
-------- 00000000 -------- 00000000
IRQ007SEL[B,H,W]
0x120
-------- 00000000 -------- 00000000
IRQ008SEL[B,H,W]
0x124
-------- 00000000 -------- 00000000
IRQ009SEL[B,H,W]
0x128
-------- 00000000 -------- 00000000
IRQ010SEL[B,H,W]
0x12C
0x130 – 0x1FC
0x200
0x204
0x208
0x20C
0x210
0x214
0x218
---00000
IRQ003SEL[B,H,W]
0x110
CONFIDENTIAL
+0
00000000 00000000 00000000 00000000
0x004 – 0x00C
146
+1
DRQSEL[B,H,W]
-------- 00000000 -------- 00000000
-
-
-
-
EXC02MON[B,H,W]
-------- -------- -------- ------00
IRQ000MON[B,H,W]
-------- -------- -------- -------0
IRQ001MON[B,H,W]
-------- -------- -------- -------0
IRQ002MON[B,H,W]
-------- -------- -------- -------0
IRQ003MON[B,H,W]
-------- -------- -------- 00000000
IRQ004MON[B,H,W]
-------- -------- -------- 00000000
IRQ005MON[B,H,W]
-------- -------- -------- 00000000
FM4_MN709-00003-4v0-E, May 27, 2015
A. Register Map
1. Register Map
P E R I P H E R A L
M A N U A L
Register
Base_Address
+ Address
0x21C
0x220
0x224
0x228
0x22C
0x230
0x234
0x238
0x23C
0x240
0x244
0x248
0x24C
0x250
0x254
0x258
0x25C
0x260
0x264
0x268
0x26C
0x270
0x274
0x278
May 27, 2015, FM4_MN709-00003-4v0-E
CONFIDENTIAL
+3
+2
+1
+0
IRQ006MON[B,H,W]
-------- -------- -------- 00000000
IRQ007MON[B,H,W]
-------- -------- -------- 00000000
IRQ008MON[B,H,W]
-------- -------- -------- 00000000
IRQ009MON[B,H,W]
-------- -------- -------- 00000000
IRQ010MON[B,H,W]
-------- -------- -------- 00000000
IRQ011MON[B,H,W]
-------- -------- -------- -------0
IRQ012MON[B,H,W]
-------- -------- -------- -------0
IRQ013MON[B,H,W]
-------- -------- -------- -------0
IRQ014MON[B,H,W]
-------- -------- -------- -------0
IRQ015MON[B,H,W]
-------- -------- -------- -------0
IRQ016MON[B,H,W]
-------- -------- -------- -------0
IRQ017MON[B,H,W]
-------- -------- -------- -------0
IRQ018MON[B,H,W]
-------- -------- -------- -------0
IRQ019MON[B,H,W]
-------- -------- -------- --000000
IRQ020MON[B,H,W]
-------- -------- -------- --000000
IRQ021MON[B,H,W]
-------- -------- -------- ----0000
IRQ022MON[B,H,W]
-------- -------- -------- ----0000
IRQ023MON[B,H,W]
-------- -------- -------- ----0000
IRQ024MON[B,H,W]
-------- -------- -------- -----000
IRQ025MON[B,H,W]
-------- -------- -------- -----000
IRQ026MON[B,H,W]
-------- -------- -------- ----0000
IRQ027MON[B,H,W]
-------- -------- -------- --000000
IRQ028MON[B,H,W]
-------- -------- -------- -----000
IRQ029MON[B,H,W]
-------- -------- -------- -----000
147
A. Register Map
1. Register Map
P E R I P H E R A L
Register
Base_Address
+ Address
0x27C
0x280
0x284
0x288
0x28C
0x290
0x294
0x298
0x29C
0x2A0
0x2A4
0x2A8
0x2AC
0x2B0
0x2B4
0x2B8
0x2BC
0x2C0
0x2C4
0x2C8
0x2CC
0x2D0
0x2D4
0x2D8
148
CONFIDENTIAL
M A N U A L
+3
+2
+1
+0
IRQ030MON[B,H,W]
-------- -------- -------- ----0000
IRQ031MON[B,H,W]
-------- -------- -------- --000000
IRQ032MON[B,H,W]
-------- -------- -------- -----000
IRQ033MON[B,H,W]
-------- -------- -------- -----000
IRQ034MON[B,H,W]
-------- -------- -------- ---00000
IRQ035MON[B,H,W]
-------- -------- -------- --000000
IRQ036MON[B,H,W]
-------- -------- -------- -----000
IRQ037MON[B,H,W]
-------- -------- -------- -----000
IRQ038MON[B,H,W]
-------- -------- -------- -----000
IRQ039MON[B,H,W]
-------- -------- -------- ------00
IRQ040MON[B,H,W]
-------- -------- -------- ------00
IRQ041MON[B,H,W]
-------- -------- -------- ------00
IRQ042MON[B,H,W]
-------- -------- -------- ------00
IRQ043MON[B,H,W]
-------- -------- -------- ------00
IRQ044MON[B,H,W]
-------- -------- -------- ------00
IRQ045MON[B,H,W]
-------- -------- -------- ------00
IRQ046MON[B,H,W]
-------- -------- -------- ------00
IRQ047MON[B,H,W]
-------- -------- -------- ------00
IRQ048MON[B,H,W]
-------- -------- -------- -------0
IRQ049MON[B,H,W]
-------- -------- -------- -------0
IRQ050MON[B,H,W]
-------- -------- -------- -------0
IRQ051MON[B,H,W]
-------- -------- -------- -------0
IRQ052MON[B,H,W]
-------- -------- -------- -------0
IRQ053MON[B,H,W]
-------- -------- -------- -------0
FM4_MN709-00003-4v0-E, May 27, 2015
A. Register Map
1. Register Map
P E R I P H E R A L
M A N U A L
Register
Base_Address
+ Address
0x2DC
0x2E0
0x2E4
0x2E8
0x2EC
0x2F0
0x2F4
0x2F8
0x2FC
0x300
0x304
0x308
0x30C
0x310
0x314
0x318
0x31C
0x320
0x324
0x328
0x32C
0x330
0x334
0x338
May 27, 2015, FM4_MN709-00003-4v0-E
CONFIDENTIAL
+3
+2
+1
+0
IRQ054MON[B,H,W]
-------- -------- -------- -------0
IRQ055MON[B,H,W]
-------- -------- -------- -------0
IRQ056MON[B,H,W]
-------- -------- -------- -------0
IRQ057MON[B,H,W]
-------- -------- -------- -------0
IRQ058MON[B,H,W]
-------- -------- -------- -------0
IRQ059MON[B,H,W]
-------- -------- -------- ----0000
IRQ060MON[B,H,W]
-------- -------- -------- -------0
IRQ061MON[B,H,W]
-------- -------- -------- ------00
IRQ062MON[B,H,W]
-------- -------- -------- -------0
IRQ063MON[B,H,W]
-------- -------- -------- ------00
IRQ064MON[B,H,W]
-------- -------- -------- -------0
IRQ065MON[B,H,W]
-------- -------- -------- ------00
IRQ066MON[B,H,W]
-------- -------- -------- -------0
IRQ067MON[B,H,W]
-------- -------- -------- ------00
IRQ068MON[B,H,W]
-------- -------- -------- -------0
IRQ069MON[B,H,W]
-------- -------- -------- ------00
IRQ070MON[B,H,W]
-------- -------- -------- -------0
IRQ071MON[B,H,W]
-------- -------- -------- ------00
IRQ072MON[B,H,W]
-------- -------- -------- -------0
IRQ073MON[B,H,W]
-------- -------- -------- ------00
IRQ074MON[B,H,W]
-------- -------- -------- -------0
IRQ075MON[B,H,W]
-------- -------- -------- ------00
IRQ076MON[B,H,W]
-------- -------- -------- ---00000
IRQ077MON[B,H,W]
-------- -------- -------- ---00000
149
A. Register Map
1. Register Map
P E R I P H E R A L
Register
Base_Address
+ Address
0x33C
0x340
0x344
0x348
0x34C
0x350
0x354
0x358
0x35C
0x360
0x364
0x368
0x36C
0x370
0x374
0x378
0x37C
0x380
0x384
0x388
0x38C
0x390
0x394
0x398
150
CONFIDENTIAL
M A N U A L
+3
+2
+1
+0
IRQ078MON[B,H,W]
-------- -------- -------- ---00000
IRQ079MON[B,H,W]
-------- -------- -------- --000000
IRQ080MON[B,H,W]
-------- -------- -------- -------0
IRQ081MON[B,H,W]
-------- -------- -------- -------0
IRQ082MON[B,H,W]
-------- -------- -------- -----000
IRQ083MON[B,H,W]
-------- -------- -------- -------0
IRQ084MON[B,H,W]
-------- -------- -------- -------0
IRQ085MON[B,H,W]
-------- -------- -------- -------0
IRQ086MON[B,H,W]
-------- -------- -------- -------0
IRQ087MON[B,H,W]
-------- -------- -------- -------0
IRQ088MON[B,H,W]
-------- -------- -------- -------0
IRQ089MON[B,H,W]
-------- -------- -------- -------0
IRQ090MON[B,H,W]
-------- -------- -------- -------0
IRQ091MON[B,H,W]
-------- -------- -------- ------00
IRQ092MON[B,H,W]
-------- -------- -------- ----0000
IRQ093MON[B,H,W]
-------- -------- -------- ----0000
IRQ094MON[B,H,W]
-------- -------- -------- ----0000
IRQ095MON[B,H,W]
-------- -------- -------- ----0000
IRQ096MON[B,H,W]
-------- -------- -------- --000000
IRQ097MON[B,H,W]
-------- -------- -------- --000000
IRQ098MON[B,H,W]
-------- -------- -------- ------00
IRQ099MON[B,H,W]
-------- -------- -------- ------00
IRQ100MON[B,H,W]
-------- -------- -------- ------00
IRQ101MON[B,H,W]
-------- -------- -------- ------00
FM4_MN709-00003-4v0-E, May 27, 2015
A. Register Map
1. Register Map
P E R I P H E R A L
M A N U A L
Register
Base_Address
+ Address
+3
IRQ103MON[B,H,W]
-------- -------- -------- -------0
IRQ104MON[B,H,W]
0x3A4
-------- -------- -------- ------00
IRQ105MON[B,H,W]
0x3A8
-------- -------- -------- -------0
IRQ106MON[B,H,W]
0x3AC
-------- -------- -------- ------00
IRQ107MON[B,H,W]
0x3B0
-------- -------- -------- -------0
IRQ108MON[B,H,W]
0x3B4
-------- -------- -------- ------00
IRQ109MON[B,H,W]
0x3B8
-------- -------- -------- -------0
IRQ110MON[B,H,W]
0x3BC
-------- -------- -------- ------00
IRQ111MON[B,H,W]
0x3C0
-------- -------- -------- ---00000
-
-
IRQ114MON[B,H,W]
-------- -------- -------- --000000
-
-
-
-
IRQ118MON[B,H,W]
0x3DC
-------- -------- -------- ------00
IRQ119MON[B,H,W]
0x3E0
-------- -------- -------- -------0
IRQ120MON[B,H,W]
0x3E4
-------- -------- -------- -------0
IRQ121MON[B,H,W]
0x3E8
-------- -------- -------- ------00
IRQ122MON[B,H,W]
0x3EC
-------- -------- -------- -------0
IRQ123MON[B,H,W]
0x3F0
-------- -------- -------- ------00
IRQ124MON[B,H,W]
0x3F4
-------- -------- -------- -------0
IRQ125MON[B,H,W]
0x3F8
-------- -------- -------- ------00
IRQ126MON[B,H,W]
0x3FC
-------- -------- -------- -------0
IRQ127MON[B,H,W]
0x400
CONFIDENTIAL
-
-------- -------- -------- ---00000
0x3CC
May 27, 2015, FM4_MN709-00003-4v0-E
IRQ113MON[B,H,W]
0x3C8
0x404 – 0xFFC
+0
-------- -------- -------- ------00
0x3A0
0x3D0 – 0x3D8
+1
IRQ102MON[B,H,W]
0x39C
0x3C4
+2
-------- -------- -------- ------00
-
-
-
-
151
A. Register Map
1. Register Map
P E R I P H E R A L
1.17.2
TYPE3-M4, TYPE5-M4 product
INT-Req. READ
Base_Address : 0x4003_1000
Register
Base_Address
+ Address
+3
+2
-
-
-
ODDPKS[B]
---00000
ODDPKS1[B]
0x014
-
-
-
0x018
-
*
-
*
0x01C – 0x10C
-
-
-
-
-------- 00000000 -------- 00000000
IRQ004SEL[B,H,W]
0x114
-------- 00000000 -------- 00000000
IRQ005SEL[B,H,W]
0x118
-------- 00000000 -------- 00000000
IRQ006SEL[B,H,W]
0x11C
-------- 00000000 -------- 00000000
IRQ007SEL[B,H,W]
0x120
-------- 00000000 -------- 00000000
IRQ008SEL[B,H,W]
0x124
-------- 00000000 -------- 00000000
IRQ009SEL[B,H,W]
0x128
-------- 00000000 -------- 00000000
IRQ010SEL[B,H,W]
0x12C
0x130 – 0x1FC
0x200
0x204
0x208
0x20C
0x210
0x214
0x218
0x21C
--00000
IRQ003SEL[B,H,W]
0x110
CONFIDENTIAL
+0
00000000 00000000 00000000 00000000
0x004 – 0x00C
0x010
+1
DRQSEL[B,H,W]
0x000
152
M A N U A L
-------- 00000000 -------- 00000000
-
-
-
-
EXC02MON[B,H,W]
-------- -------- -------- ------00
IRQ000MON[B,H,W]
-------- -------- -------- -------0
IRQ001MON[B,H,W]
-------- -------- -------- -------0
IRQ002MON[B,H,W]
-------- -------- -------- -------0
IRQ003MON[B,H,W]
-------- -------- -------- 00000000
IRQ004MON[B,H,W]
-------- -------- -------- 00000000
IRQ005MON[B,H,W]
-------- -------- -------- 00000000
IRQ006MON[B,H,W]
-------- -------- -------- 00000000
FM4_MN709-00003-4v0-E, May 27, 2015
A. Register Map
1. Register Map
P E R I P H E R A L
M A N U A L
Register
Base_Address
+ Address
0x220
0x224
0x228
0x22C
0x230
0x234
0x238
0x23C
0x240
0x244
0x248
0x24C
0x250
0x254
0x258
0x25C
0x260
0x264
0x268
0x26C
0x270
0x274
0x278
0x27C
May 27, 2015, FM4_MN709-00003-4v0-E
CONFIDENTIAL
+3
+2
+1
+0
IRQ007MON[B,H,W]
-------- -------- -------- 00000000
IRQ008MON[B,H,W]
-------- -------- -------- 00000000
IRQ009MON[B,H,W]
-------- -------- -------- 00000000
IRQ010MON[B,H,W]
-------- -------- -------- 00000000
IRQ011MON[B,H,W]
-------- -------- -------- -------0
IRQ012MON[B,H,W]
-------- -------- -------- -------0
IRQ013MON[B,H,W]
-------- -------- -------- -------0
IRQ014MON[B,H,W]
-------- -------- -------- -------0
IRQ015MON[B,H,W]
-------- -------- -------- -------0
IRQ016MON[B,H,W]
-------- -------- -------- -------0
IRQ017MON[B,H,W]
-------- -------- -------- -------0
IRQ018MON[B,H,W]
-------- -------- -------- -------0
IRQ019MON[B,H,W]
-------- -------- -------- --000000
IRQ020MON[B,H,W]
-------- -------- -------- --000000
IRQ021MON[B,H,W]
-------- -------- -------- ----0000
IRQ022MON[B,H,W]
-------- -------- -------- ----0000
IRQ023MON[B,H,W]
-------- -------- -------- ----0000
IRQ024MON[B,H,W]
-------- -------- -------- -----000
IRQ025MON[B,H,W]
-------- -------- -------- -----000
IRQ026MON[B,H,W]
-------- -------- -------- ----0000
IRQ027MON[B,H,W]
-------- -------- -------- --000000
IRQ028MON[B,H,W]
-------- -------- -------- -----000
IRQ029MON[B,H,W]
-------- -------- -------- -----000
IRQ030MON[B,H,W]
-------- -------- -------- ----0000
153
A. Register Map
1. Register Map
P E R I P H E R A L
Register
Base_Address
+ Address
0x280
0x284
0x288
0x28C
0x290
0x294
0x298
0x29C
0x2A0
0x2A4
0x2A8
0x2AC
0x2B0
0x2B4
0x2B8
0x2BC
0x2C0
0x2C4
0x2C8
0x2CC
0x2D0
0x2D4
0x2D8
0x2DC
154
CONFIDENTIAL
M A N U A L
+3
+2
+1
+0
IRQ031MON[B,H,W]
-------- -------- -------- --000000
IRQ032MON[B,H,W]
-------- -------- -------- -----000
IRQ033MON[B,H,W]
-------- -------- -------- -----000
IRQ034MON[B,H,W]
-------- -------- -------- ---00000
IRQ035MON[B,H,W]
-------- -------- -------- --000000
IRQ036MON[B,H,W]
-------- -------- -------- -----000
IRQ037MON[B,H,W]
-------- -------- -------- -----000
IRQ038MON[B,H,W]
-------- -------- -------- -----000
IRQ039MON[B,H,W]
-------- -------- -------- ------00
IRQ040MON[B,H,W]
-------- -------- -------- ------00
IRQ041MON[B,H,W]
-------- -------- -------- ------00
IRQ042MON[B,H,W]
-------- -------- -------- ------00
IRQ043MON[B,H,W]
-------- -------- -------- ------00
IRQ044MON[B,H,W]
-------- -------- -------- ------00
IRQ045MON[B,H,W]
-------- -------- -------- ------00
IRQ046MON[B,H,W]
-------- -------- -------- ------00
IRQ047MON[B,H,W]
-------- -------- -------- ------00
IRQ048MON[B,H,W]
-------- -------- -------- -------0
IRQ049MON[B,H,W]
-------- -------- -------- -------0
IRQ050MON[B,H,W]
-------- -------- -------- -------0
IRQ051MON[B,H,W]
-------- -------- -------- -------0
IRQ052MON[B,H,W]
-------- -------- -------- -------0
IRQ053MON[B,H,W]
-------- -------- -------- -------0
IRQ054MON[B,H,W]
-------- -------- -------- -------0
FM4_MN709-00003-4v0-E, May 27, 2015
A. Register Map
1. Register Map
P E R I P H E R A L
M A N U A L
Register
Base_Address
+ Address
0x2E0
0x2E4
0x2E8
0x2EC
0x2F0
0x2F4
0x2F8
0x2FC
0x300
0x304
0x308
0x30C
0x310
0x314
0x318
0x31C
0x320
0x324
0x328
0x32C
May 27, 2015, FM4_MN709-00003-4v0-E
CONFIDENTIAL
+3
+2
+1
+0
IRQ055MON[B,H,W]
-------- -------- -------- -------0
IRQ056MON[B,H,W]
-------- -------- -------- -------0
IRQ057MON[B,H,W]
-------- -------- -------- -------0
IRQ058MON[B,H,W]
-------- -------- -------- -------0
IRQ059MON[B,H,W]
-------- -------- -------- ---00000
IRQ060MON[B,H,W]
-------- -------- -------- -------0
IRQ061MON[B,H,W]
-------- -------- -------- ------00
IRQ062MON[B,H,W]
-------- -------- -------- -------0
IRQ063MON[B,H,W]
-------- -------- -------- ------00
IRQ064MON[B,H,W]
-------- -------- -------- -------0
IRQ065MON[B,H,W]
-------- -------- -------- ------00
IRQ066MON[B,H,W]
-------- -------- -------- -------0
IRQ067MON[B,H,W]
-------- -------- -------- ------00
IRQ068MON[B,H,W]
-------- -------- -------- -------0
IRQ069MON[B,H,W]
-------- -------- -------- ------00
IRQ070MON[B,H,W]
-------- -------- -------- -------0
IRQ071MON[B,H,W]
-------- -------- -------- ------00
IRQ072MON[B,H,W]
-------- -------- -------- -------0
IRQ073MON[B,H,W]
-------- -------- -------- ------00
IRQ074MON[B,H,W]
-------- -------- -------- -------0
155
A. Register Map
1. Register Map
P E R I P H E R A L
Register
Base_Address
+ Address
0x330
0x334
0x338
0x33C
0x340
0x344
0x348
0x34C
0x350
0x354
0x358
0x35C
0x360
0x364
0x368
0x36C
0x370
0x374
0x378
0x37C
156
CONFIDENTIAL
M A N U A L
+3
+2
+1
+0
IRQ075MON[B,H,W]
-------- -------- -------- ------00
IRQ076MON[B,H,W]
-------- -------- -------- ---00000
IRQ077MON[B,H,W]
-------- -------- -------- ---00000
IRQ078MON[B,H,W]
-------- -------- -------- ---00000
IRQ079MON[B,H,W]
-------- -------- -------- --000000
IRQ080MON[B,H,W]
-------- -------- -------- -------0
IRQ081MON[B,H,W]
-------- -------- -------- ---00000
IRQ082MON[B,H,W]
-------- -------- -------- -----000
IRQ083MON[B,H,W]
-------- -------- -------- -------0
IRQ084MON[B,H,W]
-------- -------- -------- -------0
IRQ085MON[B,H,W]
-------- -------- -------- -------0
IRQ086MON[B,H,W]
-------- -------- -------- -------0
IRQ087MON[B,H,W]
-------- -------- -------- -------0
IRQ088MON[B,H,W]
-------- -------- -------- -------0
IRQ089MON[B,H,W]
-------- -------- -------- -------0
IRQ090MON[B,H,W]
-------- -------- -------- -------0
IRQ091MON[B,H,W]
-------- -------- -------- ------00
IRQ092MON[B,H,W]
-------- -------- -------- ----0000
IRQ093MON[B,H,W]
-------- -------- -------- ----0000
IRQ094MON[B,H,W]
-------- -------- -------- ----0000
FM4_MN709-00003-4v0-E, May 27, 2015
A. Register Map
1. Register Map
P E R I P H E R A L
M A N U A L
Register
Base_Address
+ Address
0x380
0x384
0x388
0x38C
0x390
0x394
0x398
0x39C
0x3A0
0x3A4
0x3A8
0x3AC
0x3B0
0x3B4
0x3B8
0x3BC
0x3C0
0x3C4
0x3C8
0x3CC
May 27, 2015, FM4_MN709-00003-4v0-E
CONFIDENTIAL
+3
+2
+1
+0
IRQ095MON[B,H,W]
-------- -------- -------- ----0000
IRQ096MON[B,H,W]
-------- -------- -------- --000000
IRQ097MON[B,H,W]
-------- -------- -------- --000000
IRQ098MON[B,H,W]
-------- -------- -------- ------00
IRQ099MON[B,H,W]
-------- -------- -------- ------00
IRQ100MON[B,H,W]
-------- -------- -------- ------00
IRQ101MON[B,H,W]
-------- -------- -------- ------00
IRQ102MON[B,H,W]
-------- -------- -------- ------00
IRQ103MON[B,H,W]
-------- -------- -------- -------0
IRQ104MON[B,H,W]
-------- -------- -------- ------00
IRQ105MON[B,H,W]
-------- -------- -------- -------0
IRQ106MON[B,H,W]
-------- -------- -------- ------00
IRQ107MON[B,H,W]
-------- -------- -------- -------0
IRQ108MON[B,H,W]
-------- -------- -------- ------00
IRQ109MON[B,H,W]
-------- -------- -------- -------0
IRQ110MON[B,H,W]
-------- -------- -------- ------00
IRQ111MON[B,H,W]
-------- -------- -------- ---00000
IRQ112MON[B,H,W]
-------- -------- -------- --000000
IRQ113MON[B,H,W]
-------- -------- -------- --000000
IRQ114MON[B,H,W]
-------- -------- -------- -0000000
157
A. Register Map
1. Register Map
P E R I P H E R A L
Register
Base_Address
+ Address
+3
+2
IRQ116MON[B,H,W]
-------- -------- -------- -------IRQ117MON[B,H,W]
0x3D8
-------- -------- -------- ------00
IRQ118MON[B,H,W]
0x3DC
-------- -------- -------- ------00
IRQ119MON[B,H,W]
0x3E0
-------- -------- -------- -------0
IRQ120MON[B,H,W]
0x3E4
-------- -------- -------- -------0
IRQ121MON[B,H,W]
0x3E8
-------- -------- -------- ------00
IRQ122MON[B,H,W]
0x3EC
-------- -------- -------- -------0
IRQ123MON[B,H,W]
0x3F0
-------- -------- -------- ------00
IRQ124MON[B,H,W]
0x3F4
-------- -------- -------- -------0
IRQ125MON[B,H,W]
0x3F8
-------- -------- -------- ------00
IRQ126MON[B,H,W]
0x3FC
-------- -------- -------- -------0
IRQ127MON[B,H,W]
0x400
CONFIDENTIAL
+0
-------- -------- -------- -----000
0x3D4
158
+1
IRQ115MON[B,H,W]
0x3D0
0x404 – 0xFFC
M A N U A L
-------- -------- -------- ------00
-
-
-
-
FM4_MN709-00003-4v0-E, May 27, 2015
A. Register Map
1. Register Map
P E R I P H E R A L
1.17.3
M A N U A L
TYPE4-M4 product
INT-Req. READ
Base_Address : 0x4003_1000
Register
Base_Address
+ Address
+3
+2
0x000
-
-
-
ODDPKS[B]
---00000
ODDPKS1[B]
0x014
-
-
-
0x018
-
*
-
*
0x01C – 0x10C
-
-
-
-
00000000 00000000 -------- 00000000
IRQ004SEL[B,H,W]
0x114
00000000 00000000 -------- 00000000
IRQ005SEL[B,H,W]
0x118
00000000 00000000 -------- 00000000
IRQ006SEL[B,H,W]
0x11C
00000000 00000000 -------- 00000000
IRQ007SEL[B,H,W]
0x120
00000000 00000000 -------- 00000000
IRQ008SEL[B,H,W]
0x124
00000000 00000000 -------- 00000000
IRQ009SEL[B,H,W]
0x128
00000000 00000000 -------- 00000000
IRQ010SEL[B,H,W]
0x12C
0x130 – 0x1FC
0x200
0x204
0x208
0x20C
0x210
0x214
0x218
0x21C
May 27, 2015, FM4_MN709-00003-4v0-E
--00000
IRQ003SEL[B,H,W]
0x110
CONFIDENTIAL
+0
00000000 00000000 00000000 00000000
0x004 – 0x00C
0x010
+1
DRQSEL[B,H,W]
00000000 00000000 -------- 00000000
-
-
-
-
EXC02MON[B,H,W]
-------- -------- -------- ------00
IRQ000MON[B,H,W]
-------- -------- -------- -------0
IRQ001MON[B,H,W]
-------- -------- -------- -------0
IRQ002MON[B,H,W]
-------- -------- -------- -------0
IRQ003MON[B,H,W]
-------- -------- -------- 00000000
IRQ004MON[B,H,W]
-------- -------- -------- 00000000
IRQ005MON[B,H,W]
-------- -------- -------- 00000000
IRQ006MON[B,H,W]
-------- -------- -------- 00000000
159
A. Register Map
1. Register Map
P E R I P H E R A L
Register
Base_Address
+ Address
0x220
0x224
0x228
0x22C
0x230
0x234
0x238
0x23C
0x240
0x244
0x248
0x24C
0x250
0x254
0x258
0x25C
0x260
0x264
0x268
0x26C
0x270
0x274
0x278
0x27C
160
CONFIDENTIAL
M A N U A L
+3
+2
+1
+0
IRQ007MON[B,H,W]
-------- -------- -------- 00000000
IRQ008MON[B,H,W]
-------- -------- -------- 00000000
IRQ009MON[B,H,W]
-------- -------- -------- 00000000
IRQ010MON[B,H,W]
-------- -------- -------- 00000000
IRQ011MON[B,H,W]
-------- -------- -------- -------0
IRQ012MON[B,H,W]
-------- -------- -------- -------0
IRQ013MON[B,H,W]
-------- -------- -------- -------0
IRQ014MON[B,H,W]
-------- -------- -------- -------0
IRQ015MON[B,H,W]
-------- -------- -------- -------0
IRQ016MON[B,H,W]
-------- -------- -------- -------0
IRQ017MON[B,H,W]
-------- -------- -------- -------0
IRQ018MON[B,H,W]
-------- -------- -------- -------0
IRQ019MON[B,H,W]
-------- -------- -------- --000000
IRQ020MON[B,H,W]
-------- -------- -------- --000000
IRQ021MON[B,H,W]
-------- -------- -------- ----0000
IRQ022MON[B,H,W]
-------- -------- -------- ----0000
IRQ023MON[B,H,W]
-------- -------- -------- ----0000
IRQ024MON[B,H,W]
-------- -------- -------- -----000
IRQ025MON[B,H,W]
-------- -------- -------- -----000
IRQ026MON[B,H,W]
-------- -------- -------- ----0000
IRQ027MON[B,H,W]
-------- -------- -------- --000000
IRQ028MON[B,H,W]
-------- -------- -------- -----000
IRQ029MON[B,H,W]
-------- -------- -------- -----000
IRQ030MON[B,H,W]
-------- -------- -------- ----0000
FM4_MN709-00003-4v0-E, May 27, 2015
A. Register Map
1. Register Map
P E R I P H E R A L
M A N U A L
Register
Base_Address
+ Address
0x280
0x284
0x288
0x28C
0x290
0x294
0x298
0x29C
0x2A0
0x2A4
0x2A8
0x2AC
0x2B0
0x2B4
0x2B8
0x2BC
0x2C0
0x2C4
0x2C8
0x2CC
0x2D0
0x2D4
0x2D8
0x2DC
May 27, 2015, FM4_MN709-00003-4v0-E
CONFIDENTIAL
+3
+2
+1
+0
IRQ031MON[B,H,W]
-------- -------- -------- --000000
IRQ032MON[B,H,W]
-------- -------- -------- -----000
IRQ033MON[B,H,W]
-------- -------- -------- -----000
IRQ034MON[B,H,W]
-------- -------- -------- ---00000
IRQ035MON[B,H,W]
-------- -------- -------- --000000
IRQ036MON[B,H,W]
-------- -------- -------- -----000
IRQ037MON[B,H,W]
-------- -------- -------- -----000
IRQ038MON[B,H,W]
-------- -------- -------- -----000
IRQ039MON[B,H,W]
-------- -------- -------- ------00
IRQ040MON[B,H,W]
-------- -------- -------- ------00
IRQ041MON[B,H,W]
-------- -------- -------- ------00
IRQ042MON[B,H,W]
-------- -------- -------- ------00
IRQ043MON[B,H,W]
-------- -------- -------- ------00
IRQ044MON[B,H,W]
-------- -------- -------- ------00
IRQ045MON[B,H,W]
-------- -------- -------- ------00
IRQ046MON[B,H,W]
-------- -------- -------- ------00
IRQ047MON[B,H,W]
-------- -------- -------- ------00
IRQ048MON[B,H,W]
-------- -------- -------- -------0
IRQ049MON[B,H,W]
-------- -------- -------- ------00
IRQ050MON[B,H,W]
-------- -------- -------- -------0
IRQ051MON[B,H,W]
-------- -------- -------- -------0
IRQ052MON[B,H,W]
-------- -------- -------- -------0
IRQ053MON[B,H,W]
-------- -------- -------- -------0
IRQ054MON[B,H,W]
-------- -------- -------- -------0
161
A. Register Map
1. Register Map
P E R I P H E R A L
Register
Base_Address
+ Address
0x2E0
0x2E4
0x2E8
0x2EC
0x2F0
0x2F4
0x2F8
0x2FC
0x300
0x304
0x308
0x30C
0x310
0x314
0x318
0x31C
0x320
0x324
0x328
0x32C
162
CONFIDENTIAL
M A N U A L
+3
+2
+1
+0
IRQ055MON[B,H,W]
-------- -------- -------- -------0
IRQ056MON[B,H,W]
-------- -------- -------- -------0
IRQ057MON[B,H,W]
-------- -------- -------- -------0
IRQ058MON[B,H,W]
-------- -------- -------- -------0
IRQ059MON[B,H,W]
-------- -------- -------- --000000
IRQ060MON[B,H,W]
-------- -------- -------- -------0
IRQ061MON[B,H,W]
-------- -------- -------- ------00
IRQ062MON[B,H,W]
-------- -------- -------- -------0
IRQ063MON[B,H,W]
-------- -------- -------- ------00
IRQ064MON[B,H,W]
-------- -------- -------- -------0
IRQ065MON[B,H,W]
-------- -------- -------- ------00
IRQ066MON[B,H,W]
-------- -------- -------- -------0
IRQ067MON[B,H,W]
-------- -------- -------- ------00
IRQ068MON[B,H,W]
-------- -------- -------- -------0
IRQ069MON[B,H,W]
-------- -------- -------- ------00
IRQ070MON[B,H,W]
-------- -------- -------- -------0
IRQ071MON[B,H,W]
-------- -------- -------- ------00
IRQ072MON[B,H,W]
-------- -------- -------- -------0
IRQ073MON[B,H,W]
-------- -------- -------- ------00
IRQ074MON[B,H,W]
-------- -------- -------- -------0
FM4_MN709-00003-4v0-E, May 27, 2015
A. Register Map
1. Register Map
P E R I P H E R A L
M A N U A L
Register
Base_Address
+ Address
0x330
0x334
0x338
0x33C
0x340
0x344
0x348
0x34C
0x350
0x354
0x358
0x35C
0x360
0x364
0x368
0x36C
0x370
0x374
0x378
0x37C
May 27, 2015, FM4_MN709-00003-4v0-E
CONFIDENTIAL
+3
+2
+1
+0
IRQ075MON[B,H,W]
-------- -------- -------- ------00
IRQ076MON[B,H,W]
-------- -------- -------- ---00000
IRQ077MON[B,H,W]
-------- -------- -------- ---00000
IRQ078MON[B,H,W]
-------- -------- -------- ---00000
IRQ079MON[B,H,W]
-------- -------- -------- --000000
IRQ080MON[B,H,W]
-------- -------- -------- -------0
IRQ081MON[B,H,W]
-------- -------- -------- ---00000
IRQ082MON[B,H,W]
-------- -------- -------- -----000
IRQ083MON[B,H,W]
-------- -------- -------- -------0
IRQ084MON[B,H,W]
-------- -------- -------- -------0
IRQ085MON[B,H,W]
-------- -------- -------- -------0
IRQ086MON[B,H,W]
-------- -------- -------- -------0
IRQ087MON[B,H,W]
-------- -------- -------- -------0
IRQ088MON[B,H,W]
-------- -------- -------- -------0
IRQ089MON[B,H,W]
-------- -------- -------- -------0
IRQ090MON[B,H,W]
-------- -------- -------- -------0
IRQ091MON[B,H,W]
-------- -------- -------- ------00
IRQ092MON[B,H,W]
-------- -------- -------0 ----0000
IRQ093MON[B,H,W]
-------- -------- -------0 ----0000
IRQ094MON[B,H,W]
-------- -------- -------0 ----0000
163
A. Register Map
1. Register Map
P E R I P H E R A L
Register
Base_Address
+ Address
0x380
0x384
0x388
0x38C
0x390
0x394
0x398
0x39C
0x3A0
0x3A4
0x3A8
0x3AC
0x3B0
0x3B4
0x3B8
0x3BC
0x3C0
0x3C4
0x3C8
0x3CC
164
CONFIDENTIAL
M A N U A L
+3
+2
+1
+0
IRQ095MON[B,H,W]
-------- -------- -------0 ----0000
IRQ096MON[B,H,W]
-------- -------- -------0 --000000
IRQ097MON[B,H,W]
-------- -------- -------0 --000000
IRQ098MON[B,H,W]
-------- -------- -------0 ------00
IRQ099MON[B,H,W]
-------- -------- -------0 ------00
IRQ100MON[B,H,W]
-------- -------- -------0 ------00
IRQ101MON[B,H,W]
-------- -------- -------0 ------00
IRQ102MON[B,H,W]
-------- -------- -------0 ------00
IRQ103MON[B,H,W]
-------- -------- -------0 -------0
IRQ104MON[B,H,W]
-------- -------- -------0 ------00
IRQ105MON[B,H,W]
-------- -------- -------0 -------0
IRQ106MON[B,H,W]
-------- -------- -------0 ------00
IRQ107MON[B,H,W]
-------- -------- -------0 -------0
IRQ108MON[B,H,W]
-------- -------- -------0 ------00
IRQ109MON[B,H,W]
-------- -------- -------0 -------0
IRQ110MON[B,H,W]
-------- -------- -------0 ------00
IRQ111MON[B,H,W]
-------- -------- -------- ---00000
IRQ112MON[B,H,W]
-------- -------- ------00 00000000
IRQ113MON[B,H,W]
-------- -------- -------- --000000
IRQ114MON[B,H,W]
-------- -------- -------- -0000000
FM4_MN709-00003-4v0-E, May 27, 2015
A. Register Map
1. Register Map
P E R I P H E R A L
M A N U A L
Register
Base_Address
+ Address
+3
+2
-------- -------- -------- -----000
IRQ116MON[B,H,W]
0x3D4
-------- -------- -------- -------IRQ117MON[B,H,W]
0x3D8
-------- -------- -------- -----000
IRQ118MON[B,H,W]
0x3DC
-------- -------- -------- ------00
IRQ119MON[B,H,W]
0x3E0
-------- -------- -------- -------0
IRQ120MON[B,H,W]
0x3E4
-------- -------- -------0 -------0
IRQ121MON[B,H,W]
0x3E8
-------- -------- -------0 ------00
IRQ122MON[B,H,W]
0x3EC
-------- -------- -------0 -------0
IRQ123MON[B,H,W]
0x3F0
-------- -------- -------0 ------00
IRQ124MON[B,H,W]
0x3F4
-------- -------- -------- -------0
IRQ125MON[B,H,W]
0x3F8
-------- -------- -------- ------00
IRQ126MON[B,H,W]
0x3FC
-------- -------- -------- -------0
IRQ127MON[B,H,W]
0x400
May 27, 2015, FM4_MN709-00003-4v0-E
CONFIDENTIAL
+0
IRQ115MON[B,H,W]
0x3D0
0x404 – 0xFFC
+1
-------- -------- -------- ------00
-
-
-
-
165
A. Register Map
1. Register Map
P E R I P H E R A L
M A N U A L
1.18 D/AC
12bit D/AC unit0
Base_Address : 0x4003_3000
12bit D/AC unit1
Base_Address : 0x4003_3008
Register
Base_Address
166
CONFIDENTIAL
+ Address
+3
+2
+1
0x000
-
-
-
0x004
-
-
0x010 – 0xFFC
-
-
+0
DACR[B,H,W]
--00--00
DADR[H,W]
----XXXX XXXXXXXX
-
-
FM4_MN709-00003-4v0-E, May 27, 2015
A. Register Map
1. Register Map
P E R I P H E R A L
M A N U A L
1.19 HDMI-CEC
HDMI-CEC/Remote Control Receiver ch.0
Base_Address : 0x4003_4000
HDMI-CEC/Remote Control Receiver ch.1
Base_Address : 0x4003_4100
Register
Base_Address
+ Address
+3
+2
+1
0x000
-
-
-
0x004
-
TXCTRL[B,H,W]
--0000-0
TXDATA[B,H,W]
-
00000000
TXSTS[B,H,W]
0x008
-
-
-
0x00C
-
-
-
0x010 – 0x03C
-
-
-
-
0x040
-
-
RCCR[B,H,W]
RCST[B,H,W]
0x044
-
-
0x048
-
-
0x04C
-
-
0x050
-
-
0x054
-
-
0x058
-
-
0x060
-
-
0x064
-
-
0x068 – 0x0FC
-
-
--00---0
SFREE[B,H,W]
----0000
0---0000
00000000
RCSHW[B,H,W]
RCDAHW[B,H,W]
00000000
00000000
RCDBHW[B,H,W]
-
00000000
RCADR1[B,H,W]
RCADR2[B,H,W]
---00000
---00000
RCDTHH[B,H,W]
RCDTHL[B,H,W]
00000000
00000000
RCDTLH[B,H,W]
RCDTLL[B,H,W]
00000000
00000000
RCCKD[B,H,W]
-
0x05C
May 27, 2015, FM4_MN709-00003-4v0-E
CONFIDENTIAL
-
+0
---00000 00000000
RCRC[B,H,W]
RCRHW[B,H,W]
---0---0
00000000
RCLE[B,H,W]
00000-00
-
RCLELW[B,H,W]
RCLESW[B,H,W]
00000000
00000000
-
-
167
A. Register Map
1. Register Map
P E R I P H E R A L
M A N U A L
1.20 GPIO
1.20.1 TYPE1-M4, TYPE2-M4, TYPE6-M4 products
GPIO
Base_Address : 0x4006_F000
Register
Base_Address
+ Address
+3
PFR1[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PFR2[B,H,W]
0x008
---- ---- ---- ---- 0000 0000 0000 0000
PFR3[B,H,W]
0x00C
---- ---- ---- ---- 0000 0000 0000 0000
PFR4[B,H,W]
0x010
---- ---- ---- ---- 0000 0000 0000 0000
PFR5[B,H,W]
0x014
---- ---- ---- ---- 0000 0000 0000 0000
PFR6[B,H,W]
0x018
---- ---- ---- ---- 0000 0000 0000 0000
PFR7[B,H,W]
0x01C
---- ---- ---- ---- 0000 0000 0000 0000
PFR8[B,H,W]
0x020
---- ---- ---- ---- 0000 0000 0000 0000
PFR9[B,H,W]
0x024
---- ---- ---- ---- 0000 0000 0000 0000
PFRA[B,H,W]
0x028
---- ---- ---- ---- 0000 0000 0000 0000
PFRB[B,H,W]
0x02C
---- ---- ---- ---- 0000 0000 0000 0000
PFRC[B,H,W]
0x030
---- ---- ---- ---- 0000 0000 0000 0000
PFRD[B,H,W]
0x034
---- ---- ---- ---- 0000 0000 0000 0000
PFRE[B,H,W]
0x038
---- ---- ---- ---- 0000 0000 0000 0000
PFRF[B,H,W]
0x03C
CONFIDENTIAL
+0
---- ---- ---- ---- 0000 0000 0001 1111
0x004
168
+1
PFR0[B,H,W]
0x000
0x040 - 0x0FC
+2
---- ---- ---- ---- 0000 0000 0000 0000
-
-
-
-
FM4_MN709-00003-4v0-E, May 27, 2015
A. Register Map
1. Register Map
P E R I P H E R A L
M A N U A L
Register
Base_Address
+ Address
+3
+2
---- ---- ---- ---- 0000 0000 0001 1111
PCR1[B,H,W]
0x104
---- ---- ---- ---- 0000 0000 0000 0000
PCR2[B,H,W]
0x108
---- ---- ---- ---- 0000 0000 0000 0000
PCR3[B,H,W]
0x10C
---- ---- ---- ---- 0000 0000 0000 0000
PCR4[B,H,W]
0x110
---- ---- ---- ---- 0000 0000 0000 0000
PCR5[B,H,W]
0x114
---- ---- ---- ---- 0000 0000 0000 0000
PCR6[B,H,W]
0x118
---- ---- ---- ---- 0000 0000 0000 0000
PCR7[B,H,W]
0x11C
---- ---- ---- ---- 0000 0000 0000 0000
0x120
PCR9[B,H,W]
0x124
---- ---- ---- ---- 0000 0000 0000 0000
PCRA[B,H,W]
0x128
---- ---- ---- ---- 0000 0000 0000 0000
PCRB[B,H,W]
0x12C
---- ---- ---- ---- 0000 0000 0000 0000
PCRC[B,H,W]
0x130
---- ---- ---- ---- 0000 0000 0000 0000
PCRD[B,H,W]
0x134
---- ---- ---- ---- 0000 0000 0000 0000
PCRE[B,H,W]
0x138
---- ---- ---- ---- 0000 0000 0000 0000
PCRF[B,H,W]
0x13C
May 27, 2015, FM4_MN709-00003-4v0-E
CONFIDENTIAL
+0
PCR0[B,H,W]
0x100
0x140 - 0x1FC
+1
---- ---- ---- ---- 0000 0000 0000 0000
-
-
-
-
169
A. Register Map
1. Register Map
P E R I P H E R A L
Register
Base_Address
+ Address
+3
+0
DDR1[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
DDR2[B,H,W]
0x208
---- ---- ---- ---- 0000 0000 0000 0000
DDR3[B,H,W]
0x20C
---- ---- ---- ---- 0000 0000 0000 0000
DDR4[B,H,W]
0x210
---- ---- ---- ---- 0000 0000 0000 0000
DDR5[B,H,W]
0x214
---- ---- ---- ---- 0000 0000 0000 0000
DDR6[B,H,W]
0x218
---- ---- ---- ---- 0000 0000 0000 0000
DDR7[B,H,W]
0x21C
---- ---- ---- ---- 0000 0000 0000 0000
DDR8[B,H,W]
0x220
---- ---- ---- ---- 0000 0000 0000 0000
DDR9[B,H,W]
0x224
---- ---- ---- ---- 0000 0000 0000 0000
DDRA[B,H,W]
0x228
---- ---- ---- ---- 0000 0000 0000 0000
DDRB[B,H,W]
0x22C
---- ---- ---- ---- 0000 0000 0000 0000
DDRC[B,H,W]
0x230
---- ---- ---- ---- 0000 0000 0000 0000
DDRD[B,H,W]
0x234
---- ---- ---- ---- 0000 0000 0000 0000
DDRE[B,H,W]
0x238
---- ---- ---- ---- 0000 0000 0000 0000
DDRF[B,H,W]
0x23C
CONFIDENTIAL
+1
---- ---- ---- ---- 0000 0000 0000 0000
0x204
170
+2
DDR0[B,H,W]
0x200
0x240 - 0x2FC
M A N U A L
---- ---- ---- ---- 0000 0000 0000 0000
-
-
-
-
FM4_MN709-00003-4v0-E, May 27, 2015
A. Register Map
1. Register Map
P E R I P H E R A L
M A N U A L
Register
Base_Address
+ Address
+3
PDIR1[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PDIR2[B,H,W]
0x308
---- ---- ---- ---- 0000 0000 0000 0000
PDIR3[B,H,W]
0x30C
---- ---- ---- ---- 0000 0000 0000 0000
PDIR4[B,H,W]
0x310
---- ---- ---- ---- 0000 0000 0000 0000
PDIR5[B,H,W]
0x314
---- ---- ---- ---- 0000 0000 0000 0000
PDIR6[B,H,W]
0x318
---- ---- ---- ---- 0000 0000 0000 0000
PDIR7[B,H,W]
0x31C
---- ---- ---- ---- 0000 0000 0000 0000
PDIR8[B,H,W]
0x320
---- ---- ---- ---- 0000 0000 0000 0000
PDIR9[B,H,W]
0x324
---- ---- ---- ---- 0000 0000 0000 0000
PDIRA[B,H,W]
0x328
---- ---- ---- ---- 0000 0000 0000 0000
PDIRB[B,H,W]
0x32C
---- ---- ---- ---- 0000 0000 0000 0000
PDIRC[B,H,W]
0x330
---- ---- ---- ---- 0000 0000 0000 0000
PDIRD[B,H,W]
0x334
---- ---- ---- ---- 0000 0000 0000 0000
PDIRE[B,H,W]
0x338
---- ---- ---- ---- 0000 0000 0000 0000
PDIRF[B,H,W]
0x33C
CONFIDENTIAL
+0
---- ---- ---- ---- 0000 0000 0000 0000
0x304
May 27, 2015, FM4_MN709-00003-4v0-E
+1
PDIR0[B,H,W]
0x300
0x340 - 0x3FC
+2
---- ---- ---- ---- 0000 0000 0000 0000
-
-
-
-
171
A. Register Map
1. Register Map
P E R I P H E R A L
Register
Base_Address
+ Address
+3
PDOR1[B,H,W]
PDOR2[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PDOR3[B,H,W]
0x40C
---- ---- ---- ---- 0000 0000 0000 0000
PDOR4[B,H,W]
0x410
---- ---- ---- ---- 0000 0000 0000 0000
PDOR5[B,H,W]
0x414
---- ---- ---- ---- 0000 0000 0000 0000
PDOR6[B,H,W]
0x418
---- ---- ---- ---- 0000 0000 0000 0000
PDOR7[B,H,W]
0x41C
---- ---- ---- ---- 0000 0000 0000 0000
PDOR8[B,H,W]
0x420
---- ---- ---- ---- 0000 0000 0000 0000
PDOR9[B,H,W]
0x424
---- ---- ---- ---- 0000 0000 0000 0000
PDORA[B,H,W]
0x428
---- ---- ---- ---- 0000 0000 0000 0000
PDORB[B,H,W]
0x42C
---- ---- ---- ---- 0000 0000 0000 0000
PDORC[B,H,W]
0x430
---- ---- ---- ---- 0000 0000 0000 0000
PDORD[B,H,W]
0x434
---- ---- ---- ---- 0000 0000 0000 0000
PDORE[B,H,W]
0x438
---- ---- ---- ---- 0000 0000 0000 0000
PDORF[B,H,W]
0x43C
---- ---- ---- ---- 0000 0000 0000 0000
-
-
-
1111 1111 1111 1111 1111 1111 1111 1111
-
-
-
-
SPSR[B,H,W]
0x580
CONFIDENTIAL
ADE[B,H,W]
0x500
172
+0
---- ---- ---- ---- 0000 0000 0000 0000
0x408
0x584 - 0x5FC
+1
---- ---- ---- ---- 0000 0000 0000 0000
0x404
0x504 - 0x57C
+2
PDOR0[B,H,W]
0x400
0x440 - 0x4FC
M A N U A L
---- ---- ---- ---- ---- ---- --00 01--
-
-
-
FM4_MN709-00003-4v0-E, May 27, 2015
A. Register Map
1. Register Map
P E R I P H E R A L
M A N U A L
Register
Base_Address
+ Address
+3
EPFR01[B,H,W]
0000 0000 0000 0000 ---0 0000 0000 0000
EPFR02[B,H,W]
0x608
0000 0000 0000 0000 ---0 0000 0000 0000
EPFR03[B,H,W]
0x60C
0000 0000 0000 0000 ---0 0000 0000 0000
EPFR04[B,H,W]
0x610
--00 0000 --00 00-- --00 0000 -000 00-EPFR05[B,H,W]
0x614
--00 0000 --00 00-- --00 0000 --00 00-EPFR06[B,H,W]
0x618
0000 0000 0000 0000 0000 0000 0000 0000
EPFR07[B,H,W]
0x61C
0000 0000 0000 0000 0000 0000 0000 ---EPFR08[B,H,W]
0x620
0000 0000 0000 0000 0000 0000 0000 0000
EPFR09[B,H,W]
0x624
0000 0000 0000 0000 0000 0000 0000 0000
EPFR10[B,H,W]
0x628
0000 0000 0000 0000 0000 0000 0000 0000
EPFR11[B,H,W]
0x62C
---- --00 0000 0000 0000 0000 0000 0000
EPFR12[B,H,W]
0x630
--00 0000 --00 00-- --00 0000 --00 00-EPFR13[B,H,W]
0x634
--00 0000 --00 00-- --00 0000 --00 00-EPFR14[B,H,W]
0x638
--00 0000 0000 00-- ---- ---- --00 0000
EPFR15[B,H,W]
0x63C
0000 0000 0000 0000 0000 0000 0000 0000
EPFR16[B,H,W]
0x640
--00 0000 0000 0000 0000 0000 0000 0000
EPFR17[B,H,W]
0x644
---- 0000 0000 0000 0000 0000 0000 ---EPFR18[B,H,W]
0x648
--00 0000 0000 0000 00-- --00 0000 ---EPFR19[B,H,W]
0x64C
---- ---- ---- ---- ---- ---- ---- ---EPFR20[B,H,W]
0x650
CONFIDENTIAL
+0
---- --00 ---- --11 --0- --0- 0000 --00
0x604
May 27, 2015, FM4_MN709-00003-4v0-E
+1
EPFR00[B,H,W]
0x600
0x654 – 0x6FC
+2
---- ---0 0000 0000 0000 0000 0000 0000
-
-
-
-
173
A. Register Map
1. Register Map
P E R I P H E R A L
Register
Base_Address
+ Address
+3
+2
PZR1[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PZR2[B,H,W]
0x708
---- ---- ---- ---- 0000 0000 0000 0000
PZR3[B,H,W]
0x70C
---- ---- ---- ---- 0000 0000 0000 0000
PZR4[B,H,W]
0x710
---- ---- ---- ---- 0000 0000 0000 0000
PZR5[B,H,W]
0x714
---- ---- ---- ---- 0000 0000 0000 0000
PZR6[B,H,W]
0x718
---- ---- ---- ---- 0000 0000 0000 0000
PZR7[B,H,W]
0x71C
---- ---- ---- ---- 0000 0000 0000 0000
PZR8[B,H,W]
0x720
---- ---- ---- ---- 0000 0000 0000 0000
PZR9[B,H,W]
0x724
---- ---- ---- ---- 0000 0000 0000 0000
PZRA[B,H,W]
0x728
---- ---- ---- ---- 0000 0000 0000 0000
PZRB[B,H,W]
0x72C
---- ---- ---- ---- 0000 0000 0000 0000
PZRC[B,H,W]
0x730
---- ---- ---- ---- 0000 0000 0000 0000
PZRD[B,H,W]
0x734
---- ---- ---- ---- 0000 0000 0000 0000
PZRE[B,H,W]
0x738
---- ---- ---- ---- 0000 0000 0000 0000
PZRF[B,H,W]
0x73C
---- ---- ---- ---- 0000 0000 0000 0000
-
-
0xF00 – 0xF04
174
CONFIDENTIAL
-
-
-
-
-
-
*
-
-
-
-
0xFE0
0xFE4 - 0xFFC
+0
---- ---- ---- ---- 0000 0000 0000 0000
0x704
0xF08 – 0xFDC
+1
PZR0[B,H,W]
0x700
0x740 - 0xEFC
M A N U A L
*
FM4_MN709-00003-4v0-E, May 27, 2015
A. Register Map
1. Register Map
P E R I P H E R A L
1.20.2
M A N U A L
TYPE3-M4 product
GPIO
Base_Address : 0x4006_F000
Register
Base_Address
+ Address
+3
PFR1[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PFR2[B,H,W]
0x008
---- ---- ---- ---- 0000 0000 0000 0000
PFR3[B,H,W]
0x00C
---- ---- ---- ---- 0000 0000 0000 0000
PFR4[B,H,W]
0x010
---- ---- ---- ---- 0000 0000 0000 0000
PFR5[B,H,W]
0x014
---- ---- ---- ---- 0000 0000 0000 0000
PFR6[B,H,W]
0x018
---- ---- ---- ---- 0000 0000 0000 0000
PFR7[B,H,W]
0x01C
---- ---- ---- ---- 0000 0000 0000 0000
PFR8[B,H,W]
0x020
---- ---- ---- ---- 0000 0000 0000 0000
PFR9[B,H,W]
0x024
---- ---- ---- ---- 0000 0000 0000 0000
PFRA[B,H,W]
0x028
---- ---- ---- ---- 0000 0000 0000 0000
PFRB[B,H,W]
0x02C
---- ---- ---- ---- 0000 0000 0000 0000
PFRC[B,H,W]
0x030
---- ---- ---- ---- 0000 0000 0000 0000
PFRD[B,H,W]
0x034
---- ---- ---- ---- 0000 0000 0000 0000
PFRE[B,H,W]
0x038
---- ---- ---- ---- 0000 0000 0000 0000
PFRF[B,H,W]
0x03C
CONFIDENTIAL
+0
---- ---- ---- ---- 0000 0000 0001 1111
0x004
May 27, 2015, FM4_MN709-00003-4v0-E
+1
PFR0[B,H,W]
0x000
0x040 - 0x0FC
+2
---- ---- ---- ---- 0000 0000 0000 0000
-
-
-
-
175
A. Register Map
1. Register Map
P E R I P H E R A L
Register
Base_Address
+ Address
+3
+2
PCR1[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PCR2[B,H,W]
0x108
---- ---- ---- ---- 0000 0000 0000 0000
PCR3[B,H,W]
0x10C
---- ---- ---- ---- 0000 0000 0000 0000
PCR4[B,H,W]
0x110
---- ---- ---- ---- 0000 0000 0000 0000
PCR5[B,H,W]
0x114
---- ---- ---- ---- 0000 0000 0000 0000
PCR6[B,H,W]
0x118
---- ---- ---- ---- 0000 0000 0000 0000
PCR7[B,H,W]
0x11C
---- ---- ---- ---- 0000 0000 0000 0000
0x120
PCR9[B,H,W]
0x124
---- ---- ---- ---- 0000 0000 0000 0000
PCRA[B,H,W]
0x128
---- ---- ---- ---- 0000 0000 0000 0000
PCRB[B,H,W]
0x12C
---- ---- ---- ---- 0000 0000 0000 0000
PCRC[B,H,W]
0x130
---- ---- ---- ---- 0000 0000 0000 0000
PCRD[B,H,W]
0x134
---- ---- ---- ---- 0000 0000 0000 0000
PCRE[B,H,W]
0x138
---- ---- ---- ---- 0000 0000 0000 0000
PCRF[B,H,W]
0x13C
CONFIDENTIAL
+0
---- ---- ---- ---- 0000 0000 0001 1111
0x104
176
+1
PCR0[B,H,W]
0x100
0x140 - 0x1FC
M A N U A L
---- ---- ---- ---- 0000 0000 0000 0000
-
-
-
-
FM4_MN709-00003-4v0-E, May 27, 2015
A. Register Map
1. Register Map
P E R I P H E R A L
M A N U A L
Register
Base_Address
+ Address
+3
DDR1[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
DDR2[B,H,W]
0x208
---- ---- ---- ---- 0000 0000 0000 0000
DDR3[B,H,W]
0x20C
---- ---- ---- ---- 0000 0000 0000 0000
DDR4[B,H,W]
0x210
---- ---- ---- ---- 0000 0000 0000 0000
DDR5[B,H,W]
0x214
---- ---- ---- ---- 0000 0000 0000 0000
DDR6[B,H,W]
0x218
---- ---- ---- ---- 0000 0000 0000 0000
DDR7[B,H,W]
0x21C
---- ---- ---- ---- 0000 0000 0000 0000
DDR8[B,H,W]
0x220
---- ---- ---- ---- 0000 0000 0000 0000
DDR9[B,H,W]
0x224
---- ---- ---- ---- 0000 0000 0000 0000
DDRA[B,H,W]
0x228
---- ---- ---- ---- 0000 0000 0000 0000
DDRB[B,H,W]
0x22C
---- ---- ---- ---- 0000 0000 0000 0000
DDRC[B,H,W]
0x230
---- ---- ---- ---- 0000 0000 0000 0000
DDRD[B,H,W]
0x234
---- ---- ---- ---- 0000 0000 0000 0000
DDRE[B,H,W]
0x238
---- ---- ---- ---- 0000 0000 0000 0000
DDRF[B,H,W]
0x23C
CONFIDENTIAL
+0
---- ---- ---- ---- 0000 0000 0000 0000
0x204
May 27, 2015, FM4_MN709-00003-4v0-E
+1
DDR0[B,H,W]
0x200
0x240 - 0x2FC
+2
---- ---- ---- ---- 0000 0000 0000 0000
-
-
-
-
177
A. Register Map
1. Register Map
P E R I P H E R A L
Register
Base_Address
+ Address
+3
+0
PDIR1[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PDIR2[B,H,W]
0x308
---- ---- ---- ---- 0000 0000 0000 0000
PDIR3[B,H,W]
0x30C
---- ---- ---- ---- 0000 0000 0000 0000
PDIR4[B,H,W]
0x310
---- ---- ---- ---- 0000 0000 0000 0000
PDIR5[B,H,W]
0x314
---- ---- ---- ---- 0000 0000 0000 0000
PDIR6[B,H,W]
0x318
---- ---- ---- ---- 0000 0000 0000 0000
PDIR7[B,H,W]
0x31C
---- ---- ---- ---- 0000 0000 0000 0000
PDIR8[B,H,W]
0x320
---- ---- ---- ---- 0000 0000 0000 0000
PDIR9[B,H,W]
0x324
---- ---- ---- ---- 0000 0000 0000 0000
PDIRA[B,H,W]
0x328
---- ---- ---- ---- 0000 0000 0000 0000
PDIRB[B,H,W]
0x32C
---- ---- ---- ---- 0000 0000 0000 0000
PDIRC[B,H,W]
0x330
---- ---- ---- ---- 0000 0000 0000 0000
PDIRD[B,H,W]
0x334
---- ---- ---- ---- 0000 0000 0000 0000
PDIRE[B,H,W]
0x338
---- ---- ---- ---- 0000 0000 0000 0000
PDIRF[B,H,W]
0x33C
CONFIDENTIAL
+1
---- ---- ---- ---- 0000 0000 0000 0000
0x304
178
+2
PDIR0[B,H,W]
0x300
0x340 - 0x3FC
M A N U A L
---- ---- ---- ---- 0000 0000 0000 0000
-
-
-
-
FM4_MN709-00003-4v0-E, May 27, 2015
A. Register Map
1. Register Map
P E R I P H E R A L
M A N U A L
Register
Base_Address
+ Address
+3
PDOR1[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PDOR2[B,H,W]
0x408
---- ---- ---- ---- 0000 0000 0000 0000
PDOR3[B,H,W]
0x40C
---- ---- ---- ---- 0000 0000 0000 0000
PDOR4[B,H,W]
0x410
---- ---- ---- ---- 0000 0000 0000 0000
PDOR5[B,H,W]
0x414
---- ---- ---- ---- 0000 0000 0000 0000
PDOR6[B,H,W]
0x418
---- ---- ---- ---- 0000 0000 0000 0000
PDOR7[B,H,W]
0x41C
---- ---- ---- ---- 0000 0000 0000 0000
PDOR8[B,H,W]
0x420
---- ---- ---- ---- 0000 0000 0000 0000
PDOR9[B,H,W]
0x424
---- ---- ---- ---- 0000 0000 0000 0000
PDORA[B,H,W]
0x428
---- ---- ---- ---- 0000 0000 0000 0000
PDORB[B,H,W]
0x42C
---- ---- ---- ---- 0000 0000 0000 0000
PDORC[B,H,W]
0x430
---- ---- ---- ---- 0000 0000 0000 0000
PDORD[B,H,W]
0x434
---- ---- ---- ---- 0000 0000 0000 0000
PDORE[B,H,W]
0x438
---- ---- ---- ---- 0000 0000 0000 0000
PDORF[B,H,W]
0x43C
---- ---- ---- ---- 0000 0000 0000 0000
-
CONFIDENTIAL
-
-
1111 1111 1111 1111 1111 1111 1111 1111
-
-
-
-
SPSR[B,H,W]
0x580
May 27, 2015, FM4_MN709-00003-4v0-E
ADE[B,H,W]
0x500
0x584 - 0x5FC
+0
---- ---- ---- ---- 0000 0000 0000 0000
0x404
0x504 - 0x57C
+1
PDOR0[B,H,W]
0x400
0x440 - 0x4FC
+2
---- ---- ---- ---- ---- ---- --00 01--
-
-
-
179
A. Register Map
1. Register Map
P E R I P H E R A L
Register
Base_Address
+ Address
0x600
0x604
0x608
0x60C
0x610
0x614
0x618
0x61C
0x620
0x624
0x628
0x62C
0x630
0x634
0x638
0x63C
0x640
0x644
0x648
0x64C
0x650
180
CONFIDENTIAL
M A N U A L
+3
+2
+1
+0
EPFR00[B,H,W]
---- 0000 ---- --11 --0- --0- 0000 –00
EPFR01[B,H,W]
0000 0000 0000 0000 ---0 0000 0000 0000
EPFR02[B,H,W]
0000 0000 0000 0000 ---0 0000 0000 0000
EPFR03[B,H,W]
0000 0000 0000 0000 ---0 0000 0000 0000
EPFR04[B,H,W]
--00 0000 --00 00-- --00 0000 -000 00-EPFR05[B,H,W]
--00 0000 --00 00-- --00 0000 --00 00-EPFR06[B,H,W]
0000 0000 0000 0000 0000 0000 0000 0000
EPFR07[B,H,W]
0000 0000 0000 0000 0000 0000 0000 ---EPFR08[B,H,W]
0000 0000 0000 0000 0000 0000 0000 0000
EPFR09[B,H,W]
0000 0000 0000 0000 0000 0000 0000 0000
EPFR10[B,H,W]
0000 0000 0000 0000 0000 0000 0000 0000
EPFR11[B,H,W]
---- --00 0000 0000 0000 0000 0000 0000
EPFR12[B,H,W]
--00 0000 --00 00-- --00 0000 --00 00-EPFR13[B,H,W]
--00 0000 --00 00-- --00 0000 --00 00-EPFR14[B,H,W]
--00 0000 0000 00-- ---- ---- --00 0000
EPFR15[B,H,W]
0000 0000 0000 0000 0000 0000 0000 0000
EPFR16[B,H,W]
--00 0000 0000 0000 0000 0000 0000 0000
EPFR17[B,H,W]
---- 0000 0000 0000 0000 0000 0000 ---EPFR18[B,H,W]
--00 0000 0000 0000 00-- --00 0000 0000
EPFR19[B,H,W]
---- ---- ---- ---- ---- ---- ---- ---EPFR20[B,H,W]
---- ---0 0000 0000 0000 0000 0000 0000
FM4_MN709-00003-4v0-E, May 27, 2015
A. Register Map
1. Register Map
P E R I P H E R A L
M A N U A L
Register
Base_Address
+ Address
+3
EPFR22[B,H,W]
---- ---- ---- ---- ---- ---- ---- ---EPFR23[B,H,W]
0x65C
---- ---- ---- ---- 0000 0000 0000 0000
EPFR24[B,H,W]
0x660
---- ---- ---- ---- ---- 0000 0000 0000
EPFR25[B,H,W]
0x664
---- ---- ---- ---- ---- ---- ---- 0000
EPFR26[B,H,W]
0x668
CONFIDENTIAL
+0
---- ---- ---- ---- ---- ---- ---- ----
0x658
May 27, 2015, FM4_MN709-00003-4v0-E
+1
EPFR21[B,H,W]
0x654
0x66C – 0x6FC
+2
---- ---- ---- --00 0000 0000 0000 0000
-
-
-
-
181
A. Register Map
1. Register Map
P E R I P H E R A L
Register
Base_Address
+ Address
0x700
0x704
0x708
0x70C
0x710
0x714
0x718
0x71C
0x720
0x724
0x728
0x72C
0x730
0x734
0x738
0x73C
0x740
0x744
0x748
0x74C
0x750
0x754
182
CONFIDENTIAL
M A N U A L
+3
+2
+1
+0
PZR0[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PZR1[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PZR2[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PZR3[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PZR4[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PZR5[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PZR6[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PZR7[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PZR8[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PZR9[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PZRA[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PZRB[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PZRC[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PZRD[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PZRE[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PZRF[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PDSR0[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PDSR1[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PDSR2[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PDSR3[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PDSR4[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PDSR5[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
FM4_MN709-00003-4v0-E, May 27, 2015
A. Register Map
1. Register Map
P E R I P H E R A L
M A N U A L
Register
Base_Address
+ Address
+3
PDSR7[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PDSR8[B,H,W]
0x760
---- ---- ---- ---- 0000 0000 0000 0000
PDSR9[B,H,W]
0x764
---- ---- ---- ---- 0000 0000 0000 0000
PDSRA[B,H,W]
0x768
---- ---- ---- ---- 0000 0000 0000 0000
PDSRB[B,H,W]
0x76C
---- ---- ---- ---- 0000 0000 0000 0000
PDSRC[B,H,W]
0x770
---- ---- ---- ---- 0000 0000 0000 0000
PDSRD[B,H,W]
0x774
---- ---- ---- ---- 0000 0000 0000 0000
PDSRE[B,H,W]
0x778
---- ---- ---- ---- 0000 0000 0000 0000
PDSRF[B,H,W]
0x77C
---- ---- ---- ---- 0000 0000 0000 0000
-
-
-
-
-
-
0xF00 – 0xF04
May 27, 2015, FM4_MN709-00003-4v0-E
CONFIDENTIAL
-
-
-
-
-
-
*
0xFE0
0xFE4 - 0xFFC
+0
---- ---- ---- ---- 0000 0000 0000 0000
0x75C
0xF08 – 0xFDC
+1
PDSR6[B,H,W]
0x758
0x780 - 0xEFC
+2
*
183
A. Register Map
1. Register Map
P E R I P H E R A L
1.20.3
TYPE4-M4 product
GPIO
Base_Address : 0x4006_F000
Register
Base_Address
+ Address
+3
+0
PFR1[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PFR2[B,H,W]
0x008
---- ---- ---- ---- 0000 0000 0000 0000
PFR3[B,H,W]
0x00C
---- ---- ---- ---- 0000 0000 0000 0000
PFR4[B,H,W]
0x010
---- ---- ---- ---- 0000 0000 0000 0000
PFR5[B,H,W]
0x014
---- ---- ---- ---- 0000 0000 0000 0000
PFR6[B,H,W]
0x018
---- ---- ---- ---- 0000 0000 0000 0000
PFR7[B,H,W]
0x01C
---- ---- ---- ---- 0000 0000 0000 0000
PFR8[B,H,W]
0x020
---- ---- ---- ---- 0000 0000 0000 0000
PFR9[B,H,W]
0x024
---- ---- ---- ---- 0000 0000 0000 0000
PFRA[B,H,W]
0x028
---- ---- ---- ---- 0000 0000 0000 0000
PFRB[B,H,W]
0x02C
---- ---- ---- ---- 0000 0000 0000 0000
PFRC[B,H,W]
0x030
---- ---- ---- ---- 0000 0000 0000 0000
PFRD[B,H,W]
0x034
---- ---- ---- ---- 0000 0000 0000 0000
PFRE[B,H,W]
0x038
---- ---- ---- ---- 0000 0000 0000 0000
PFRF[B,H,W]
0x03C
CONFIDENTIAL
+1
---- ---- ---- ---- 0000 0000 0001 1111
0x004
0x040 - 0x0FC
+2
PFR0[B,H,W]
0x000
184
M A N U A L
---- ---- ---- ---- 0000 0000 0000 0000
-
-
-
-
FM4_MN709-00003-4v0-E, May 27, 2015
A. Register Map
1. Register Map
P E R I P H E R A L
M A N U A L
Register
Base_Address
+ Address
+3
+2
---- ---- ---- ---- 0000 0000 0001 1111
PCR1[B,H,W]
0x104
---- ---- ---- ---- 0000 0000 0000 0000
PCR2[B,H,W]
0x108
---- ---- ---- ---- 0000 0000 0000 0000
PCR3[B,H,W]
0x10C
---- ---- ---- ---- 0000 0000 0000 0000
PCR4[B,H,W]
0x110
---- ---- ---- ---- 0000 0000 0000 0000
PCR5[B,H,W]
0x114
---- ---- ---- ---- 0000 0000 0000 0000
PCR6[B,H,W]
0x118
---- ---- ---- ---- 0000 0000 0000 0000
PCR7[B,H,W]
0x11C
---- ---- ---- ---- 0000 0000 0000 0000
0x120
PCR9[B,H,W]
0x124
---- ---- ---- ---- 0000 0000 0000 0000
PCRA[B,H,W]
0x128
---- ---- ---- ---- 0000 0000 0000 0000
PCRB[B,H,W]
0x12C
---- ---- ---- ---- 0000 0000 0000 0000
PCRC[B,H,W]
0x130
---- ---- ---- ---- 0000 0000 0000 0000
PCRD[B,H,W]
0x134
---- ---- ---- ---- 0000 0000 0000 0000
PCRE[B,H,W]
0x138
---- ---- ---- ---- 0000 0000 0000 0000
PCRF[B,H,W]
0x13C
May 27, 2015, FM4_MN709-00003-4v0-E
CONFIDENTIAL
+0
PCR0[B,H,W]
0x100
0x140 - 0x1FC
+1
---- ---- ---- ---- 0000 0000 0000 0000
-
-
-
-
185
A. Register Map
1. Register Map
P E R I P H E R A L
Register
Base_Address
+ Address
+3
+0
DDR1[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
DDR2[B,H,W]
0x208
---- ---- ---- ---- 0000 0000 0000 0000
DDR3[B,H,W]
0x20C
---- ---- ---- ---- 0000 0000 0000 0000
DDR4[B,H,W]
0x210
---- ---- ---- ---- 0000 0000 0000 0000
DDR5[B,H,W]
0x214
---- ---- ---- ---- 0000 0000 0000 0000
DDR6[B,H,W]
0x218
---- ---- ---- ---- 0000 0000 0000 0000
DDR7[B,H,W]
0x21C
---- ---- ---- ---- 0000 0000 0000 0000
DDR8[B,H,W]
0x220
---- ---- ---- ---- 0000 0000 0000 0000
DDR9[B,H,W]
0x224
---- ---- ---- ---- 0000 0000 0000 0000
DDRA[B,H,W]
0x228
---- ---- ---- ---- 0000 0000 0000 0000
DDRB[B,H,W]
0x22C
---- ---- ---- ---- 0000 0000 0000 0000
DDRC[B,H,W]
0x230
---- ---- ---- ---- 0000 0000 0000 0000
DDRD[B,H,W]
0x234
---- ---- ---- ---- 0000 0000 0000 0000
DDRE[B,H,W]
0x238
---- ---- ---- ---- 0000 0000 0000 0000
DDRF[B,H,W]
0x23C
CONFIDENTIAL
+1
---- ---- ---- ---- 0000 0000 0000 0000
0x204
186
+2
DDR0[B,H,W]
0x200
0x240 - 0x2FC
M A N U A L
---- ---- ---- ---- 0000 0000 0000 0000
-
-
-
-
FM4_MN709-00003-4v0-E, May 27, 2015
A. Register Map
1. Register Map
P E R I P H E R A L
M A N U A L
Register
Base_Address
+ Address
+3
PDIR1[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PDIR2[B,H,W]
0x308
---- ---- ---- ---- 0000 0000 0000 0000
PDIR3[B,H,W]
0x30C
---- ---- ---- ---- 0000 0000 0000 0000
PDIR4[B,H,W]
0x310
---- ---- ---- ---- 0000 0000 0000 0000
PDIR5[B,H,W]
0x314
---- ---- ---- ---- 0000 0000 0000 0000
PDIR6[B,H,W]
0x318
---- ---- ---- ---- 0000 0000 0000 0000
PDIR7[B,H,W]
0x31C
---- ---- ---- ---- 0000 0000 0000 0000
PDIR8[B,H,W]
0x320
---- ---- ---- ---- 0000 0000 0000 0000
PDIR9[B,H,W]
0x324
---- ---- ---- ---- 0000 0000 0000 0000
PDIRA[B,H,W]
0x328
---- ---- ---- ---- 0000 0000 0000 0000
PDIRB[B,H,W]
0x32C
---- ---- ---- ---- 0000 0000 0000 0000
PDIRC[B,H,W]
0x330
---- ---- ---- ---- 0000 0000 0000 0000
PDIRD[B,H,W]
0x334
---- ---- ---- ---- 0000 0000 0000 0000
PDIRE[B,H,W]
0x338
---- ---- ---- ---- 0000 0000 0000 0000
PDIRF[B,H,W]
0x33C
CONFIDENTIAL
+0
---- ---- ---- ---- 0000 0000 0000 0000
0x304
May 27, 2015, FM4_MN709-00003-4v0-E
+1
PDIR0[B,H,W]
0x300
0x340 - 0x3FC
+2
---- ---- ---- ---- 0000 0000 0000 0000
-
-
-
-
187
A. Register Map
1. Register Map
P E R I P H E R A L
Register
Base_Address
+ Address
+3
PDOR1[B,H,W]
PDOR2[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PDOR3[B,H,W]
0x40C
---- ---- ---- ---- 0000 0000 0000 0000
PDOR4[B,H,W]
0x410
---- ---- ---- ---- 0000 0000 0000 0000
PDOR5[B,H,W]
0x414
---- ---- ---- ---- 0000 0000 0000 0000
PDOR6[B,H,W]
0x418
---- ---- ---- ---- 0000 0000 0000 0000
PDOR7[B,H,W]
0x41C
---- ---- ---- ---- 0000 0000 0000 0000
PDOR8[B,H,W]
0x420
---- ---- ---- ---- 0000 0000 0000 0000
PDOR9[B,H,W]
0x424
---- ---- ---- ---- 0000 0000 0000 0000
PDORA[B,H,W]
0x428
---- ---- ---- ---- 0000 0000 0000 0000
PDORB[B,H,W]
0x42C
---- ---- ---- ---- 0000 0000 0000 0000
PDORC[B,H,W]
0x430
---- ---- ---- ---- 0000 0000 0000 0000
PDORD[B,H,W]
0x434
---- ---- ---- ---- 0000 0000 0000 0000
PDORE[B,H,W]
0x438
---- ---- ---- ---- 0000 0000 0000 0000
PDORF[B,H,W]
0x43C
---- ---- ---- ---- 0000 0000 0000 0000
-
-
-
1111 1111 1111 1111 1111 1111 1111 1111
-
-
-
-
SPSR[B,H,W]
0x580
CONFIDENTIAL
ADE[B,H,W]
0x500
188
+0
---- ---- ---- ---- 0000 0000 0000 0000
0x408
0x584 - 0x5FC
+1
---- ---- ---- ---- 0000 0000 0000 0000
0x404
0x504 - 0x57C
+2
PDOR0[B,H,W]
0x400
0x440 - 0x4FC
M A N U A L
---- ---- ---- ---- ---- ---- --00 01--
-
-
-
FM4_MN709-00003-4v0-E, May 27, 2015
A. Register Map
1. Register Map
P E R I P H E R A L
M A N U A L
Register
Base_Address
+ Address
0x600
0x604
0x608
0x60C
0x610
0x614
0x618
0x61C
0x620
0x624
0x628
0x62C
0x630
0x634
0x638
0x63C
0x640
0x644
0x648
0x64C
0x650
May 27, 2015, FM4_MN709-00003-4v0-E
CONFIDENTIAL
+3
+2
+1
+0
EPFR00[B,H,W]
---- 0000 ---- --11 --0- --0- 0000 –00
EPFR01[B,H,W]
0000 0000 0000 0000 ---0 0000 0000 0000
EPFR02[B,H,W]
0000 0000 0000 0000 ---0 0000 0000 0000
EPFR03[B,H,W]
0000 0000 0000 0000 ---0 0000 0000 0000
EPFR04[B,H,W]
--00 0000 --00 00-- --00 0000 -000 00-EPFR05[B,H,W]
--00 0000 --00 00-- --00 0000 --00 00-EPFR06[B,H,W]
0000 0000 0000 0000 0000 0000 0000 0000
EPFR07[B,H,W]
0000 0000 0000 0000 0000 0000 0000 ---EPFR08[B,H,W]
0000 0000 0000 0000 0000 0000 0000 0000
EPFR09[B,H,W]
0000 0000 0000 0000 0000 0000 0000 0000
EPFR10[B,H,W]
0000 0000 0000 0000 0000 0000 0000 0000
EPFR11[B,H,W]
---- --00 0000 0000 0000 0000 0000 0000
EPFR12[B,H,W]
--00 0000 --00 00-- --00 0000 --00 00-EPFR13[B,H,W]
--00 0000 --00 00-- --00 0000 --00 00-EPFR14[B,H,W]
--00 0000 0000 00-- ---- ---- --00 0000
EPFR15[B,H,W]
0000 0000 0000 0000 0000 0000 0000 0000
EPFR16[B,H,W]
--00 0000 0000 0000 0000 0000 0000 0000
EPFR17[B,H,W]
---- 0000 0000 0000 0000 0000 0000 ---EPFR18[B,H,W]
--00 0000 0000 0000 00-- --00 0000 0000
EPFR19[B,H,W]
---- ---- ---- ---- ---- ---- ---- ---EPFR20[B,H,W]
---- ---0 0000 0000 0000 0000 0000 0000
189
A. Register Map
1. Register Map
P E R I P H E R A L
Register
Base_Address
+ Address
+3
---- ---- ---- ---- ---- ---- ---- ---EPFR23[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
EPFR24[B,H,W]
0x660
---- 0000 0000 0000 ---- 0000 0000 0000
EPFR25[B,H,W]
0x664
---- ---- ---- ---- ---- ---- ---- 0000
EPFR26[B,H,W]
0x668
---- ---- ---- --00 0000 0000 0000 0000
EPFR27[B,H,W]
0x66C
0000 0000 0000 0000 0000 0000 0000 0000
EPFR28[B,H,W]
0x670
0000 0000 0000 0000 0000 0000 0000 0000
EPFR29[B,H,W]
0x674
0000 0000 0000 00-- 0000 0000 0000 0000
EPFR30[B,H,W]
0x67C
0x708
0x70C
0x710
0x714
0x718
0x71C
0x720
0x724
0x728
0x72C
0x730
0x734
190
CONFIDENTIAL
+0
EPFR22[B,H,W]
0x65C
0x704
+1
---- ---- ---- ---- ---- ---- ---- ----
0x658
0x700
+2
EPFR21[B,H,W]
0x654
0x680 – 0x6FC
M A N U A L
---- --00 0000 0000 ---- 0000 0000 0000
-
-
-
-
PZR0[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PZR1[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PZR2[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PZR3[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PZR4[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PZR5[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PZR6[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PZR7[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PZR8[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PZR9[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PZRA[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PZRB[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PZRC[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PZRD[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
FM4_MN709-00003-4v0-E, May 27, 2015
A. Register Map
1. Register Map
P E R I P H E R A L
M A N U A L
Register
Base_Address
+ Address
+3
PZRF[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
-
-
-
-
-
-
0xF00 – 0xF04
May 27, 2015, FM4_MN709-00003-4v0-E
CONFIDENTIAL
-
-
-
-
-
-
*
0xFE0
0xFE4 - 0xFFC
+0
---- ---- ---- ---- 0000 0000 0000 0000
0x73C
0xF08 – 0xFDC
+1
PZRE[B,H,W]
0x738
0x740 - 0xEFC
+2
*
191
A. Register Map
1. Register Map
P E R I P H E R A L
1.20.4
TYPE5-M4 product
GPIO
Base_Address : 0x4006_F000
Register
Base_Address
+ Address
+3
+0
PFR1[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PFR2[B,H,W]
0x008
---- ---- ---- ---- 0000 0000 0000 0000
PFR3[B,H,W]
0x00C
---- ---- ---- ---- 0000 0000 0000 0000
PFR4[B,H,W]
0x010
---- ---- ---- ---- 0000 0000 0000 0000
PFR5[B,H,W]
0x014
---- ---- ---- ---- 0000 0000 0000 0000
PFR6[B,H,W]
0x018
---- ---- ---- ---- 0000 0000 0000 0000
PFR7[B,H,W]
0x01C
---- ---- ---- ---- 0000 0000 0000 0000
PFR8[B,H,W]
0x020
---- ---- ---- ---- 0000 0000 0000 0000
PFR9[B,H,W]
0x024
---- ---- ---- ---- 0000 0000 0000 0000
PFRA[B,H,W]
0x028
---- ---- ---- ---- 0000 0000 0000 0000
PFRB[B,H,W]
0x02C
---- ---- ---- ---- 0000 0000 0000 0000
PFRC[B,H,W]
0x030
---- ---- ---- ---- 0000 0000 0000 0000
PFRD[B,H,W]
0x034
---- ---- ---- ---- 0000 0000 0000 0000
PFRE[B,H,W]
0x038
---- ---- ---- ---- 0000 0000 0000 0000
PFRF[B,H,W]
0x03C
CONFIDENTIAL
+1
---- ---- ---- ---- 0000 0000 0001 1111
0x004
0x040 - 0x0FC
+2
PFR0[B,H,W]
0x000
192
M A N U A L
---- ---- ---- ---- 0000 0000 0000 0000
-
-
-
-
FM4_MN709-00003-4v0-E, May 27, 2015
A. Register Map
1. Register Map
P E R I P H E R A L
M A N U A L
Register
Base_Address
+ Address
+3
+2
---- ---- ---- ---- 0000 0000 0001 1111
PCR1[B,H,W]
0x104
---- ---- ---- ---- 0000 0000 0000 0000
PCR2[B,H,W]
0x108
---- ---- ---- ---- 0000 0000 0000 0000
PCR3[B,H,W]
0x10C
---- ---- ---- ---- 0000 0000 0000 0000
PCR4[B,H,W]
0x110
---- ---- ---- ---- 0000 0000 0000 0000
PCR5[B,H,W]
0x114
---- ---- ---- ---- 0000 0000 0000 0000
PCR6[B,H,W]
0x118
---- ---- ---- ---- 0000 0000 0000 0000
PCR7[B,H,W]
0x11C
---- ---- ---- ---- 0000 0000 0000 0000
0x120
PCR9[B,H,W]
0x124
---- ---- ---- ---- 0000 0000 0000 0000
PCRA[B,H,W]
0x128
---- ---- ---- ---- 0000 0000 0000 0000
PCRB[B,H,W]
0x12C
---- ---- ---- ---- 0000 0000 0000 0000
PCRC[B,H,W]
0x130
---- ---- ---- ---- 0000 0000 0000 0000
PCRD[B,H,W]
0x134
---- ---- ---- ---- 0000 0000 0000 0000
PCRE[B,H,W]
0x138
---- ---- ---- ---- 0000 0000 0000 0000
PCRF[B,H,W]
0x13C
May 27, 2015, FM4_MN709-00003-4v0-E
CONFIDENTIAL
+0
PCR0[B,H,W]
0x100
0x140 - 0x1FC
+1
---- ---- ---- ---- 0000 0000 0000 0000
-
-
-
-
193
A. Register Map
1. Register Map
P E R I P H E R A L
Register
Base_Address
+ Address
+3
+0
DDR1[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
DDR2[B,H,W]
0x208
---- ---- ---- ---- 0000 0000 0000 0000
DDR3[B,H,W]
0x20C
---- ---- ---- ---- 0000 0000 0000 0000
DDR4[B,H,W]
0x210
---- ---- ---- ---- 0000 0000 0000 0000
DDR5[B,H,W]
0x214
---- ---- ---- ---- 0000 0000 0000 0000
DDR6[B,H,W]
0x218
---- ---- ---- ---- 0000 0000 0000 0000
DDR7[B,H,W]
0x21C
---- ---- ---- ---- 0000 0000 0000 0000
DDR8[B,H,W]
0x220
---- ---- ---- ---- 0000 0000 0000 0000
DDR9[B,H,W]
0x224
---- ---- ---- ---- 0000 0000 0000 0000
DDRA[B,H,W]
0x228
---- ---- ---- ---- 0000 0000 0000 0000
DDRB[B,H,W]
0x22C
---- ---- ---- ---- 0000 0000 0000 0000
DDRC[B,H,W]
0x230
---- ---- ---- ---- 0000 0000 0000 0000
DDRD[B,H,W]
0x234
---- ---- ---- ---- 0000 0000 0000 0000
DDRE[B,H,W]
0x238
---- ---- ---- ---- 0000 0000 0000 0000
DDRF[B,H,W]
0x23C
CONFIDENTIAL
+1
---- ---- ---- ---- 0000 0000 0000 0000
0x204
194
+2
DDR0[B,H,W]
0x200
0x240 - 0x2FC
M A N U A L
---- ---- ---- ---- 0000 0000 0000 0000
-
-
-
-
FM4_MN709-00003-4v0-E, May 27, 2015
A. Register Map
1. Register Map
P E R I P H E R A L
M A N U A L
Register
Base_Address
+ Address
+3
PDIR1[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PDIR2[B,H,W]
0x308
---- ---- ---- ---- 0000 0000 0000 0000
PDIR3[B,H,W]
0x30C
---- ---- ---- ---- 0000 0000 0000 0000
PDIR4[B,H,W]
0x310
---- ---- ---- ---- 0000 0000 0000 0000
PDIR5[B,H,W]
0x314
---- ---- ---- ---- 0000 0000 0000 0000
PDIR6[B,H,W]
0x318
---- ---- ---- ---- 0000 0000 0000 0000
PDIR7[B,H,W]
0x31C
---- ---- ---- ---- 0000 0000 0000 0000
PDIR8[B,H,W]
0x320
---- ---- ---- ---- 0000 0000 0000 0000
PDIR9[B,H,W]
0x324
---- ---- ---- ---- 0000 0000 0000 0000
PDIRA[B,H,W]
0x328
---- ---- ---- ---- 0000 0000 0000 0000
PDIRB[B,H,W]
0x32C
---- ---- ---- ---- 0000 0000 0000 0000
PDIRC[B,H,W]
0x330
---- ---- ---- ---- 0000 0000 0000 0000
PDIRD[B,H,W]
0x334
---- ---- ---- ---- 0000 0000 0000 0000
PDIRE[B,H,W]
0x338
---- ---- ---- ---- 0000 0000 0000 0000
PDIRF[B,H,W]
0x33C
CONFIDENTIAL
+0
---- ---- ---- ---- 0000 0000 0000 0000
0x304
May 27, 2015, FM4_MN709-00003-4v0-E
+1
PDIR0[B,H,W]
0x300
0x340 - 0x3FC
+2
---- ---- ---- ---- 0000 0000 0000 0000
-
-
-
-
195
A. Register Map
1. Register Map
P E R I P H E R A L
Register
Base_Address
+ Address
+3
PDOR1[B,H,W]
PDOR2[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PDOR3[B,H,W]
0x40C
---- ---- ---- ---- 0000 0000 0000 0000
PDOR4[B,H,W]
0x410
---- ---- ---- ---- 0000 0000 0000 0000
PDOR5[B,H,W]
0x414
---- ---- ---- ---- 0000 0000 0000 0000
PDOR6[B,H,W]
0x418
---- ---- ---- ---- 0000 0000 0000 0000
PDOR7[B,H,W]
0x41C
---- ---- ---- ---- 0000 0000 0000 0000
PDOR8[B,H,W]
0x420
---- ---- ---- ---- 0000 0000 0000 0000
PDOR9[B,H,W]
0x424
---- ---- ---- ---- 0000 0000 0000 0000
PDORA[B,H,W]
0x428
---- ---- ---- ---- 0000 0000 0000 0000
PDORB[B,H,W]
0x42C
---- ---- ---- ---- 0000 0000 0000 0000
PDORC[B,H,W]
0x430
---- ---- ---- ---- 0000 0000 0000 0000
PDORD[B,H,W]
0x434
---- ---- ---- ---- 0000 0000 0000 0000
PDORE[B,H,W]
0x438
---- ---- ---- ---- 0000 0000 0000 0000
PDORF[B,H,W]
0x43C
---- ---- ---- ---- 0000 0000 0000 0000
-
-
-
1111 1111 1111 1111 1111 1111 1111 1111
-
-
-
-
SPSR[B,H,W]
0x580
CONFIDENTIAL
ADE[B,H,W]
0x500
196
+0
---- ---- ---- ---- 0000 0000 0000 0000
0x408
0x584 - 0x5FC
+1
---- ---- ---- ---- 0000 0000 0000 0000
0x404
0x504 - 0x57C
+2
PDOR0[B,H,W]
0x400
0x440 - 0x4FC
M A N U A L
---- ---- ---- ---- ---- ---- --00 01--
-
-
-
FM4_MN709-00003-4v0-E, May 27, 2015
A. Register Map
1. Register Map
P E R I P H E R A L
M A N U A L
Register
Base_Address
+ Address
0x600
0x604
0x608
0x60C
0x610
0x614
0x618
0x61C
0x620
0x624
0x628
0x62C
0x630
0x634
0x638
0x63C
0x640
0x644
0x648
0x64C
0x650
May 27, 2015, FM4_MN709-00003-4v0-E
CONFIDENTIAL
+3
+2
+1
+0
EPFR00[B,H,W]
---- 0000 ---- --11 --0- --0- 0000 –00
EPFR01[B,H,W]
0000 0000 0000 0000 ---0 0000 0000 0000
EPFR02[B,H,W]
0000 0000 0000 0000 ---0 0000 0000 0000
EPFR03[B,H,W]
---- ---- ---- ---- ---- ---- ---- ---EPFR04[B,H,W]
--00 0000 --00 00-- --00 0000 -000 00-EPFR05[B,H,W]
--00 0000 --00 00-- --00 0000 --00 00-EPFR06[B,H,W]
0000 0000 0000 0000 0000 0000 0000 0000
EPFR07[B,H,W]
0000 0000 0000 0000 0000 0000 0000 ---EPFR08[B,H,W]
0000 0000 0000 0000 0000 0000 0000 0000
EPFR09[B,H,W]
0000 0000 0000 0000 0000 0000 0000 0000
EPFR10[B,H,W]
0000 0000 0000 0000 0000 0000 0000 0000
EPFR11[B,H,W]
---- --00 0000 0000 0000 0000 0000 0000
EPFR12[B,H,W]
--00 0000 --00 00-- --00 0000 --00 00-EPFR13[B,H,W]
--00 0000 --00 00-- --00 0000 --00 00-EPFR14[B,H,W]
--00 0000 0000 00-- ---- ---- --00 0000
EPFR15[B,H,W]
0000 0000 0000 0000 0000 0000 0000 0000
EPFR16[B,H,W]
--00 0000 0000 0000 0000 0000 0000 0000
EPFR17[B,H,W]
---- ---- ---- ---- ---- ---- ---- ---EPFR18[B,H,W]
--00 0000 0000 0000 00-- --00 0000 0000
EPFR19[B,H,W]
---- ---- ---- ---- ---- ---- ---- ---EPFR20[B,H,W]
---- ---0 0000 0000 0000 0000 0000 0000
197
A. Register Map
1. Register Map
P E R I P H E R A L
Register
Base_Address
+ Address
+3
---- ---- ---- ---- ---- ---- ---- ---EPFR23[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
EPFR24[B,H,W]
0x660
---- ---- ---- ---- ---- 0000 0000 0000
EPFR25[B,H,W]
0x664
---- ---- ---- ---- ---- ---- ---- 0000
EPFR26[B,H,W]
0x668
---- ---- ---- --00 0000 0000 0000 0000
-
-
-
---- 0000 0000 0000 ---- 0000 0000 0000
-
-
-
-
EPFR35[B,H,W]
0x68C
CONFIDENTIAL
EPFR33[B,H,W]
0x684
198
+0
EPFR22[B,H,W]
0x65C
0x690 – 0x6FC
+1
---- ---- ---- ---- ---- ---- ---- ----
0x658
0x688
+2
EPFR21[B,H,W]
0x654
0x66C – 0x680
M A N U A L
---- 0000 0000 0000 ---- ---- ---- ----
-
-
-
FM4_MN709-00003-4v0-E, May 27, 2015
A. Register Map
1. Register Map
P E R I P H E R A L
M A N U A L
Register
Base_Address
+ Address
0x700
0x704
0x708
0x70C
0x710
0x714
0x718
0x71C
0x720
0x724
0x728
0x72C
0x730
0x734
0x738
0x73C
0x740
0x744
0x748
0x74C
0x750
0x754
May 27, 2015, FM4_MN709-00003-4v0-E
CONFIDENTIAL
+3
+2
+1
+0
PZR0[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PZR1[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PZR2[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PZR3[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PZR4[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PZR5[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PZR6[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PZR7[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PZR8[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PZR9[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PZRA[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PZRB[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PZRC[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PZRD[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PZRE[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PZRF[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PDSR0[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PDSR1[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PDSR2[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PDSR3[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PDSR4[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PDSR5[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
199
A. Register Map
1. Register Map
P E R I P H E R A L
Register
Base_Address
+ Address
+3
+2
PDSR7[B,H,W]
---- ---- ---- ---- 0000 0000 0000 0000
PDSR8[B,H,W]
0x760
---- ---- ---- ---- 0000 0000 0000 0000
PDSR9[B,H,W]
0x764
---- ---- ---- ---- 0000 0000 0000 0000
PDSRA[B,H,W]
0x768
---- ---- ---- ---- 0000 0000 0000 0000
PDSRB[B,H,W]
0x76C
---- ---- ---- ---- 0000 0000 0000 0000
PDSRC[B,H,W]
0x770
---- ---- ---- ---- 0000 0000 0000 0000
PDSRD[B,H,W]
0x774
---- ---- ---- ---- 0000 0000 0000 0000
PDSRE[B,H,W]
0x778
---- ---- ---- ---- 0000 0000 0000 0000
PDSRF[B,H,W]
0x77C
---- ---- ---- ---- 0000 0000 0000 0000
-
-
-
-
-
-
0xF00 – 0xF04
200
CONFIDENTIAL
-
-
-
-
-
-
*
0xFE0
0xFE4 - 0xFFC
+0
---- ---- ---- ---- 0000 0000 0000 0000
0x75C
0xF08 – 0xFDC
+1
PDSR6[B,H,W]
0x758
0x780 - 0xEFC
M A N U A L
*
FM4_MN709-00003-4v0-E, May 27, 2015
A. Register Map
1. Register Map
P E R I P H E R A L
M A N U A L
1.21 LVD
LVD
Base_Address : 0x4003_5000
Register
Base_Address
+ Address
0x000
0x004
0x008
+3
+2
-
+1
-
-
-
-
-
+0
LVD_CTL[B,H,W]
000111-LVD_STR[B,H,W]
-
-
0------LVD_CLR[B,H,W]
-
1-------
LVD_RLR[W]
0x00C
00000000 00000000 00000000 00000001
LVD_STR2 [B,H,W]
0x010
-
-
-
0x014 - 0x0FC
-
-
-
-
0------
1.22 DS_Mode
DS_Mode Base_Address : 0x4003_5100
Register
Base_Address
+ Address
+3
+2
+1
+0
0x000
-
-
-
*
0x004
-
-
-
0x008 - 0x6FC
-
-
-
0x700
-
-
-
0x704
-
-
-
0x708
-
-
0x70C
-
-
0x710
-
-
0x714
0x718 - 0x7FC
0x800
0x804
0x808
0x80C
0x810 - 0xEFC
May 27, 2015, FM4_MN709-00003-4v0-E
CONFIDENTIAL
-
-
RCK_CTL[B,H,W]
------01
PMD_CTL[B,H,W]
-------0
WRFSR[B,H,W]
------00
WIFSR[B,H,W]
------00 00000000
WIER[B,H,W]
------00 00000-00
-
WILVR[B,H,W]
---00000
DSRAMR[B,H,W]
------00
-
-
-
-
BUR04[B,H,W]
BUR03[B,H,W]
BUR02[B,H,W]
BUR01[B,H,W]
00000000
00000000
00000000
00000000
BUR08[B,H,W]
BUR07[B,H,W]
BUR06[B,H,W]
BUR05[B,H,W]
00000000
00000000
00000000
00000000
BUR012[B,H,W]
BUR11[B,H,W]
BUR10[B,H,W]
BUR09[B,H,W]
00000000
00000000
00000000
00000000
BUR16[B,H,W]
BUR15[B,H,W]
BUR14[B,H,W]
BUR13[B,H,W]
00000000
00000000
00000000
00000000
-
-
-
201
A. Register Map
1. Register Map
P E R I P H E R A L
M A N U A L
1.23 USB Clock
USB Clock
Base_Address : 0x4003_6000
Register
Base_Address
+ Address
0x000
0x004
-
-
-
+1
-
-
-
-
-
0x00C
-
-
-
0x010
-
-
-
0x014
-
-
-
0x018
-
-
-
0x01C
-
-
-
0x024
CONFIDENTIAL
-
+2
0x008
0x020
202
+3
-
-
-
0x028
-
-
-
0x02C
-
-
-
0x030
-
-
-
0x034
-
-
-
0x038 - 0x0FC
-
-
-
+0
UCCR[B,H,W]
-0000000
UPCR1[B,H,W]
------00
UPCR2[B,H,W]
-----000
UPCR3[B,H,W]
---00000
UPCR4[B,H,W]
-0111011
UP_STR[B,H,W]
-------0
UPINT_ENR[B,H,W]
-------0
UPINT_CLR[B,H,W]
-------0
UPINT_STR[B,H,W]
-------0
UPCR5[B,H,W]
----0100
UPCR6[B,H,W]
----0010
UPCR7[B,H,W]
-------0
USBEN0[B,H,W]
-------0
USBEN1[B,H,W]
-------0
-
FM4_MN709-00003-4v0-E, May 27, 2015
A. Register Map
1. Register Map
P E R I P H E R A L
M A N U A L
1.24 CAN_Prescaler
CAN_Prescaler
Base_Address : 0x4003_7000
Register
Base_Address
+ Address
+3
+2
+1
+0
CANPRE[B,H,W]
0x000
-
-
-
0x004 - 0xFFC
-
-
-
-
+0
----1011
1.25 MFS
MFS ch.0 Base_Address : 0x4003_8000
MFS ch.1 Base_Address : 0x4003_8100
MFS ch.2 Base_Address : 0x4003_8200
MFS ch.3 Base_Address : 0x4003_8300
MFS ch.4 Base_Address : 0x4003_8400
MFS ch.5 Base_Address : 0x4003_8500
MFS ch.6 Base_Address : 0x4003_8600
MFS ch.7 Base_Address : 0x4003_8700
MFS ch.8 Base_Address : 0x4003_8800
MFS ch.9 Base_Address : 0x4003_8900
MFS ch.10Base_Address : 0x4003_8A00
MFS ch.11 Base_Address : 0x4003_8B00
MFS ch.12Base_Address : 0x4003_8C00
MFS ch.13Base_Address : 0x4003_8D00
MFS ch.14Base_Address : 0x4003_8E00
MFS ch.15Base_Address : 0x4003_8F00
Register
Base_Address
+ Address
+3
+2
+1
0x000
-
-
IBCR[B,H,W]
SCR /
SMR[B,H,W]
000-00-0
0--00000
0x004
-
0x008
-
SSR[B,H,W]
0-000011
ESCR /
IBSR[B,H,W]
00000000
RDR/TDR[H,W]
-
00000000 00000000
(*1) RDR/TDR[H,W]
00000000 00000000 00000000 00000000
May 27, 2015, FM4_MN709-00003-4v0-E
CONFIDENTIAL
203
A. Register Map
1. Register Map
P E R I P H E R A L
Register
Base_Address
+ Address
+3
+3
0x00C
-
-
0x010
-
-
0x014
-
-
0x018
0x01C
0x020
0x024
0x028
M A N U A L
-
-
-
-
-
-
0x02C
-
-
0x030
-
-
0x034
-
-
0x038
-
-
0x03C
-
-
0x040
-
-
0x0144 - 0x1FC
-
-
+3
+3
BGR1[B,H,W]
BGR0[B,H,W]
00000000
00000000
ISMK[B,H,W]
ISBA[B,H,W]
--------
--------
FCR1[B,H,W]
FCR0[B,H,W]
---00100
-0000000
FBYTE2[B,H,W]
FBYTE1[B,H,W]
00000000
00000000
SCSTR1/
SCSTR0/
EIBCR[B,H,W]
NFCR[B,H,W]
00000000
00000000
SCSTR3[B,H,W]
SCSTR2[B,H,W]
00000000
00000000
SACSR1[B,H,W]
SACSR0[B,H,W]
00000000
00000000
STMR1[B,H,W]
STMR0[B,H,W]
00000000
00000000
STMCR1[B,H,W]
STMCR0[B,H,W]
00000000
00000000
SCSCR1[B,H,W]
SCSCR0[B,H,W]
00000000
00100000
SCSFR1[B,H,W]
SCSFR0[B,H,W]
10000000
10000000
-
SCSFR2[B,H,W]
10000000
TBYTE1[B,H,W]
TBYTE0[B,H,W]
00000000
00000000
TBYTE3[B,H,W]
TBYTE2[B,H,W]
00000000
00000000
-
-
Note:
−
204
CONFIDENTIAL
(*1): RDR/TDR register’s higher 16 bits can be accessed by word operation in I2S mode.
FM4_MN709-00003-4v0-E, May 27, 2015
A. Register Map
1. Register Map
P E R I P H E R A L
M A N U A L
1.26 CRC
CRC
Base_Address : 0x4003_9000
Base_Address
+ Address
0x000
Register
+3
-
+2
+1
-
+0
CRCCR[B,H,W]
-
-0000000
CRCINIT[B,H,W]
0x004
11111111 11111111 11111111 11111111
CRCIN[B,H,W]
0x008
00000000 00000000 00000000 00000000
CRCR[B,H,W]
0x00C
11111111 11111111 11111111 11111111
1.27 Watch Counter
Watch Counter
Base_Address : 0x4003_A000
Base_Address
+3
+2
+1
+0
0x000
-
WCCR[B,H,W]
WCRL[B,H,W]
WCRD[B,H,W]
00--0000
--000000
--000000
0x004 - 0x00C
-
-
-
-
0x010
-
-
0x014
-
-
-
0x018 - 0xFFC
-
-
-
May 27, 2015, FM4_MN709-00003-4v0-E
CONFIDENTIAL
Register
+ Address
CLK_SEL[B,H,W]
-----000 -------0
CLK_EN[B,H,W]
------00
-
205
A. Register Map
1. Register Map
P E R I P H E R A L
M A N U A L
1.28 RTC
1.28.1 TYPE1-M4, TYPE2-M4, TYPE3-M4, TYPE6-M4 products
RTC
Base_Address : 0x4003_B000
Register
Base_Address
+ Address
0x100
-
+1
-
-
-
-
0x108
-
-
-
0x10C
-
-
-
0x110
-
-
-
0x114
-
-
-
0x118
-
-
-
0x11C
-
-
-
0x120
-
-
-
0x124
-
-
-
0x128
-
-
-
0x12C
-
-
-
-
-
-
0x134
-
-
-
0x138
-
-
-
0x13C
-
-
-
0x140
-
-
-
0x144
-
-
-
0x148
-
-
-
0x14C
-
-
-
0x150
0x154
CONFIDENTIAL
-
+2
0x104
0x130
206
+3
-
-
-
+0
WTCR10[B,H,W]
00000000
WTCR11[B,H,W]
---00000
WTCR12[B,H,W]
00000000
WTCR13[B,H,W]
00000000
WTCR20[B,H,W]
--000000
WTCR21[B,H,W]
-----000
*
WTSR[B,H,W]
-0000000
WTMIR[B,H,W]
-0000000
WTHR[B,H,W]
--000000
WTDR[B,H,W]
--000000
WTDW[B,H,W]
-----000
WTMOR[B,H,W]
---00000
WTYR[B,H,W]
00000000
ALMIR[B,H,W]
-0000000
ALHR[B,H,W]
--000000
ALDR[B,H,W]
--000000
ALMOR[B,H,W]
---00000
ALYR[B,H,W]
00000000
WTTR0[B,H,W]
00000000
WTTR1[B,H,W]
00000000
WTTR2[B,H,W]
------00
FM4_MN709-00003-4v0-E, May 27, 2015
A. Register Map
1. Register Map
P E R I P H E R A L
M A N U A L
Register
Base_Address
+ Address
+3
+2
+1
0x158
-
-
-
0x15C
-
-
0x160
-
-
-
0x164
-
-
-
0x168
-
-
-
0x16C
-
-
-
0x170
-
-
-
0x174
-
-
-
0x178
-
-
-
0x17C
-
-
-
0x180
-
-
-
0x184
-
-
-
0x188
-
-
-
0x18C
-
-
-
0x190
-
-
-
0x194
-
-
-
0x198
-
-
-
0x19C
-
-
-
0x1A0
-
-
-
0x1A4
-
-
-
0x1A8
-
-
-
0x1AC
-
-
-
0x0B0
-
-
-
0x1B4-1FF
-
-
-
May 27, 2015, FM4_MN709-00003-4v0-E
CONFIDENTIAL
-
+0
WTCAL0[B,H,W]
00000000
WTCAL1[B,H,W]
------00
WTCALEN[B,H,W]
-------0
WTDIV[B,H,W]
----0000
WTDIVEN[B,H,W]
------00
WTCALPRD[B,H,W]
--010011
WTCOSEL[B,H,W]
-------0
VB_CLKDIV[B,H,W]
00000111
WTOSCCNT[B,H,W]
------01
CCS[B,H,W]
00001000
CCB[B,H,W]
00010000
*
BOOST[B,H,W]
------11
EWKUP[B,H,W]
-------0
VDET[B,H,W]
00-----*
HIBRST[B,H,W]
-------0
VBPFR[B,H,W]
--011100
VBPCR[B,H,W]
----0000
VBDDR[B,H,W]
----XXXX
VBDIR[B,H,W]
----0000
VBDOR[B,H,W]
----1111
VBPZR[B,H,W]
------11
-
207
A. Register Map
1. Register Map
P E R I P H E R A L
M A N U A L
Register
Base_Address
+ Address
0x200
0x204
0x208
0x20C
0x210
0x214
0x218
0x21C
0x220
0x224
0x228
0x22C
0x230
0x234
0x238
0x23C
0x240
0x244
0x248
0x24C
0x250
0x254
0x258
208
CONFIDENTIAL
+3
+2
+1
+0
BREG03[B,H,W]
BREG02[B,H,W]
BREG01[B,H,W]
BREG00[B,H,W]
00000000
00000000
00000000
00000000
BREG07[B,H,W]
BREG06[B,H,W]
BREG05[B,H,W]
BREG04[B,H,W]
00000000
00000000
00000000
00000000
BREG0B[B,H,W]
BREG0A[B,H,W]
BREG09[B,H,W]
BREG08[B,H,W]
00000000
00000000
00000000
00000000
BREG0F[B,H,W]
BREG0E[B,H,W]
BREG0D[B,H,W]
BREG0C[B,H,W]
00000000
00000000
00000000
00000000
BREG13[B,H,W]
BREG12[B,H,W]
BREG11[B,H,W]
BREG10[B,H,W]
00000000
00000000
00000000
00000000
BREG17[B,H,W]
BREG16[B,H,W]
BREG15[B,H,W]
BREG14[B,H,W]
00000000
00000000
00000000
00000000
BREG1B[B,H,W]
BREG1A[B,H,W]
BREG19[B,H,W]
BREG18[B,H,W]
00000000
00000000
00000000
00000000
BREG1F[B,H,W]
BREG1E[B,H,W]
BREG1D[B,H,W]
BREG1C[B,H,W]
00000000
00000000
00000000
00000000
BREG23[B,H,W]
BREG22[B,H,W]
BREG21[B,H,W]
BREG20[B,H,W]
00000000
00000000
00000000
00000000
BREG27[B,H,W]
BREG26[B,H,W]
BREG25[B,H,W]
BREG24[B,H,W]
00000000
00000000
00000000
00000000
BREG2B[B,H,W]
BREG2A[B,H,W]
BREG29[B,H,W]
BREG28[B,H,W]
00000000
00000000
00000000
00000000
BREG2F[B,H,W]
BREG2E[B,H,W]
BREG2D[B,H,W]
BREG2C[B,H,W]
00000000
00000000
00000000
00000000
BREG33[B,H,W]
BREG32[B,H,W]
BREG31[B,H,W]
BREG30[B,H,W]
00000000
00000000
00000000
00000000
BREG37[B,H,W]
BREG36[B,H,W]
BREG35[B,H,W]
BREG34[B,H,W]
00000000
00000000
00000000
00000000
BREG3B[B,H,W]
BREG3A[B,H,W]
BREG39[B,H,W]
BREG38[B,H,W]
00000000
00000000
00000000
00000000
BREG3F[B,H,W]
BREG3E[B,H,W]
BREG3D[B,H,W]
BREG3C[B,H,W]
00000000
00000000
00000000
00000000
BREG43[B,H,W]
BREG42[B,H,W]
BREG41[B,H,W]
BREG40[B,H,W]
00000000
00000000
00000000
00000000
BREG47[B,H,W]
BREG46[B,H,W]
BREG45[B,H,W]
BREG44[B,H,W]
00000000
00000000
00000000
00000000
BREG4B[B,H,W]
BREG4A[B,H,W]
BREG49[B,H,W]
BREG48[B,H,W]
00000000
00000000
00000000
00000000
BREG4F[B,H,W]
BREG4E[B,H,W]
BREG4D[B,H,W]
BREG4C[B,H,W]
00000000
00000000
00000000
00000000
BREG53[B,H,W]
BREG52[B,H,W]
BREG51[B,H,W]
BREG50[B,H,W]
00000000
00000000
00000000
00000000
BREG57[B,H,W]
BREG56[B,H,W]
BREG55[B,H,W]
BREG54[B,H,W]
00000000
00000000
00000000
00000000
BREG5B[B,H,W]
BREG5A[B,H,W]
BREG59[B,H,W]
BREG58[B,H,W]
00000000
00000000
00000000
00000000
FM4_MN709-00003-4v0-E, May 27, 2015
A. Register Map
1. Register Map
P E R I P H E R A L
M A N U A L
Register
Base_Address
+ Address
0x25C
0x260
0x264
0x268
0x26C
0x270
0x274
0x278
0x27C
0x280-0xFFC
1.28.2
+3
+2
+1
+0
BREG5F[B,H,W]
BREG5E[B,H,W]
BREG5D[B,H,W]
BREG5C[B,H,W]
00000000
00000000
00000000
00000000
BREG63[B,H,W]
BREG62[B,H,W]
BREG61[B,H,W]
BREG60[B,H,W]
00000000
00000000
00000000
00000000
BREG67[B,H,W]
BREG66[B,H,W]
BREG65[B,H,W]
BREG64[B,H,W]
00000000
00000000
00000000
00000000
BREG6B[B,H,W]
BREG6A[B,H,W]
BREG69[B,H,W]
BREG68[B,H,W]
00000000
00000000
00000000
00000000
BREG6F[B,H,W]
BREG6E[B,H,W]
BREG6D[B,H,W]
BREG6C[B,H,W]
00000000
00000000
00000000
00000000
BREG73[B,H,W]
BREG72[B,H,W]
BREG71[B,H,W]
BREG70[B,H,W]
00000000
00000000
00000000
00000000
BREG77[B,H,W]
BREG76[B,H,W]
BREG75[B,H,W]
BREG74[B,H,W]
00000000
00000000
00000000
00000000
BREG7B[B,H,W]
BREG7A[B,H,W]
BREG79[B,H,W]
BREG78[B,H,W]
00000000
00000000
00000000
00000000
BREG7F[B,H,W]
BREG7E[B,H,W]
BREG7D[B,H,W]
BREG7C[B,H,W]
00000000
00000000
00000000
00000000
-
-
-
-
TYPE4-M4 product
RTC
Base_Address : 0x4003_B000
Register
Base_Address
+ Address
+2
+1
0x100
-
-
-
0x104
-
-
-
0x108
-
-
-
0x10C
-
-
-
0x110
-
-
-
0x114
-
-
-
0x118
-
-
-
0x11C
-
-
-
0x120
-
-
-
0x124
-
-
-
0x128
-
-
-
May 27, 2015, FM4_MN709-00003-4v0-E
CONFIDENTIAL
+3
+0
WTCR10[B,H,W]
00000000
WTCR11[B,H,W]
---00000
WTCR12[B,H,W]
00000000
WTCR13[B,H,W]
00000000
WTCR20[B,H,W]
--000000
WTCR21[B,H,W]
-----000
*
WTSR[B,H,W]
-0000000
WTMIR[B,H,W]
-0000000
WTHR[B,H,W]
--000000
WTDR[B,H,W]
--000000
209
A. Register Map
1. Register Map
P E R I P H E R A L
Register
Base_Address
+ Address
+3
+2
+1
0x12C
-
-
-
0x130
-
-
-
-
-
0x138
-
-
-
0x13C
-
-
-
0x140
-
-
-
-
-
-
0x148
-
-
-
0x14C
-
-
-
0x150
-
-
-
0x154
-
-
-
0x158
-
-
-
0x15C
0x160
CONFIDENTIAL
-
0x134
0x144
210
M A N U A L
-
-
-
0x164
-
-
-
0x168
-
-
-
0x16C
-
-
-
0x170
-
-
-
0x174
-
-
-
0x178
-
-
-
0x17C
-
-
-
0x180
-
-
-
0x184
-
-
-
0x188
-
-
-
+0
WTDW[B,H,W]
-----000
WTMOR[B,H,W]
---00000
WTYR[B,H,W]
00000000
ALMIR[B,H,W]
-0000000
ALHR[B,H,W]
--000000
ALDR[B,H,W]
--000000
ALMOR[B,H,W]
---00000
ALYR[B,H,W]
00000000
WTTR0[B,H,W]
00000000
WTTR1[B,H,W]
00000000
WTTR2[B,H,W]
------00
WTCAL0[B,H,W]
00000000
WTCAL1[B,H,W]
------00
WTCALEN[B,H,W]
-------0
WTDIV[B,H,W]
----0000
WTDIVEN[B,H,W]
------00
WTCALPRD[B,H,W]
--010011
WTCOSEL[B,H,W]
-------0
VB_DIVCLK[B,H,W]
00000111
WTOSCCNT[B,H,W]
------01
CCS[B,H,W]
11001110
CCB[B,H,W]
11001110
*
BOOST[B,H,W]
------11
FM4_MN709-00003-4v0-E, May 27, 2015
A. Register Map
1. Register Map
P E R I P H E R A L
M A N U A L
Register
Base_Address
+ Address
+3
+2
+1
0x18C
-
-
-
0x190
-
-
-
0x194
-
-
-
0x198
-
-
-
0x19C
-
-
EWKUP[B,H,W]
-------0
VDET[B,H,W]
00-----*
HIBRST[B,H,W]
-------0
VBPFR[B,H,W]
--011100
VBPCR[B,H,W]
0x1A0
-
-
-
0x1A4
-
-
-
0x1A8
-
-
-
0x1AC
-
-
-
0x1B0
-
-
-
0x1B4-1FF
-
-
-
-
BREG03[B,H,W]
BREG02[B,H,W]
BREG01[B,H,W]
BREG00[B,H,W]
00000000
00000000
00000000
00000000
BREG07[B,H,W]
BREG06[B,H,W]
BREG05[B,H,W]
BREG04[B,H,W]
0x200
0x204
0x208
0x20C
0x210
0x214
0x218
0x21C
0x220
0x224
0x228
0x22C
0x230
May 27, 2015, FM4_MN709-00003-4v0-E
CONFIDENTIAL
-
+0
----0000
VBDDR[B,H,W]
----0000
VBDIR[B,H,W]
----XXXX
VBDOR[B,H,W]
----1111
VBPZR[B,H,W]
------11
00000000
00000000
00000000
00000000
BREG0B[B,H,W]
BREG0A[B,H,W]
BREG09[B,H,W]
BREG08[B,H,W]
00000000
00000000
00000000
00000000
BREG0F[B,H,W]
BREG0E[B,H,W]
BREG0D[B,H,W]
BREG0C[B,H,W]
00000000
00000000
00000000
00000000
BREG13[B,H,W]
BREG12[B,H,W]
BREG11[B,H,W]
BREG10[B,H,W]
00000000
00000000
00000000
00000000
BREG17[B,H,W]
BREG16[B,H,W]
BREG15[B,H,W]
BREG14[B,H,W]
00000000
00000000
00000000
00000000
BREG1B[B,H,W]
BREG1A[B,H,W]
BREG19[B,H,W]
BREG18[B,H,W]
00000000
00000000
00000000
00000000
BREG1F[B,H,W]
BREG1E[B,H,W]
BREG1D[B,H,W]
BREG1C[B,H,W]
00000000
00000000
00000000
00000000
BREG23[B,H,W]
BREG22[B,H,W]
BREG21[B,H,W]
BREG20[B,H,W]
00000000
00000000
00000000
00000000
BREG27[B,H,W]
BREG26[B,H,W]
BREG25[B,H,W]
BREG24[B,H,W]
00000000
00000000
00000000
00000000
BREG2B[B,H,W]
BREG2A[B,H,W]
BREG29[B,H,W]
BREG28[B,H,W]
00000000
00000000
00000000
00000000
BREG2F[B,H,W]
BREG2E[B,H,W]
BREG2D[B,H,W]
BREG2C[B,H,W]
00000000
00000000
00000000
00000000
BREG33[B,H,W]
BREG32[B,H,W]
BREG31[B,H,W]
BREG30[B,H,W]
00000000
00000000
00000000
00000000
211
A. Register Map
1. Register Map
P E R I P H E R A L
M A N U A L
Register
Base_Address
+ Address
0x234
0x238
0x23C
0x240
0x244
0x248
0x24C
0x250
0x254
0x258
0x25C
0x260
0x264
0x268
0x26C
0x270
0x274
0x278
0x27C
0x280-0xFFC
212
CONFIDENTIAL
+3
+2
+1
+0
BREG37[B,H,W]
BREG36[B,H,W]
BREG35[B,H,W]
BREG34[B,H,W]
00000000
00000000
00000000
00000000
BREG3B[B,H,W]
BREG3A[B,H,W]
BREG39[B,H,W]
BREG38[B,H,W]
00000000
00000000
00000000
00000000
BREG3F[B,H,W]
BREG3E[B,H,W]
BREG3D[B,H,W]
BREG3C[B,H,W]
00000000
00000000
00000000
00000000
BREG43[B,H,W]
BREG42[B,H,W]
BREG41[B,H,W]
BREG40[B,H,W]
00000000
00000000
00000000
00000000
BREG47[B,H,W]
BREG46[B,H,W]
BREG45[B,H,W]
BREG44[B,H,W]
00000000
00000000
00000000
00000000
BREG4B[B,H,W]
BREG4A[B,H,W]
BREG49[B,H,W]
BREG48[B,H,W]
00000000
00000000
00000000
00000000
BREG4F[B,H,W]
BREG4E[B,H,W]
BREG4D[B,H,W]
BREG4C[B,H,W]
00000000
00000000
00000000
00000000
BREG53[B,H,W]
BREG52[B,H,W]
BREG51[B,H,W]
BREG50[B,H,W]
00000000
00000000
00000000
00000000
BREG57[B,H,W]
BREG56[B,H,W]
BREG55[B,H,W]
BREG54[B,H,W]
00000000
00000000
00000000
00000000
BREG5B[B,H,W]
BREG5A[B,H,W]
BREG59[B,H,W]
BREG58[B,H,W]
00000000
00000000
00000000
00000000
BREG5F[B,H,W]
BREG5E[B,H,W]
BREG5D[B,H,W]
BREG5C[B,H,W]
00000000
00000000
00000000
00000000
BREG63[B,H,W]
BREG62[B,H,W]
BREG61[B,H,W]
BREG60[B,H,W]
00000000
00000000
00000000
00000000
BREG67[B,H,W]
BREG66[B,H,W]
BREG65[B,H,W]
BREG64[B,H,W]
00000000
00000000
00000000
00000000
BREG6B[B,H,W]
BREG6A[B,H,W]
BREG69[B,H,W]
BREG68[B,H,W]
00000000
00000000
00000000
00000000
BREG6F[B,H,W]
BREG6E[B,H,W]
BREG6D[B,H,W]
BREG6C[B,H,W]
00000000
00000000
00000000
00000000
BREG73[B,H,W]
BREG72[B,H,W]
BREG71[B,H,W]
BREG70[B,H,W]
00000000
00000000
00000000
00000000
BREG77[B,H,W]
BREG76[B,H,W]
BREG75[B,H,W]
BREG74[B,H,W]
00000000
00000000
00000000
00000000
BREG7B[B,H,W]
BREG7A[B,H,W]
BREG79[B,H,W]
BREG78[B,H,W]
00000000
00000000
00000000
00000000
BREG7F[B,H,W]
BREG7E[B,H,W]
BREG7D[B,H,W]
BREG7C[B,H,W]
00000000
00000000
00000000
00000000
-
-
-
-
FM4_MN709-00003-4v0-E, May 27, 2015
A. Register Map
1. Register Map
P E R I P H E R A L
1.28.3
M A N U A L
TYPE5-M4 product
RTC
Base_Address : 0x4003_B000
Register
Base_Address
+ Address
+3
WTCR2[B,H,W]
-------- -------- -----000 -------0
WTBR [B,H,W]
0x008
0x014
0x018
-------- 00000000 00000000 00000000
WTDR[B,H,W]
WTHR[B,H,W]
WTMIR[B,H,W]
WTSR[B,H,W]
--000000
--000000
-0000000
-0000000
WTYR[B,H,W]
WTMOR[B,H,W]
WTDW[B,H,W]
00000000
---00000
-----000
ALDR[B,H,W]
ALHR[B,H,W]
ALMIR[B,H,W]
--000000
--000000
-0000000
ALYR[B,H,W]
ALMOR[B,H,W]
00000000
---00000
-
-
0x024
CONFIDENTIAL
-
-------- ------00 00000000 00000000
-
-
0x028
-
-
0x02C-0x0FF
-
-
May 27, 2015, FM4_MN709-00003-4v0-E
-
WTTR [B,H,W]
0x01C
0x020
+0
00000000 00000000 ---00000 -00000-0
0x004
0x010
+1
WTCR1 [B,H,W]
0x000
0x00C
+2
WTCLKM[B,H,W]
WTCLKS[B,H,W]
------00
-------0
WTCALEN[B,H,W]
WTCAL[B,H,W]
-------0
-0000000
WTDIVEN[B,H,W]
WTDIV[B,H,W]
-------00
----0000
-
-
213
A. Register Map
1. Register Map
P E R I P H E R A L
M A N U A L
1.29 Low-speed CR Prescaler
Low-speed CR Prescaler
Base_Address : 0x4003_C000
Base_Address
+ Address
214
CONFIDENTIAL
Register
+3
+2
+1
0x000
-
-
-
0x004 – 0x0FC
-
-
-
+0
LCR_PRSLD[B,H,W],
--000000
-
FM4_MN709-00003-4v0-E, May 27, 2015
A. Register Map
1. Register Map
P E R I P H E R A L
M A N U A L
1.30 Peripheral Clock Gating
1.30.1 TYPE1-M1, TYPE2-M4 products
Peripheral Clock Gating
Base_Address : 0x4003_C100
Register
Base_Address
+ Address
+3
+2
---1-1-1 ----1111 11111111 11111111
MRST0[B,H,W]
0x004
-----0-0 ----0000 00000000 00000000
-
-
-
-
CKEN1[B,H,W]
0x010
-------- ----1111 ----1111 ----1111
MRST1[B,H,W]
0x014
0x018 – 0x01F
+0
CKEN0[B,H,W]
0x000
0x008 – 0x00F
+1
-------- ----0000 ----0000 ----0000
-
-
-
-
CKEN2[B,H,W]
-------- -------- -------0 --**--00
0x020
Products with CAN : *="1"
Products without CAN : *="0"
MRST2[B,H,W]
0x024
0x028 – 0x67C
1.30.2
-------- -------- -------0 --00--00
-
-
-
-
TYPE3-M4, TYPE4-M4 products
Peripheral Clock Gating
Base_Address : 0x4003_C100
Register
Base_Address
+ Address
+3
+0
---1-1-1 ----1111 11111111 11111111
MRST0[B,H,W]
0x004
-----0-0 ----0000 00000000 00000000
-
-
-
-
CKEN1[B,H,W]
0x010
-------- ----1111 ----1111 ----1111
MRST1[B,H,W]
0x014
0x018 – 0x01F
+1
CKEN0[B,H,W]
0x000
0x008 – 0x00F
+2
-------- ----0000 ----0000 ----0000
-
-
-
-
CKEN2[B,H,W]
---0--11 ---1--00 -------0 -***--00
0x020
Products with : *="1"
Products without CAN : *="0"
MRST2[B,H,W]
0x024
0x028 – 0x67C
May 27, 2015, FM4_MN709-00003-4v0-E
CONFIDENTIAL
---0--00 ---0--00 -------0 -000--00
-
-
-
-
215
A. Register Map
1. Register Map
P E R I P H E R A L
1.30.3
M A N U A L
TYPE5-M4, TYPE6-M4 products
Peripheral Clock Gating
Base_Address : 0x4003_C100
Register
Base_Address
+ Address
+3
+0
---1-1-1 ----1111 11111111 11111111
MRST0[B,H,W]
0x004
-----0-0 ----0000 00000000 00000000
-
-
-
-
CKEN1[B,H,W]
0x010
-------- ----1111 ----1111 ----1111
MRST1[B,H,W]
0x014
0x018 – 0x01F
+1
CKEN0[B,H,W]
0x000
0x008 – 0x00F
+2
-------- ----0000 ----0000 ----0000
-
-
-
-
CKEN2[B,H,W]
---0--11 ---1--00 1111---0 -***--00
0x020
Products with : *="1"
Products without CAN : *="0"
MRST2[B,H,W]
0x024
0x028 – 0x67C
216
CONFIDENTIAL
---0--00 ---0--00 0000---0 -000--00
-
-
-
-
FM4_MN709-00003-4v0-E, May 27, 2015
A. Register Map
1. Register Map
P E R I P H E R A L
M A N U A L
1.31 Smart Card Interface
IC-Card Interface ch.0
Base_Address : 0x4003_C900
IC-Card Interface ch.1
Base_Address : 0x4003_C980
Register
Base_Address
+ Address
+3
+2
0x00
-
-
0x04
-
-
0x08
-
-
0x0C
-
-
0x10
-
-
0x14
-
-
0x18
-
-
0x1C
-
-
0x20
-
-
0x24
-
-
0x28
-
-
0x2C
-
-
0x30
-
-
0x34
-
0x38
-
-
0x3C
-
-
0x40
-
-
0x44- 0x7C
-
-
May 27, 2015, FM4_MN709-00003-4v0-E
CONFIDENTIAL
-
+1
+0
GLOBALCONTROL1[H,W]
-0001000 00000000
STATUS[H,W]
--000000 00000001
PORTCONTROL[H,W]
0000--00 00-0-0-0
DATA[H,W]
-------0 00000000
CARDCLOCK [H,W]
00000000 00101000
BAUDRATE[H,W]
0000001 01110100
GUARDTIMER[H,W]
-------- 00000000
IDLETIMER[H,W]
00000000 00000000
GLOBALCONTROL2[H,W]
-------- ----1-00
DATA_FIFO[H,W]
-------0 00000000
FIFO_LEVEL_READ[H,W]
00000000 00000000
FIFO_LEVEL_WRITE[H,W]
00000000 00000000
FIFO_MODE[H,W]
00000000 ----0000
FIFO_CLEAR_MSB_WRITE[H,W]
-------- -------0
FIFO_CLEAR_MSB_ READ[H,W]
-------- -------0
-
IRQ_STATUS[H,W]
-------- 00000000
-
-
217
A. Register Map
1. Register Map
P E R I P H E R A L
M A N U A L
1.32 MFSI2S
MFSI2S ch.A
Base_Address : 0x4003_CA00
Register
Base_Address
+ Address
+3
+2
0x00
-
-
0x04
-
-
0x08
-
-
0x0C- 0xFC
-
-
+1
+0
CNTLREG[B, H,W]
-----0-0 -0000-01
I2SCLK[B, H,W]
00------ 00000000
I2SST[B,H,W]
I2SRST[B,H,W]
------00
00000000
-
-
Note:
−
218
CONFIDENTIAL
In TYPE5-M4 product, MFSI2S ch.A applies to MFS ch.1.
FM4_MN709-00003-4v0-E, May 27, 2015
A. Register Map
1. Register Map
P E R I P H E R A L
M A N U A L
1.33 I2S Prescaler
1.33.1 TYPE1-M4, TYPE2-M4, TYPE3-M4 products
I2S_Prescaler
Base_Address : 0x4003_D000
Register
Base_Address
+ Address
+3
IPCR1[B,H,W]
-------- -------- -------- -------0
IPCR2[B,H,W]
0x008
-------- -------- -------- -----000
IPCR3[B,H,W]
0x00C
-------- -------- -------- ---00001
IPCR4[B,H,W]
0x010
-------- -------- -------- -0011111
IP_STR[B,H,W]
0x014
-------- -------- -------- -------0
IPINT_ENR[B,H,W]
0x018
-------- -------- -------- -------0
IPINT_CLR[B,H,W]
0x01C
-------- -------- -------- -------0
IPINT_STR[B,H,W]
0x020
-------- -------- -------- -------0
IPCR5[B,H,W]
0x024
CONFIDENTIAL
+0
-------- -------- -------- ------00
0x004
May 27, 2015, FM4_MN709-00003-4v0-E
+1
ICCR[B,H,W]
0x000
0x028 – 0xFFC
+2
-------- -------- -------- -0011000
-
-
-
-
219
A. Register Map
1. Register Map
P E R I P H E R A L
1.33.2
TYPE4-M4 product
I2S_Prescaler
Base_Address : 0x4003_D000
Register
Base_Address
+ Address
+3
-------- -------- -------- -------0
IPCR2[B,H,W]
-------- -------- -------- -----000
IPCR3[B,H,W]
0x00C
-------- -------- -------- ---00001
IPCR4[B,H,W]
0x010
-------- -------- -------- -0011111
IP_STR[B,H,W]
0x014
-------- -------- -------- -------0
IPINT_ENR[B,H,W]
0x018
-------- -------- -------- -------0
IPINT_CLR[B,H,W]
0x01C
-------- -------- -------- -------0
IPINT_STR[B,H,W]
0x020
-------- -------- -------- -------0
IPCR5[B,H,W]
0x024
-------- -------- -------- -0011000
-
-
-
-
ICCR_1[B,H,W]
0x030
-------- -------- -------- -----000
IPCR5_1[B,H,W]
0x034
CONFIDENTIAL
+0
IPCR1[B,H,W]
0x008
0x038 – 0xFFC
+1
-------- -------- -------- ------00
0x004
0x028 – 0x02C
+2
ICCR[B,H,W]
0x000
220
M A N U A L
-------- -------- -------- -0000000
-
-
-
-
FM4_MN709-00003-4v0-E, May 27, 2015
A. Register Map
1. Register Map
P E R I P H E R A L
M A N U A L
1.34 GDC_Prescaler
GDC_Prescaler
Base_Address : 0x4003_D100
Register
Base_Address
+ Address
+3
+2
0x000
GPCR1[B,H,W]
-------- -------- -------- ------00
GPCR2[B,H,W]
0x008
-------- -------- -------- -----000
GPCR3 [B,H,W]
0x00C
-------- -------- -------- ---00000
GPCR4 [B,H,W]
0x010
-------- -------- -------- -0000000
GP_STR[B,H,W]
0x014
-------- -------- -------- -------0
GPINT_ENR[B,H,W]
0x018
-------- -------- -------- -------0
GPINT_CLR[B,H,W]
0x01C
-------- -------- -------- -------0
GPINT_STR[B,H,W]
0x020
-------- -------- -------- -------0
-
-
-
-
GCSR[B,H,W]
0x028
-------- -------- ---0---0 ---0--00
GRCR[B,H,W]
0x02C
-------- -------- -------- -------0
GMCR[B,H,W]
0x030
0x034- 0xFFC
+0
-------- -------- -------- -------0
0x004
0x024
+1
GCCR[B,H,W]
-------- -------- -------- -------0
-
-
-
-
Note:
−
For the register details of GDC, refer to the Chapter:GDC.
May 27, 2015, FM4_MN709-00003-4v0-E
CONFIDENTIAL
221
A. Register Map
1. Register Map
P E R I P H E R A L
M A N U A L
1.35 EXT-Bus I/F
1.35.1 TYPE1-M4 product
EXT-Bus I/F
Base_Address : 0x4003_F000
Register
Base_Address
+ Address
0x0000
0x0004
0x0008
0x000C
0x0010
0x0014
0x0018
0x001C
0x0020
0x0024
0x0028
0x002C
0x0030
0x0034
0x0038
0x003C
222
CONFIDENTIAL
+3
+2
+1
+0
MODE0[W]
-------- -------- --000-00 00000000
MODE1[W]
-------- -------- --000-00 00000000
MODE2[W]
-------- -------- --000-00 00000000
MODE3[W]
-------- -------- --000-00 00000000
MODE4[W]
-------- -------- --000-00 00000001
MODE5[W]
-------- -------- --000-00 00000000
MODE6[W]
-------- -------- --000-00 00000000
MODE7[W]
-------- -------- --000-00 00000000
TIM0[W]
00000101 01011111 11110000 00001111
TIM1[W]
00000101 01011111 11110000 00001111
TIM2[W]
00000101 01011111 11110000 00001111
TIM3[W]
00000101 01011111 11110000 00001111
TIM4[W]
00000101 01011111 11110000 00001111
TIM5[W]
00000101 01011111 11110000 00001111
TIM6[W]
00000101 01011111 11110000 00001111
TIM7[W]
00000101 01011111 11110000 00001111
FM4_MN709-00003-4v0-E, May 27, 2015
A. Register Map
1. Register Map
P E R I P H E R A L
M A N U A L
Register
Base_Address
+ Address
+3
AREA1[W]
-------- -0001111 -------- 00010000
AREA2[W]
0x0048
-------- -0001111 -------- 00100000
AREA3[W]
0x004C
-------- -0001111 -------- 00110000
AREA4[W]
0x0050
-------- -0001111 -------- 01000000
AREA5[W]
0x0054
-------- -0001111 -------- 01010000
AREA6[W]
0x0058
-------- -0001111 -------- 01100000
AREA7[W]
0x005C
-------- -0001111 -------- 01110000
ATIM0[W]
0x0060
-------- -------- ----0100 01011111
ATIM1[W]
0x0064
-------- -------- ----0100 01011111
ATIM2[W]
0x0068
-------- -------- ----0100 01011111
ATIM3[W]
0x006C
-------- -------- ----0100 01011111
ATIM4[W]
0x0070
-------- -------- ----0100 01011111
ATIM5[W]
0x0074
-------- -------- ----0100 01011111
ATIM6[W]
0x0078
-------- -------- ----0100 01011111
ATIM7[W]
0x007C
-------- -------- ----0100 01011111
-
-------0 00000000 0000000000110011
PWRDWN[W]
-------- -------- 00000000 00000000
SDTIM[W]
0x010C
------00 01000010 00010001 0100--01
SDCMD[W]
0x0110
CONFIDENTIAL
-
REFTIM[W]
0x0108
May 27, 2015, FM4_MN709-00003-4v0-E
-
-------- -------0 00010011 --00-000
0x0104
0x01FC
SDMODE[W]
0x0100
0x0114 -
+0
-------- -0001111 -------- 00000000
0x0044
0x00FC
+1
AREA0[W]
0x0040
0x0080 -
+2
0------- ---00000 00000000 00000000
-
-
-
-
223
A. Register Map
1. Register Map
P E R I P H E R A L
Register
Base_Address
+ Address
+3
0x02FC
-
0x0FFC
224
CONFIDENTIAL
-
EST
WEAD
00000000 00000000 000000000 00000000
ESCLR[W]
-------- -------- -------- -------1
AMODE[W]
0x0310
0x0F18 –
-
-------- -------- -------- -------0
0x030C
0x0F14
-
-------- -------- -------- ---01111
0x0308
0x0F00 –
+0
DCLKR[W]
0x0304
0x0EFC
+1
-------- -------- -------- ----0000
0x0300
0x031C -
+2
MEMCERR[W]
0x0200
0x0204 –
M A N U A L
-------- -------- -------- -------1
-
-
-
-
*
*
*
*
-
-
-
-
FM4_MN709-00003-4v0-E, May 27, 2015
A. Register Map
1. Register Map
P E R I P H E R A L
1.35.2
M A N U A L
TYPE3-M4, TYPE4-M4, TYPE5-M4, TYPE6-M4 products
EXT-Bus I/F
Base_Address : 0x4003_F000
Register
Base_Address
+ Address
0x0000
0x0004
0x0008
0x000C
0x0010
0x0014
0x0018
0x001C
0x0020
0x0024
0x0028
0x002C
0x0030
0x0034
0x0038
0x003C
May 27, 2015, FM4_MN709-00003-4v0-E
CONFIDENTIAL
+3
+2
+1
+0
MODE0[W]
-------- -------- --000-00 00000000
MODE1[W]
-------- -------- --000-00 00000000
MODE2[W]
-------- -------- --000-00 00000000
MODE3[W]
-------- -------- --000-00 00000000
MODE4[W]
-------- -------- --000-00 00000001
MODE5[W]
-------- -------- --000-00 00000000
MODE6[W]
-------- -------- --000-00 00000000
MODE7[W]
-------- -------- --000-00 00000000
TIM0[W]
00000101 01011111 11110000 00001111
TIM1[W]
00000101 01011111 11110000 00001111
TIM2[W]
00000101 01011111 11110000 00001111
TIM3[W]
00000101 01011111 11110000 00001111
TIM4[W]
00000101 01011111 11110000 00001111
TIM5[W]
00000101 01011111 11110000 00001111
TIM6[W]
00000101 01011111 11110000 00001111
TIM7[W]
00000101 01011111 11110000 00001111
225
A. Register Map
1. Register Map
P E R I P H E R A L
Register
Base_Address
+ Address
+3
AREA1[W]
AREA2[W]
-------- -0001111 -------- 00100000
AREA3[W]
0x004C
-------- -0001111 -------- 00110000
AREA4[W]
0x0050
-------- -0001111 -------- 01000000
AREA5[W]
0x0054
-------- -0001111 -------- 01010000
AREA6[W]
0x0058
-------- -0001111 -------- 01100000
AREA7[W]
0x005C
-------- -0001111 -------- 01110000
ATIM0[W]
0x0060
-------- -------- ----0100 01011111
ATIM1[W]
0x0064
-------- -------- ----0100 01011111
ATIM2[W]
0x0068
-------- -------- ----0100 01011111
ATIM3[W]
0x006C
-------- -------- ----0100 01011111
ATIM4[W]
0x0070
-------- -------- ----0100 01011111
ATIM5[W]
0x0074
-------- -------- ----0100 01011111
ATIM6[W]
0x0078
-------- -------- ----0100 01011111
ATIM7[W]
0x007C
-------- -------- ----0100 01011111
-
-
REFTIM[W]
-------0 00000000 0000000000110011
PWRDWN[W]
0x0108
-------- -------- 00000000 00000000
SDTIM[W]
0x010C
0-----00 01000010 00010001 0100--01
SDCMD[W]
0x0110
CONFIDENTIAL
-
-------- -------0 00010011 --00-000
0x0104
226
SDMODE[W]
0x0100
0x01FC
+0
-------- -0001111 -------- 00010000
0x0048
0x0114 -
+1
-------- -0001111 -------- 00000000
0x0044
0x00FC
+2
AREA0[W]
0x0040
0x0080 -
M A N U A L
0------- ---00000 00000000 00000000
-
-
-
-
FM4_MN709-00003-4v0-E, May 27, 2015
A. Register Map
1. Register Map
P E R I P H E R A L
M A N U A L
Register
Base_Address
+ Address
+3
0x02FC
-
EST
WEAD
00000000 00000000 000000000 00000000
ESCLR[W]
-------- -------- -------- -------1
AMODE[W]
0x0310
0x0F18 –
0x0FFC
May 27, 2015, FM4_MN709-00003-4v0-E
CONFIDENTIAL
-
-------- -------- -------- -------0
0x030C
0x0F14
-
-------- -------- -------- ---01111
0x0308
0x0F00 –
DCLKR[W]
0x0304
0x0EFC
+0
-------- -------- -------- ----0000
0x0300
0x031C -
+1
MEMCERR[W]
0x0200
0x0204 –
+2
-------- -------- -------- -------1
-
-
-
-
*
*
*
*
-
-
-
-
227
A. Register Map
1. Register Map
P E R I P H E R A L
M A N U A L
1.36 USB
USB ch.0 Base_Address : 0x4004_0000
USB ch.1 Base_Address : 0x4005_0000
Register
Base_Address
+ Address
+3
+2
0x2100
-
-
0x2104
-
-
0x2108
-
-
0x210C
-
-
0x2110
0x2114
228
CONFIDENTIAL
-
-
+1
+0
HCNT1[B,H,W]
HCNT0[B,H,W]
-----001
00000000
HERR[B,H,W]
HIRQ[B,H,W]
00000011
0-000000
HFCOMP[B,H,W]
HSTATE[B,H,W]
00000000
--010010
HRTIMER(1/0)[B,H,W]
00000000 00000000
HADR[B,H,W]
HRTIMER(2)[B,H,W]
-0000000
------00
HEOF(1/0)[B,H,W]
-
0x2118
-
-
0x211C
-
-
0x2120
-
-
0x2124
-
-
0x2128
-
-
0x212C
-
-
0x2130
-
-
0x2134
-
-
0x2138
-
-
0x213C
-
-
0x2140
-
-
0x2144
-
-
0x2148
-
-
0x214C
-
-
--000000 00000000
HFRAME(1/0)[B,H,W]
-----000 00000000
HTOKEN[B,H,W]
-
00000000
UDCC[B,H,W]
-------- 10100-00
EP0C[H,W]
------0- -1000000
EP1C[H,W]
01100001 00000000
EP2C[H,W]
0110000- -1000000
EP3C[H,W]
0110000- -1000000
EP4C[H,W]
0110000- -1000000
EP5C[H,W]
0110000- -1000000
TMSP[H,W]
-----000 00000000
UDCIE[B,H,W]
UDCS[B,H,W]
--000000
--000000
EP0IS[H,W]
10---1-- -------EP0OS[H,W]
100--00- -XXXXXXX
EP1S[H,W]
100-000X XXXXXXXX
FM4_MN709-00003-4v0-E, May 27, 2015
A. Register Map
1. Register Map
P E R I P H E R A L
M A N U A L
Register
Base_Address
+ Address
+3
+2
0x2150
-
-
0x2154
-
-
0x2158
-
-
0x215C
-
-
0x2160
-
0x2164
-
-
0x2168
-
-
0x216C
-
-
0x2170
-
-
0x2174
-
-
-
-
0x2178 0x217C
May 27, 2015, FM4_MN709-00003-4v0-E
CONFIDENTIAL
-
+1
+0
EP2S[H,W]
100-000- -XXXXXXX
EP3S[H,W]
100-000- -XXXXXXX
EP4S[H,W]
100-000- -XXXXXXX
EP5S[H,W]
100-000- -XXXXXXX
EP0DTH[B,H,W]
EP0DTL[B,H,W]
XXXXXXXX
XXXXXXXX
EP1DTH[B,H,W]
EP1DTL[B,H,W]
XXXXXXXX
XXXXXXXX
EP2DTH[B,H,W]
EP2DTL[B,H,W]
XXXXXXXX
XXXXXXXX
EP3DTH[B,H,W]
EP3DTL[B,H,W]
XXXXXXXX
XXXXXXXX
EP4DTH[B,H,W]
EP4DTL[B,H,W]
XXXXXXXX
XXXXXXXX
EP5DTH[B,H,W]
EP5DTL[B,H,W]
XXXXXXXX
XXXXXXXX
-
-
229
A. Register Map
1. Register Map
P E R I P H E R A L
M A N U A L
1.37 DMAC
DMAC
Base_Address : 0x4006_0000
Base_Address
+ Address
0x0000
0x0010
0x0014
0x0018
0x001C
0x0020
0x0024
0x0028
0x002C
0x0030
0x0034
0x0038
0x003C
0x0040
0x0044
0x0048
0x004C
0x0050
0x0054
0x0058
0x005C
0x0060
230
CONFIDENTIAL
Register
+3
+2
+1
+0
DMACR[B,H,W]
00-00000 -------- -------- -------DMACA0[B,H,W]
00000000 0---0000 00000000 00000000
DMACB0[B,H,W]
--000000 00000000 00000000 -------0
DMACSA0[B,H,W]
00000000 00000000 00000000 00000000
DMACDA0[B,H,W]
00000000 00000000 00000000 00000000
DMACA1[B,H,W]
00000000 0---0000 00000000 00000000
DMACB1[B,H,W]
--000000 00000000 00000000 -------0
DMACSA1[B,H,W]
00000000 00000000 00000000 00000000
DMACDA1[B,H,W]
00000000 00000000 00000000 00000000
DMACA2[B,H,W]
00000000 0---0000 00000000 00000000
DMACB2[B,H,W]
--000000 00000000 00000000 -------0
DMACSA2[B,H,W]
00000000 00000000 00000000 00000000
DMACDA2[B,H,W]
00000000 00000000 00000000 00000000
DMACA3[B,H,W]
00000000 0---0000 00000000 00000000
DMACB3[B,H,W]
--000000 00000000 00000000 -------0
DMACSA3[B,H,W]
00000000 00000000 00000000 00000000
DMACDA3[B,H,W]
00000000 00000000 00000000 00000000
DMACA4[B,H,W]
00000000 0---0000 00000000 00000000
DMACB4[B,H,W]
--000000 00000000 00000000 -------0
DMACSA4[B,H,W]
00000000 00000000 00000000 00000000
DMACDA4[B,H,W]
00000000 00000000 00000000 00000000
DMACA5[B,H,W]
00000000 0---0000 00000000 00000000
FM4_MN709-00003-4v0-E, May 27, 2015
A. Register Map
1. Register Map
P E R I P H E R A L
M A N U A L
Register
Base_Address
+ Address
+3
DMACSA5[B,H,W]
00000000 00000000 00000000 00000000
DMACDA5[B,H,W]
0x006C
00000000 00000000 00000000 00000000
DMACA6[B,H,W]
0x0070
00000000 0---0000 00000000 00000000
DMACB6[B,H,W]
0x0074
--000000 00000000 00000000 -------0
DMACSA6[B,H,W]
0x0078
00000000 00000000 00000000 00000000
DMACDA6[B,H,W]
0x007C
00000000 00000000 00000000 00000000
DMACA7[B,H,W]
0x0080
00000000 0---0000 00000000 00000000
DMACB7[B,H,W]
0x0084
--000000 00000000 00000000 -------0
DMACSA7[B,H,W]
0x0088
00000000 00000000 00000000 00000000
DMACDA7[B,H,W]
0x008C
May 27, 2015, FM4_MN709-00003-4v0-E
CONFIDENTIAL
+0
--000000 00000000 00000000 -------0
0x0068
0x00FC
+1
DMACB5[B,H,W]
0x0064
0x0090 -
+2
00000000 00000000 00000000 00000000
-
-
-
-
231
A. Register Map
1. Register Map
P E R I P H E R A L
M A N U A L
1.38 DSTC
DSTC
Base_Address : 0x4006_1000
Base_Address
+ Address
Register
+3
+2
0x0000
0x0004
0x0008
0x000C
0x0010
0x0014
0x0018
0x001C
0x0020
0x0024
0x0028
0x002C
0x0030
0x0034
0x0038
0x003C
0x0040
0x0044
0x0048
0x004C
0x0050
0x0054
232
CONFIDENTIAL
+1
+0
DESTP[B,H,W]
00000000 00000000 00000000 00000000
HWDESP[B,H,W]
00XXXXXX XXXXXX00 00000000 00000000
SWTR[H]
CFG[B]
CMD[B]
00000000 00000000
01000000
00000001
MONERS[B,H,W]
00XXXXXX XXXXXX00 XXXXXXXX XXX00000
DREQENB[31:0] [B,H,W]
00000000 00000000 00000000 00000000
DREQENB[63:32] [B,H,W]
00000000 00000000 00000000 00000000
DREQENB[95:64] [B,H,W]
00000000 00000000 00000000 00000000
DREQENB[127:96] [B,H,W]
00000000 00000000 00000000 00000000
DREQENB[159:128] [B,H,W]
00000000 00000000 00000000 00000000
DREQENB[191:160] [B,H,W]
00000000 00000000 00000000 00000000
DREQENB[223:192] [B,H,W]
00000000 00000000 00000000 00000000
DREQENB[255:224] [B,H,W]
00000000 00000000 00000000 00000000
HWINT[31:0] [B,H,W]
00000000 00000000 00000000 00000000
HWINT[63:32] [B,H,W]
00000000 00000000 00000000 00000000
HWINT[95:64] [B,H,W]
00000000 00000000 00000000 00000000
HWINT[127:96] [B,H,W]
00000000 00000000 00000000 00000000
HWINT[159:128] [B,H,W]
00000000 00000000 00000000 00000000
HWINT[191:160] [B,H,W]
00000000 00000000 00000000 00000000
HWINT[223:192] [B,H,W]
00000000 00000000 00000000 00000000
HWINT[255:224] [B,H,W]
00000000 00000000 00000000 00000000
HWINTCLR[31:0] [B,H,W]
00000000 00000000 00000000 00000000
HWINTCLR[63:32] [B,H,W]
00000000 00000000 00000000 00000000
FM4_MN709-00003-4v0-E, May 27, 2015
A. Register Map
1. Register Map
P E R I P H E R A L
M A N U A L
Base_Address
+ Address
Register
+3
HWINTCLR[127:96] [B,H,W]
00000000 00000000 00000000 00000000
HWINTCLR[159:128] [B,H,W]
0x060
00000000 00000000 00000000 00000000
HWINTCLR[191:160] [B,H,W]
0x064
00000000 00000000 00000000 00000000
HWINTCLR[223:192] [B,H,W]
0x068
00000000 00000000 00000000 00000000
HWINTCLR[255:224] [B,H,W]
0x06C
00000000 00000000 00000000 00000000
DQMSK[31:0] [B,H,W]
0x070
00000000 00000000 00000000 00000000
DQMSK[63:32] [B,H,W]
0x074
00000000 00000000 00000000 00000000
DQMSK[95:64] [B,H,W]
0x078
00000000 00000000 00000000 00000000
DQMSK[127:96] [B,H,W]
0x07C
00000000 00000000 00000000 00000000
DQMSK[159:128] [B,H,W]
0x080
00000000 00000000 00000000 00000000
DQMSK[191:160] [B,H,W]
0x084
00000000 00000000 00000000 00000000
DQMSK[223:192] [B,H,W]
0x088
00000000 00000000 00000000 00000000
DQMSK[255:224] [B,H,W]
0x08C
00000000 00000000 00000000 00000000
DQMSKCLR[31:0] [B,H,W]
0x090
00000000 00000000 00000000 00000000
DQMSKCLR[63:32] [B,H,W]
0x094
00000000 00000000 00000000 00000000
DQMSKCLR[95:64] [B,H,W]
0x098
00000000 00000000 00000000 00000000
DQMSKCLR[127:96] [B,H,W]
0x09C
00000000 00000000 00000000 00000000
DQMSKCLR[159:128] [B,H,W]
0x0A0
00000000 00000000 00000000 00000000
DQMSKCLR[191:160] [B,H,W]
0x0A4
00000000 00000000 00000000 00000000
DQMSKCLR[223:192] [B,H,W]
0x0A8
00000000 00000000 00000000 00000000
DQMSKCLR[255:224] [B,H,W]
0x0AC
May 27, 2015, FM4_MN709-00003-4v0-E
CONFIDENTIAL
+0
00000000 00000000 00000000 00000000
0x005C
0x0FFC
+1
HWINTCLR[95:64] [B,H,W]
0x0058
0x00B0 -
+2
00000000 00000000 00000000 00000000
-
-
-
-
233
A. Register Map
1. Register Map
P E R I P H E R A L
M A N U A L
1.39 CAN
CAN ch.0 Base_Address : 0x4006_2000
CAN ch.1 Base_Address : 0x4006_3000
Register
Base_Address
+ Address
+3
0x0000
0x0004
0x0008
0x000C
0x0014
0x0018
0x0024
0x0028 0x002F
0x0034
0x0038 0x003C
0x0044
0x0048
0x0054
0x005C
234
CONFIDENTIAL
ERRCNT[B,H,W]
00000000 00000000
TESTR[B,H,W]
INTR[B,H,W]
-------- X00000--
00000000 00000000
-
BRPER[B,H,W]
-
-------- ----0000
IF1CMSK[B,H,W]
IF1CREQ[B,H,W]
-------- 00000000
0------- 00000001
IF1MSK2[B,H,W]
IF1MSK1[B,H,W]
11-11111 11111111
11111111 11111111
IF1ARB2[B,H,W]
IF1ARB1[B,H,W]
00000000 00000000
00000000 00000000
IF1MCTR[B,H,W]
-
00000000 0---0000
IF1DTA2[B,H,W]
IF1DTA1[B,H,W]
00000000 00000000
00000000 00000000
IF1DTB2[B,H,W]
IF1DTB1[B,H,W]
00000000 00000000
00000000 00000000
-
-
-
IF1DTA1[B,H,W]
IF1DTA2[B,H,W]
00000000 00000000
00000000 00000000
IF1DTB1[B,H,W]
IF1DTB2[B,H,W]
00000000 00000000
00000000 00000000
-
-
-
IF2CMSK[B,H,W]
IF2CREQ[B,H,W]
-------- 00000000
0------- 00000001
IF2MSK2[B,H,W]
IF2MSK1[B,H,W]
11-11111 11111111
11111111 11111111
IF2ARB2[B,H,W]
IF2ARB1[B,H,W]
00000000 00000000
00000000 00000000
-
0x0050
0x0058 -
BTR[B,H,W]
-0100011 00000001
-
0x0040
0x004C
CTRLR[B,H,W]
-------- 000-0001
-
0x0030
+0
STATR[B,H,W]
-
0x0020
+1
-------- 00000000
-
0x0010
0x001C
+2
IF2MCTR[B,H,W]
-
00000000 0---0000
IF2DTA2[B,H,W]
IF2DTA1[B,H,W]
00000000 00000000
00000000 00000000
IF2DTB2[B,H,W]
IF2DTB1[B,H,W]
00000000 00000000
00000000 00000000
-
-
-
FM4_MN709-00003-4v0-E, May 27, 2015
A. Register Map
1. Register Map
P E R I P H E R A L
M A N U A L
Register
Base_Address
+ Address
+3
0x0060
0x0064
0x0068 0x007C
0x008F
0x0094 0x009F
0x00A4 0x00AF
0x0FFC
May 27, 2015, FM4_MN709-00003-4v0-E
CONFIDENTIAL
IF2DTB1[B,H,W]
IF2DTB2[B,H,W]
00000000 00000000
00000000 00000000
-
-
-
-
TREQR2[B,H,W]
TREQR1[B,H,W]
00000000 00000000
00000000 00000000
-
-
-
NEWDT2[B,H,W]
NEWDT1[B,H,W]
00000000 00000000
00000000 00000000
-
-
-
INTPND2[B,H,W]
INTPND1[B,H,W]
00000000 00000000
00000000 00000000
-
0x00B0
0x00B4 -
IF2DTA2[B,H,W]
00000000 00000000
-
0x00A0
+0
IF2DTA1[B,H,W]
-
0x0090
+1
00000000 00000000
-
0x0080
0x0084 -
+2
-
-
-
MSGVAL2[B,H,W]
MSGVAL1[B,H,W]
00000000 00000000
00000000 00000000
-
-
-
235
A. Register Map
1. Register Map
P E R I P H E R A L
M A N U A L
1.40 Ethernet-MAC
Ethernet-MAC
Base_Address : 0x4006_4000
Register
Base_Address
+ Address
0x0000 –
0x1FFC
+3
+2
+1
+0
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
Note:
−
For the register details of Ethernet-MAC block, refer to the "Ethernet part".
1.41 Ethernet-Control
Ethernet-Control
Base_Address : 0x4006_6000
Register
Base_Address
+ Address
+3
+2
+1
+0
0x000 - 0xFFC
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
Note:
−
236
CONFIDENTIAL
For the register details of Ethernet-Control block, refer to the Ethernet part.
FM4_MN709-00003-4v0-E, May 27, 2015
A. Register Map
1. Register Map
P E R I P H E R A L
M A N U A L
1.42 I2S
I2S ch.0
Base_Address : 0x4006_C000
I2S ch.1
Base_Address : 0x4006_C800
Register
Base_Address
+ Address
+3
+1
+0
RXFDAT[B,H,W]
0x000
00000000 00000000 00000000 00000000
TXFDAT[B,H,W]
0x004
00000000 00000000 00000000 00000000
CNTREG[B,H,W]
0x008
00000000 00000000 00000000 00000000
MCR0REG[B,H,W]
0x00C
-0000000 00000000 -0000000 00000000
MCR1REG[B,H,W]
0x010
00000000 00000000 00000000 00000000
MCR2REG[B,H,W]
0x014
00000000 00000000 00000000 00000000
OPRREG[B,H,W]
0x018
-------0 -------0 -------- -------0
SRST[B,H,W]
0x01C
-------- -------- -------- -------0
INTCNT[B,H,W]
0x020
-1111111 --111111 ----0000 --000000
STATUS[B,H,W]
0x024
00000000 ----0000 00000000 00000000
DMAACT[B,H,W]
0x028
-------0 -------0 -------0 -------0
TSTREG[B,H,W]
0x02C
0x030 - 0xFFC
+2
-------- -------- -------- -------0
-
-
-
-
1.43 SD-Card
SD-Card
Base_Address : 0x4006_E000
Base_Address
Register
+ Address
+3
+2
+1
+0
0x000 – 0xFFC
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
Note:
−
For the register details of SD-Card block, refer to the Chapter SD Card Interface.
May 27, 2015, FM4_MN709-00003-4v0-E
CONFIDENTIAL
237
A. Register Map
1. Register Map
P E R I P H E R A L
M A N U A L
1.44 CAN FD
CAN FD
Base_Address : 0x4007_0000
Register
Base_Address
+ Address
+3
ENDN[B,H,W]
10000111 01100101 01000011 00100001
-
-------- -------- --000000 X000---RWD[B,H,W]
-------- -------- 00000000 00000000
CCCR[B,H,W]
0x018
-------- -------- -0000000 00000001
BTP[B,H,W]
0x01C
------00 00000000 --001010 00110011
TSCC[B,H,W]
0x020
-------- ----0000 -------- ------00
TSCV[B,H,W]
0x024
-------- -------- 00000000 00000000
TOCC[B,H,W]
0x028
11111111 11111111 -------- -----000
TOCV[B,H,W]
0x02C
-------- -------- 11111111 11111111
-
-
-
-
ECR[B,H,W]
0x040
-------- 00000000 00000000 00000000
PSR[B,H,W]
0x044
-------- -------- --000111 00000111
-
-
-
-
IR[B,H,W]
0x050
00000000 00000000 00000000 00000000
IE[B,H,W]
0x054
00000000 00000000 00000000 00000000
ILS[B,H,W]
0x058
00000000 00000000 00000000 00000000
ILE[B,H,W]
0x05C
CONFIDENTIAL
-
TEST[B,H,W]
0x014
238
-
---00000 0--00000 ----1010 -011--11
0x010
0x060 - 0x07C
FBTP[B,H,W]
0x00C
0x048 - 0x04C
+0
00110000 00010011 00000101 0000110
0x004
0x030 - 0x03C
+1
CREL[B,H,W]
0x000
0x008
+2
-------- -------- -------- ------00
-
-
-
-
FM4_MN709-00003-4v0-E, May 27, 2015
A. Register Map
1. Register Map
P E R I P H E R A L
M A N U A L
Register
Base_Address
+ Address
+3
SIDFC[B,H,W]
-------- 00000000 00000000 000000-XIDFC[B,H,W]
0x088
0x094
0x098
0x09C
0x0A0
0x0A4
0x0A8
0x0AC
0x0B0
0x0B4
0x0B8
0x0BC
0x0C0
0x0C4
0x0C8
0x0CC
0x0D0
0x0D4
0x0D8
0x0DC
May 27, 2015, FM4_MN709-00003-4v0-E
CONFIDENTIAL
+0
-------- -------- -------- --000000
0x084
0x090
+1
GFC[B,H,W]
0x080
0x08C
+2
-------- -0000000 00000000 000000--
-
-
-
XIDAM[B,H,W]
---11111 11111111 11111111 11111111
HPMS[B,H,W]
-------- -------- 00000000 00000000
NDAT1[B,H,W]
00000000 00000000 00000000 00000000
NDAT2[B,H,W]
00000000 00000000 00000000 00000000
RXF0C[B,H,W]
00000000 -0000000 00000000 000000-RXF0S[B,H,W]
------00 --000000 --000000 -0000000
RXF0A[B,H,W]
-------- -------- -------- --000000
RXBC[B,H,W]
-------- -------- 00000000 000000-RXF1C[B,H,W]
00000000 -0000000 00000000 000000-RXF1S[B,H,W]
00----00 --000000 --000000 -0000000
RXF1A[B,H,W]
-------- -------- -------- --000000
RXESC[B,H,W]
-------- -------- -----000 -000-000
TXBC[B,H,W]
-0000000 --000000 00000000 000000-TXFQS[B,H,W]
-------- --000000 ---00000 –000000
TXESC[B,H,W]
-------- -------- -------- -----000
TXBRP[B,H,W]
00000000 00000000 00000000 00000000
TXBAR[B,H,W]
00000000 00000000 00000000 00000000
TXBCR[B,H,W]
00000000 00000000 00000000 00000000
TXBTO[B,H,W]
00000000 00000000 00000000 00000000
TXBCF[B,H,W]
00000000 00000000 00000000 00000000
239
A. Register Map
1. Register Map
P E R I P H E R A L
Register
Base_Address
+ Address
+3
+2
TXBCIE[B,H,W]
00000000 00000000 00000000 00000000
-
-
-
--000000 --000000 00000000 000000-TXEFS[B,H,W]
0x0F4
------00 ---00000 ---00000 --000000
TXEFA[B,H,W]
0x0F8
-------- -------- -------- ---00000
-
0x200
0x204
-
-
-
FDSEAR[B,H,W]
FDESR[B,H,W]
FDECR[B,H,W]
00000000 00000000
------00
----0000
FDDEAR[B,H,W]
FDESCR[B,H,W]
00000000 00000000
------00
-
FDFECR[B,H,W]
0x208
0------- -----000 00000000 00000000
-
0x210
-
-
-
TSMDR[B,H,W]
TSCNTR[B,H,W]
-------- -------0
-------- -------0
TSDIVR[B,H,W]
0x214
-------- -------- 00000000 00000000
0x218
0x21C - 0xFFC
TXEFC[B,H,W]
0x0F0
0x20C
+0
00000000 00000000 00000000 00000000
0x0E4
0x0FC - 0x1FC
+1
TXBTIE[B,H,W]
0x0E0
0x0E8 - 0x0EC
M A N U A L
TSCPCLR[B,H,W]
TSCDTR[B,H,W]
00000000 00000000
00000000 00000000
-
-
+3
+2
-
-
+1
+0
CAN FD Message RAM
Message RAM
Base_Address
+ Address
Rx Buffer and FIFO Element [W]
0x8000 0xBFFC
Tx Buffer Element [W]
Tx Event FIFO Element [W]
Standard Message ID Filter Element [W]
Extended Message ID Filter Element [W]
Note:
−
240
CONFIDENTIAL
For the register details of CAN FD Message RAM block, refer to the Chapter CAN FD Controller.
FM4_MN709-00003-4v0-E, May 27, 2015
A. Register Map
1. Register Map
P E R I P H E R A L
M A N U A L
1.45 Programmable-CRC
Programmable-CRC
Base_Address : 0x4008_0000
Register
Base_Address
+ Address
+3
+1
+0
CRCn_PORY[B,H,W]
0x000
00000100 11000001 00011101 10110111
CRCn_SEED[B,H,W]
0x004
11111111 11111111 11111111 11111111
CRCn_FXOR[B,H,W]
0x008
11111111 11111111 11111111 11111111
CRCn_CFG[B,H,W]
0x00C
00000000 11100000 00000000 00000000
CRCn_WR[B,H,W]
0x010
00000000 00000000 00000000 00000000
CRCn_RD[B,H,W]
0x014
0x018 - 0xFFC
+2
00000000 00000000 00000000 00000000
-
-
-
-
+1
+0
-
-
1.46 WorkFlash_IF
WorkFlash_IF
Base_Address : 0x200E_0000
Base_Address
+ Address
Register
+3
+2
0x000
WFASZR[B,H,W]
0x004
WFRWTR[B,H,W]
0x008
0x00C - 0xFFF
WFSTR[B,H,W]
-
-
Note:
−
For the register details of Workflash IF block, refer to the Flash Programming Manual of the product
used.
May 27, 2015, FM4_MN709-00003-4v0-E
CONFIDENTIAL
241
A. Register Map
1. Register Map
P E R I P H E R A L
M A N U A L
1.47 High-Speed Quad SPI Controller
1.47.1 TYPE1-M4, TYPE2-M4, TYPE3-M4 products
High-Speed Quad SPI Controller
Base_Address : 0xD000_0000
Register
Base_Address
+ Address
+3
+2
0x000
HSSPIn_PCC0[B,H,W]
-------- -1111111 00000000 00000000
HSSPIn_PCC1[B,H,W]
0x008
-------- -1111111 00000000 00000000
HSSPIn_PCC2[B,H,W]
0x00C
-------- -1111111 00000000 00000000
HSSPIn_PCC3[B,H,W]
0x010
-------- -1111111 00000000 00000000
HSSPIn_TXF[B,H,W]
0x014
-------- -------- -------- -0000000
HSSPIn_TXE[B,H,W]
0x018
-------- -------- -------- -0000000
HSSPIn_TXC[B,H,W]
0x01C
-------- -------- -------- -0000000
HSSPIn_RXF[B,H,W]
0x020
-------- -------- -------- -0000000
HSSPIn_RXE[B,H,W]
0x024
-------- -------- -------- -0000000
HSSPIn_RXC[B,H,W]
0x028
-------- -------- -------- -0000000
HSSPIn_FAULTF[B,H,W]
0x02C
-------- -------- -------- ---00000
HSSPIn_FAULTC[B,H,W]
0x030
0x038
-------- -------- -------- ---00000
-
HSSPIn_DMDMAEN
HSSPIn_DMCFG
[B,H,W]
[B,H,W]
------00
-----001
HSSPIn_DMPSEL
HSSPIn_DMSTOP
HSSPIn_DMSTART
[B,H,W]
[B,H,W]
[B,H,W]
[B,H,W]
----0000
------00
-------0
-------0
HSSPIn_DMBCS[B,H,W]
HSSPIn_DMBCC[B,H,W]
00000000 00000000
00000000 00000000
HSSPIn_DMSTATUS[B,H,W]
0x040
-------- ---00000 ---00000 ------00
0x044
-
-
-
-
0x048
-
-
-
-
0x04C
CONFIDENTIAL
-
HSSPIn_DMTRP
0x03C
242
+0
-------- -------- -------- --000-00
0x004
0x034
+1
HSSPIn_MCTRL[B,H,W]
HSSPIn_FIFOCFG[B,H,W]
--------_--------_---00000_01110111
FM4_MN709-00003-4v0-E, May 27, 2015
A. Register Map
1. Register Map
P E R I P H E R A L
M A N U A L
Register
Base_Address
+ Address
0x050
0x054
0x058
0x05C
0x060
0x064
0x068
0x06C
0x070
0x074
0x078
0x07C
0x080
0x084
0x088
0x08C
0x090
0x094
0x098
0x09C
0x0A0
0x0A4
0x0A8
May 27, 2015, FM4_MN709-00003-4v0-E
CONFIDENTIAL
+3
+2
+1
+0
HSSPIn_TXFIFO0[B,H,W]
00000000 00000000 00000000 00000000
HSSPIn_TXFIFO1[B,H,W]
00000000 00000000 00000000 00000000
HSSPIn_TXFIFO2[B,H,W]
00000000 00000000 00000000 00000000
HSSPIn_TXFIFO3[B,H,W]
00000000 00000000 00000000 00000000
HSSPIn_TXFIFO4[B,H,W]
00000000 00000000 00000000 00000000
HSSPIn_TXFIFO5[B,H,W]
00000000 00000000 00000000 00000000
HSSPIn_TXFIFO6[B,H,W]
00000000 00000000 00000000 00000000
HSSPIn_TXFIFO7[B,H,W]
00000000 00000000 00000000 00000000
HSSPIn_TXFIFO8[B,H,W]
00000000 00000000 00000000 00000000
HSSPIn_TXFIFO9[B,H,W]
00000000 00000000 00000000 00000000
HSSPIn_TXFIFO10[B,H,W]
00000000 00000000 00000000 00000000
HSSPIn_TXFIFO11[B,H,W]
00000000 00000000 00000000 00000000
HSSPIn_TXFIFO12[B,H,W]
00000000 00000000 00000000 00000000
HSSPIn_TXFIFO13[B,H,W]
00000000 00000000 00000000 00000000
HSSPIn_TXFIFO14[B,H,W]
00000000 00000000 00000000 00000000
HSSPIn_TXFIFO15[B,H,W]
00000000 00000000 00000000 00000000
HSSPIn_RXFIFO0[B,H,W]
00000000 00000000 00000000 00000000
HSSPIn_RXFIFO1[B,H,W]
00000000 00000000 00000000 00000000
HSSPIn_RXFIFO2[B,H,W]
00000000 00000000 00000000 00000000
HSSPIn_RXFIFO3[B,H,W]
00000000 00000000 00000000 00000000
HSSPIn_RXFIFO4[B,H,W]
00000000 00000000 00000000 00000000
HSSPIn_RXFIFO5[B,H,W]
00000000 00000000 00000000 00000000
HSSPIn_RXFIFO6[B,H,W]
00000000 00000000 00000000 00000000
243
A. Register Map
1. Register Map
P E R I P H E R A L
Register
Base_Address
+ Address
+3
+2
HSSPIn_RXFIFO8[B,H,W]
00000000 00000000 00000000 00000000
HSSPIn_RXFIFO9[B,H,W]
0x0B4
00000000 00000000 00000000 00000000
HSSPIn_RXFIFO10[B,H,W]
0x0B8
00000000 00000000 00000000 00000000
HSSPIn_RXFIFO11[B,H,W]
0x0BC
00000000 00000000 00000000 00000000
HSSPIn_RXFIFO12[B,H,W]
0x0C0
00000000 00000000 00000000 00000000
HSSPIn_RXFIFO13[B,H,W]
0x0C4
00000000 00000000 00000000 00000000
HSSPIn_RXFIFO14[B,H,W]
0x0C8
00000000 00000000 00000000 00000000
HSSPIn_RXFIFO15[B,H,W]
0x0CC
00000000 00000000 00000000 00000000
HSSPIn_CSCFG[B,H,W]
0x0D0
-------- ----0000 ----0000 --000000
HSSPIn_CSITIME[B,H,W]
0x0D4
-------- -------- 11111111 11111111
HSSPIn_CSAEXT[B,H,W]
0x0D8
0x0E4
0x0E8
0x0EC
0x0F0
0x0F4
0x0F8
00000000 00000000 000----- -------HSSPIn_RDCSDC1[B,H,W]
CONFIDENTIAL
HSSPIn_RDCSDC0[B,H,W]
00000000 ----0000
00000000 ----0000
HSSPIn_RDCSDC3[B,H,W]
HSSPIn_RDCSDC2[B,H,W]
00000000 ----0000
00000000 ----0000
HSSPIn_RDCSDC5[B,H,W]
HSSPIn_RDCSDC4[B,H,W]
00000000 ----0000
00000000 ----0000
HSSPIn_RDCSDC7[B,H,W]
HSSPIn_RDCSDC6[B,H,W]
00000000 ----0000
00000000 ----0000
HSSPIn_WRCSDC1[B,H,W]
HSSPIn_WRCSDC0[B,H,W]
00000000 ----0000
00000000 ----0000
HSSPIn_WRCSDC3[B,H,W]
HSSPIn_WRCSDC2[B,H,W]
00000000 ----0000
00000000 ----0000
HSSPIn_WRCSDC5[B,H,W]
HSSPIn_WRCSDC4[B,H,W]
00000000 ----0000
00000000 ----0000
HSSPIn_WRCSDC7[B,H,W]
HSSPIn_WRCSDC6[B,H,W]
00000000 ----0000
00000000 ----0000
HSSPIn_MID[B,H,W]
0x0FC
244
+0
00000000 00000000 00000000 00000000
0x0B0
0x0E0
+1
HSSPIn_RXFIFO7[B,H,W]
0x0AC
0x0DC
M A N U A L
00000000 00000000 00000110 00110000
0x100 - 0x3FC
-
-
-
0x400
-
-
-
0x404
-
-
-
0x408 - 0xFFC
-
-
-
QDCLKR[B,H,W]
----1111
DBCNT[B,H,W]
------00
-
FM4_MN709-00003-4v0-E, May 27, 2015
A. Register Map
1. Register Map
P E R I P H E R A L
1.47.2
M A N U A L
TYPE4-M4 product
High-Speed Quad SPI Controller
Base_Address : 0xD0A0_4000
Register
Base_Address
+ Address
+3
+2
0x000
HSSPIn_PCC0[B,H,W]
-------- -1111111 00000000 00000000
HSSPIn_PCC1[B,H,W]
0x008
-------- -1111111 00000000 00000000
HSSPIn_PCC2[B,H,W]
0x00C
-------- -1111111 00000000 00000000
HSSPIn_PCC3[B,H,W]
0x010
-------- -1111111 00000000 00000000
HSSPIn_TXF[B,H,W]
0x014
-------- -------- -------- -0000000
HSSPIn_TXE[B,H,W]
0x018
-------- -------- -------- -0000000
HSSPIn_TXC[B,H,W]
0x01C
-------- -------- -------- -0000000
HSSPIn_RXF[B,H,W]
0x020
-------- -------- -------- -0000000
HSSPIn_RXE[B,H,W]
0x024
-------- -------- -------- -0000000
HSSPIn_RXC[B,H,W]
0x028
-------- -------- -------- -0000000
HSSPIn_FAULTF[B,H,W]
0x02C
-------- -------- -------- ---00000
HSSPIn_FAULTC[B,H,W]
0x030
0x038
-------- -------- -------- ---00000
-
-
HSSPIn_DMDMAEN
HSSPIn_DMCFG
[B,H,W]
[B,H,W]
------00
-----001
HSSPIn_DMTRP
HSSPIn_DMPSEL
HSSPIn_DMSTOP
HSSPIn_DMSTART
[B,H,W]
[B,H,W]
[B,H,W]
[B,H,W]
----0000
------00
-------0
-------0
0x03C
HSSPIn_DMBCS[B,H,W]
HSSPIn_DMBCC[B,H,W]
00000000 00000000
00000000 00000000
HSSPIn_DMSTATUS[B,H,W]
0x040
-------- ---00000 ---00000 ------00
0x044
-
-
-
-
0x048
-
-
-
-
0x04C
May 27, 2015, FM4_MN709-00003-4v0-E
CONFIDENTIAL
+0
-------- -------- -------- --000-00
0x004
0x034
+1
HSSPIn_MCTRL[B,H,W]
HSSPIn_FIFOCFG[B,H,W]
--------_--------_---00000_01110111
245
A. Register Map
1. Register Map
P E R I P H E R A L
Register
Base_Address
+ Address
0x050
0x054
0x058
0x05C
0x060
0x064
0x068
0x06C
0x070
0x074
0x078
0x07C
0x080
0x084
0x088
0x08C
0x090
0x094
0x098
0x09C
0x0A0
0x0A4
0x0A8
0x0AC
246
CONFIDENTIAL
M A N U A L
+3
+2
+1
+0
HSSPIn_TXFIFO0[B,H,W]
00000000 00000000 00000000 00000000
HSSPIn_TXFIFO1[B,H,W]
00000000 00000000 00000000 00000000
HSSPIn_TXFIFO2[B,H,W]
00000000 00000000 00000000 00000000
HSSPIn_TXFIFO3[B,H,W]
00000000 00000000 00000000 00000000
HSSPIn_TXFIFO4[B,H,W]
00000000 00000000 00000000 00000000
HSSPIn_TXFIFO5[B,H,W]
00000000 00000000 00000000 00000000
HSSPIn_TXFIFO6[B,H,W]
00000000 00000000 00000000 00000000
HSSPIn_TXFIFO7[B,H,W]
00000000 00000000 00000000 00000000
HSSPIn_TXFIFO8[B,H,W]
00000000 00000000 00000000 00000000
HSSPIn_TXFIFO9[B,H,W]
00000000 00000000 00000000 00000000
HSSPIn_TXFIFO10[B,H,W]
00000000 00000000 00000000 00000000
HSSPIn_TXFIFO11[B,H,W]
00000000 00000000 00000000 00000000
HSSPIn_TXFIFO12[B,H,W]
00000000 00000000 00000000 00000000
HSSPIn_TXFIFO13[B,H,W]
00000000 00000000 00000000 00000000
HSSPIn_TXFIFO14[B,H,W]
00000000 00000000 00000000 00000000
HSSPIn_TXFIFO15[B,H,W]
00000000 00000000 00000000 00000000
HSSPIn_RXFIFO0[B,H,W]
00000000 00000000 00000000 00000000
HSSPIn_RXFIFO1[B,H,W]
00000000 00000000 00000000 00000000
HSSPIn_RXFIFO2[B,H,W]
00000000 00000000 00000000 00000000
HSSPIn_RXFIFO3[B,H,W]
00000000 00000000 00000000 00000000
HSSPIn_RXFIFO4[B,H,W]
00000000 00000000 00000000 00000000
HSSPIn_RXFIFO5[B,H,W]
00000000 00000000 00000000 00000000
HSSPIn_RXFIFO6[B,H,W]
00000000 00000000 00000000 00000000
HSSPIn_RXFIFO7[B,H,W]
00000000 00000000 00000000 00000000
FM4_MN709-00003-4v0-E, May 27, 2015
A. Register Map
1. Register Map
P E R I P H E R A L
M A N U A L
Register
Base_Address
+ Address
+3
+2
00000000 00000000 00000000 00000000
HSSPIn_RXFIFO9[B,H,W]
0x0B4
00000000 00000000 00000000 00000000
HSSPIn_RXFIFO10[B,H,W]
0x0B8
00000000 00000000 00000000 00000000
HSSPIn_RXFIFO11[B,H,W]
0x0BC
00000000 00000000 00000000 00000000
HSSPIn_RXFIFO12[B,H,W]
0x0C0
00000000 00000000 00000000 00000000
HSSPIn_RXFIFO13[B,H,W]
0x0C4
00000000 00000000 00000000 00000000
HSSPIn_RXFIFO14[B,H,W]
0x0C8
00000000 00000000 00000000 00000000
HSSPIn_RXFIFO15[B,H,W]
0x0CC
00000000 00000000 00000000 00000000
HSSPIn_CSCFG[B,H,W]
0x0D0
-------- ----0000 ----0000 --000000
HSSPIn_CSITIME[B,H,W]
0x0D4
-------- -------- 11111111 11111111
HSSPIn_CSAEXT[B,H,W]
0x0D8
0x0E0
0x0E4
0x0E8
0x0EC
0x0F0
0x0F4
0x0F8
00000000 00000000 000----- -------HSSPIn_RDCSDC1[B,H,W]
CONFIDENTIAL
HSSPIn_RDCSDC0[B,H,W]
00000000 ----0000
00000000 ----0000
HSSPIn_RDCSDC3[B,H,W]
HSSPIn_RDCSDC2[B,H,W]
00000000 ----0000
00000000 ----0000
HSSPIn_RDCSDC5[B,H,W]
HSSPIn_RDCSDC4[B,H,W]
00000000 ----0000
00000000 ----0000
HSSPIn_RDCSDC7[B,H,W]
HSSPIn_RDCSDC6[B,H,W]
00000000 ----0000
00000000 ----0000
HSSPIn_WRCSDC1[B,H,W]
HSSPIn_WRCSDC0[B,H,W]
00000000 ----0000
00000000 ----0000
HSSPIn_WRCSDC3[B,H,W]
HSSPIn_WRCSDC2[B,H,W]
00000000 ----0000
00000000 ----0000
HSSPIn_WRCSDC5[B,H,W]
HSSPIn_WRCSDC4[B,H,W]
00000000 ----0000
00000000 ----0000
HSSPIn_WRCSDC7[B,H,W]
HSSPIn_WRCSDC6[B,H,W]
00000000 ----0000
00000000 ----0000
HSSPIn_MID[B,H,W]
0x0FC
00000000 00000000 00000110 00110000
0x100 - 0x3FC
-
-
-
0x400
-
-
-
0x404
-
-
-
0x408 - 0xFFC
-
-
-
May 27, 2015, FM4_MN709-00003-4v0-E
+0
HSSPIn_RXFIFO8[B,H,W]
0x0B0
0x0DC
+1
QDCLKR[B,H,W]
----1111
DBCNT[B,H,W]
------00
-
247
A. Register Map
1. Register Map
P E R I P H E R A L
1.48
M A N U A L
HyperBus Interface
HyperBus Interface
Base_Address : 0xD0A0_5000
Register
Base_Address
+ Address
+3
+2
0x000
IEN[B,H,W]
0------- -------- -------- -------0
ISR[B,H,W]
0x008
-------- -------- -------- -------0
-
-
MBR1[B,H,W]
00000000 00000000 00000000 00000000
MCR0[B,H,W]
0x018
-------- ------00 -------- --00--11
MCR1[B,H,W]
0x01C
-------- ------00 -------- --00--11
MTR0[B,H,W]
0x020
00000000 00000000 00000000 ----0000
MTR1[B,H,W]
0x024
00000000 00000000 00000000 ----0000
GPOR[B,H,W]
0x028
-------- -------- -------- ------00
WPR[B,H,W]
0x02C
-------- -------- -------- -------0
TEST[B,H,W]
0x030
CONFIDENTIAL
-
00000000 00000000 00000000 00000000
0x014
248
MBR0[B,H,W]
0x010
0x034- 0xFFC
+0
-----000 -------0 ----0000 -------0
0x004
0x024
+1
CSR[B,H,W]
-------- -------- -------- -------0
-
-
-
-
FM4_MN709-00003-4v0-E, May 27, 2015
A. Register Map
1. Register Map
P E R I P H E R A L
M A N U A L
1.49 GDC Sub System Controller
GDC Sub system Controller
Base_Address : 0xD0A0_0000
Register
Base_Address
+ Address
0x000
0x004
0x008
0x00C
0x010
0x014
0x018
0x01C
0x020
0x024
0x028
0x02C
0x030
0x034
+2
+1
00000000 00000000 00000000 00000000
LockStatus[W]
-------- -------- -------0 ---0---0
*[W]
CnfigClockControl[W]
-------- -------- -------- -----001
VRamInterruptEnable[W]
-------- -------- -------- ------11
*[W]
VRamInterruptClear[W]
-------- -------- -------- ------00
VRamInterruptStatus[W]
-------- -------- -------- ------00
ExtFlashDevSelect[W]
-------- -------- -------- -------1
VRamRemapDisable[W]
-------- -------- -------- -------0
PanicSwitch[W]
-------- -------- -------- -------1
GDC_ClockDivider[W]
-------- -----100 00000000 -------WkupTriggerMask[W]
-----000 -----000 00000000 00000000
ClockDomainStatus[W]
-------- -------- -------- ----0000
-
0x03C
-
0x044
0x048
0x04C
0x050
May 27, 2015, FM4_MN709-00003-4v0-E
+0
LockUnlock[W]
0x038
0x040
CONFIDENTIAL
+3
dsp_LockUnlock[W]
00000000 00000000 00000000 00000000
dsp_LockStatus[W]
-------- -------- -------0 ---0---0
dsp0_ClockDivider[W]
-------- 01000001 11100000 -------dsp0_DomainControl[W]
-------- -------1 -------- -------0
dsp0_ClockShift[W]
-------- -------- -------- -------1
249
A. Register Map
1. Register Map
P E R I P H E R A L
Register
Base_Address
+ Address
0x054
0x058
0x05C
0x060
+2
+1
dsp0_PowerEnControl[W]
-------- -------- -------- -------0
dsp0_ClockGateModeLock[W]
00000000 00000000 00000000 00000000
dsp0_ClockGateControl[W]
-------- -------- -------- -------0
0x068
-
0x06C
-
0x070
-
0x074
-
0x080
0x084
0x088
0x08C
SDRAMC_ClcokDivider[W]
-------- 00000100 00000000 -------SDRAMC_DomainControl[W]
-------- -------1 -------- -------0
HSSPIC_ClockDivider[W]
-------- 00000100 00000000 -------HSSPIC_DomainControl[W]
-------- -------1 -------- -------0
RPCC_ClcokDivider[W]
-------- -------- -------- -----000
RPCC_DomainControl[W]
-------- -------1 -------- -------0
0x090
-
0x094
-
0x098
-
0x09C
-
0x100
0x104
0x108
0x10C
+0
*[W]
-
0x07C
CONFIDENTIAL
+3
0x064
0x078
250
M A N U A L
vram_LockUnlock[W]
00000000 00000000 00000000 00000000
vram_LockStatus[W]
-------- -------- -------0 ---0---0
vram_sram_select[W]
-------- -------- ----0000 00000000
*[W]
FM4_MN709-00003-4v0-E, May 27, 2015
A. Register Map
1. Register Map
P E R I P H E R A L
M A N U A L
Register
Base_Address
+ Address
+2
+1
0x110
*[W]
0x114
*[W]
0x118
*[W]
0x11C
*[W]
0x120
*[W]
0x124
*[W]
0x128
*[W]
0x12C
-
0x130
-
0x134
-
0x138
-
0x13C
0x140
0x144
0x148
0x14C-0xFFC
May 27, 2015, FM4_MN709-00003-4v0-E
CONFIDENTIAL
+3
+0
vram_sberraddr_s0[W]
00000000 00000000 0000000 00000000
vram_sberraddr_s1[W]
00000000 00000000 0000000 00000000
vram_arbiter_priority[W]
-------- -------- -------- 00000000
-
251
A. Register Map
1. Register Map
P E R I P H E R A L
M A N U A L
1.50 GDC Sub System SDRAM Controller
GDC Sub System SDRAM Controller
Base_Address : 0xD0A0_3000
Register
Base_Address
+ Address
0x000-0x0FF
0x100
0x104
0x108
0x10C
0x110
0x114-0xFFC
252
CONFIDENTIAL
+3
+2
+1
+0
SDMODE[W]
-------- -------0 00010011 --00-000
REFTIM[W]
-------0 00000000 0000000000110011
PWRDWN[W]
-------- -------- 00000000 00000000
SDTIM[W]
0-----00 01000010 00010001 0100--01
SDCMD[W]
0------- ---00000 00000000 00000000
-
FM4_MN709-00003-4v0-E, May 27, 2015
B. List of Notes
This section explains notes for each function.
1. Notes When High-speed CR Is Used for the Master Clock
CODE: 9BPRECAUTION-E01.3
May 27, 2015, FM4_MN709-00003-4v0-E
CONFIDENTIAL
253
B. List of Notes
1. Notes When High-speed CR Is Used for the Master Clock
P E R I P H E R A L
1.
M A N U A L
Notes When High-speed CR Is Used for the Master Clock
This section explains notes when the high-speed CR is used for the master clock.
The frequency of the high-speed CR varies depending on the temperature and/or the power supply voltage.
The following table shows notes on each function macro when the high-speed CR is used for the master
clock.
Furthermore, pay attention to notes when the high-speed CR is used as an input clock of the PLL and the
master clock is selected for PLL.
Notes on Each Macro
Macro
Function/mode
HCLK/FCLK/PCLK0/
Internal Bus Clock
PCLK1/PCLK2/
Notes
When the frequency of the high-speed CR is the maximum
value, the setting of the internal operating clock frequency
shall not exceed the upper limit specified in the "data
TPIUCLK
sheet" for the product that you are using.
Multi-function Timer
Base Timer
Timer
Watch Timer
The frequency variation of the high-speed CR should be
Dual Timer
considered for the timer count value of each macro.
Watch Dog Timer
Quadrature
Considering the frequency variation of the high-speed CR,
A/D Converter
Sampling Time
the sampling time and the compare time of the A/D
Compare Time
converter shall satisfy the specification specified in the
"data sheet" for the product that you are using.
USB
Ethernet-MAC
As the frequency accuracy does not meet the required
CAN
-
specification, these macros cannot be used when the
high-speed CR is used for the master clock.
CAN-FD
I2S
Even if the frequency of the high-speed CR is the minimum
or the maximum value, the baud rate error should be
UART
considered.
The baud rate error shall not exceed the limit.
Multi-Function
CSIO
The frequency variation of the high-speed CR should be
I2C
considered for the communication of each macro.
Serial Interface
As the required frequency accuracy cannot be met, this
function cannot be used as master.
As a slave, the specified baud rate has more error at the
LIN
maximum/minimum frequency of high-speed clock. So, if
the error limit of the baud rate is exceeded, this function
cannot be used.
Debug Interface
As the frequency variation of the high-speed CR, the
Serial Wire
SWV(Serial Wire View) may not be used.
When the external bus clock output is used, the frequency
External Bus Interface
Clock Output
variation of the high-speed CR should be considered for
devices to be connected.
High-Speed Quad
SPI
SD card Interface
254
CONFIDENTIAL
-
The frequency variation of the high-speed CR should be
considered for devices to be connected.
The frequency variation of the high-speed CR should be
considered for devices to be connected.
FM4_MN709-00003-4v0-E, May 27, 2015
B. List of Notes
1. Notes When High-speed CR Is Used for the Master Clock
P E R I P H E R A L
Macro
M A N U A L
Function/mode
Notes
Panel Output
GDC
High-Speed Quad SPI
The frequency variation of the high-speed CR should be
HyperBus Interface
considered for devices to be connected.
SDRAM Interface
May 27, 2015, FM4_MN709-00003-4v0-E
CONFIDENTIAL
255
P E R I P H E R A L
M A N U A L
Major Changes
Page
Section
Changes
Revision 1.0
-
-
Initial release
The target products in this manual
Added TYPE1-M4, TYPE2-M4, TYPE3-M4 product
Revision 2.0
6 to 7
12 -bit A/D Converter bit A/D
18
Converter bit A/D Converter bit A/D
Converter bit
Added "DMA transfer triggered by an interrupt request"
1. Overview
12 -bit A/D Converter bit A/D
41
Converter bit A/D Converter bit A/D
Converter bit
Revised the description of the explanation
3.6 Starting DMA
-
-
Company name and layout design change
4
Peripheral Manual
Added "GDC Part"
8
The target products in this manual
Added TYPE4-M4
84
CHAPTER1-3:A/D Timer Trigger
Added "The multiple A/D converters can use same start factor."
Revision 3.0
Selection
Revision 4.0
6 to 10
The target products in this manual
Added TYPE5-M4 and TYPE6-M4 and the other target products.
8
The target products in this manual
Revised TYPE4-M4 Product list.
91 to 104
CHAPTER 1-4: A/D Converter
Added a new chapter.
Offset Calibration
252
Appendixes
Corrected Base Address of GDC Sub System SDRAM Controller
A. Register Map
1. Register Map
256
CONFIDENTIAL
FM4_MN709-00003-4v0-E, May 27, 2015
P E R I P H E R A L
M A N U A L
MN709-00003-4v0-E
Cypress・Controller Manual
32-BIT MICROCONTROLLER
FM4 Family
PERIPHERAL MANUAL
Analog Macro Part
May 2015
Rev. 4.0
Published : Cypress Semiconductor Corp.
Edited
: Communications Dept.
May 27, 2015, FM4_MN709-00003-4v0-E
CONFIDENTIAL
257
P E R I P H E R A L
M A N U A L
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use,
including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not
designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless
extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury,
severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control,
mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where
chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Cypress will not be liable to
you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any
semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures
by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention
of over-current levels and other abnormal operating conditions. If any products described in this document represent goods
or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the
US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective
government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a Cypress
product under development by Cypress. Cypress reserves the right to change or discontinue work on any product without
notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy,
completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other
warranty, express, implied, or statutory. Cypress assumes no liability for any damages of any kind arising out of the use of
the information in this document.
®
Copyright © 2013-2015 Cypress Semiconductor Corp. All rights reserved. Cypress, Cypress logo, Spansion , the
®
®
TM
TM
TM
TM
Spansion logo, MirrorBit , MirrorBit Eclipse , ORNAND , Easy DesignSim , Traveo and combinations thereof, are
trademarks and registered trademarks of Cypress Semiconductor Corp. in the United States and other countries. Other
names used are for informational purposes only and may be trademarks of their respective owners.
258
CONFIDENTIAL
FM4_MN709-00003-4v0-E, May 27, 2015