The following document contains information on Cypress products.
FM0+ S6E1A1 Series
32-bit ARM® Cortex®-M0+ based Microcontroller
S6E1A11B0A/S6E1A11C0A,S6E1A12B0A/S6E1A12C0A
Data Sheet (Full Production)
Notice to Readers: This document states the current technical specifications regarding the Spansion
product(s) described herein. Spansion Inc. deems the products to have been in sufficient production volume
such that subsequent versions of this document are not expected to change. However, typographical or
specification corrections, or modifications to the valid combinations offered may occur.
Publication Number S6E1A1_DS710-00001
CONFIDENTIAL
Revision 1.0
Issue Date July 16, 2014
D a t a S h e e t
Notice On Data Sheet Designations
Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of
product information or intended specifications throughout the product life cycle, including development,
qualification, initial production, and full production. In all cases, however, readers are encouraged to verify
that they have the latest information before finalizing their design. The following descriptions of Spansion
data sheet designations are presented here to highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion Inc. is developing one or more specific
products, but has not committed any design to production. Information presented in a document with this
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Inc. therefore places the following conditions upon Advance Information content:
“This document contains information on one or more products under development at Spansion Inc.
The information is intended to help you evaluate this product. Do not design in this product without
contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this
proposed product without notice.”
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The Preliminary designation indicates that the product development has progressed such that a commitment
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places the following conditions upon Preliminary content:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. The Preliminary status of this document indicates that product qualification has
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page refers the reader to the notice on this page.
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When a product has been in production for a period of time such that no changes or only nominal changes
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conditions to documents in this category:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. Spansion Inc. deems the products to have been in sufficient production volume
such that subsequent versions of this document are not expected to change. However,
typographical or specification corrections, or modifications to the valid combinations offered may
occur.”
Questions regarding these document designations may be directed to your local sales office.
2
CONFIDENTIAL
S6E1A1_DS710-00001-1v0-E, July 16, 2014
FM0+ S6E1A1 Series
32-bit ARM® Cortex®-M0+ based Microcontroller
S6E1A11B0A/S6E1A11C0A,S6E1A12B0A/S6E1A12C0A
Data Sheet (Full Production)
1. Description
The S6E1A1 Series is a series of highly integrated 32-bit microcontrollers designed for embedded
controllers aiming at low power consumption and low cost.
This series has the ARM Cortex-M0+ Processor with on-chip Flash memory and SRAM, and consists of
2
peripheral functions such as various timers, ADCs and communication interfaces (UART, CSIO, I C, LIN).
The products which are described in this data sheet are placed into TYPE1-M0+ product categories in
"FM0+ Family PERIPHERAL MANUAL".
Note:
−
ARM and Cortex are the registered trademarks of ARM Limited in the EU and other countries.
Publication Number S6E1A1_DS710-00001
Revision 1.0
Issue Date July 16, 2014
This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient
production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the
valid combinations offered may occur.
CONFIDENTIAL
D a t a S h e e t
Table of Contents
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
4
CONFIDENTIAL
Description ..................................................................................................................................... 3
Features ......................................................................................................................................... 5
Product Lineup ............................................................................................................................... 9
Packages ...................................................................................................................................... 10
Pin Assignment............................................................................................................................. 11
List of Pin Functions ..................................................................................................................... 16
I/O Circuit Type............................................................................................................................. 27
Handling Precautions ................................................................................................................... 32
8.1
Precautions for Product Design ......................................................................................... 32
8.2
Precautions for Package Mounting ................................................................................... 33
8.3
Precautions for Use Environment ...................................................................................... 35
Handling Devices.......................................................................................................................... 36
Block Diagram .............................................................................................................................. 39
Memory Size ................................................................................................................................ 39
Memory Map ................................................................................................................................ 40
Pin Status in Each CPU State ...................................................................................................... 43
Electrical Characteristics .............................................................................................................. 46
14.1 Absolute Maximum Ratings ............................................................................................... 46
14.2 Recommended Operating Conditions ............................................................................... 47
14.3 DC Characteristics ............................................................................................................ 48
14.3.1
Current Rating .................................................................................................. 48
14.3.2
Pin Characteristics ........................................................................................... 51
14.4 AC Characteristics............................................................................................................. 52
14.4.1
Main Clock Input Characteristics ...................................................................... 52
14.4.2
Sub Clock Input Characteristics ....................................................................... 53
14.4.3
Built-in CR Oscillation Characteristics .............................................................. 54
14.4.4
Operating Conditions of Main PLL (In the case of using the main clock as the
input clock of the PLL) ...................................................................................... 55
14.4.5
Operating Conditions of Main PLL (In the case of using the built-in high-speed
CR clock as the input clock of the main PLL) ................................................... 55
14.4.6
Reset Input Characteristics .............................................................................. 56
14.4.7
Power-on Reset Timing .................................................................................... 56
14.4.8
Base Timer Input Timing ................................................................................... 57
14.4.9
CSIO Timing ..................................................................................................... 58
14.4.10 External Input Timing ........................................................................................ 75
14.4.11 QPRC Timing ................................................................................................... 76
2
14.4.12 I C Timing ......................................................................................................... 78
14.4.13 SW-DP Timing .................................................................................................. 79
14.5 12-bit A/D Converter.......................................................................................................... 80
14.6 Low-voltage Detection Characteristics .............................................................................. 83
14.6.1
Low-voltage Detection Reset............................................................................ 83
14.6.2
Low-voltage Detection Interrupt ........................................................................ 84
14.7 Flash Memory Write/Erase Characteristics ....................................................................... 85
14.8 Return Time from Low-Power Consumption Mode............................................................ 86
14.8.1
Return Factor: Interrupt/WKUP ........................................................................ 86
14.8.2
Return Factor: Reset ........................................................................................ 88
Ordering Information..................................................................................................................... 90
Package Dimensions .................................................................................................................... 91
Major Changes ............................................................................................................................. 96
S6E1A1_DS710-00001-1v0-E, July 16, 2014
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2. Features
32-bit ARM Cortex-M0+ Core
Processor version: r0p1
Maximum operating frequency: 40 MHz
Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and 32 peripheral interrupt
with 4 selectable interrupt priority levels
24-bit System timer (Sys Tick): System timer for OS task management
Bit Band operation
Compatible with Cortex-M3 bit band operation.
On-chip Memory
Flash memory
− Up to 88 Kbyte
− Read cycle:0 wait-cycle
− Security function for code protection
SRAM
The on-chip SRAM of this series has one independent SRAM .
− SRAM: 6 Kbyte
Multi-function Serial Interface (Max 3channels)
128 bytes with FIFO in all channels (The number of FIFO steps varies depending on the settings of the
communication mode or bit length.)
The operation mode of each channel can be selected from one of the following.
− UART
− CSIO
− LIN
− I2 C
UART
− Full duplex double buffer
− Parity can be enabled or disabled.
− Built-in dedicated baud rate generator
− External clock available as a serial clock
− Various error detection functions (parity errors, framing errors, and overrun errors)
CSIO
− Full duplex double buffer
− Built-in dedicated baud rate generator
− Overrun error detection function
− Serial chip select function (ch.1 and ch.3 only)
− Data length: 5 to 16 bits
LIN
− LIN protocol Rev.2.1 supported
− Full duplex double buffer
− Master/Slave mode supported
− LIN break field generation function (The length is variable between 13 bits and 16 bits.)
− LIN break delimiter generation function (The length is variable between 1 bit and 4 bits.)
− Various error detection functions available (parity errors, framing errors, and overrun errors)
I2 C
− Standard-mode (Max: 100 kbps) supported / Fast-mode (Max 400kbps) supported.
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DMA Controller (2 channels)
The DMA Controller has its own bus independent of the CPU, and CPU and DMA Controller can process
simultaneously.
2 independently configurable and operable channels
It can start a transfer with a software request or a request from a built-in peripheral.
Transfer address area: 32 bits (4 Gbyte)
Transfer mode: block transfer/burst transfer/demand transfer
Transfer data type: byte/halfword/word
Transfer block count: 1 to 16
Number of transfers: 1 to 65536
A/D Converter (Max: 8 channels)
12-bit A/D Converter
− Successive approximation type
− Conversion time: 0.8 μs @ 5 V (S6E1A1xC0A) / 2.0 μs (S6E1A1xB0A)
− Priority conversion available (2 levels of priority)
− Scan conversion mode
− Built-in FIFO for conversion data storage (for scan conversion: 16 steps, for priority conversion: 4
steps)
Base Timer (Max: 4 channels)
The operation mode of each channel can be selected from one of the following.
16-bit PWM timer
16-bit PPG timer
16/32-bit reload timer
16/32-bit PWC timer
General-purpose I/O Port
This series can use its pin as a general-purpose I/O port when it is not used for an external bus or a
peripheral function. All ports can be set to fast general-purpose I/O ports or slow general-purpose I/O ports.
In addition, this series has a port relocate function that can set to which I/O port a peripheral function can be
allocated.
All ports are Fast GPIO which can be accessed by 1cycle
Capable of controlling the pull-up of each pin
Capable of reading pin level directly
Port relocate function
Up to 37 fast general-purpose I/O ports @48pin package
Certain ports are 5 V tolerant.
See "5. Pin Assignment" and "7. I/O Circuit Type" for details of such pins.
Dual Timer (32/16-bit Down Counter)
The Dual Timer consists of two programmable 32/16-bit down counters. The operation mode of each timer
channel can be selected from one of the following.
Free-running mode
Periodic mode (= Reload mode)
One-shot mode
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S6E1A1_DS710-00001-1v0-E, July 16, 2014
D a t a S h e e t
Quadrature Position/Revolution Counter (QPRC)
The Quadrature Position/Revolution Counter (QPRC) is used to measure the position of the position
encoder. In addition, it can be used as an up/down counter.
The detection edge for the three external event input pins AIN, BIN and ZIN is configurable.
16-bit position counter
16-bit revolution counter
Two 16-bit compare registers
Multi-function Timer
The Multi-function Timer consists of the following blocks.
16-bit free-run timer × 3 channels
Input capture × 4 channels
Output compare × 6 channels
ADC start compare × 6 channel
Waveform generator × 3 channels
16-bit PPG timer × 3 channels
IGBT mode is contained.
The following function can be used to achieve the motor control.
PWM signal output function
DC chopper waveform output function
Dead time function
Input capture function
ADC start function
DTIF (motor emergency stop) interrupt function
Real-time Clock (RTC)
The Real-time Clock counts year/month/day/hour/minute/second/day of the week from year 01 to year 99.
The RTC can generate an interrupt at a specific time (year/month/day/hour/minute/second/day of the
week) and can also generate an interrupt in a specific year, in a specific month, on a specific day, at a
specific hour or at a specific minute.
It has a timer interrupt function generating an interrupt upon a specific time or at specific intervals.
It can keep counting while rewriting the time.
It can count leap years automatically.
Watch Counter
The Watch Counter wakes up the microcontroller from the low power consumption mode. The clock source
can be selected from the main clock, the sub clock, the built-in high-speed CR clock or the built-in low-speed
CR clock.
Interval timer: up to 64 s (sub clock: 32.768 kHz)
External Interrupt Controller Unit
Up to 8 external interrupt input pins
Non-maskable interrupt (NMI) input pin: 1
Watchdog Timer (2 channels)
The watchdog timer generates an interrupt or a reset when the counter reaches a time-out value.
This series consists of two different watchdogs, "hardware" watchdog and "software" watchdog.
The "hardware" watchdog timer is clocked by the built-in low-speed CR oscillator. Therefore, the "hardware"
watchdog is active in any low-power consumption modes except RTC mode and STOP mode.
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Clock and Reset
Clocks
A clock can be selected from five clock sources (two external oscillators, two built-in CR oscillator, and main
PLL).
−
−
−
−
−
Main clock
Sub clock
Built-in high-speed CR clock
Built-in low-speed CR clock
Main PLL clock
: 4 MHz to 40MHz
: 32.768 kHz
: 4 MHz
: 100 kHz
Resets
− Reset request from the INITX pin
− Power on reset
− Software reset
− Watchdog timer reset
− Low-voltage detection reset
− Clock supervisor reset
Clock Supervisor (CSV)
The Clock Supervisor monitors the failure of external clocks with a clock generated by a built-in CR
oscillator.
If an external clock failure (clock stop) is detected, a reset is asserted.
If an external frequency anomaly is detected, an interrupt or a reset is asserted.
Low-voltage Detector (LVD)
This series monitors the voltage on the VCC pin with a 2-stage mechanism. When the voltage falls below a
designated voltage, the Low-voltage Detector generates an interrupt or a reset.
LVD1: error reporting via an interrupt
LVD2: auto-reset operation
Low Power Consumption Mode
This series has four low power consumption modes.
SLEEP
TIMER
RTC
STOP
Peripheral Clock Gating
The system can reduce the current consumption of the total system with gating the operation clocks of
peripheral functions not used.
Debug
Serial Wire Debug Port (SW-DP)
Micro Trace Buffer (MTB)
Unique ID
A 41-bit unique value of the device has been set.
Power Supply
Wide voltage range: VCC = 2.7 V to 5.5 V
8
CONFIDENTIAL
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D a t a S h e e t
3. Product Lineup
Memory size
Product name
S6E1A11B0A
S6E1A12B0A
S6E1A11C0A
S6E1A12C0A
On-chip Flash memory
56 Kbyte
88 Kbyte
On-chip SRAM
6 Kbyte
6 Kbyte
Function
Product name
Pin count
CPU
S6E1A11B0A
S6E1A11C0A
S6E1A12B0A
S6E1A12C0A
32
Frequency
40 MHz
Power supply voltage range
2.7 V to 5.5 V
DMAC
2 ch.
Multi-function Serial Interface
3 ch. (Max)
(UART/CSIO/I2C)
ch.0/ch.1/ch.3: FIFO
Base Timer
4 ch. (Max)
(PWC/Reload timer/PWM/PPG)
Multi-function
Timer
48/52
Cortex-M0+
A/D start compare
6 ch.
Input capture
4 ch.
Free-run timer
3 ch.
Output compare
6 ch.
Waveform generator
3 ch.
PPG
3 ch.
1 unit
QPRC
1 ch.
Dual Timer
1 unit
Real-time Clock
1 unit
Watch Counter
1 unit
Watchdog timer
1 ch. (SW) + 1 ch. (HW)
External Interrupt
8 pins (Max) + NMI × 1
I/O port
23 pins (Max)
12-bit A/D converter
5 ch. (1 unit)
37 pins (Max)
8 ch. (1 unit)
CSV (Clock Supervisor)
Yes
LVD (Low-voltage Detection)
2 ch.
Built-in CR
High-speed
4 MHz
Low-speed
100 kHz
Debug Function
SW-DP
Unique ID
Yes
Note:
−
All signals of the peripheral function in each product cannot be allocated by limiting the pins of
package. It is necessary to use the port relocate function of the I/O port according to your function
use.
See "14. ELECTRICAL CHARACTERISTICS 14.4 AC Characteristics 14.4.3 Built-in CR Oscillation
Characteristics" for accuracy of built-in CR.
July 16, 2014, S6E1A1_DS710-00001-1v0-E
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D a t a S h e e t
4. Packages
Product name
Package
S6E1A11B0A
S6E1A11C0A
S6E1A12B0A
S6E1A12C0A
LQFP: FPT-32P-M30 (0.80 mm pitch)
-
QFN: LCC-32P-M73 (0.50 mm pitch)
-
LQFP: FPT-48P-M49 (0.50 mm pitch)
-
QFN: LCC-48P-M74 (0.50 mm pitch)
-
LQFP: FPT-52P-M02 (0.65 mm pitch)
-
: Available
Note:
−
10
CONFIDENTIAL
See "16. Package Dimensions" for detailed information on each package.
S6E1A1_DS710-00001-1v0-E, July 16, 2014
D a t a S h e e t
5. Pin Assignment
FPT-32P-M30
25 P21/SIN0_0/INT06_1/TIOB1_1/IC01_1/BIN0_1/FRCK0_0
26 P01/SWCLK
27 P03/SWDIO
28 P04/SCK3_0/INT03_2/TIOB0_1/IGTRG0_1
29 P0F/NMIX/SUBOUT_0/CROUT_1/RTCCO_0
30 P61/SOT3_0/TIOB2_2/DTTI0X_2/SCS11_2
31 P60/SIN3_0/TIOA2_2/INT15_1/IC00_0/IGTRG0_0/SCS10_2
32 VSS
(TOP VIEW)
P3A/RTO00_0/TIOA0_1/AIN0_3/SUBOUT_2/RTCCO_2/INT03_0/SCK0_2 1
24 P22/AN07/SOT0_0/TIOB2_0/IC03_1/ZIN0_1/INT05_1
P3B/RTO01_0/TIOA1_1/BIN0_3/SOT0_2/INT04_0/SCS31_2 2
23 P23/AN06/SCK0_0/TIOA2_0/IC02_1/AIN0_1/INT04_1
P3C/RTO02_0/TIOA2_1/ZIN0_3/SIN0_2/INT05_0/SCS30_2 3
22 AVSS
P3D/RTO03_0/TIOA3_1/INT06_0/AIN0_0/SCK3_2 4
21 AVCC
LQFP - 32
P3E/RTO04_0/TIOA0_0/BIN0_0/SOT3_2/INT15_0 5
20 P13/AN03/SCK1_1/SUBOUT_1/IC01_2/RTCCO_1/INT00_1
P3F/RTO05_0/TIOA1_0/ZIN0_0/SIN3_2 6
19 P12/AN02/SOT1_1/IC00_2/INT01_1
VSS 7
18 P11/AN01/SIN1_1/INT02_1/FRCK0_2/IC02_0
PE3/X1 16
PE2/X0 15
MD0 14
PE0/ADTG_1/DTTI0X_1/INT02_2 13
INITX 12
P47/X1A 11
VCC 9
17 VSS
P46/X0A 10
C 8
Note:
−
The number after the underscore ("_") in a pin name such as XXX_1 and XXX_2 indicates the
relocated port number. The channel on such pin has multiple functions, each of which has its own
pin name. Use the Extended Port Function Register (EPFR) to select the pin to be used.
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D a t a S h e e t
LCC-32P-M73
25 P21/SIN0_0/INT06_1/TIOB1_1/IC01_1/BIN0_1/FRCK0_0
26 P01/SWCLK
27 P03/SWDIO
28 P04/SCK3_0/INT03_2/TIOB0_1/IGTRG0_1
29 P0F/NMIX/SUBOUT_0/CROUT_1/RTCCO_0
30 P61/SOT3_0/TIOB2_2/DTTI0X_2/SCS11_2
31 P60/SIN3_0/TIOA2_2/INT15_1/IC00_0/IGTRG0_0/SCS10_2
32 VSS
(TOP VIEW)
P3A/RTO00_0/TIOA0_1/AIN0_3/SUBOUT_2/RTCCO_2/INT03_0/SCK0_2 1
24 P22/AN07/SOT0_0/TIOB2_0/IC03_1/ZIN0_1/INT05_1
P3B/RTO01_0/TIOA1_1/BIN0_3/SOT0_2/INT04_0/SCS31_2 2
23 P23/AN06/SCK0_0/TIOA2_0/IC02_1/AIN0_1/INT04_1
P3C/RTO02_0/TIOA2_1/ZIN0_3/SIN0_2/INT05_0/SCS30_2 3
22 AVSS
P3D/RTO03_0/TIOA3_1/INT06_0/AIN0_0/SCK3_2 4
21 AVCC
QFN - 32
P3E/RTO04_0/TIOA0_0/BIN0_0/SOT3_2/INT15_0 5
20 P13/AN03/SCK1_1/SUBOUT_1/IC01_2/RTCCO_1/INT00_1
P3F/RTO05_0/TIOA1_0/ZIN0_0/SIN3_2 6
19 P12/AN02/SOT1_1/IC00_2/INT01_1
VSS 7
18 P11/AN01/SIN1_1/INT02_1/FRCK0_2/IC02_0
PE3/X1 16
PE2/X0 15
MD0 14
PE0/ADTG_1/DTTI0X_1/INT02_2 13
INITX 12
P47/X1A 11
VCC 9
17 VSS
P46/X0A 10
C 8
Note:
−
12
CONFIDENTIAL
The number after the underscore ("_") in a pin name such as XXX_1 and XXX_2 indicates the
relocated port number. The channel on such pin has multiple functions, each of which has its own
pin name. Use the Extended Port Function Register (EPFR) to select the pin to be used.
S6E1A1_DS710-00001-1v0-E, July 16, 2014
D a t a S h e e t
FPT-48P-M49
37 P00
38 P01/SWCLK
39 P02
40 P03/SWDIO
41 P04/SCK3_0/INT03_2/TIOB0_1/IGTRG0_1
42 P0F/NMIX/SUBOUT_0/CROUT_1/RTCCO_0
43 P61/SOT3_0/TIOB2_2/DTTI0X_2/SCS11_2
44 P60/SIN3_0/TIOA2_2/INT15_1/IC00_0/IGTRG0_0/SCS10_2
45 P80/SCK1_2/FRCK0_1
46 P81/SOT1_2
47 P82/SIN1_2
48 VSS
(TOP VIEW)
VCC 1
36 P21/SIN0_0/INT06_1/TIOB1_1/IC01_1/BIN0_1/FRCK0_0
P50/INT00_0/AIN0_2/SIN3_1/IC01_0 2
35 P22/AN07/SOT0_0/TIOB2_0/IC03_1/ZIN0_1/INT05_1
P51/INT01_0/BIN0_2/SOT3_1 3
34 P23/AN06/SCK0_0/TIOA2_0/IC02_1/AIN0_1/INT04_1
P52/INT02_0/ZIN0_2/SCK3_1 4
33 AVSS
P39/DTTI0X_0/ADTG_2 5
32 AVRH
LQFP - 48
P3A/RTO00_0/TIOA0_1/AIN0_3/SUBOUT_2/RTCCO_2/INT03_0/SCK0_2 6
31 AVCC
P3B/RTO01_0/TIOA1_1/BIN0_3/SOT0_2/INT04_0/SCS31_2 7
30 P15/AN05/SOT0_1/SCS11_1/IC03_2/INT15_2
P3C/RTO02_0/TIOA2_1/ZIN0_3/SIN0_2/INT05_0/SCS30_2 8
29 P14/AN04/SIN0_1/SCS10_1/INT03_1/IC02_2
P3D/RTO03_0/TIOA3_1/INT06_0/AIN0_0/SCK3_2 9
28 P13/AN03/SCK1_1/SUBOUT_1/IC01_2/RTCCO_1/INT00_1
P3E/RTO04_0/TIOA0_0/BIN0_0/SOT3_2/INT15_0 10
27 P12/AN02/SOT1_1/IC00_2/INT01_1
P3F/RTO05_0/TIOA1_0/ZIN0_0/SIN3_2 11
26 P11/AN01/SIN1_1/INT02_1/FRCK0_2/IC02_0
VSS 24
PE3/X1 23
PE2/X0 22
MD0 21
PE0/ADTG_1/DTTI0X_1/INT02_2 20
P4A/TIOB1_0 19
P49/TIOB0_0 18
INITX 17
P47/X1A 16
P46/X0A 15
C 13
25 P10/AN00
VCC 14
VSS 12
Note:
−
The number after the underscore ("_") in a pin name such as XXX_1 and XXX_2 indicates the
relocated port number. The channel on such pin has multiple functions, each of which has its own
pin name. Use the Extended Port Function Register (EPFR) to select the pin to be used.
July 16, 2014, S6E1A1_DS710-00001-1v0-E
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13
D a t a S h e e t
LCC-48P-M74
37 P00
38 P01/SWCLK
39 P02
40 P03/SWDIO
41 P04/SCK3_0/INT03_2/TIOB0_1/IGTRG0_1
42 P0F/NMIX/SUBOUT_0/CROUT_1/RTCCO_0
43 P61/SOT3_0/TIOB2_2/DTTI0X_2/SCS11_2
44 P60/SIN3_0/TIOA2_2/INT15_1/IC00_0/IGTRG0_0/SCS10_2
45 P80/SCK1_2/FRCK0_1
46 P81/SOT1_2
47 P82/SIN1_2
48 VSS
(TOP VIEW)
VCC 1
36 P21/SIN0_0/INT06_1/TIOB1_1/IC01_1/BIN0_1/FRCK0_0
P50/INT00_0/AIN0_2/SIN3_1/IC01_0 2
35 P22/AN07/SOT0_0/TIOB2_0/IC03_1/ZIN0_1/INT05_1
P51/INT01_0/BIN0_2/SOT3_1 3
34 P23/AN06/SCK0_0/TIOA2_0/IC02_1/AIN0_1/INT04_1
P52/INT02_0/ZIN0_2/SCK3_1 4
33 AVSS
P39/DTTI0X_0/ADTG_2 5
32 AVRH
QFN- 48
P3A/RTO00_0/TIOA0_1/AIN0_3/SUBOUT_2/RTCCO_2/INT03_0/SCK0_2 6
31 AVCC
P3B/RTO01_0/TIOA1_1/BIN0_3/SOT0_2/INT04_0/SCS31_2 7
30 P15/AN05/SOT0_1/SCS11_1/IC03_2/INT15_2
P3C/RTO02_0/TIOA2_1/ZIN0_3/SIN0_2/INT05_0/SCS30_2 8
29 P14/AN04/SIN0_1/SCS10_1/INT03_1/IC02_2
P3D/RTO03_0/TIOA3_1/INT06_0/AIN0_0/SCK3_2 9
28 P13/AN03/SCK1_1/SUBOUT_1/IC01_2/RTCCO_1/INT00_1
P3E/RTO04_0/TIOA0_0/BIN0_0/SOT3_2/INT15_0 10
27 P12/AN02/SOT1_1/IC00_2/INT01_1
P3F/RTO05_0/TIOA1_0/ZIN0_0/SIN3_2 11
26 P11/AN01/SIN1_1/INT02_1/FRCK0_2/IC02_0
VSS 24
PE3/X1 23
PE2/X0 22
MD0 21
PE0/ADTG_1/DTTI0X_1/INT02_2 20
P4A/TIOB1_0 19
P49/TIOB0_0 18
INITX 17
P47/X1A 16
P46/X0A 15
C 13
25 P10/AN00
VCC 14
VSS 12
Note:
−
14
CONFIDENTIAL
The number after the underscore ("_") in a pin name such as XXX_1 and XXX_2 indicates the
relocated port number. The channel on such pin has multiple functions, each of which has its own
pin name. Use the Extended Port Function Register (EPFR) to select the pin to be used.
S6E1A1_DS710-00001-1v0-E, July 16, 2014
D a t a S h e e t
FPT-52P-M02
40 NC
41 P00
42 P01/SWCLK
43 P02
44 P03/SWDIO
45 P04/SCK3_0/INT03_2/TIOB0_1/IGTRG0_1
46 P0F/NMIX/SUBOUT_0/CROUT_1/RTCCO_0
47 P61/SOT3_0/TIOB2_2/DTTI0X_2/SCS11_2
48 P60/SIN3_0/TIOA2_2/INT15_1/IC00_0/IGTRG0_0/SCS10_2
49 P80/SCK1_2/FRCK0_1
50 P81/SOT1_2
51 P82/SIN1_2
52 VSS
(TOP VIEW)
VCC 1
39 P21/SIN0_0/INT06_1/TIOB1_1/IC01_1/BIN0_1/FRCK0_0
P50/INT00_0/AIN0_2/SIN3_1/IC01_0 2
38 P22/AN07/SOT0_0/TIOB2_0/IC03_1/ZIN0_1/INT05_1
P51/INT01_0/BIN0_2/SOT3_1 3
37 P23/AN06/SCK0_0/TIOA2_0/IC02_1/AIN0_1/INT04_1
P52/INT02_0/ZIN0_2/SCK3_1 4
36 NC
NC 5
35 AVSS
P39/DTTI0X_0/ADTG_2 6
34 AVRH
LQFP - 52
P3A/RTO00_0/TIOA0_1/AIN0_3/SUBOUT_2/RTCCO_2/INT03_0/SCK0_2 7
33 AVCC
P3B/RTO01_0/TIOA1_1/BIN0_3/SOT0_2/INT04_0/SCS31_2 8
32 P15/AN05/SOT0_1/SCS11_1/IC03_2/INT15_2
P3C/RTO02_0/TIOA2_1/ZIN0_3/SIN0_2/INT05_0/SCS30_2 9
31 P14/AN04/SIN0_1/SCS10_1/INT03_1/IC02_2
P3D/RTO03_0/TIOA3_1/INT06_0/AIN0_0/SCK3_2 10
30 P13/AN03/SCK1_1/SUBOUT_1/IC01_2/RTCCO_1/INT00_1
P3E/RTO04_0/TIOA0_0/BIN0_0/SOT3_2/INT15_0 11
29 P12/AN02/SOT1_1/IC00_2/INT01_1
P3F/RTO05_0/TIOA1_0/ZIN0_0/SIN3_2 12
28 P11/AN01/SIN1_1/INT02_1/FRCK0_2/IC02_0
27 P10/AN00
VSS 26
PE3/X1 25
PE2/X0 24
MD0 23
PE0/ADTG_1/DTTI0X_1/INT02_2 22
NC 21
P4A/TIOB1_0 20
P49/TIOB0_0 19
INITX 18
P47/X1A 17
P46/X0A 16
C 14
VCC 15
VSS 13
Note:
−
The number after the underscore ("_") in a pin name such as XXX_1 and XXX_2 indicates the
relocated port number. The channel on such pin has multiple functions, each of which has its own
pin name. Use the Extended Port Function Register (EPFR) to select the pin to be used.
July 16, 2014, S6E1A1_DS710-00001-1v0-E
CONFIDENTIAL
15
D a t a S h e e t
6. List of Pin Functions
List of pin numbers
The number after the underscore ("_") in a pin name such as XXX_1 and XXX_2 indicates the relocated port
number. The channel on such pin has multiple functions, each of which has its own pin name. Use the
Extended Port Function Register (EPFR) to select the pin to be used.
Pin no.
LQFP-52
1
LQFP-48
LQFP-32
QFN-48
QFN-32
1
-
Pin name
I/O circuit type
VCC
Pin state type
-
P50
INT00_0
2
2
-
AIN0_2
I*
J
I*
J
I*
J
E
I
F
J
F
J
SIN3_1
IC01_0
P51
INT01_0
3
3
BIN0_2
SOT3_1
P52
INT02_0
4
4
ZIN0_2
SCK3_1
P39
6
5
-
DTTI0X_0
ADTG_2
P3A
RTO00_0
TIOA0_1
AIN0_3
7
6
1
SUBOUT_2
RTCCO_2
INT03_0
SCK0_2
P3B
RTO01_0
TIOA1_1
8
7
2
BIN0_3
SOT0_2
INT04_0
SCS31_2
16
CONFIDENTIAL
S6E1A1_DS710-00001-1v0-E, July 16, 2014
D a t a S h e e t
Pin no.
LQFP-52
LQFP-48
LQFP-32
QFN-48
QFN-32
Pin name
I/O circuit type
Pin state type
F
J
F
J
F
J
F
I
P3C
RTO02_0
TIOA2_1
9
8
3
ZIN0_3
SIN0_2
INT05_0
SCS30_2
P3D
RTO03_0
TIOA3_1
10
9
4
INT06_0
AIN0_0
SCK3_2
P3E
RTO04_0
TIOA0_0
11
10
5
BIN0_0
SOT3_2
INT15_0
P3F
RTO05_0
12
11
6
TIOA1_0
ZIN0_0
SIN3_2
13
12
7
VSS
-
14
13
8
C
-
15
14
9
VCC
-
16
15
10
P46
D
E
D
F
B
C
E
I
E
I
C
J
X0A
P47
17
16
11
X1A
18
17
12
19
18
-
INITX
P49
TIOB0_0
P4A
20
19
TIOB1_0
PE0
ADTG_1
22
20
13
DTTI0X_1
INT02_2
July 16, 2014, S6E1A1_DS710-00001-1v0-E
CONFIDENTIAL
17
D a t a S h e e t
Pin no.
LQFP-48
LQFP-32
QFN-48
QFN-32
23
21
14
24
22
15
LQFP-52
Pin name
I/O circuit type
Pin state type
MD0
J
D
A
A
A
B
PE2
X0
PE3
25
23
16
X1
26
24
17
27
25
-
VSS
-
P10
G
K
H*
L
H*
L
H*
L
H*
L
H*
L
AN00
P11
AN01
SIN1_1
28
26
18
INT02_1
FRCK0_2
IC02_0
P12
AN02
29
27
19
SOT1_1
IC00_2
INT01_1
P13
AN03
SCK1_1
30
28
20
SUBOUT_1
IC01_2
RTCCO_1
INT00_1
P14
AN04
SIN0_1
31
29
SCS10_1
INT03_1
IC02_2
P15
AN05
SOT0_1
32
30
SCS11_1
IC03_2
INT15_2
33
31
21
AVCC
-
34
32
-
AVRH
-
18
CONFIDENTIAL
S6E1A1_DS710-00001-1v0-E, July 16, 2014
D a t a S h e e t
Pin no.
LQFP-52
35
LQFP-48
LQFP-32
QFN-48
QFN-32
33
22
Pin name
I/O circuit type
AVSS
Pin state type
-
P23
AN06
SCK0_0
37
34
23
TIOA2_0
G
L
G
L
E
J
E
I
E
H
E
I
E
H
I*
J
E
G
IC02_1
AIN0_1
INT04_1
P22
AN07
SOT0_0
38
35
24
TIOB2_0
IC03_1
ZIN0_1
INT05_1
P21
SIN0_0
INT06_1
39
36
25
TIOB1_1
IC01_1
BIN0_1
FRCK0_0
41
37
-
42
38
26
P00
P01
SWCLK
43
39
-
44
40
27
P02
P03
SWDIO
P04
SCK3_0
45
41
28
INT03_2
TIOB0_1
IGTRG0_1
P0F
NMIX
46
42
29
SUBOUT_0
CROUT_1
RTCCO_0
July 16, 2014, S6E1A1_DS710-00001-1v0-E
CONFIDENTIAL
19
D a t a S h e e t
Pin no.
LQFP-52
LQFP-48
LQFP-32
QFN-48
QFN-32
Pin name
I/O circuit type
Pin state type
I*
I
I*
J
K
I
K
I
K
I
P61
SOT3_0
47
43
30
TIOB2_2
DTTI0X_2
SCS11_2
P60
SIN3_0
TIOA2_2
48
44
31
INT15_1
IC00_0
IGTRG0_0
SCS10_2
P80
49
45
-
SCK1_2
FRCK0_1
P81
50
46
SOT1_2
P82
51
47
SIN1_2
52
48
32
VSS
-
5,21,36,40
-
-
NC
-
*: 5V tolerant I/O
20
CONFIDENTIAL
S6E1A1_DS710-00001-1v0-E, July 16, 2014
D a t a S h e e t
List of pin functions
The number after the underscore ("_") in a pin name such as XXX_1 and XXX_2 indicates the relocated port
number. The channel on such pin has multiple functions, each of which has its own pin name. Use the
Extended Port Function Register (EPFR) to select the pin to be used.
Pin no.
Pin function
Pin name
Function description
LQFP-52
LQFP-48
LQFP-32
QFN-48
QFN-32
A/D converter external trigger
22
20
13
input pin
6
5
-
AN00
27
25
-
AN01
28
26
18
AN02
29
27
19
ADTG_1
ADTG_2
ADC
AN03
A/D converter analog input pin.
30
28
20
AN04
ANxx describes ADC ch.xx.
31
29
-
AN05
32
30
-
AN06
37
34
23
AN07
38
35
24
11
10
5
7
6
1
19
18
-
45
41
28
12
11
6
8
7
2
20
19
-
TIOB1_1
39
36
25
TIOA2_0
37
34
23
9
8
3
48
44
31
38
35
24
TIOA0_0
Base timer ch.0 TIOA pin
TIOA0_1
Base Timer 0
TIOB0_0
Base timer ch.0 TIOB pin
TIOB0_1
TIOA1_0
Base timer ch.1 TIOA pin
TIOA1_1
Base Timer 1
TIOB1_0
Base timer ch.1 TIOB pin
TIOA2_1
Base Timer 2
Base timer ch.2 TIOA pin
TIOA2_2
TIOB2_0
Base timer ch.2 TIOB pin
TIOB2_2
Base Timer 3
47
43
30
TIOA3_1
Base timer ch.3 TIOA pin
10
9
4
SWCLK
Serial wire debug interface clock input pin
42
38
26
44
40
27
Debugger
SWDIO
Serial wire debug interface data
input / output pin
July 16, 2014, S6E1A1_DS710-00001-1v0-E
CONFIDENTIAL
21
D a t a S h e e t
Pin no.
Pin function
Pin name
Function description
LQFP-52
LQFP-48
LQFP-32
QFN-48
QFN-32
2
2
-
30
28
20
3
3
-
INT01_1
29
27
19
INT02_0
4
4
-
28
26
18
INT02_2
22
20
13
INT03_0
7
6
1
31
29
-
45
41
28
8
7
2
37
34
23
9
8
3
38
35
24
INT00_0
External interrupt request 00 input pin
INT00_1
INT01_0
External interrupt request 01 input pin
INT02_1
INT03_1
External
INT03_2
Interrupt
INT04_0
External interrupt request 02 input pin
External interrupt request 03 input pin
External interrupt request 04 input pin
INT04_1
INT05_0
External interrupt request 05 input pin
INT05_1
INT06_0
10
9
4
INT06_1
39
36
25
INT15_0
11
10
5
48
44
31
32
30
-
46
42
29
P00
41
37
-
P01
42
38
26
External interrupt request 06 input pin
INT15_1
External interrupt request 15 input pin
INT15_2
NMIX
Non-Maskable Interrupt input pin
P02
43
39
-
P03
44
40
27
P04
45
41
28
P0F
46
42
29
P10
27
25
-
P11
28
26
18
29
27
19
P13
30
28
20
P14
31
29
-
P15
32
30
-
P21
39
36
25
38
35
24
P23
37
34
23
P39
6
5
-
P3A
7
6
1
P3B
8
7
2
General-purpose I/O port 0
P12
General-purpose I/O port 1
GPIO
P22
P3C
22
CONFIDENTIAL
General-purpose I/O port 2
9
8
3
P3D
General-purpose I/O port 3
10
9
4
P3E
11
10
5
P3F
12
11
6
S6E1A1_DS710-00001-1v0-E, July 16, 2014
D a t a S h e e t
Pin no.
Pin function
Pin name
Function description
LQFP-52
LQFP-48
LQFP-32
QFN-48
QFN-32
16
15
10
17
16
11
P49
19
18
-
P4A
20
19
-
P50
2
2
-
3
3
-
P46
P47
General-purpose I/O port 4
P51
GPIO
General-purpose I/O port 5
P52
4
4
-
P60
48
44
31
P61
47
43
30
P80
49
45
-
50
46
-
P82
51
47
-
PE0*
22
20
13
24
22
15
PE3
25
23
16
SIN0_0
39
36
25
31
29
-
9
8
3
38
35
24
32
30
-
8
7
2
37
34
23
7
6
1
28
26
18
51
47
-
29
27
19
50
46
-
30
28
20
49
45
-
General-purpose I/O port 6
P81
PE2
SIN0_1
General-purpose I/O port 8
General-purpose I/O port E
Multi-function serial interface ch.0 input pin
SIN0_2
SOT0_0
(SDA0_0)
SOT0_1
Multi-function
Serial 0
(SDA0_1)
SOT0_2
(SDA0_2)
Multi-function serial interface ch.0 output pin.
This pin operates as SOT0 when used as a
UART/CSIO/LIN pin (operation mode 0 to 3)
and as SDA0 when used as an I2C pin
(operation mode 4).
SCK0_0
Multi-function serial interface ch.0 clock I/O pin.
(SCL0_0)
This pin operates as SCK0 when used as a
SCK0_2
(SCL0_2)
CSIO pin (operation mode 2) and as SCL0
when used as an I2C pin (operation mode 4).
SIN1_1
Multi-function serial interface ch.1 input pin
SIN1_2
SOT1_1
(SDA1_1)
SOT1_2
(SDA1_2)
Multi-function serial interface ch.1 output pin.
This pin operates as SOT1 when used as a
UART/CSIO/LIN pin (operation mode 0 to 3)
and as SDA1 when used as an I2C pin
(operation mode 4).
Multi-function
SCK1_1
Multi-function serial interface ch.1 clock I/O pin.
Serial 1
(SCL1_1)
This pin operates as SCK1 when used as a
SCK1_2
CSIO pin (operation mode 2) and as SCL1
(SCL1_2)
when used as an I2C pin (operation mode 4).
SCS10_1
Multi-function serial interface ch.1 serial chip
31
29
-
SCS10_2
select 0 output/input pin.
48
44
31
SCS11_1
Multi-function serial interface ch.1 serial chip
32
30
-
SCS11_2
select 1 output pin.
47
43
30
July 16, 2014, S6E1A1_DS710-00001-1v0-E
CONFIDENTIAL
23
D a t a S h e e t
Pin no.
Pin function
Pin name
Function description
SIN3_0
SIN3_1
Multi-function serial interface ch.3 input pin
SIN3_2
SOT3_0
(SDA3_0)
SOT3_1
(SDA3_1)
Multi-
SOT3_2
function
(SDA3_2)
Multi-function serial interface ch.3 output pin.
UART/CSIO/LIN pin (operation mode 0 to 3)
(operation mode 4).
SCK3_0
3
Multi-function serial interface ch.3 clock I/O pin.
SCK3_1
This pin operates as SCK3 when used as a
(SCL3_1)
CSIO (operation mode 2) and as SCL3 when
SCK3_2
used as an I2C pin (operation mode 4).
(SCL3_2)
24
CONFIDENTIAL
QFN-48
QFN-32
48
44
31
2
2
-
12
11
6
47
43
30
3
3
-
11
10
5
45
41
28
4
4
-
10
9
4
9
8
3
8
7
2
and as SDA3 when used as an I2C pin
(SCL3_0)
SCS31_2
LQFP-32
This pin operates as SOT3 when used as a
Serial
SCS30_2
LQFP-52
LQFP-48
Multi-function serial interface ch.3 serial chip
select 0 input/output pin.
Multi-function serial interface ch.3 serial chip
select 1 output pin.
S6E1A1_DS710-00001-1v0-E, July 16, 2014
D a t a S h e e t
Pin no.
Pin function
Pin name
Function description
LQFP-52
LQFP-48
LQFP-32
QFN-48
QFN-32
Input signal of waveform generator controlling
6
5
-
DTTI0X_1
RTO00 to RTO05 outputs of Multi-function
22
20
13
DTTI0X_2
Timer 0.
47
43
30
39
36
25
49
45
-
FRCK0_2
28
26
18
IC00_0
48
44
31
IC00_2
29
27
19
IC01_0
2
2
-
39
36
25
30
28
20
28
26
18
IC02_1
37
34
23
IC02_2
31
29
-
IC03_1
38
35
24
IC03_2
32
30
-
7
6
1
8
7
2
9
8
3
10
9
4
11
10
5
12
11
6
48
44
31
45
41
28
DTTI0X_0
FRCK0_0
FRCK0_1
16-bit free-run timer ch.0 external clock input
pin.
IC01_1
IC01_2
16-bit input capture input pin of Multi-function
timer 0.
IC02_0
ICxx describes channel number.
Waveform generator output pin of
RTO00_0
(PPG00_0)
Multi-function
Multi-function timer 0.
This pin operates as PPG00 when it is used in
PPG0 output mode.
Timer 0
Waveform generator output pin of
RTO01_0
(PPG00_0)
Multi-function timer 0.
This pin operates as PPG00 when it is used in
PPG0 output mode.
Waveform generator output pin of
RTO02_0
(PPG02_0)
Multi-function timer 0.
This pin operates as PPG02 when it is used in
PPG0 output mode.
Waveform generator output pin of
RTO03_0
(PPG02_0)
Multi-function timer 0.
This pin operates as PPG02 when it is used in
PPG0 output mode.
Waveform generator output pin of
RTO04_0
(PPG04_0)
Multi-function timer 0.
This pin operates as PPG04 when it is used in
PPG0 output mode.
Waveform generator output pin of
RTO05_0
(PPG04_0)
Multi-function timer 0.
This pin operates as PPG04 when it is used in
PPG0 output mode.
IGTRG0_0
PPG IGBT mode external trigger input pin
IGTRG0_1
July 16, 2014, S6E1A1_DS710-00001-1v0-E
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D a t a S h e e t
Pin no.
Pin function
Pin name
Function description
LQFP-52
LQFP-48
LQFP-32
QFN-48
QFN-32
10
9
4
37
34
23
AIN0_2
2
2
-
AIN0_3
7
6
1
Quadrature
BIN0_0
11
10
5
39
36
25
AIN0_0
AIN0_1
QPRC ch.0 AIN input pin
Position/
BIN0_1
Revolution
BIN0_2
3
3
-
Counter
BIN0_3
8
7
2
ZIN0_0
12
11
6
38
35
24
ZIN0_2
4
4
-
ZIN0_3
9
8
3
RTCCO_0
46
42
29
30
28
20
QPRC ch.0 BIN input pin
ZIN0_1
QPRC ch.0 ZIN input pin
RTCCO_1
0.5-seconds pulse output pin of Real-time clock
Real-time
RTCCO_2
7
6
1
clock
SUBOUT_0
46
42
29
30
28
20
7
6
1
18
17
12
23
21
14
SUBOUT_1
Sub clock output pin
SUBOUT_2
RESET
INITX
External Reset Input pin.
A reset is valid when INITX="L".
Mode 0 pin.
Mode
MD0
During normal operation, input MD0="L".
During serial programming to Flash memory,
input MD0="H".
VCC
Power supply pin
1
1
-
VCC
Power supply pin
15
14
9
VSS
GND pin
13
12
7
VSS
GND pin
26
24
17
VSS
GND pin
52
48
32
X0
Main clock (oscillation) input pin
24
22
15
X0A
Sub clock (oscillation) input pin
16
15
10
X1
Main clock (oscillation) I/O pin
25
23
16
X1A
Sub clock (oscillation) I/O pin
17
16
11
46
42
29
33
31
21
34
32
-
35
33
22
14
13
8
POWER
GND
CLOCK
CROUT_1
Analog
POWER
Analog
GND
C pin
AVCC
AVRH
AVSS
C
Built-in high-speed CR oscillation clock output
port
A/D converter analog power supply pin
A/D converter analog reference voltage input
pin
A/D converter analog reference voltage input
pin
Power supply stabilization capacitance pin
*: PE0 is an open drain pin, cannot output high.
26
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7. I/O Circuit Type
Type
Circuit
P-ch
P-ch
Remarks
Digital output
X1
N-ch
Digital output
R
It is possible to select the main
Pull-up resistor control
Digital input
Standby mode control
Clock input
A
oscillation / GPIO function
When the main oscillation is selected.
−
Oscillation feedback resistor
: Approximately 1MΩ
−
With standby mode control
When the GPIO is selected.
Standby mode control
Digital input
−
CMOS level output.
−
CMOS level hysteresis input
−
With pull-up resistor control
−
With standby mode control
−
Pull-up resistor
Standby mode control
: Approximately 50kΩ
−
IOH= -4mA, IOL= 4mA
−
CMOS level hysteresis input
−
Pull-up resistor
R
P-ch
P-ch
Digital output
N-ch
Digital output
X0
Pull-up resistor control
Pull-up resistor
B
Digital input
: Approximately 50kΩ
July 16, 2014, S6E1A1_DS710-00001-1v0-E
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D a t a S h e e t
Type
Circuit
Remarks
Digital input
C
Digital output
N-ch
P-ch
P-ch
−
Open drain output
−
CMOS level hysteresis input
Digital output
X1A
N-ch
Digital output
R
It is possible to select the sub oscillation /
Pull-up resistor control
Digital input
Standby mode control
Clock input
D
GPIO function
When the sub oscillation is selected.
−
Oscillation feedback resistor
: Approximately 5MΩ
−
With standby mode control
When the GPIO is selected.
Standby mode control
Digital input
−
CMOS level output.
−
CMOS level hysteresis input
−
With pull-up resistor control
−
With standby mode control
−
Pull-up resistor
Standby mode control
: Approximately 50kΩ
−
R
P-ch
P-ch
Digital output
N-ch
Digital output
IOH= -4mA, IOL= 4mA
X0A
Pull-up resistor control
28
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S6E1A1_DS710-00001-1v0-E, July 16, 2014
D a t a S h e e t
Type
Circuit
P-ch
E
P-ch
N-ch
Remarks
Digital output
−
CMOS level output
−
CMOS level hysteresis input
−
With pull-up resistor control
−
With standby mode control
−
Pull-up resistor
Digital output
R
: Approximately 50kΩ
−
IOH= -4mA, IOL= 4mA
−
When this pin is used as an I2C pin, the
digital output
Pull-up resistor control
P-ch transistor is always off
Digital input
Standby mode control
P-ch
P-ch
Digital output
−
CMOS level output
−
CMOS level hysteresis input
−
With pull-up resistor control
−
With standby mode control
−
Pull-up resistor
F
: Approximately 50kΩ
N-ch
Digital output
R
−
IOH= -12mA, IOL= 12mA
−
When this pin is used as an I2C pin, the
digital output
P-ch transistor is always off
Pull-up resistor control
Digital input
Standby mode control
July 16, 2014, S6E1A1_DS710-00001-1v0-E
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29
D a t a S h e e t
Type
Circuit
P-ch
P-ch
N-ch
Remarks
Digital output
Digital output
G
Pull-up resistor control
R
Digital input
−
CMOS level output
−
CMOS level hysteresis input
−
With input control
−
Analog input
−
With pull-up resistor control
−
With standby mode control
−
Pull-up resistor
: Approximately 50kΩ
−
IOH= -4mA, IOL= 4mA
−
When this pin is used as an I2C pin, the
digital output
Standby mode control
P-ch transistor is always off
Analog input
Input control
P-ch
P-ch
N-ch
Digital output
Digital output
H
−
CMOS level output
−
CMOS level hysteresis input
−
With input control
−
Analog input
−
5V tolerant
−
With pull-up resistor control
−
With standby mode control
−
Pull-up resistor
: Approximately 50kΩ
R
Pull-up resistor control
Digital input
Standby mode control
−
IOH= -4mA, IOL= 4mA
−
Available to control of PZR registers.
−
When this pin is used as an I2C pin, the
digital output
P-ch transistor is always off
Analog input
Input control
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S6E1A1_DS710-00001-1v0-E, July 16, 2014
D a t a S h e e t
Type
Circuit
P-ch
P-ch
Remarks
Digital output
I
N-ch
−
CMOS level output
−
CMOS level hysteresis input
−
5V tolerant
−
With pull-up resistor control
−
With standby mode control
−
Pull-up resistor
: Approximately 50kΩ
Digital output
R
−
IOH= -4mA, IOL= 4mA
−
Available to control PZR registers
−
When this pin is used as an I2C pin, the
digital output
Pull-up resistor control
P-ch transistor is always off
Digital input
Standby mode control
Mode input
J
P-ch
Digital output
K
N-ch
CMOS level hysteresis input
Digital output
R
−
CMOS level output
−
CMOS level hysteresis input
−
With standby mode control
−
IOH= -4mA, IOL= 4mA
−
When this pin is used as an I2C pin, the
digital output
P-ch transistor is always off
Digital input
Standby mode control
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8. Handling Precautions
Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly
affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This
page describes precautions that must be observed to minimize the chance of failure and to obtain higher
reliability from your Spansion semiconductor devices.
8.1
Precautions for Product Design
This section describes precautions when designing electronic equipment using semiconductor devices.
Absolute Maximum Ratings
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature,
etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings.
Recommended Operating Conditions
Recommended operating conditions are normal operating ranges for the semiconductor device. All the
device's electrical characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside these
ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data
sheet. Users considering application outside the listed conditions are advised to contact their sales
representative beforehand.
Processing and Protection of Pins
These precautions must be followed when handling the pins which connect semiconductor devices to power
supply and input/output functions.
1. Preventing Over-Voltage and Over-Current Conditions
Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause
deterioration within the device, and in extreme cases leads to permanent damage of the device. Try
to prevent such overvoltage or over-current conditions at the design stage.
2. Protection of Output Pins
Shorting of output pins to supply pins or other output pins, or connection to large capacitance can
cause large current flows. Such conditions if present for extended periods of time can damage the
device.
Therefore, avoid this type of connection.
3. Handling of Unused Input Pins
Unconnected input pins with very high impedance levels can adversely affect stability of operation.
Such pins should be connected through an appropriate resistance to a power supply pin or ground
pin.
Code: DS00-00004-2Ea
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Latch-up
Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When
subjected to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may be
formed, causing large current levels in excess of several hundred mA to flow continuously at the power
supply pin. This condition is called latch-up.
CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but
can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the
following:
1. Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include
attention to abnormal noise, surge levels, etc.
2. Be sure that abnormal current flows do not occur during the power-on sequence.
Observance of Safety Regulations and Standards
Most countries in the world have established standards and regulations regarding safety, protection from
electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards
in the design of products.
Fail-Safe Design
Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage
or loss from such failures by incorporating safety design measures into your facility and equipment such as
redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions.
Precautions Related to Usage of Devices
Spansion semiconductor devices are intended for use in standard applications (computers, office
automation and other office equipment, industrial, communications, and measurement equipment, personal
or household devices, etc.).
CAUTION: Customers considering the use of our products in special applications where failure or abnormal
operation may directly affect human lives or cause physical injury or property damage, or where extremely
high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor
repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with
sales representatives before such use. The company will not be responsible for damages arising from such
use without prior approval.
8.2
Precautions for Package Mounting
Package mounting may be either lead insertion type or surface mount type. In either case, for heat
resistance during soldering, you should only mount under Spansion's recommended conditions. For detailed
information about mount conditions, contact your sales representative.
Lead Insertion Type
Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct
soldering on the board, or mounting by using a socket.
Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board
and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the soldering
process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for storage
temperature. Mounting processes should conform to Spansion recommended mounting conditions.
If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can
lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment
of socket contacts and IC leads be verified before mounting.
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D a t a S h e e t
Surface Mount Type
Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads
are more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results
in increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges.
You must use appropriate mounting techniques. Spansion recommends the solder reflow method, and has
established a ranking of mounting conditions for each product. Users are advised to mount packages in
accordance with Spansion ranking of recommended conditions.
Lead-Free Packaging
CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic
soldering, junction strength may be reduced under some conditions of use.
Storage of Semiconductor Devices
Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions
will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed
moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To
prevent, do the following:
1. Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product.
Store products in locations where temperature changes are slight.
2. Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at
temperatures between 5°C and 30°C.
When you open Dry Package that recommends humidity 40% to 70% relative humidity.
3. When necessary, Spansion packages semiconductor devices in highly moisture-resistant aluminum
laminate bags, with a silica gel desiccant. Devices should be sealed in their aluminum laminate bags for
storage.
4. Avoid storing packages where they are exposed to corrosive gases or high levels of dust.
Baking
Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Spansion
recommended conditions for baking.
Condition: 125°C/24 h
Static Electricity
Because semiconductor devices are particularly susceptible to damage by static electricity, you must take
the following precautions:
1. Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion
generation may be needed to remove electricity.
2. Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment.
3. Eliminate static body electricity by the use of rings or bracelets connected to ground through high
resistance (on the level of 1 MΩ).
Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize
shock loads is recommended.
4. Ground all fixtures and instruments, or protect with anti-static measures.
5. Avoid the use of styrofoam or other highly static-prone materials for storage of completed board
assemblies.
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D a t a S h e e t
8.3
Precautions for Use Environment
Reliability of semiconductor devices depends on ambient temperature and other conditions as described
above.
For reliable performance, do the following:
1. Humidity
Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If
high humidity levels are anticipated, consider anti-humidity processing.
2. Discharge of Static Electricity
When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal
operation. In such cases, use anti-static measures or processing to prevent discharges.
3. Corrosive Gases, Dust, or Oil
Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will
adversely affect the device. If you use devices in such conditions, consider ways to prevent such
exposure or to protect the devices.
4. Radiation, Including Cosmic Radiation
Most devices are not designed for environments involving exposure to radiation or cosmic radiation.
Users should provide shielding as appropriate.
5. Smoke, Flame
CAUTION: Plastic molded devices are flammable, and therefore should not be used near
combustible substances. If devices begin to smoke or burn, there is danger of the release of toxic
gases.
Customers considering the use of Spansion products in other special environmental conditions should
consult with sales representatives.
Please check the latest handling precautions at the following URL.
http://www.spansion.com/fjdocuments/fj/datasheet/e-ds/DS00-00004.pdf
July 16, 2014, S6E1A1_DS710-00001-1v0-E
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D a t a S h e e t
9. Handling Devices
Power supply pins
In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected within
the device in order to prevent malfunctions such as latch-up. However, all of these pins should be connected
externally to the power supply or ground lines in order to reduce electromagnetic emission levels, to prevent
abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total
output current rating.
Moreover, connect the current supply source with each Power supply pin and GND pin of this device at low
impedance. It is also advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass
capacitor between each Power supply pin and GND pin near this device.
Stabilizing supply voltage
A malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is
within the recommended operating conditions of the VCC power supply voltage. As a rule, with voltage
stabilization, suppress the voltage fluctuation so that the fluctuation in VCC ripple (peak-to-peak value) at
the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the VCC value in the recommended
operating conditions, and the transient fluctuation rate does not exceed 0.1 V/μs when there is a momentary
fluctuation on switching the power supply.
Crystal oscillator circuit
Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit
board so that X0/X1, X0A/X1A pins, the crystal oscillator, and the bypass capacitor to ground are located as
close to the device as possible.
It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins
are surrounded by ground plane as this is expected to produce stable operation.
Evaluate oscillation of your using crystal oscillator by your mount board.
Sub crystal oscillator
This series sub oscillator circuit is low gain to keep the low current consumption. The crystal oscillator to fill
the following conditions is recommended for sub crystal oscillator to stabilize the oscillation.
Surface mount type
Size: More than 3.2mm × 1.5mm
Load capacitance: Approximately 6pF to 7pF
Lead type
Load capacitance: Approximately 6pF to 7pF
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Using an external clock
When using an external clock as an input of the main clock, set X0/X1 to the external clock input, and input
the clock to X0. X1(PE3) can be used as a general-purpose I/O port.
Similarly, when using an external clock as an input of the sub clock, set X0A/X1A to the external clock input,
and input the clock to X0A. X1A (P47) can be used as a general-purpose I/O port.
Example of Using an External Clock
Device
X0(X0A)
Can be used as
general-purpose
I/O ports.
X1(PE3),
X1A (P47)
Set as
External clock
input
2
Handling when using Multi-function serial pin as I C pin
2
If it is using the multi-function serial pin as I C pins, P-ch transistor of digital output is always disabled.
2
However, I C pins need to keep the electrical characteristic like other pins and not to connect to the external
2
I C bus system with power OFF.
C Pin
This series contains the regulator. Be sure to connect a smoothing capacitor (C S) for the regulator between
the C pin and the GND pin. Please use a ceramic capacitor or a capacitor of equivalent frequency
characteristics as a smoothing capacitor.
However, some laminated ceramic capacitors have the characteristics of capacitance variation due to
thermal fluctuation (F characteristics and Y5V characteristics). Please select the capacitor that meets the
specifications in the operating conditions to use by evaluating the temperature characteristics of a capacitor.
A smoothing capacitor of about 4.7μF would be recommended for this series.
C
Device
CS
VSS
GND
Mode pins (MD0)
Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the
pull-up/down resistance stays low, as well as the distance between the mode pins and VCC pins or VSS
pins is as short as possible and the connection impedance is low, when the pins are pulled-up/down such as
for switching the pin level and rewriting the Flash memory data. It is because of preventing the device
erroneously switching to test mode due to noise.
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D a t a S h e e t
Notes on power-on
Turn power on/off in the following order or at the same time.
Turning on :
VCC → AVCC → AVRH
Turning off :
AVRH →AVCC →VCC
Serial Communication
There is a possibility to receive wrong data due to the noise or other causes on the serial communication.
Therefore, design a printed circuit board so as to avoid noise.
Consider the case of receiving wrong data due to noise, perform error detection such as by applying a
checksum of data at the end. If an error is detected, retransmit the data.
Differences in features among the products with different memory sizes and between
Flash memory products and MASK products
The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and
oscillation characteristics among the products with different memory sizes and between Flash memory
products and MASK products are different because chip layout and memory structures are different.
If you are switching to use a different product of the same series, please make sure to evaluate the electric
characteristics.
Pull-Up function of 5V tolerant I/O
Please do not input the signal more than VCC voltage at the time of Pull-Up function use of 5V tolerant I/O.
Handling when using debug pins
When debug pins (SWDIO/SWCLK) are set to GPIO or other peripheral functions, only set them as output,
do not set them as input.
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10. Block Diagram
S6E1A11/S6E1A12
SWCLK,
SWDIO
To PIN-Function-Ctrl
SW-DP
Fast
GPIO
Cortex-M0+ Core
@40MHz(Max)
AHB-APB Bridge:
APB0(Max 40MHz)
System ROM
table
Dual-Timer
WatchDog Timer
(Software)
Clock Reset
Generator
WatchDog Timer
(Hardware)
Multi-layer AHB (Max 40MHz)
Bit Band
Wrapper
NVIC
INITX
On-Chip SRAM
6 Kbyte
MTB
Flash I/F
On-Chip Flash
56 Kbyte/
88 Kbyte
Security
DMAC
2ch.
CSV
CLK
X0A
X1A
Main
Osc
Sub
Osc
PLL
CR
4MHz
Source Clock
AHB-AHB
Bridge
X0
X1
CR
100kHz
CROUT
AVCC,
AVSS
AVRH
(only 48/52pin
PKG)
12-bit A/D Converter
Power-On
Reset
Unit 0
ANxx
TIOAx
TIOBx
AINx
BINx
ZINx
Base Timer
16-bit 4ch./
32-bit 2ch.
QPRC
1ch.
A/D Activation
Compare 6ch.
IC0x
FRCKx
16-bit Input Capture
4ch.
16-bit Free-run Timer
3ch.
AHB-APB Bridge : APB1 (Max 40MHz)
ADTG
LVD Ctrl
LVD
IRQ-Monitor
Regulator
Watch Counter
RTCCO,
SUBOUT
Real-Time Clock
External Interrupt
Controller
8pin + NMI
INTx
MODE-Ctrl
MD0
NMIX
Low-speed CR
Prescaler
To Fast GPIO
Peripheral Clock Gating
16-bit Output
Compare 6ch.
DTTI0X
RTO0x
Waveform Generator
3ch.
C
GPIO
PIN-Function-Ctrl
P0x,
P1x,
.
.
.
Pxx
SCKx
IGTRGx
16-bit PPG
3ch.
Multi-function Serial I/F
3ch.
(with FIFO)
Multi-function Timer
SINx
SOTx
SCSx
11. Memory Size
See "Memory size" in "3. Product Lineup" to confirm the memory size.
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12. Memory Map
Memory map (1)
0x41FF_FFFF
Peripheral area
0xFFFF_FFFF
Reserved
0xF802_0000
0xF800_0000
Fast GPIO
(Single-cycle I/O port)
Reserved
Reserved
0xF000_3000
ROM table
0xF000_2000
0xF000_1000
0xF000_0000
MTB_DWT
MTB registers(SFR)
Cortex-M0+ Private
Peripherals
0xE000_0000
0x4006_1000
0x4006_0000
0x4003_C800
0x4003_C100
0x4003_C000
0x4003_B000
0x4003_A000
0x4003_9000
0x4003_8000
32 Mbytes Bit Band alias
0x4200_0000
Peripherals
0x4000_0000
0x4003_5100
0x4003_5000
0x4003_4000
0x4003_3000
0x4003_2000
0x4003_1000
0x4003_0000
0x4002_F000
0x4002_E000
32 Mbytes Bit Band alias
0x2200_0000
Reserved
RTC
Watch Counter
Reserved
MFS
LVD
Reserved
GPIO
Reserved
INT-Req READ
EXTI
Reserved
CR Trim
Reserved
Reserved
0x2400_0000
Peripheral Clock Gating
Low Speed CR Prescaler
Reserved
Reserved
0x4400_0000
DMAC
Reserved
0x4002_8000
0x4002_7000
0x4002_6000
0x4002_5000
0x4002_4000
A/DC
QPRC
Base Timer
PPG
0x2008_0000
SRAM
Reserved
0x2000_0000
0x4002_1000
0x4002_0000
Reserved
Reserved
See
map(2)"
See "lMemory
“Memory map
(2)” forfor
the memory
memory size
the
sizedetails.
details.
0x4001_6000
0x4001_5000
CR Trim
Security
Flash
0x4001_3000
0x4001_2000
0x4001_1000
0x4001_0000
CONFIDENTIAL
SW WDT
HW WDT
Clock/Reset
Reserved
0x4000_1000
0x4000_0000
40
Dual Timer
Reserved
0x0010_0008
0x0010_0004
0x0010_0000
0x0000_0000
MFT unit 0
Flash I/F
S6E1A1_DS710-00001-1v0-E, July 16, 2014
D a t a S h e e t
Memory map (2)
S6E1A12B0A
S6E1A12C0A
0x2008_0000
S6E1A11B0A
S6E1A11C0A
0x2008_0000
Reserved
Reserved
0x2000_1800
0x2000_1800
SRAM
6K bytes
SRAM
6K bytes
0x2000_0000
0x2000_0000
Reserved
0x0010_0004
0x0010_0000
Reserved
CR trimming
Security
0x0010_0004
0x0010_0000
CR trimming
Security
Reserved
Reserved
0x0001_6000
0x0000_E000
Flash 88K bytes
*
Flash 56Kbytes *
0x0000_0000
0x0000_0000
*: See "S6E1A11/S6E1A12 Series Flash Programming Manual" to check details of the Flash memory.
July 16, 2014, S6E1A1_DS710-00001-1v0-E
CONFIDENTIAL
41
D a t a S h e e t
Peripheral Address Map
Start address
End address
0x4000_0000
0x4000_0FFF
Bus
Peripheral
Flash memory I/F register
AHB
0x4000_1000
0x4000_FFFF
Reserved
0x4001_0000
0x4001_0FFF
Clock/Reset Control
0x4001_1000
0x4001_1FFF
Hardware Watchdog Timer
0x4001_2000
0x4001_2FFF
Software Watchdog Timer
APB0
0x4001_3000
0x4001_4FFF
Reserved
0x4001_5000
0x4001_5FFF
Dual-Timer
0x4001_6000
0x4001_FFFF
Reserved
0x4002_0000
0x4002_0FFF
Multi-function Timer unit0
0x4002_1000
0x4002_3FFF
Reserved
0x4002_4000
0x4002_4FFF
PPG
0x4002_5000
0x4002_5FFF
Base Timer
0x4002_6000
0x4002_6FFF
Quadrature Position/Revolution Counter
0x4002_7000
0x4002_7FFF
A/D Converter
0x4002_8000
0x4002_DFFF
Reserved
0x4002_E000
0x4002_EFFF
Built-in CR trimming
0x4002_F000
0x4002_FFFF
Reserved
0x4003_0000
0x4003_0FFF
External Interrupt Controller
0x4003_1000
0x4003_1FFF
Interrupt Request Batch-Read Function
0x4003_2000
0x4003_2FFF
0x4003_3000
0x4003_3FFF
GPIO
0x4003_4000
0x4003_4FFF
Reserved
0x4003_5000
0x4003_57FF
Low-Voltage Detection
0x4003_5800
0x4003_7FFF
Reserved
0x4003_8000
0x4003_8FFF
Multi-function Serial Interface
0x4003_9000
0x4003_9FFF
Reserved
0x4003_A000
0x4003_AFFF
Watch Counter
0x4003_B000
0x4003_BFFF
Real-time clock
0x4003_C000
0x4003_C0FF
Low-speed CR Prescaler
0x4003_C100
0x4003_C7FF
Peripheral Clock Gating
0x4003_C800
0x4003_FFFF
Reserved
0x4004_0000
0x4005_FFFF
Reserved
0x4006_0000
0x4006_0FFF
0x4006_1000
0x41FF_FFFF
42
CONFIDENTIAL
APB1
AHB
Reserved
DMAC register
Reserved
S6E1A1_DS710-00001-1v0-E, July 16, 2014
D a t a S h e e t
13. Pin Status in Each CPU State
The terms used for pin status have the following meanings.
INITX=0
This is the period when the INITX pin is the "L" level.
INITX=1
This is the period when the INITX pin is the "H" level.
SPL=0
This is the status that the standby pin level setting bit (SPL) in the Standby Mode Control Register
(STB_CTL) is set to "0".
SPL=1
This is the status that the standby pin level setting bit (SPL) in the Standby Mode Control Register
(STB_CTL) is set to "1".
Input enabled
Indicates that the input function can be used.
Internal input fixed at "0"
This is the status that the input function cannot be used. Internal input is fixed at "L".
Hi-Z
Indicates that the pin drive transistor is disabled and the pin is put in the Hi-Z state.
Setting disabled
Indicates that the setting is disabled.
Maintain previous state
Maintains the state in which a pin was immediately prior to entering the current mode.
If a built-in peripheral function is operating, the output follows the peripheral function.
If the pin is being used as a port, that output is maintained.
Analog input is enabled
Indicates that the analog input is enabled.
July 16, 2014, S6E1A1_DS710-00001-1v0-E
CONFIDENTIAL
43
D a t a S h e e t
List of Pin Status
State upon
Pin status type
power-on
reset or
low-voltage
Function group
A
input
State upon
State in Run
State in TIMER mode,
device internal
mode or SLEEP
RTC mode, or
reset
mode
STOP mode
detection
Power supply
unstable
GPIO selected
State at INITX
Power supply stable
Power supply
stable
-
INITX = 0
INITX = 1
INITX = 1
-
-
-
-
Setting
Setting
disabled
disabled
Input enabled
Input enabled
Setting
Setting
Setting disabled
Power supply stable
INITX = 1
SPL = 0
SPL = 1
Maintain
Maintain
Hi-Z / Internal
previous state
previous state
input fixed at "0"
Input enabled
Input enabled
Input enabled
Maintain
Maintain
Hi-Z / Internal
previous state
previous state
input fixed at "0"
Maintain
Maintain
Hi-Z / Internal
previous state
previous state
input fixed at "0"
Maintain
Maintain
Maintain
previous
previous
previous
state/When
state/When
state/When
oscillation
oscillation
oscillation
Main crystal
oscillator input pin/
External main clock
Input enabled
input selected
GPIO selected
disabled
disabled
External main clock
Setting
Setting
input selected
disabled
disabled
B
Hi-Z /
Main crystal
oscillator output pin
Internal input
fixed at "0"/
Input enabled
C
INITX input pin
D
Mode input pin
GPIO selected
E
Hi-Z / Internal
input fixed at
"0"
Setting disabled
Setting disabled
Hi-Z / Internal
input fixed at "0"
1
stops* ,
1
stops* ,
stops*1,
Hi-Z /
Hi-Z /
Hi-Z /
Internal input
Internal input
Internal input
fixed at "0"
fixed at "0"
fixed at "0"
Pull-up / Input
Pull-up / Input
Pull-up / Input
Pull-up / Input
Pull-up / Input
Pull-up / Input
enabled
enabled
enabled
enabled
enabled
enabled
Input enabled
Input enabled
Input enabled
Input enabled
Input enabled
Input enabled
Setting
Setting
Maintain
Maintain
Hi-Z / Internal
disabled
disabled
previous state
previous state
input fixed at "0"
Input enabled
Input enabled
Input enabled
Input enabled
Input enabled
Setting disabled
Sub crystal
oscillator input pin /
External sub clock
Input enabled
input selected
GPIO selected
Setting
Setting
disabled
disabled
External sub clock
Setting
Setting
input selected
disabled
disabled
Setting disabled
Setting disabled
Maintain
Maintain
Hi-Z / Internal
previous state
previous state
input fixed at "0"
Maintain
Maintain
Hi-Z / Internal
previous state
previous state
input fixed at "0"
Maintain
Maintain
F
Hi-Z /
Sub crystal
Internal input
oscillator output pin
fixed at "0"/
Input enabled
44
CONFIDENTIAL
Hi-Z / Internal
input fixed at
"0"
Hi-Z / Internal
Maintain
input fixed at "0"
previous state
previous
previous
state/When
state/When
oscillation
oscillation
stops*2,
stops*2,
Hi-Z / Internal
Hi-Z / Internal
input fixed at "0"
input fixed at "0"
S6E1A1_DS710-00001-1v0-E, July 16, 2014
D a t a S h e e t
State upon
Pin status type
power-on
reset or
low-voltage
Function group
G
unstable
State in Run
State in TIMER mode,
device internal
mode or SLEEP
RTC mode, or
reset
mode
STOP mode
Power supply stable
selected
GPIO selected
INITX = 0
INITX = 1
INITX = 1
-
-
-
Setting
Setting
disabled
disabled
Hi-Z
Hi-Z
Hi-Z /
Input enabled
Input enabled
Pull-up / Input
Pull-up / Input
enabled
enabled
Setting
Setting
disabled
Hi-Z
Power supply stable
INITX = 1
SPL = 0
Setting disabled
SPL = 1
Maintain
Setting disabled
Hi-Z /
disabled
Resource selected
I
stable
-
GPIO selected
Serial wire debug
Power supply
-
Resource other than
the above selected
H
input
State upon
detection
Power supply
NMIX selected
State at INITX
previous state
Maintain
Maintain
previous state
previous state
Hi-Z / Internal
input fixed at "0"
Maintain
Maintain
Maintain
previous state
previous state
previous state
Hi-Z / Internal
input fixed at "0"
Hi-Z /
Hi-Z /
Maintain
Maintain
Hi-Z / Internal
Input enabled
Input enabled
previous state
previous state
input fixed at "0"
GPIO selected
J
External interrupt
Setting
Setting
enabled selected
disabled
disabled
Resource other than
the above selected
Hi-Z
Maintain
Setting disabled
previous state
Maintain
Maintain
previous state
previous state
Hi-Z /
Hi-Z /
Input enabled
Input enabled
Hi-Z / Internal
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Internal input
Internal input
Internal input
Internal input
Internal input
fixed at "0" /
fixed at "0" /
fixed at "0" /
fixed at "0" /
fixed at "0" /
Analog input
Analog input
Analog input
Analog input
Analog input
enabled
enabled
enabled
enabled
enabled
input fixed at "0"
GPIO selected
Analog input
selected
Hi-Z
K
Resource other than
the above selected
Setting
Setting
disabled
disabled
Setting disabled
Maintain
Maintain
Hi-Z / Internal
previous state
previous state
input fixed at "0"
GPIO selected
Analog input
selected
L
Hi-Z
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Internal input
Internal input
Internal input
Internal input
Internal input
fixed at "0" /
fixed at "0" /
fixed at "0" /
fixed at "0" /
fixed at "0" /
Analog input
Analog input
Analog input
Analog input
Analog input
enabled
enabled
enabled
enabled
enabled
External interrupt
Maintain
enabled selected
previous state
Resource other than
Setting
Setting
the above selected
disabled
disabled
GPIO selected
Setting disabled
Maintain
Maintain
previous state
previous state
Hi-Z / Internal
input fixed at "0"
*1: Oscillation stops in Sub timer mode, Low-speed CR timer mode, STOP mode, RTC mode.
*2: Oscillation stops in STOP mode.
July 16, 2014, S6E1A1_DS710-00001-1v0-E
CONFIDENTIAL
45
D a t a S h e e t
14. Electrical Characteristics
14.1 Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
Min
Max
VCC
VSS - 0.5
VSS + 6.5
V
Analog power supply voltage* *
AVCC
VSS - 0.5
VSS + 6.5
V
Analog reference voltage*1, *3
AVRH
VSS - 0.5
VSS + 6.5
V
Power supply voltage*1, *2
1, 3
Input voltage*1
VI
VSS - 0.5
VSS - 0.5
Analog pin input voltage*1
VIA
VSS - 0.5
Output voltage*1
VO
VSS - 0.5
"L" level maximum output current*4
IOL
-
IOLAV
-
"L" level total maximum output current
∑IOL
"L" level total average output current*6
∑IOLAV
"L" level average output current*5
"H" level maximum output current*4
"H" level average output current*5
IOH
VCC + 0.5
(≤ 6.5 V)
VSS + 6.5
AVCC + 0.5
(≤ 6.5 V)
Vcc + 0.5
(≤ 6.5 V)
Remarks
Only
S6E1A1xC0A
V
V
5V tolerant
V
V
10
mA
4 mA type
20
mA
12 mA type
4
mA
4 mA type
12
mA
12 mA type
-
100
mA
-
50
mA
- 10
mA
4 mA type
- 20
mA
12 mA type
-4
mA
4 mA type
- 12
mA
12 mA type
-
IOHAV
-
"H" level total maximum output current
∑IOH
-
- 100
mA
"H" level total average output current*6
∑IOHAV
-
- 50
mA
Power consumption
PD
-
200
mW
Storage temperature
TSTG
- 55
+ 150
°C
*1: These parameters are based on the condition that V SS = AVss = 0 V.
*2: Vcc must not drop below VSS - 0.5 V.
*3: Ensure that the voltage does not to exceed VCC + 0.5 V at power-on.
*4: The maximum output current is the peak value for a single pin.
*5: The average output is the average current for a single pin over a period of 100 ms.
*6: The total average output current is the average current for all pins over a period of 100 ms.
<WARNING>
−
Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
46
CONFIDENTIAL
S6E1A1_DS710-00001-1v0-E, July 16, 2014
D a t a S h e e t
14.2 Recommended Operating Conditions
(VSS = AVSS = 0.0V)
Parameter
Symbol
Conditions
Power supply voltage
VCC
Analog power supply voltage
Analog reference voltage
Value
Unit
Min
Max
-
2.7*2
5.5
V
AVCC
-
2.7
5.5
V
AVRH
-
2.7
AVCC
V
Smoothing capacitor
CS
-
1
10
μF
Operating temperature
Ta
-
- 40
+ 105
°C
Remarks
AVCC = VCC
Only
S6E1A1xC0A
For regulator*1
*1: See "C Pin" in "9. Handling Devices" for the connection of the smoothing capacitor.
*2: In between less than the minimum power supply voltage and low voltage reset/interrupt detection voltage
or more, instruction execution and low voltage detection function by built-in High-speed CR(including Main
PLL is used) or built-in Low-speed CR is possible to operate only.
<WARNING>
1. The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device's electrical characteristics are warranted when the device is
operated within these ranges.
2. Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
3. No warranty is made with respect to uses, operating conditions, or combinations not represented on the
data sheet.
4. Users considering application outside the listed conditions are advised to contact their representatives
beforehand.
July 16, 2014, S6E1A1_DS710-00001-1v0-E
CONFIDENTIAL
47
D a t a S h e e t
14.3 DC Characteristics
14.3.1 Current Rating
Symbol
Frequency*4
Typ*1
Max*2
4MHz
0.7
1.5
NOP code executed
8MHz
1.3
2.3
Built-in high speed CR stopped
20MHz
2.8
4.0
40MHz
5.7
7.3
4MHz external clock input, PLL ON*
4MHz
0.6
1.4
Benchmark code executed
8MHz
1.2
2.1
Built-in high speed CR stopped
20MHz
2.6
3.7
PCLK1 stopped
40MHz
4.8
6.3
4MHz crystal oscillation, PLL ON*8
4MHz
1.0
2.9
NOP code executed
8MHz
1.7
3.6
Built-in high speed CR stopped
20MHz
3.4
5.6
40MHz
5.7
8.2
4MHz external clock input, PLL ON*
4MHz
0.5
1.2
NOP code executed
8MHz
0.9
1.8
Built-in high speed CR stopped
20MHz
2.0
2.9
All peripheral clock stopped by CKENx
40MHz
3.7
4.8
40MHz
2.8
4MHz
4MHz external clock input, PLL ON*8
All peripheral clock stopped by CKENx
8
Run mode,
code executed from
Flash
All peripheral clock stopped by CKENx
8
Run mode,
Icc
(VCC)
code executed from
RAM
Run mode,
code executed from
Flash
Value
HCLK
Conditions
(Pin name)
Unit
Remarks
mA
*3
mA
*3
mA
*3
mA
*3
3.7
mA
*3,*6,*7
0.8
1.5
mA
*3
32kHz
65
900
μA
*3
100kHz
73
920
μA
*3
mA
*3
4MHz external clock input, PLL ON
NOP code executed
Built-in high speed CR stopped
PCLK1 stopped
Built-in high speed CR*5
NOP code executed
All peripheral clock stopped by CKENx
Run mode,
code executed from
Flash
32kHz crystal oscillation
NOP code executed
All peripheral clock stopped by CKENx
Built-in low speed CR
NOP code executed
All peripheral clock stopped by CKENx
Iccs
(VCC)
4MHz
0.4
1.2
4MHz external clock input, PLL ON*8
8MHz
0.7
1.6
All peripheral clock stopped by CKENx
20MHz
1.5
2.4
40MHz
2.7
3.7
4MHz
0.5
1.2
mA
*3
32kHz
63
880
μA
*3
100kHz
66
890
μA
*3
5
SLEEP operation
Built-in high speed CR*
All peripheral clock stopped by CKENx
32kHz crystal oscillation
All peripheral clock stopped by CKENx
Built-in low speed CR
All peripheral clock stopped by CKENx
*1 : Ta=+25℃,VCC=3.0V
*2 : Ta=+105℃,VCC=5.5V
*3 : All ports are fixed
*4 : PCLK0=HCLK/8
*5 : The frequency is set to 4MHz by trimming
*6 : Flash sync down is set to FRWTR.RWT = 11 and FSYNDN.SD = 1111
*7 : VCC=2.7V
*8 : When HCLK=4MHz, PLL OFF
48
CONFIDENTIAL
S6E1A1_DS710-00001-1v0-E, July 16, 2014
D a t a S h e e t
Symbol
Conditions
(Pin name)
Value
Unit
Remarks
Typ
Max
5.6
28
μA
*1
6.7
30
μA
*1
-
540
μA
*1
12
42
μA
*1
13
44
μA
*1
-
730
μA
*1
9
36
μA
*1
10
38
μA
*1
-
570
μA
*1
Ta=25℃
Vcc=3.0V
LVD off
ICCH
(VCC)
Ta=25℃
STOP mode
Vcc=5.0V
LVD off
Ta=105℃
Vcc=5.5V
LVD off
Ta=25℃
Vcc=3.0V
32kHz crystal oscillation
LVD off
Ta=25℃
ICCT
(VCC)
Sub timer mode
Vcc=5.0V
32kHz crystal oscillation
LVD off
Ta=105℃
Vcc=5.5V
32kHz crystal oscillation
LVD off
Ta=25℃
Vcc=3.0V
32kHz crystal oscillation
LVD off
Ta=25℃
ICCR
(VCC)
RTC mode
Vcc=5.0V
32kHz crystal oscillation
LVD off
Ta=105℃
Vcc=5.5V
32kHz crystal oscillation
LVD off
*1: All ports are fixed.
July 16, 2014, S6E1A1_DS710-00001-1v0-E
CONFIDENTIAL
49
D a t a S h e e t
LVD current
(VCC = 2.7V to 5.5V, VSS = AVSS = 0V, Ta = - 40°C to + 105°C)
Parameter
Symbol
Pin name
Conditions
ICCLVD
VCC
At operation
Value
Low-Voltage
detection circuit
(LVD) power
supply current
Unit
Remarks
Typ
Max
0.13
0.3
μA
For occurrence of reset
0.13
0.3
μA
For occurrence of interrupt
Flash memory current
(VCC = 2.7V to 5.5V, VSS = AVSS = 0V, Ta = - 40°C to + 105°C)
Parameter
Flash memory
write/erase current
Symbol
Pin name
Conditions
ICCFLASH
VCC
At Write/Erase
Value
Typ
Max
9.5
11.2
Unit
Remarks
mA
A/D convertor current (S6E1A1xC0A)
(VCC = 2.7V to 5.5V, VSS = AVSS = 0V, Ta = - 40°C to + 105°C)
Parameter
Power supply
current
Symbol
Pin name
ICCAD
AVCC
ICCAVRH
AVRH
Reference power
supply current
(AVRH)
Value
Conditions
Unit
Typ
Max
At operation
0.7
0.9
mA
At stop
0.13
13
μA
At operation
1.1
1.97
mA
At stop
0.1
1.7
μA
Remarks
AVRH=5.5V
A/D convertor current (S6E1A1xB0A)
(VCC = 2.7V to 5.5V, VSS = AVSS = 0V, Ta = - 40°C to + 105°C)
Parameter
Power supply
current
Symbol
Pin name
ICCAD
AVCC
Conditions
Value
Unit
Typ
Max
At operation
1.8
2.87
mA
At stop
0.23
14.7
μA
Remarks
Peripheral current dissipation
Clock
system
HCLK
PCLK1
50
CONFIDENTIAL
Peripheral
Conditions
GPIO
DMAC
Frequency (MHz)
4
8
20
40
At all ports operation
0.11
0.22
0.55
1.10
At 2ch operation
0.05
0.11
0.25
0.51
Base timer
At 4ch operation
0.03
0.05
0.15
0.30
Multi-functional timer/PPG
At 1unit/4ch operation
0.14
0.28
0.68
1.38
Quadrature
position/Revolution counter
At 1unit operation
0.02
0.04
0.11
0.22
ADC
At 1unit operation
0.07
0.14
0.37
0.73
Multi-function serial
At 1ch operation
0.15
0.31
0.77
1.54
Unit
Remarks
mA
mA
S6E1A1_DS710-00001-1v0-E, July 16, 2014
D a t a S h e e t
14.3.2
Pin Characteristics
(VCC =AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V, Ta = - 40°C to + 105°C)
Parameter
Symbol
Pin name
Value
Conditions
Unit
Min
Typ
Max
-
VCC × 0.8
-
VCC + 0.3
V
-
VCC × 0.8
-
VSS + 5.5
V
-
VSS - 0.3
-
VCC × 0.2
V
-
VSS - 0.3
-
VCC × 0.2
V
VCC - 0.5
-
VCC
V
VCC - 0.5
-
VCC
V
VSS
-
0.4
V
VSS
-
0.4
V
-
-5
-
+5
μA
VCC ≥ 4.5 V
33
50
90
VCC < 4.5 V
-
-
180
-
-
5
15
Remarks
CMOS
"H" level input
hysteresis
voltage
input pin,
(hysteresis
VIHS
input)
MD0, PE0
5V tolerant
input pin
CMOS
hysteresis
"L" level input
voltage
(hysteresis
VILS
input)
input pin,
MD0, PE0
5V tolerant
input pin
VCC ≥ 4.5 V,
4 mA type
"H" level
output voltage
IOH = - 4 mA
VCC < 4.5 V,
IOH = - 2 mA
VOH
VCC ≥ 4.5 V,
12 mA type
IOH = - 12 mA
VCC < 4.5 V,
IOH = - 8 mA
VCC ≥ 4.5 V,
4 mA type
"L" level
output voltage
IOL = 4 mA
VCC < 4.5 V,
IOL = 2 mA
VOL
VCC ≥ 4.5 V,
12 mA type
IOL = 12 mA
VCC < 4.5 V,
IOL = 8 mA
Input leak current
Pull-up resistance
value
IIL
-
RPU
Pull-up pin
kΩ
Other than
Input capacitance
CIN
VCC, VSS,
AVCC, AVSS,
pF
AVRH
July 16, 2014, S6E1A1_DS710-00001-1v0-E
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51
D a t a S h e e t
14.4 AC Characteristics
14.4.1 Main Clock Input Characteristics
(VCC = AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V, Ta = - 40°C to + 105°C)
Parameter
Symbol
Input frequency
FCH
Input clock cycle
tCYLH
Input clock pulse width
-
Input clock rising time
tCF,
and falling time
Pin
name
X0,
X1
Conditions
Max
Unit
VCC ≥ 4.5V
4
40
VCC < 4.5V
4
20
-
4
40
MHz
-
25
250
ns
45
55
%
-
-
5
ns
PWH/tCYLH,
PWL/tCYLH
tCR
Value
Min
MHz
Remarks
When the crystal oscillator is
connected
When the external
clock is used
When the external
clock is used
When the external
clock is used
When the external
clock is used
FCM
-
-
-
41.2
MHz
Master clock
Internal operating
FCC
-
-
-
41.2
MHz
Base clock (HCLK/FCLK)
clock*1 frequency
FCP0
-
-
-
41.2
MHz
APB0 bus clock*2
FCP1
-
-
-
41.2
MHz
APB1 bus clock*2
tCYCC
tCYCP0
tCYCP1
-
-
24.27
-
ns
Base clock (HCLK/FCLK)
-
-
24.27
-
ns
APB0 bus clock*2
-
-
24.27
-
ns
APB1 bus clock*2
Internal operating
clock*1 cycle time
*1: For details of each internal operating clock, refer to "CHAPTER: Clock" in "FM0+ Family PERIPHERAL
MANUAL".
*2: For details of the APB bus to which a peripheral is connected, see "10. Block Diagram".
X0
52
CONFIDENTIAL
S6E1A1_DS710-00001-1v0-E, July 16, 2014
D a t a S h e e t
14.4.2
Sub Clock Input Characteristics
(VCC = AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V, Ta = - 40°C to + 105°C)
Parameter
Input frequency
Symbol
Pin
name
Input clock pulse
width
Value
Unit
Min
Typ
Max
-
-
32.768
-
kHz
-
32
-
100
kHz
-
10
-
31.25
μs
45
-
55
%
1/tCYLL
X0A,
Input clock cycle
Conditions
tCYLL
X1A
-
PWH/tCYLL,
PWL/tCYLL
Remarks
When the crystal
oscillator is connected
When the external
clock is used
When the external
clock is used
When the external
clock is used
*: See "Sub crystal oscillator" in "9. Handling Devices" for the crystal oscillator used.
X0A
July 16, 2014, S6E1A1_DS710-00001-1v0-E
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D a t a S h e e t
14.4.3
Built-in CR Oscillation Characteristics
Built-in high-speed CR
(VCC = AVCC = 2.7 V to 5.5 V, VSS =AVSS = 0 V, Ta = - 40°C to + 105°C)
Parameter
Symbol
Value
Conditions
Ta = + 25°C,
3.6V < VCC ≤ 5.5V
Ta =0°C to + 85°C,
3.6V < VCC ≤ 5.5V
Ta = - 40°C to + 105°C,
3.6V < VCC ≤ 5.5V
Ta = + 25°C,
Clock frequency
FCRH
2.7V ≤ VCC ≤ 3.6V
Max
3.92
4
4.08
3.9
4
4.1
3.88
4
4.12
3.94
4
4.06
3.92
4
4.08
3.9
4
4.1
3.88
4
4.12
Ta = - 40°C to + 105°C
2.8
4
5.2
-
-
-
30
2.7V ≤ VCC ≤ 3.6V
Ta = - 20°C to + 105°C,
2.7V ≤ VCC ≤ 3.6V
Ta = - 40°C to + 105°C,
2.7V ≤ VCC ≤ 3.6V
time
Typ
tCRWT
Unit
Remarks
During trimming*1
MHz
Ta = - 20°C to + 85°C,
Frequency stabilization
Min
Not during trimming
μs
*2
*1: In the case of using the values in CR trimming area of Flash memory at shipment for frequency
trimming/temperature trimming.
*2: This is time from the trim value setting to stable of the frequency of the High-speed CR clock.
After setting the trim value, the period when the frequency stability time passes can use the High-speed
CR clock as a source clock.
Built-in low-speed CR
(VCC = AVCC = 2.7 V to 5.5 V, VSS =AVSS = 0 V, Ta = - 40°C to + 105°C)
Parameter
Clock frequency
54
CONFIDENTIAL
Symbol
Conditions
FCRL
-
Value
Min
Typ
Max
50
100
150
Unit
Remarks
kHz
S6E1A1_DS710-00001-1v0-E, July 16, 2014
D a t a S h e e t
14.4.4
Operating Conditions of Main PLL
(In the case of using the main clock as the input clock of the PLL)
(VCC = AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V, Ta = - 40°C to + 105°C)
Value
Parameter
PLL oscillation stabilization wait time*1 (LOCK UP
time)
PLL input clock frequency
PLL multiple rate
PLL macro oscillation clock frequency
Main PLL clock frequency*2
Symbol
Unit
Min
Typ
Max
tLOCK
100
-
-
FPLLI
4
-
16
MHz
-
5
-
37
multiple
FPLLO
75
-
150
MHz
FCLKPLL
-
-
40
MHz
Remarks
μs
*1: The wait time is the time it takes for PLL oscillation to stabilize.
*2: For details of the main PLL clock (CLKPLL), refer to "CHAPTER: Clock" in "FM0+ Family PERIPHERAL
MANUAL".
14.4.5
Operating Conditions of Main PLL
(In the case of using the built-in high-speed CR clock as the input
clock of the main PLL)
(VCC = AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V, Ta = - 40°C to + 105°C)
Value
Parameter
PLL oscillation stabilization wait time*1 (LOCK UP
time)
PLL input clock frequency
PLL multiple rate
PLL macro oscillation clock frequency
Main PLL clock frequency*2
Symbol
Unit
Min
Typ
Max
tLOCK
100
-
-
μs
FPLLI
3.88
4
4.12
MHz
-
19
-
35
multiple
FPLLO
72
-
150
MHz
FCLKPLL
-
-
41.2
MHz
Remarks
*1: The wait time is the time it takes for PLL oscillation to stabilize.
*2: For details of the main PLL clock (CLKPLL), refer to "CHAPTER: Clock" in "FM0+ Family PERIPHERAL
MANUAL".
Note:
−
For the main PLL source clock, input the high-speed CR clock (CLKHC) whose frequency has been
trimmed.
July 16, 2014, S6E1A1_DS710-00001-1v0-E
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55
D a t a S h e e t
14.4.6
Reset Input Characteristics
(VCC =AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V, Ta = - 40°C to + 105°C)
Parameter
Symbol
Reset input time
14.4.7
tINITX
Pin name
Value
Conditions
INITX
-
Unit
Min
Max
500
-
Remarks
ns
Power-on Reset Timing
(VCC = AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V, Ta = - 40°C to + 105°C)
Value
Parameter
Symbol
Power supply rising time
Pin name
Tr
Power supply shut down time
Toff
Time until releasing
VCC
Tprt
Power-on reset
Unit
Min
Max
0
-
ms
1
-
ms
0.43
3.4
ms
Remarks
VCC_minimum
VCC
VDH_minimum
0.2V
0.2V
0.2V
Tr
Tprt
Internal RST
CPU Operation
RST Active
Toff
Release
start
Glossary
− VCC_minimum : Minimum VCC of recommended operating conditions.
− VDH_minimum : Minimum release voltage (when SVHR=0000) of Low-Voltage detection reset.
See "6. Low-Voltage Detection Characteristics".
56
CONFIDENTIAL
S6E1A1_DS710-00001-1v0-E, July 16, 2014
D a t a S h e e t
14.4.8
Base Timer Input Timing
Timer input timing
(VCC = AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V, Ta = - 40°C to + 105°C)
Parameter
Symbol
Pin name
Conditions
tTIWH, tTIWL
(when using as
Value
Min
Max
2 tCYCP
-
Unit
Remarks
TIOAn/TIOBn
Input pulse width
-
ns
ECK, TIN)
tTIWH
tTIWL
ECK
VIHS
TIN
VIHS
VILS
VILS
Trigger input timing
(VCC = AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V, Ta = - 40°C to + 105°C)
Parameter
Symbol
Pin name
tTRGH, tTRGL
(when using as
Conditions
Value
Min
Max
2 tCYCP
-
Unit
Remarks
TIOAn/TIOBn
Input pulse width
-
ns
TGIN)
tTRGH
VIHS
TGIN
tTRGL
VIHS
VILS
VILS
Note:
−
tCYCP indicates the APB bus clock cycle time.
For the number of the APB bus to which the Base Timer has been connected, see "10. Block
Diagram".
July 16, 2014, S6E1A1_DS710-00001-1v0-E
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57
D a t a S h e e t
14.4.9
CSIO Timing
Synchronous serial (SPI = 0, SCINV = 0)
(VCC = AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V, Ta = - 40°C to + 105°C)
Parameter
Serial clock cycle time
Symbol
tSCYC
SCK ↓ → SOT delay time
tSLOVI
SIN → SCK ↑ setup time
tIVSHI
SCK ↑ → SIN hold time
tSHIXI
Serial clock "L" pulse width
tSLSH
Serial clock "H" pulse width
tSHSL
SCK ↓ → SOT delay time
tSLOVE
SIN → SCK ↑ setup time
tIVSHE
SCK ↑ → SIN hold time
tSHIXE
Pin
name
Conditions
VCC ≥ 4.5 V
VCC < 4.5 V
Unit
Min
Max
Min
Max
4 tCYCP
-
4 tCYCP
-
ns
- 30
+ 30
- 20
+ 20
ns
50
-
30
-
ns
0
-
0
-
ns
SCKx
2 tCYCP - 10
-
-
ns
SCKx
tCYCP + 10
-
tCYCP + 10
-
ns
-
50
-
30
ns
10
-
10
-
ns
20
-
20
-
ns
SCKx
SCKx,
SOTx
Internal shift
SCKx,
clock
SINx
operation
SCKx,
SINx
SCKx,
SOTx
External shift
SCKx,
clock
SINx
operation
SCKx,
SINx
2 tCYCP 10
SCK falling time
tF
SCKx
-
5
-
5
ns
SCK rising time
tR
SCKx
-
5
-
5
ns
Notes:
−
−
−
−
58
CONFIDENTIAL
The above AC characteristics are for CLK synchronous mode.
tCYCP represents the APB bus clock cycle time.
For the number of the APB bus to which Multi-function Serial has been connected, see "10. Block
Diagram ".
The characteristics are only applicable when the relocate port numbers are the same.
For instance, they are not applicable for the combination of SCLKx_0 and SOTx_1.
External load capacitance CL = 30 pF
S6E1A1_DS710-00001-1v0-E, July 16, 2014
D a t a S h e e t
tSCYC
VOH
SCK
VOL
VOL
tSLOVI
VOH
VOL
SOT
tIVSHI
SIN
tSHIXI
VIH
VIL
VIH
VIL
MS bit = 0
tSLSH
SCK
VIH
tF
SOT
VIL
tSHSL
VIL
VIH
VIH
tR
tSLOVE
VOH
VOL
SIN
tIVSHE
VIH
VIL
tSHIXE
VIH
VIL
MS bit = 1
July 16, 2014, S6E1A1_DS710-00001-1v0-E
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59
D a t a S h e e t
Synchronous serial (SPI = 0, SCINV = 1)
(VCC = AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V, Ta = - 40°C to + 105°C)
Parameter
Symbol
Serial clock cycle time
tSCYC
SCK ↑ → SOT delay time
tSHOVI
SIN → SCK ↓ setup time
tIVSLI
SCK ↓ → SIN hold time
tSLIXI
Serial clock "L" pulse width
tSLSH
Serial clock "H" pulse width
tSHSL
SCK ↑ → SOT delay time
tSHOVE
SIN → SCK ↓ setup time
tIVSLE
SCK ↓ → SIN hold time
tSLIXE
Pin
name
VCC ≥ 4.5V
VCC < 4.5V
Conditions
Unit
Min
Max
Min
Max
4 tCYCP
-
4 tCYCP
-
ns
- 30
+ 30
- 20
+ 20
ns
50
-
30
-
ns
0
-
0
-
ns
SCKx
2 tCYCP - 10
-
2 tCYCP - 10
-
ns
SCKx
tCYCP + 10
-
tCYCP + 10
-
ns
-
50
-
30
ns
10
-
10
-
ns
20
-
20
-
ns
SCKx
SCKx,
SOTx
Internal shift
SCKx,
clock
SINx
operation
SCKx,
SINx
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
External shift
clock
operation
SCK falling time
tF
SCKx
-
5
-
5
ns
SCK rising time
tR
SCKx
-
5
-
5
ns
Notes:
−
−
The above AC characteristics are for CLK synchronous mode.
tCYCP represents the APB bus clock cycle time.
For the number of the APB bus to which Multi-function Serial has been connected, see "10. Block
Diagram ".
−
The characteristics are only applicable when the relocate port numbers are the same.
For instance, they are not applicable for the combination of SCLKx_0 and SOTx_1.
External load capacitance CL = 30 pF
−
60
CONFIDENTIAL
S6E1A1_DS710-00001-1v0-E, July 16, 2014
D a t a S h e e t
tSCYC
VOH
SCK
VOH
VOL
tSHOVI
VOH
VOL
SOT
tIVSLI
SIN
tSLIXI
VIH
VIL
VIH
VIL
MS bit = 0
tSHSL
SCK
VIH
VIH
VIL
tR
SOT
tSLSH
VIL
VIL
tF
tSHOVE
VOH
VOL
SIN
tIVSLE
VIH
VIL
tSLIXE
VIH
VIL
MS bit = 1
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61
D a t a S h e e t
Synchronous serial (SPI = 1, SCINV = 0)
(VCC = AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V, Ta = - 40°C to + 105°C)
Parameter
Symbol
Serial clock cycle time
tSCYC
SCK ↑ → SOT delay time
tSHOVI
SIN → SCK ↓ setup time
tIVSLI
SCK ↓→ SIN hold time
tSLIXI
SOT → SCK ↓ delay time
tSOVLI
Serial clock "L" pulse width
tSLSH
Serial clock "H" pulse width
tSHSL
SCK ↑ → SOT delay time
tSHOVE
SIN → SCK ↓ setup time
tIVSLE
SCK ↓→ SIN hold time
tSLIXE
Pin
name
Conditions
VCC ≥ 4.5 V
VCC < 4.5 V
Unit
Min
Max
Min
Max
4 tCYCP
-
4 tCYCP
-
ns
- 30
+ 30
- 20
+ 20
ns
50
-
30
-
ns
0
-
0
-
ns
2 tCYCP - 30
-
2 tCYCP - 30
-
ns
SCKx
2 tCYCP - 10
-
2 tCYCP - 10
-
ns
SCKx
tCYCP + 10
-
tCYCP + 10
-
ns
-
50
-
30
ns
10
-
10
-
ns
20
-
20
-
ns
SCKx
SCKx,
SOTx
SCKx,
Internal shift
SINx
clock
SCKx,
operation
SINx
SCKx,
SOTx
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
External shift
clock
operation
SCK falling time
tF
SCKx
-
5
-
5
ns
SCK rising time
tR
SCKx
-
5
-
5
ns
Notes:
−
−
−
−
62
CONFIDENTIAL
The above AC characteristics are for CLK synchronous mode.
tCYCP represents the APB bus clock cycle time.
For the number of the APB bus to which Multi-function Serial has been connected, see "10. Block
Diagram ".
The characteristics are only applicable when the relocate port numbers are the same.
For instance, they are not applicable for the combination of SCLKx_0 and SOTx_1.
External load capacitance CL = 30 pF
S6E1A1_DS710-00001-1v0-E, July 16, 2014
D a t a S h e e t
tSCYC
VOH
VOL
SCK
VOH
VOL
SOT
VOH
VOL
tIVSLI
tSLIXI
VIH
VIL
SIN
VOL
tSHOVI
tSOVLI
VIH
VIL
MS bit = 0
tSLSH
SCK
VIH
tR
VIH
tSHOVE
VOH
VOL
VOH
VOL
tIVSLE
SIN
VIH
VIL
VIL
tF
*
SOT
tSHSL
tSLIXE
VIH
VIL
VIH
VIL
MS bit = 1
*: This changes as data is written to the TDR register.
July 16, 2014, S6E1A1_DS710-00001-1v0-E
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63
D a t a S h e e t
Synchronous serial (SPI = 1, SCINV = 1)
(VCC = AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V, Ta = - 40°C to + 105°C)
Parameter
Symbol
Serial clock cycle time
tSCYC
SCK ↓ → SOT delay time
tSLOVI
SIN → SCK ↑ setup time
tIVSHI
SCK ↑ → SIN hold time
tSHIXI
SOT → SCK ↑ delay time
tSOVHI
Serial clock "L" pulse width
tSLSH
Serial clock "H" pulse width
tSHSL
SCK ↓ → SOT delay time
SIN → SCK ↑ setup time
SCK ↑ → SIN hold time
tSLOVE
tIVSHE
tSHIXE
Pin
name
Conditions
VCC ≥ 4.5 V
VCC < 4.5 V
Unit
Min
Max
Min
Max
4 tCYCP
-
4 tCYCP
-
ns
- 30
+ 30
- 20
+ 20
ns
50
-
30
-
ns
0
-
0
-
ns
2 tCYCP - 30
-
2 tCYCP - 30
-
ns
SCKx
2 tCYCP - 10
-
2 tCYCP - 10
-
ns
SCKx
tCYCP + 10
-
tCYCP + 10
-
ns
-
50
-
30
ns
10
-
10
-
ns
20
-
20
-
ns
SCKx
SCKx,
SOTx
SCKx,
Internal shift
SINx
clock
SCKx,
operation
SINx
SCKx,
SOTx
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
External shift
clock
operation
SCK falling time
tF
SCKx
-
5
-
5
ns
SCK rising time
tR
SCKx
-
5
-
5
ns
Notes:
−
−
The above AC characteristics are for CLK synchronous mode.
tCYCP represents the APB bus clock cycle time.
For the number of the APB bus to which Multi-function Serial has been connected, see "10. Block
Diagram ".
−
The characteristics are only applicable when the relocate port numbers are the same.
For instance, they are not applicable for the combination of SCLKx_0 and SOTx_1.
External load capacitance CL = 30 pF
−
64
CONFIDENTIAL
S6E1A1_DS710-00001-1v0-E, July 16, 2014
D a t a S h e e t
tSCYC
VOH
SCK
tSOVHI
tSLOVI
VOH
VOL
SOT
VOH
VOL
tSHIXI
tIVSHI
VIH
VIL
SIN
VOH
VOL
VIH
VIL
MS bit = 0
tSHSL
tR
SCK
VIL
tSLSH
VIH
VIH
VIL
tF
VIL
VIH
tSLOVE
SOT
VOH
VOL
VOH
VOL
tIVSHE
SIN
tSHIXE
VIH
VIL
VIH
VIL
MS bit = 1
July 16, 2014, S6E1A1_DS710-00001-1v0-E
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65
D a t a S h e e t
When using synchronous serial chip select (SPI = 1, SCINV = 0, MS=0, CSLVL=1)
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
SCS↓→SCK↓ setup time
tCSSI
SCK↑→SCS↑ hold time
tCSHI
Internal shift
clock operation
SCS deselect time
tCSDI
SCS↓→SCK↓ setup time
tCSSE
SCK↑→SCS↑ hold time
tCSHE
External shift
VCC ≥ 4.5V
VCC < 4.5V
Conditions
Unit
Min
Max
Min
Max
(*1)-50
(*1)+0
(*1)-50
(*1)+0
ns
(*2)+0
(*2)+50
(*2)+0
(*2)+50
ns
(*3)-50
(*3)+50
(*3)-50
(*3)+50
+5tCYCP
+5tCYCP
+5tCYCP
+5tCYCP
3tCYCP+30
-
3tCYCP+30
-
ns
0
-
0
-
ns
3tCYCP+30
-
3tCYCP+30
-
ns
ns
SCS deselect time
tCSDE
SCS↓→SUT delay time
tDSE
-
40
-
40
ns
SCS↑→SUT delay time
tDEE
0
-
0
-
ns
clock operation
(*1): CSSU bit value × serial chip select timing operating clock cycle [ns]
(*2): CSHD bit value × serial chip select timing operating clock cycle [ns]
(*3): CSDS bit value × serial chip select timing operating clock cycle [ns]
Notes:
−
−
−
66
CONFIDENTIAL
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function Serial is connected to, see "10. Block Diagram ".
About CSSU, CSHD, CSDS, serial chip select timing operating clock, see "FM0+ Family
PERIPHERAL MANUAL".
When the external load capacitance CL = 30pF.
S6E1A1_DS710-00001-1v0-E, July 16, 2014
D a t a S h e e t
SCS output
tCSDI
tCSSI
tCSHI
tCSSE
tCSHE
SCK output
SOT
(SPI=0)
SOT
(SPI=1)
SCS input
tCSDE
SCK input
tDEE
SOT
(SPI=0)
tDSE
SOT
(SPI=1)
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When using synchronous serial chip select (SPI = 1, SCINV = 1, MS=0, CSLVL=1)
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
SCS↓→SCK↑ setup time
tCSSI
SCK↓→SCS↑ hold time
tCSHI
SCS deselect time
tCSDI
SCS↓→SCK↑ setup time
tCSSE
SCK↓→SCS↑ hold time
tCSHE
SCS deselect time
tCSDE
SCS↓→SOT delay time
SCS↑→SOT delay time
VCC ≥ 4.5V
VCC < 4.5V
Conditions
Unit
Min
Max
Min
Max
(*1)-50
(*1)+0
(*1)-50
(*1)+0
ns
Internal shift
(*2)+0
(*2)+50
(*2)+0
(*2)+50
ns
clock operation
(*3)-50
(*3)+50
(*3)-50
(*3)+50
+5tCYCP
+5tCYCP
+5tCYCP
+5tCYCP
3tCYCP+30
-
3tCYCP+30
-
ns
ns
0
-
0
-
ns
3tCYCP+30
-
3tCYCP+30
-
ns
tDSE
-
40
-
40
ns
tDEE
0
-
0
-
ns
External shift
clock operation
(*1): CSSU bit value × serial chip select timing operating clock cycle [ns]
(*2): CSHD bit value × serial chip select timing operating clock cycle [ns]
(*3): CSDS bit value × serial chip select timing operating clock cycle [ns]
Notes:
−
−
−
68
CONFIDENTIAL
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function Serial is connected to, see "10. Block Diagram ".
About CSSU, CSHD, CSDS, serial chip select timing operating clock, see "FM0+ Family
PERIPHERAL MANUAL".
When the external load capacitance CL = 30pF.
S6E1A1_DS710-00001-1v0-E, July 16, 2014
D a t a S h e e t
SCS output
tCSDI
tCSSI
tCSHI
SCK output
SOT
(SPI=0)
SOT
(SPI=1)
SCS input
tCSDE
tCSSE
tCSHE
SCK
input
tDEE
SOT
(SPI=0)
tDSE
SOT
(SPI=1)
July 16, 2014, S6E1A1_DS710-00001-1v0-E
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When using synchronous serial chip select (SPI = 1, SCINV = 0, MS=0, CSLVL=0)
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
SCS↑→SCK↓ setup time
tCSSI
SCK↑→SCS↓ hold time
tCSHI
Conditions
Internal shift
clock operation
SCS deselect time
tCSDI
VCC ≥ 4.5V
VCC < 4.5V
Min
Max
Unit
Max
Min
(*1)-50
(*1)+0
(*1)-50
(*1)+0
ns
(*2)+0
(*2)+50
(*2)+0
(*2)+50
ns
(*3)-50
(*3)+50
(*3)-50
(*3)+50
+5tCYCP
+5tCYCP
+5tCYCP
+5tCYCP
ns
SCS↑→SCK↓ setup time
tCSSE
3tCYCP+30
-
3tCYCP+30
-
ns
SCK↑→SCS↓ hold time
tCSHE
0
-
0
-
ns
3tCYCP+30
-
3tCYCP+30
-
ns
External shift
SCS deselect time
tCSDE
SCS↑→SOT delay time
tDSE
-
40
-
40
ns
SCS↓→SOT delay time
tDEE
0
-
0
-
ns
clock operation
(*1): CSSU bit value × serial chip select timing operating clock cycle [ns]
(*2): CSHD bit value × serial chip select timing operating clock cycle [ns]
(*3): CSDS bit value × serial chip select timing operating clock cycle [ns]
Notes:
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function Serial is connected to, see "10. Block Diagram ".
−
About CSSU, CSHD, CSDS, serial chip select timing operating clock, see "FM0+ Family
PERIPHERAL MANUAL".
When the external load capacitance CL = 30pF.
−
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D a t a S h e e t
tCSDI
SCS output
tCSSI
tCSHI
SCK output
SOT
(SPI=0)
SOT
(SPI=1)
tCSDE
SCS input
tCSSE
tCSHE
SCK
input
tDEE
SOT
(SPI=0)
SOT
(SPI=1)
July 16, 2014, S6E1A1_DS710-00001-1v0-E
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tDSE
71
D a t a S h e e t
When using synchronous serial chip select (SPI = 1, SCINV = 1, MS=0, CSLVL=0)
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
SCS↑→SCK↑ setup time
tCSSI
SCK↓→SCS↓ hold time
tCSHI
Conditions
Internal shift
clock operation
SCS deselect time
tCSDI
VCC ≥ 4.5V
VCC < 4.5V
Min
Max
Unit
Max
Min
(*1)-50
(*1)+0
(*1)-50
(*1)+0
ns
(*2)+0
(*2)+50
(*2)+0
(*2)+50
ns
(*3)-50
(*3)+50
(*3)-50
(*3)+50
+5tCYCP
+5tCYCP
+5tCYCP
+5tCYCP
ns
SCS↑→SCK↑ setup time
tCSSE
3tCYCP+30
-
3tCYCP+30
-
ns
SCK↓→SCS↓ hold time
tCSHE
0
-
0
-
ns
3tCYCP+30
-
3tCYCP+30
-
ns
External shift
SCS deselect time
tCSDE
SCS↑→SOT delay time
tDSE
-
40
-
40
ns
SCS↓→SOT delay time
tDEE
0
-
0
-
ns
clock operation
(*1): CSSU bit value × serial chip select timing operating clock cycle [ns]
(*2): CSHD bit value × serial chip select timing operating clock cycle [ns]
(*3): CSDS bit value × serial chip select timing operating clock cycle [ns]
Notes:
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function Serial is connected to, see "10. Block Diagram ".
−
About CSSU, CSHD, CSDS, serial chip select timing operating clock, see "FM0+ Family
PERIPHERAL MANUAL".
When the external load capacitance CL = 30pF.
−
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D a t a S h e e t
tCSDI
SCS output
tCSSI
tCSHI
SCK output
SOT
(SPI=0)
SOT
(SPI=1)
SCS input
tCSDE
tCSSE
tCSHE
SCK
input
tDEE
SOT
(SPI=0)
SOT
(SPI=1)
tDSE
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External clock (EXT = 1): asynchronous only
(VCC = AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V, Ta = - 40°C to + 105°C)
Parameter
Symbol
Serial clock "L" pulse width
tSLSH
Serial clock "H" pulse width
tSHSL
SCK falling time
tF
SCK rising time
tR
CL = 30 pF
tR
SCK
VIL
74
CONFIDENTIAL
Value
Conditions
Max
tCYCP + 10
-
ns
tCYCP + 10
-
ns
-
5
ns
-
5
ns
tSHSL
VIH
VIL
Remarks
tF
tSLSH
VIH
Unit
Min
VIL
VIH
S6E1A1_DS710-00001-1v0-E, July 16, 2014
D a t a S h e e t
14.4.10 External Input Timing
(VCC = AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V, Ta = - 40°C to + 105°C)
Parameter
Symbol
Pin name
Conditions
Value
Min
Max
Unit
A/D converter
ADTGx
FRCKx
Input pulse width
tINH, tINL
trigger input
-
2 tCYCP*1
-
ns
Input capture
-
2 tCYCP*1
-
Wave form
-
ns
2 tCYCP + 100*
-
ns
External interrupt,
500*2
-
ns
NMI
1
INTxx, NMIX
Free-run timer
input clock
ICxx
DTTIxX
Remarks
generator
*1: tCYCP represents the APB bus clock cycle time except when the APB bus clock stops in STOP mode or
in TIMER mode. For the number of the APB bus to which the Multi-function Timer is connected and that
of the APB bus to which the External Interrupt Controller is connected, see "10. Block Diagram".
*2: In STOP mode and TIMER mode
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14.4.11 QPRC Timing
(VCC = AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V, Ta = - 40°C to + 105°C)
Parameter
Value
Symbol
Conditions
AIN pin "H" width
tAHL
-
AIN pin "L" width
tALL
-
BIN pin "H" width
tBHL
-
BIN pin "L" width
tBLL
-
Time from AIN pin "H" level to BIN rise
tAUBU
PC_Mode2 or PC_Mode3
Time from BIN pin "H" level to AIN fall
tBUAD
PC_Mode2 or PC_Mode3
Time from AIN pin "L" level to BIN fall
tADBD
PC_Mode2 or PC_Mode3
Time from BIN pin "L" level to AIN rise
tBDAU
PC_Mode2 or PC_Mode3
Time from BIN pin "H" level to AIN rise
tBUAU
PC_Mode2 or PC_Mode3
Time from AIN pin "H" level to BIN fall
tAUBD
PC_Mode2 or PC_Mode3
Time from BIN pin "L" level to AIN fall
tBDAD
PC_Mode2 or PC_Mode3
Time from AIN pin "L" level to BIN rise
tADBU
PC_Mode2 or PC_Mode3
ZIN pin "H" width
tZHL
QCR:CGSC="0"
ZIN pin "L" width
tZLL
QCR:CGSC="0"
tZABE
QCR:CGSC="1"
tABEZ
QCR:CGSC="1"
Time from determined ZIN level to
AIN/BIN rise and fall
Time from AIN/BIN rise and fall time to
determined ZIN level
Min
Max
2 tCYCP*
-
Unit
ns
*: tCYCP represents the APB bus clock cycle time except when the APB bus clock stops in STOP mode or in
TIMER mode. For the number of the APB bus to which the QPRC is connected, see "10. Block Diagram".
tALL
tAHL
AIN
tAUBU
tADBD
tBUAD
tBDAU
BIN
tBHL
76
CONFIDENTIAL
tBLL
S6E1A1_DS710-00001-1v0-E, July 16, 2014
D a t a S h e e t
tBLL
tBHL
BIN
tBUAU
tBDAD
tAUBD
tADBU
AIN
tAHL
tALL
ZIN
ZIN
AIN/BIN
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14.4.12 I2C Timing
(VCC = AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V, Ta = - 40°C to + 105°C)
Parameter
Symbol
Conditions
Standard-mode
Fast-mode
Unit
Min
Max
Min
Max
FSCL
0
100
0
400
kHz
tHDSTA
4.0
-
0.6
-
μs
SCL clock "L" width
tLOW
4.7
-
1.3
-
μs
SCL clock "H" width
tHIGH
4.0
-
0.6
-
μs
4.7
-
0.6
-
μs
0
3.45*2
0
0.9*3
μs
tSUDAT
250
-
100
-
ns
tSUSTO
4.0
-
0.6
-
μs
tBUF
4.7
-
1.3
-
μs
2 tCYCP*4
-
2 tCYCP*4
-
ns
SCL clock frequency
Remarks
(Repeated) START condition
hold time
SDA ↓ → SCL ↓
(Repeated) START setup time
SCL ↑ → SDA ↓
tSUSTA
CL = 30 pF,
Data hold time
tHDDAT
SCL ↓ → SDA ↓ ↑
Data setup time
SDA ↓ ↑ → SCL ↑
STOP condition setup time
SCL ↑ → SDA ↑
R = (Vp/IOL)*1
Bus free time between
"STOP condition" and
"START condition"
Noise filter
tSP
-
*1: R represents the pull-up resistance of the SCL and SDA lines, and CL the load capacitance of the SCL
and SDA lines. Vp represents the power supply voltage of the pull-up resistance, and IOL the VOL
guaranteed current.
*2: The maximum tHDDAT must satisfy at least the condition that the period during which the device is
holding the SCL signal at "L" (tLOW) does not extend.
2
2
*3: A Fast-mode I C bus device can be used in a Standard-mode I C bus system, provided that the
condition of "tSUDAT ≥ 250 ns" is fulfilled.
*4: tCYCP represents the APB bus clock cycle time.
2
For the number of the APB bus to which the I C is connected, see "10. Block Diagram".
To use Standard-mode, set the APB bus clock at 2MHz or more.
To use Fast-mode, set the APB bus clock at 8 MHz or more.
SDA
SCL
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CONFIDENTIAL
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D a t a S h e e t
14.4.13 SW-DP Timing
(VCC = AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V, Ta = - 40°C to + 105°C)
Parameter
Symbol
SWDIO setup time
tSWS
SWDIO hold time
tSWH
SWDIO delay time
tSWD
Pin name
SWCLK,
SWDIO
SWCLK,
SWDIO
SWCLK,
SWDIO
Conditions
Value
Unit
Min
Max
-
15
-
ns
-
15
-
ns
-
-
45
ns
Remarks
Note:
−
External load capacitance CL = 30 pF
SWCLK
SWDIO
(When input)
SWD
SWDIO
(When output)
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79
D a t a S h e e t
14.5 12-bit A/D Converter
Electrical characteristics of A/D Converter
(VCC = AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V, Ta = - 40°C to + 105°C)
Parameter
Symbol
Pin name
Resolution
-
Integral Nonlinearity
Differential Nonlinearity
Zero transition voltage
Full-scale transition voltage
Conversion time
Value
Unit
Min
Typ
Max
-
-
-
12
bit
-
-
- 4.5
-
4.5
LSB
-
-
- 2.5
-
+ 2.5
LSB
VZT
ANxx
VFST
ANxx
-
-
- 20
-
+ 20
mV
AVRH - 20
-
AVRH+ 20
mV
AVCC-20
-
AVCC+20
0.8*1
-
-
-
-
2.0*1
Ts
-
S6E1A1xC0A
μs
S6E1A1xC0A
-
0.5
AVCC ≥ 4.5V
10
μs
-
S6E1A1xB0A
S6E1A1xC0A
-
50
AVCC ≥ 4.5V
1000
ns
permission
Analog input capacity
Analog input resistance
S6E1A1xB0A
Tstt
-
-
-
1.0
μs
CAIN
-
-
-
9.7
pF
RAIN
-
-
-
1.6
2.3
kΩ
Interchannel disparity
-
-
-
-
4
LSB
Analog port input current
-
ANxx
-
-
5
μA
AVSS
-
AVRH
V
AVSS
-
AVCC
2.7
-
AVCC
Analog input voltage
-
ANxx
Reference voltage
-
AVRH
S6E1A1xC0A
AVCC < 4.5V
100
State transition time to operation
S6E1A1xC0A
AVCC < 4.5V
40
Tcck
AVCC ≥ 4.5V
S6E1A1xB0A
0.6
Compare clock cycle*3
S6E1A1xC0A
S6E1A1xB0A
0.24
Sampling time*2
Remarks
AVCC ≥ 4.5V
AVCC < 4.5V
S6E1A1xC0A
S6E1A1xB0A
V
Only S6E1A1xB0A
*1: The conversion time is the value of "sampling time (Ts) + compare time (Tc)".
The minimum conversion time is computed according to the following conditions: sampling time = 240
ns, compare time = 560 ns (AVcc ≥ 4.5 V). Must be set 25MHz to the Base clock (HCLK).
Ensure that the conversion time satisfies the specifications of the sampling time (Ts) and compare clock
cycle (Tcck).
For details of the settings of the sampling time and compare clock cycle, refer to "CHAPTER: A/D
Converter" in "FM0+ Family PERIPHERAL MANUAL Analog Macro Part".
The register settings of the A/D Converter are reflected in the operation according to the APB bus clock
timing.
For the number of the APB bus to which the A/D Converter is connected, see "10. Block Diagram".
The base clock (HCLK) is used to generate the sampling time and the compare clock cycle.
*2: The required sampling time varies according to the external impedance.
Set a sampling time that satisfies (Equation 1).
*3: The compare time (Tc) is the result of (Equation 2).
80
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D a t a S h e e t
ANxx,
Analog input pins
Rext
Comparator
RAIN
Analog signal
source
CAIN
(Equation 1) Ts ≥ (RAIN + Rext ) × CAIN × 9
Ts:
RAIN:
CAIN:
Rext:
Sampling time
Input resistance of A/D Converter = 1.6 kΩ with 4.5 < AVCC < 5.5 ch.1 to ch.5
Input resistance of A/D Converter = 1.4 kΩ with 4.5 < AVCC < 5.5 ch.0, ch.6, ch.7
Input resistance of A/D Converter = 2.3 kΩ with 2.7 < AVCC < 4.5 ch.1 to ch.5
Input resistance of A/D Converter = 2.0 kΩ with 2.7 < AVCC < 4.5 ch.0, ch.6, ch.7
Input capacitance of A/D Converter = 9.7 pF with 2.7 < AVCC < 5.5
Output impedance of external circuit
(Equation 2) Tc = Tcck × 14
Tc:
Tcck:
July 16, 2014, S6E1A1_DS710-00001-1v0-E
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Compare time
Compare clock cycle
81
D a t a S h e e t
Definitions of 12-bit A/D Converter terms
Resolution
Integral Nonlinearity
: Analog variation that is recognized by an A/D converter.
: Deviation of the line between the zero-transition point (0b000000000000 ←→
0b000000000001) and the full-scale transition point (0b111111111110 ←→
0b111111111111) from the actual conversion characteristics.
Differential Nonlinearity : Deviation from the ideal value of the input voltage that is required to change the
output code by 1 LSB.
Integral Nonlinearity
Differential Nonlinearity
0xFFF
Actual conversion
characteristics
0xFFE
0x(N+1)
{1 LSB(N-1) + VZT}
VFST
VNT
0x004
(Actuallymeasured
value)
(Actually-measured
value)
0x003
Digital output
Digital output
0xFFD
0xN
Actual conversion
characteristics
Ideal characteristics
V(N+1)T
0x(N-1)
(Actually-measured
value)
Actual conversion
characteristics
Ideal characteristics
0x002
VNT
(Actually-measured
value)
0x(N-2)
0x001
VZT (Actually-measured value)
Actual conversion characteristics
*1
AVSS
AVRH
*1
AVSS
Analog input
AVRH
Analog input
*1: At the 32pin product, it is AVCC
Integral Nonlinearity of digital output N =
Differential Nonlinearity of digital output N =
1LSB =
N
VZT
VFST
VNT
82
CONFIDENTIAL
:
:
:
:
VNT - {1LSB × (N - 1) + VZT}
1LSB
V(N + 1) T - VNT
1LSB
[LSB]
- 1 [LSB]
VFST – VZT
4094
A/D converter digital output value.
Voltage at which the digital output changes from 0x000 to 0x001.
Voltage at which the digital output changes from 0xFFE to 0xFFF.
Voltage at which the digital output changes from 0x(N − 1) to 0xN.
S6E1A1_DS710-00001-1v0-E, July 16, 2014
D a t a S h e e t
14.6 Low-voltage Detection Characteristics
14.6.1 Low-voltage Detection Reset
(Ta = - 40°C to + 105°C)
Parameter
Symbol
Detected voltage
VDL
Released voltage
VDH
Detected voltage
VDL
Released voltage
VDH
Detected voltage
VDL
Released voltage
VDH
Detected voltage
VDL
Released voltage
VDH
Detected voltage
VDL
Released voltage
VDH
Detected voltage
VDL
Released voltage
VDH
Detected voltage
VDL
Released voltage
VDH
Detected voltage
VDL
Released voltage
VDH
Conditions
SVHR*1 = 00000
SVHR*1 = 00001
SVHR*1 = 00010
SVHR*1 = 00011
SVHR*1 = 00100
SVHR*1 = 00101
SVHR*1 = 00110
SVHR*1 = 00111
Value
Max
2.25
2.45
2.65
V
When voltage drops
2.30
2.50
2.70
V
When voltage rises
2.39
2.60
2.81
V
When voltage drops
Same as SVHR = 00000 value
V
When voltage rises
2.48
V
When voltage drops
Same as SVHR = 00000 value
V
When voltage rises
2.58
2.70
2.80
V
When voltage drops
V
When voltage rises
2.76
3.00
3.02
V
When voltage drops
Same as SVHR = 00000 value
V
When voltage rises
2.94
V
When voltage drops
Same as SVHR = 00000 value
V
When voltage rises
3.31
V
When voltage drops
Same as SVHR = 00000 value
V
When voltage rises
3.40
3.20
3.60
3.70
3.24
3.46
3.89
V
When voltage drops
Same as SVHR = 00000 value
V
When voltage rises
3.68
VDL
VDH
Detected voltage
VDL
Released voltage
VDH
Detected voltage
VDL
Released voltage
VDH
LVD stabilization wait time
TLVDW
-
-
-
LVD detection delay time
TLVDDL
-
-
-
SVHR*1 = 01010
2.92
Same as SVHR = 00000 value
Released voltage
SVHR*1 = 01001
Remarks
Typ
Detected voltage
SVHR*1 = 01000
Unit
Min
4.00
4.00
V
When voltage drops
Same as SVHR = 00000 value
V
When voltage rises
3.77
V
When voltage drops
Same as SVHR = 00000 value
V
When voltage rises
3.86
V
When voltage drops
V
When voltage rises
4.10
4.20
4.32
4.43
4.54
Same as SVHR = 00000 value
8160×
tCYCP*2
200
μs
μs
*1: SVHR bit of Low-Voltage Detection Voltage Control Register (LVD_CTL) is reset to SVHR = 00000 by
low voltage detection reset.
*2: tCYCP indicates the APB1 bus clock cycle time.
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D a t a S h e e t
14.6.2
Low-voltage Detection Interrupt
(Ta = - 40°C to + 105°C)
Parameter
Symbol
Detected voltage
VDL
Released voltage
VDH
Detected voltage
VDL
Released voltage
VDH
Detected voltage
VDL
Released voltage
VDH
Detected voltage
VDL
Released voltage
VDH
Detected voltage
VDL
Released voltage
VDH
Detected voltage
VDL
Released voltage
VDH
Detected voltage
VDL
Released voltage
VDH
Detected voltage
VDL
Released voltage
VDH
Conditions
SVHI = 00011
SVHI = 00100
SVHI = 00101
SVHI = 00110
SVHI = 00111
SVHI = 01000
SVHI = 01001
SVHI = 01010
Value
Unit
Remarks
Min
Typ
Max
2.58
2.80
3.02
V
When voltage drops
2.67
2.90
3.13
V
When voltage rises
2.76
3.00
3.24
V
When voltage drops
2.85
3.10
3.35
V
When voltage rises
2.94
3.20
3.46
V
When voltage drops
3.04
3.30
3.56
V
When voltage rises
3.31
3.60
3.89
V
When voltage drops
3.40
3.70
4.00
V
When voltage rises
3.40
3.70
4.00
V
When voltage drops
3.50
3.80
4.10
V
When voltage rises
3.68
4.00
4.32
V
When voltage drops
3.77
4.10
4.43
V
When voltage rises
3.77
4.10
4.43
V
When voltage drops
3.86
4.20
4.54
V
When voltage rises
3.86
4.20
4.54
V
When voltage drops
3.96
4.30
4.64
V
When voltage rises
LVD stabilization wait time
TLVDW
-
-
-
LVD detection delay time
TLVDDL
-
-
-
8160 ×
tCYCP*
200
μs
μs
*: tCYCP represents the APB1 bus clock cycle time.
84
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14.7 Flash Memory Write/Erase Characteristics
(VCC = 2.7 V to 5.5 V, Ta = - 40°C to + 105°C)
Value
Parameter
Large
sector
Sector erase time
Min
Typ
Max
-
0.7
2.2
Unit
s
Small
sector
0.3
0.9
Halfword (16-bit) write time
-
30
528
μs
Chip erase time
-
2.6
8
s
Remarks
The sector erase time includes the time of writing
prior to internal erase.
The halfword (16-bit) write time excludes the
system-level overhead.
The chip erase time includes the time of writing
prior to internal erase.
Write/erase cycle and data hold time
Write/erase cycle
Data hold time (year)
1,000
20*
10,000
10*
Remarks
*: This value was converted from the result of a technology reliability assessment. (This value was converted
from the result of a high temperature accelerated test using the Arrhenius equation with the average
temperature value being + 85°C).
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14.8 Return Time from Low-Power Consumption Mode
14.8.1 Return Factor: Interrupt
The return time from Low-Power consumption mode is indicated as follows. It is from receiving the return
factor to starting the program operation.
Return Count Time
(VCC = 2.7V to 5.5V, Ta = - 40°C to + 105°C)
Parameter
Symbol
− Value*
Typ
SLEEP mode
Max
Unit
Remarks
μs
tCYCC
High-speed CR TIMER mode,
Main TIMER mode,
40 + 17×tCYCC
80 + 17×tCYCC
μs
360
720
μs
191
381
μs
819
1090
μs
PLL TIMER mode
Low-speed CR TIMER mode
Sub TIMER mode
RTC mode,
STOP mode
Ticnt
*: The value depends on the accuracy of built-in CR.
The stabilization time of Main clock/Sub clock/Main PLL clock is not included.
Operation example of return from Low-Power consumption mode (by external interrupt*)
Ext.INT
Interrupt factor
accept
Active
Ticnt
CPU
Operation
Interrupt factor
clear by CPU
Start
*: External interrupt is set to detecting fall edge.
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Operation example of return from Low-Power consumption mode (by internal resource
interrupt*)
Internal
Resource INT
Interrupt factor
accept
Active
Ticnt
CPU
Operation
Interrupt factor
clear by CPU
Start
*: Internal resource interrupt is not included in return factor by the kind of Low-Power consumption mode.
Notes:
−
The return factor is different in each Low-Power consumption modes.
See "Chapter: Low Power Consumption Mode" and "Operations of Standby Modes" in FM0+ Family
PERIPHERAL MANUAL.
−
When interrupt recoveries, the operation mode that CPU recoveries depends on the state before the
Low-Power consumption mode transition. See "CHAPTER: Low Power Consumption Mode" in
"FM0+ Family PERIPHERAL MANUAL".
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14.8.2
Return Factor: Reset
The return time from Low-Power consumption mode is indicated as follows. It is from releasing reset to
starting the program operation.
Return Count Time
(VCC = 2.7V to 5.5V, Ta = - 40°C to + 105°C)
Parameter
Symbol
Value
Unit
Typ
Max*
208
378
μs
208
378
μs
Low-speed CR TIMER mode
398
758
μs
Sub TIMER mode
490
849
μs
RTC/STOP mode
288
538
μs
SLEEP mode
Remarks
High-speed CR TIMER mode,
Main TIMER mode,
PLL TIMER mode
Trcnt
*: The maximum value depends on the accuracy of built-in CR.
Operation example of return from Low-Power consumption mode (by INITX)
INITX
Internal RST
RST Active
Release
Trcnt
CPU
Operation
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S6E1A1_DS710-00001-1v0-E, July 16, 2014
D a t a S h e e t
Operation example of return from low power consumption mode (by internal resource
reset*)
Internal
Resource RST
Internal RST
RST Active
Release
Trcnt
CPU
Operation
Start
*: Internal resource reset is not included in return factor by the kind of Low-Power consumption mode.
Notes:
−
−
−
The return factor is different in each Low-Power consumption modes.
See "Chapter: Low Power Consumption Mode" and "Operations of Standby Modes" in FM0+ Family
PERIPHERAL MANUAL.
When interrupt recoveries, the operation mode that CPU recoveries depends on the state before the
Low-Power consumption mode transition. See "CHAPTER: Low Power Consumption Mode" in
"FM0+ Family PERIPHERAL MANUAL".
The time during the power-on reset/low-voltage detection reset is excluded. See "14.4.7 Power-on
Reset Timing " for the detail on the time during the power-on reset/low -voltage detection reset.
−
When in recovery from reset, CPU changes to the high-speed CR run mode. When using the main
clock or the PLL clock, it is necessary to add the main clock oscillation stabilization wait time or the
main PLL clock stabilization wait time.
−
The internal resource reset means the watchdog reset and the CSV reset.
July 16, 2014, S6E1A1_DS710-00001-1v0-E
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15. Ordering Information
90
CONFIDENTIAL
Part number
Package
S6E1A11B0AGP2
Plastic LQFP (0.80 mm pitch), 32 pins
S6E1A12B0AGP2
(FPT-32P-M30)
S6E1A11B0AGN2
Plastic QFN (0.50 mm pitch), 32 pins
S6E1A12B0AGN2
(LCC-32P-M73)
S6E1A11C0AGV2
Plastic LQFP (0.50 mm pitch), 48 pins
S6E1A12C0AGV2
(FPT-48P-M49)
S6E1A11C0AGN2
Plastic QFN (0.50 mm pitch), 48 pins
S6E1A12C0AGN2
(LCC-48P-M74)
S6E1A11C0AGF2
Plastic LQFP (0.65 mm pitch), 52 pins
S6E1A12C0AGF2
(FPT-52P-M02)
S6E1A1_DS710-00001-1v0-E, July 16, 2014
D a t a S h e e t
16. Package Dimensions
32-pin plastic LQFP
Lead pitch
0.80 mm
Package width ×
package length
7.00 mm × 7.00 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.60 mm MAX
(FPT-32P-M30)
32-pin plastic LQFP
(FPT-32P-M30)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
9.00±0.20(.354±.008)SQ
+0.05
* 7.00±0.10(.276±.004)SQ
24
0.13 –0.00
+.002
.005 –.000
17
16
25
0.10(.004)
Details of "A" part
1.60 MAX (Mounting height)
(.063) MAX
INDEX
0.25(.010)
9
32
0~7°
1
0.80(.031)
C
"A"
8
+0.08
–0.03
+.003
–.001
0.35
.014
0.20(.008)
0.60±0.15
(.024±.006)
M
2009-2010 FUJITSU SEMICONDUCTOR LIMITED F32051S-c-1-2
0.10±0.05
(.004±.002)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
July 16, 2014, S6E1A1_DS710-00001-1v0-E
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D a t a S h e e t
32-pin plastic QFN
Lead pitch
0.50 mm
Package width ×
package length
5.00 mm × 5.00 mm
Sealing method
Plastic mold
Mounting height
0.80 mm MAX
Weight
0.06 g
(LCC-32P-M73)
32-pin plastic QFN
(LCC-32P-M73)
5.00±0.10
(.197±.004)
3.20±0.10
(.068±.004)
0.25±0.05
(.010±.002)
INDEX AREA
5.00±0.10
(.197±.004)
3.20±0.10
(.068±.004)
0.50(.020)
(TYP)
0.75±0.05
(.030±.002)
(0.20)
((.008))
C
0.40±0.05
(.016±.002)
1PIN CORNER
C0.25(C.010)
0.02 +0.03
-0.02
(.0008 +.0012
-.0008 )
2013 FUJITSU SEMICONDUCTOR LIMITED HMbC32-73Sc-1-1
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
92
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D a t a S h e e t
48-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
7.00 mm × 7.00 mm
Lead shape
Gullwing
Lead bend
direction
Normal bend
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Weight
0.17 g
(FPT-48P-M49)
48-pin plastic LQFP
(FPT-48P-M49)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
9.00 ± 0.20(.354 ± .008)SQ
*7.00± 0.10(.276 ± .004)SQ
36
0.145± 0.055
(.006 ± .002)
25
37
24
0.08(.003)
INDEX
48
+0.20
1.50 –0.10 (Mounting height)
+.008
.059 –.004
13
"A"
1
0.50(.020)
C
Details of "A" part
0°~8°
0.10 ± 0.10
(.004 ± .004)
(Stand off)
12
0.22 ± 0.05
(.008 ± .002)
0.08(.003)
0.25(.010)
M
2010 FUJITSU SEMICONDUCTOR LIMITED HMbF48-49Sc-1-2
0.60 ± 0.15
(.024 ± .006)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
July 16, 2014, S6E1A1_DS710-00001-1v0-E
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93
D a t a S h e e t
48-pin plastic QFN
Lead pitch
0.50 mm
Package width×
package length
7.00 mm × 7.00 mm
Sealing method
Plastic mold
Mounting height
0.80 mm MAX
Weight
0.12 g
(LCC-48P-M74)
48-pin plastic QFN
(LCC-48P-M74)
7.00±0.10
(.276±.004)
INDEX AREA
4.65±0.15
(.183±.006)
7.00±0.10
(.276±.004)
4.65±0.15
(.183±.006)
+0.05
0.25 -0.07
(.010 +.002
)
-.003
1PIN CORNER
C0.30(C.020)
0.50(.020)
(TYP)
0.75±0.05
(.030±.002)
+0.03
(0.20)
((.008))
C
0.50±0.05
(.020±.002)
0.02 -0.02
(.0008 +.0012
)
-.0008
2013 FUJITSU SEMICONDUCTOR LIMITED HMbC48-74Sc-1-1
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
94
CONFIDENTIAL
S6E1A1_DS710-00001-1v0-E, July 16, 2014
D a t a S h e e t
52-pin plastic LQFP
Lead pitch
0.65 mm
Package width ×
package length
10.00 × 10.00 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Weight
0.32 g
Code
(Reference)
P-LFQFP52-10 × 10-0.65
(FPT-52P-M02)
52-pin plastic LQFP
(FPT-52P-M02)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
12.00±0.20(.472±.008)SQ
*10.00±0.10(.394±.004)SQ
39
0.145±0.055
(.006±.002)
27
40
Details of "A" part
26
+0.20
1.50 –0.10
+.008 (Mounting height)
.059 –.004
0.25(.010)
INDEX
0~8˚
0.10(.004)
52
14
"A"
1
13
0.65(.026)
+0.065
0.30 –0.035
+.0026
.012 –.0014
C
0.50±0.20
(.020±.008)
0.13(.005)
0.60±0.15
(.024±.006)
M
2010 FUJITSU SEMICONDUCTOR LIMITED F52002Sc-2-1
0.10±0.10
(.004±.004)
(Stand off)
Dimensions in mm (inches).
Note: The values in parentheses are reference values
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
July 16, 2014, S6E1A1_DS710-00001-1v0-E
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17. Major Changes
Page
Section
Change Results
Revision 0.1
-
-
Initial release
-
Revised from "Preliminary" to "Full Production"
Revision 1.0 [July 16,2014]
3
1. Description
Revised from "TYPE1" product to "TYPE1-M0+" product
5
2. Features
Revised "Processor version"
6
2. Features
Revised "Conversion time" of 12-bit A/D converter
9
3. Product Lineup
Added "Note" for accuracy of built-in CR
21,22,23,
24,25
23
40
41
46
47
6. List of Pin Functions
List of pin functions
6. List of Pin Functions
List of pin functions
12. Memory Map
Memory map (1)
12. Memory Map
Memory map (2)
14. Electrical Characteristics
14.1 Absolute Maximum Ratings
14. Electrical Characteristics
14.2 Recommended Operating Conditions
14. Electrical Characteristics
48,49,50
14.3 DC Characteristics
14.3.1 Current Rating
14. Electrical Characteristics
52
14.4 AC Characteristics
14.4.1 Main Clock Input Characteristics
Revised Pin number 30 and 31 of LQFP-32 and QFN-32
Revised Function description of SOT1_x(SDA1_x)
Revised from "MTB resister" to "MTB resister(SFR)"
Revised product name and RAM address
Revised Analog pin input voltage
Added note "*2"
• Revised and added "Conditions"
• Revised the value of "TBD"
Revised the value of "Internal operating clock frequency" and "Internal
operating clock cycle time"
14. Electrical Characteristics
54
14.4 AC Characteristics
Revised the value of "TBD"
14.4.3 Built-in CR Oscillation Characteristics
14. Electrical Characteristics
14.4 AC Characteristics
55
14.4.5 Operating Conditions of Main PLL(In the
case of using the built-in high-speed CR clock
• Revised the value of "TBD"
• Revised the maximum value of "Main PLL clock frequency"
as the input clock of the main PLL)
14. Electrical Characteristics
56
14.4 AC Characteristics
14.4.7 Power-on Reset Timing
14. Electrical Characteristics
78
14.4 AC Characteristics
14.4.12 I2C Timing
• Revised the value of "TBD"
• Revised from "LVDL_minimum" to "VDH_minimum"
• Revised the condition of "Noise filter"
• Revised the note for noise filter
• Revised the value of "Conversion time", "Sampling time" and "Compare
80
14. Electrical Characteristics
clock cycle"
14.5 12-bit A/D Converter
• Revised the value of "State transition time to operation permission"
• Revised the note
83,84
85
14. Electrical Characteristics
14.6 Low-voltage Detection Characteristics
Revised the value of SVHR and SVHI
14. Electrical Characteristics
• Revised the value of "TBD"
14.7 Flash Memory Write/Erase Characteristics
• Revised the value of typical
96
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Page
Section
Change Results
14. Electrical Characteristics
86,88
14.8 Return Time from Low-Power
Revised the value of "TBD"
Consumption Mode
90
15. Ordering Information
July 16, 2014, S6E1A1_DS710-00001-1v0-E
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Revised from "LCC-52P-M02" to "FPT-52P-M02"
97
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D a t a S h e e t
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use,
including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not
designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless
extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury,
severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control,
mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where
chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable
to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating conditions. If any products described in this document
represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law
of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the
respective government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a Spansion
product under development by Spansion. Spansion reserves the right to change or discontinue work on any product without
notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy,
completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other
warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind arising out of the use of
the information in this document.
®
®
®
TM
Copyright © 2013-2014 Spansion All rights reserved. Spansion , the Spansion logo, MirrorBit , MirrorBit Eclipse ,
TM
ORNAND and combinations thereof, are trademarks and registered trademarks of Spansion LLC in the United States and
other countries. Other names used are for informational purposes only and may be trademarks of their respective owners.
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S6E1A1_DS710-00001-1v0-E, July 16, 2014