DS07-13752-4E

The following document contains information on Cypress products.
FUJITSU MICROELECTRONICS
DATA SHEET
DS07-13752-4E
16-bit Microcontrollers
CMOS
F2MC-16LX MB90950 Series
MB90F952JDS/F952MDS/
MB90V950AJAS/V950AMAS
■ DESCRIPTION
The MB90950-series with 2 FULL-CAN interfaces and Flash ROM is especially designed for automotive and other
industrial applications. Its main feature are the on-board CAN Interfaces, which conform to V2.0 Part A and Part
B, while supporting a very flexible message buffer scheme and so offering more functions than a normal FULLCAN approach. With the new 0.18 μm CMOS technology, Fujitsu now offers on-chip Flash ROM program memory
256 Kbytes.
The power to the MCU core (1.8 V) is supplied by a built-in regulator circuit, giving these microcontrollers superior
performance in terms of power consumption and tolerance to EMI.
Note : F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
For the information for microcontroller supports, see the following web site.
http://edevice.fujitsu.com/micom/en-support/
Copyright©2008-2009 FUJITSU MICROELECTRONICS LIMITED All rights reserved
2009.6
MB90950 Series
■ FEATURES
• CPU
• Instruction system best suited to controller
- Wide choice of data types (bit, byte, word, and long word)
- Wide choice of addressing modes (23 types)
- Enhanced functionality with signed multiply and divide instructions and the RETI instruction
- Enhanced high-precision computing with 32-bit accumulator
• Instruction system compatible with high-level language (C language) and multitask
- Employing system stack pointer
- Various enhanced pointer indirect instructions
- Barrel shift instructions
• Increased processing speed
4-byte instruction queue
• Serial interface
• UART (LIN/SCI): 7 channels
- Equipped with full-duplex double buffer
- Clock-asynchronous or clock-synchronous serial transmission is available
• I2C interface: 2 channels
Up to 400 kbps transfer rate
• Interrupt controller
• Powerful 8-level, 34-condition interrupt feature
• Up to 16 external interrupts are supported
• Automatic data transfer function independent of CPU
Expanded intelligent I/O service function (EI2OS): up to 16 channels
DMA function: up to 16 channels
• I/O ports
• General-purpose input/output port (CMOS output) : 82 ports
• 8/10-bit A/D converter: 24 channels
• Resolution is selectable between 8-bit and 10-bit.
• Activation by external trigger input is allowed.
• Conversion time: 3 μs (at 32-MHz machine clock, including sampling time)
• 8-bit D/A converter: 2 channels
• Program patch function
Detects address matches against 6 address pointers
• Timer
• Time-base timer, watch timer, watchdog timer: 1 channel
• 8/16-bit PPG timer: 8-bit × 16 channels, or 16-bit × 8 channels
• 16-bit reload timer: 4 channels
• 16-bit input/output timer
- 16-bit free-run timer: 2 channels
(FRT0: ICU 0/1/2/3, OCU 0/1/2/3, FRT1: ICU 4/5/6/7, OCU 4/5/6/7)
- 16-bit input capture: (ICU): 8 channels
- 16-bit output compare: (OCU): 8 channels
(Continued)
2
DS07-13752-4E
MB90950 Series
(Continued)
• FULL-CAN controller
• 2 channels
• Compliant with Ver2.0A and Ver2.0B CAN specifications
• 16 built-in message buffers
• CAN wake-up function
• Low power consumption (standby) mode
• Sleep mode (a mode that halts CPU operating clock)
• Timebase timer mode (a mode where only the oscillation clock, sub clock, timebase timer and watch timer
operate)
• Watch mode (a mode that operates sub clock and clock timer only)
• Stop mode (a mode that stops oscillation clock and sub clock)
• CPU intermittent operation mode
• Technology
0.18 μm CMOS technology
DS07-13752-4E
3
MB90950 Series
■ PRODUCT LINEUP
Part Number
MB90V950AJAS
MB90V950AMAS
MB90F952JDS
MB90F952MDS
Parameter
Type
Evaluation products
Flash memory products
2
F MC-16LX CPU
CPU
On-chip PLL clock multiplier (×1, ×2, ×3, ×4, ×6, ×8, 1/2 when PLL stops)
Minimum instruction execution time : 31.25 ns (4 MHz osc. PLL × 8)
System clock
ROM
External
Main 256 Kbytes
Satellite 32 Kbytes
RAM
30 Kbytes
16 Kbytes
Yes
⎯
Rev 050617
⎯
MB2147-20 Rev.04C or later
⎯
Emulator-specific
power supply*1
FPGA data*2
Adaptor board*
2
Clock supervisor
Yes
No
Yes
No
Clock calibration
unit
Yes
No
Yes
No
Low-voltage/CPU
operation detection
reset
No
(CPU operation
detection reset only)
No
Yes
No
Technology
0.35 μm CMOS with built-in
power supply regulator
0.18 μm CMOS with built-in power supply
regulator + Flash memory with Charge pump
for programming voltage
5 V ± 10%
3.0 V to 5.5 V : When normal operating
4.0 V to 5.5 V : When Flash programming
4.5 V to 5.5 V : When using the external bus
⎯
−40 °C to +105 °C
PGA-299
QFP-100, LQFP-100
Operating
voltage range
Operating ambient
temperature
Package
7 channels
UART
I2C (400 kbps)
Wide range of baud rate settings using a dedicated reload timer
Special synchronous options for adapting to different synchronous serial protocols
LIN functionality working either as master or slave LIN device
2 channels
24 input channels
A/D Converter
10-bit or 8-bit resolution
Conversion time : Min 3 μs include sample time (per one channel)
16-bit Reload Timer Operation clock frequency : fsys/21, fsys/23, fsys/25 (fsys = Machine clock frequency)
Supports External Event Count function
(4 channels)
(Continued)
4
DS07-13752-4E
MB90950 Series
Part Number
MB90V950AJAS
MB90V950AMAS
MB90F952JDS
MB90F952MDS
Parameter
16-bit I/O Timer
(2 channels)
Generates an interrupt signal on overflow
Supports Timer Clear when the output compare finds a match
Operation clock freq. : fsys, fsys/21, fsys/22, fsys/23, fsys/24, fsys/25, fsys/26, fsys/27
(fsys = Machine clock freq.)
I/O Timer 0 (clock input FRCK0) corresponds to ICU0/1/2/3, OCU 0/1/2/3
I/O Timer 1 (clock input FRCK1) corresponds to ICU4/5/6/7, OCU 4/5/6/7
16-bit Output
Compare
(8 channels)
Generates an interrupt signal when one of the 16-bit I/O timer matches the output compare
register
A pair of compare registers can be used to generate an output signal.
16-bit Input Capture Holds free-run timer on rising edge, falling edge or rising & falling edge
(8 channels)
Signals an interrupt upon external event
8/16-bit
Programmable
Pulse Generator
8 channels (16-bit) /16 channels (8-bit)
Sixteen 8-bit reload counters
Sixteen 8-bit reload registers for L pulse width
Sixteen 8-bit reload registers for H pulse width
Supports 8-bit and 16-bit operation modes
A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as
8-bit prescaler plus 8-bit reload counter
Operating clock freq. : fsys, fsys/21, fsys/22, fsys/23, fsys/24 or 128 [email protected] = 4 MHz
(fsys = Machine clock frequency, fosc = Oscillation clock frequency)
3 channels
CAN Interface
External Interrupt
(16 channels)
2 channels
Conforms to CAN Specification Version 2.0 Part A and B
Automatic re-transmission in case of error
Automatic transmission in response to Remote Frames
Prioritized 16 message buffers for data and ID’s
Supports multiple messages
Flexible configuration of acceptance filtering :
Full bit compare/Full bit mask/Two partial bit masks
Supports up to 1 Mbps
Can be used rising edge, falling edge, starting up by H/L level input, external interrupt,
expanded intelligent I/O services (EI2OS) and DMA
D/A converter
Sub clock
I/O Ports
2 channels
Yes
No
Yes
No
Virtually all external pins can be used as general purpose I/O port
All ports are push-pull outputs
Bit-wise settable as input/output or peripheral signal
Can be configured 8 as CMOS schmitt trigger/ automotive inputs (in blocks of 8 pins)
TTL input level settable for external bus (32-pin only for external bus)
(Continued)
DS07-13752-4E
5
MB90950 Series
(Continued)
Part Number
MB90V950AJAS
MB90V950AMAS
MB90F952JDS
MB90F952MDS
Parameter
Flash Memory
⎯
Supports automatic programming, Embedded Algorithm
Write/Erase/Erase-Suspend/Resume commands
A flag indicating completion of the algorithm
Boot block configuration
Erase can be performed on each block
Block protection with external programming
voltage
Flash Security Feature for protecting the
content of the Flash
*1 : It is setting of Jumper switch (TOOL VCC) when Emulator (MB2147-01) is used.
Please refer to the Emulator hardware manual for details.
*2 : Customers considering the use of other FPGA data and the adaptor boards should consult with sales representatives.
6
DS07-13752-4E
MB90950 Series
■ PIN ASSIGNMENTS
• MB90F952JDS, MB90F952MDS
MD2
RST
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
50
81
82
49
83
48
84
47
85
46
86
45
87
44
88
43
89
42
90
41
91
40
92
39
93
38
94
37
95
36
96
35
97
34
98
33
99
32
100
31
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
P75/AN21/INT5
P74/AN20/INT4
P73/AN19/INT3
P72/AN18/INT2
P71/AN17/INT1
P70/AN16/INT0
Vss
P67/AN7/PPGE(F)
P66/AN6/PPGC(D)
P65/AN5/PPGA(B)
P64/AN4/PPG8(9)
P63/AN3/PPG6(7)
P62/AN2/PPG4(5)
P61/AN1/PPG2(3)
P60/AN0/PPG0(1)
AVss
AVRL
AVRH
AVcc
P57/AN15/DA1
P36/RDY/OUT6
P37/CLK/OUT7
P40
P41
Vcc
Vss
C
P42/IN6/RX1/INT9R
P43/IN7/TX1
P44/SDA0/FRCK0
P45/SCL0/FRCK1
P46/SDA1
P47/SCL1
P50/AN8/SIN2
P51/AN9/SOT2
P52/AN10/SCK2
P53/AN11/TIN3
P54/AN12/TOT3
P55/AN13
P56/AN14/DA0
P34/HRQ/OUT4
P35/HAK/OUT5
P31/RD/IN5
P32/WRL/WR/INT10R
P33/WRH
QFP - 100
P24/A20/IN0
P25/A21/IN1
P26/A22/IN2
P27/A23/IN3
P30/ALE/IN4
P04/AD04/INT12
P05/AD05/INT13
P06/AD06/INT14
P07/AD07/INT15
P10/AD08/TIN1
P11/AD09/TOT1
P12/AD10/SIN3/INT11R
P13/AD11/SOT3
P14/AD12/SCK3
Vcc
Vss
X1
X0
P15/AD13/SIN4
P16/AD14/SOT4
P17/AD15/SCK4
P20/A16/PPG9(8)
P21/A17/PPGB(A)
P22/A18/PPGD(C)
P23/A19/PPGF(E)
MD0
MD1
P03/AD03/INT11
P02/AD02/INT10
P01/AD01/INT9
P00/AD00/INT8
PA1/TX0
PA0/RX0/INT8R
P97/OUT3
P96/OUT2/SCK6
P95/OUT1/SOT6
P94/OUT0/SIN6
P93/PPG7(6)
P92/PPG5(4)/SCK5
P91/PPG3(2)/SOT5
P90/PPG1(0)/SIN5
Vss
Vcc
P87/SCK1
P86/SOT1
P85/SIN1
P84/SCK0/INT15R
P83/SOT0/TOT2
P82/SIN0/TIN2/INT14R
P81/TOT0/CKOT/INT13R
P80/TIN0/ADTG/INT12R
P77/AN23/INT7
P76/AN22/INT6
(TOP VIEW)
(FPT-100P-M06)
(Continued)
DS07-13752-4E
7
MB90950 Series
(Continued)
MD0
RST
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
76
50
77
49
78
48
47
79
46
80
45
81
44
82
43
83
42
84
41
85
40
86
39
87
38
88
37
89
36
90
35
91
34
92
33
93
32
94
31
95
30
96
29
97
98
28
99
27
100
26
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
MD1
MD2
P75/AN21/INT5
P74/AN20/INT4
P73/AN19/INT3
P72/AN18/INT2
P71/AN17/INT1
P70/AN16/INT0
Vss
P67/AN7/PPGE(F)
P66/AN6/PPGC(D)
P65/AN5/PPGA(B)
P64/AN4/PPG8(9)
P63/AN3/PPG6(7)
P62/AN2/PPG4(5)
P61/AN1/PPG2(3)
P60/AN0/PPG0(1)
AVss
AVRL
AVRH
AVcc
P57/AN15/DA1
P56/AN14/DA0
P55/AN13
P54/AN12/TOT3
P32/WRL/WR/INT10R
P33/WRH
P34/HRQ/OUT4
P35/HAK/OUT5
P36/RDY/OUT6
P37/CLK/OUT7
P40
P41
Vcc
Vss
C
P42/IN6/RX1/INT9R
P43/IN7/TX1
P44/SDA0/FRCK0
P45/SCL0/FRCK1
P46/SDA1
P47/SCL1
P50/AN8/SIN2
P51/AN9/SOT2
P52/AN10/SCK2
P53/AN11/TIN3
LQFP - 100
P26/A22/IN2
P27/A23/IN3
P30/ALE/IN4
P31/RD/IN5
P01/AD01/INT9
P02/AD02/INT10
P03/AD03/INT11
P04/AD04/INT12
P05/AD05/INT13
P06/AD06/INT14
P07/AD07/INT15
P10/AD08/TIN1
P11/AD09/TOT1
P12/AD10/SIN3/INT11R
P13/AD11/SOT3
P14/AD12/SCK3
Vcc
Vss
X1
X0
P15/AD13/SIN4
P16/AD14/SOT4
P17/AD15/SCK4
P20/A16/PPG9(8)
P21/A17/PPGB(A)
P22/A18/PPGD(C)
P23/A19/PPGF(E)
P24/A20/IN0
P25/A21/IN1
P81/TOT0/CKOT/INT13R
P80/TIN0/ADTG/INT12R
P77/AN23/INT7
P76/AN22/INT6
P00/AD00/INT8
PA1/TX0
PA0/RX0/INT8R
P97/OUT3
P96/OUT2/SCK6
P95/OUT1/SOT6
P94/OUT0/SIN6
P93/PPG7(6)
P92/PPG5(4)/SCK5
P91/PPG3(2)/SOT5
P90/PPG1(0)/SIN5
Vss
Vcc
P87/SCK1
P86/SOT1
P85/SIN1
P84/SCK0/INT15R
P83/SOT0/TOT2
P82/SIN0/TIN2/INT14R
(TOP VIEW)
(FPT-100P-M20)
8
DS07-13752-4E
MB90950 Series
■ PIN DESCRIPTION
Pin No.
Pin name
LQFP100*1
QFP100*2
90
92
X1
91
93
X0
52
54
RST
I/O
Circuit
type*3
A
E
83
84
77 to 84
AD00
to
AD07
G
I/O pins for 8 lower bits of the external address/data bus.
This function is enabled when the external bus is
enabled.
P10
General purpose I/O port
The register can be set to select whether to use a pullup resistor. This function is enabled in single-chip mode.
G
AD08
I/O pin of the external address/data bus (AD08). This
function is enabled when the external bus is enabled.
TIN1
Event input pin for the reload timer 1
P11
General purpose I/O port
The register can be set to select whether to use a pullup resistor. This function is enabled in single-chip mode.
86
G
AD09
I/O pin of the external address/data bus (AD09). This
function is enabled when the external bus is enabled.
TOT1
Output pin for the reload timer 1
General purpose I/O port
The register can be set to select whether to use a pullup resistor. This function is enabled in single-chip mode.
AD10
N
SIN3
External interrupt request input pin for INT11R
General purpose I/O port
The register can be set to select whether to use a pullup resistor. This function is enabled in single-chip mode.
P13
88
I/O pin of the external address/data bus (AD10). This
function is enabled when the external bus is enabled.
Serial data input pin for UART3
INT11R
86
Reset input pin
External interrupt request input pins for INT8 to INT15.
85
87
Oscillation input pin
INT8
to
INT15
P12
85
Oscillation output pin
General purpose I/O ports
The register can be set to select whether to use a pullup resistor. This function is enabled in single-chip mode.
P00 to P07
75 to 82
Function
G
AD11
I/O pin of the external address/data bus (AD11). This
function is enabled when the external bus is enabled.
SOT3
Serial data output pin for UART3
(Continued)
DS07-13752-4E
9
MB90950 Series
Pin No.
LQFP100*1
QFP100*2
Pin name
I/O
Circuit
type*3
General purpose I/O port
The register can be set to select whether to use a pullup resistor. This function is enabled in single-chip mode.
P14
87
89
G
AD12
I/O pin of the external address/data bus (AD12). This
function is enabled when the external bus is enabled.
SCK3
Clock I/O pin for UART3
General purpose I/O port
The register can be set to select whether to use a pullup resistor. This function is enabled in single-chip mode.
P15
92
93
94
N
AD13
I/O pin of the external address/data bus (AD13). This
function is enabled when the external bus is enabled.
SIN4
Serial data input pin for UART4
P16
General purpose I/O port
The register can be set to select whether to use a pullup resistor. This function is enabled in single-chip mode.
95
G
AD14
I/O pin of the external address/data bus (AD14). This
function is enabled when the external bus is enabled.
SOT4
Serial data output pin for UART4
General purpose I/O port
The register can be set to select whether to use a pullup resistor. This function is enabled in single-chip mode.
P17
94
96
G
AD15
I/O pin of the external address/data bus (AD15). This
function is enabled when the external bus is enabled.
SCK4
Clock I/O pin for UART4
General purpose I/O ports
The register can be set to select whether to use a pullup resistor.In external bus mode, the pin is enabled as a
general-purpose I/O port when the corresponding bit in
the external address output control register (HACR) is 1.
P20 to P23
95 to 98
97 to 100
Function
A16 to A19
PPG9,
PPGB,
PPGD,
PPGF
G
A16 to A19 for output pins of the external address/data
bus. When the corresponding bit in the external address
output control register (HACR) is 0, the pins are enabled
as high address output pins (A16 to A19).
Output pins for PPGs
(Continued)
10
DS07-13752-4E
MB90950 Series
Pin No.
LQFP100*1
QFP100*2
Pin name
I/O
Circuit
type*3
General purpose I/O ports
The register can be set to select whether to use a pull-up
resistor. In external bus mode, the pin is enabled as a
general-purpose I/O port when the corresponding bit in the
external address output control register (HACR) is 1.
P24 to P27
99, 100, 1, 2
1 to 4
G
A20 to A23
A20 to A23 for output pins of the external address/data
bus. When the corresponding bit in the external address
output control register (HACR) is 0, the pins are enabled as
high address output pins (A20 to A23).
IN0 to IN3
Data sample input pins for input capture ICU0 to ICU3.
General purpose I/O port
The register can be set to select whether to use a pull-up
resistor. This function is enabled in single-chip mode.
P30
3
4
5
Function
5
G
ALE
Address latch enable output pin. This function is enabled
when the external bus is enabled.
IN4
Data sample input pin for input capture ICU4.
P31
General purpose I/O port
The register can be set to select whether to use a pull-up
resistor. This function is enabled in single-chip mode.
6
G
RD
External read strobe output pin for data bus. This function
is enabled when the external bus is enabled.
IN5
Data sample input pin for input capture ICU5.
P32
General purpose I/O port
The register can be set to select whether to use a pull-up
resistor. This function is enabled either in single-chip mode
or when the WR/WRL pin output is disabled.
7
G
WRL/
WR
INT10R
Write strobe output pin for the external data bus. This
function is enabled when both the external bus and the
WR/WRL pin output are enabled. WRL is used to
write-strobe 8 lower bits of the data bus in 16-bit access
while WR is used to write-strobe 8 bits of the data bus in
8-bit access.
External interrupt request input pin for INT10R.
General purpose I/O port
The register can be set to select whether to use a pull-up resistor.
P33
6
8
G
WRH
This function is enabled either in single-chip mode or when
the WRH pin output is disabled.
Write strobe output pin for the upper 8 bits of the external
data bus. This function is enabled when the external bus is
enabled, when the external bus 16-bit mode is selected,
and when the WRH output pin is enabled.
(Continued)
DS07-13752-4E
11
MB90950 Series
Pin No.
LQFP100*1
QFP100*2
Pin name
I/O
Circuit
type*3
P34
7
9
G
General purpose I/O port
The register can be set to select whether to use a pull-up
resistor.This function is enabled either in single-chip
mode or when the hold function is disabled.
HRQ
Hold request input pin. This function is enabled when both
the external bus and the hold function are enabled.
OUT4
Waveform output pin for output compare OCU4.
General purpose I/O port
The register can be set to select whether to use a pull-up
resistor.This function is enabled either in single-chip
mode or when the hold function is disabled.
P35
8
Function
10
G
HAK
OUT5
Hold acknowledge output pin. This function is enabled
when both the external bus and the hold function are
enabled.
Waveform output pin for output compare OCU5.
General purpose I/O port
The register can be set to select whether to use a pull-up resistor. This function is enabled either in single-chip mode or
P36
9
11
G
RDY
Ready input pin. This function is enabled when both the
external bus and the external ready function are enabled.
OUT6
Waveform output pin for output compare OCU6.
P37
10
12
G
OUT7
13, 14
P40, P41
Waveform output pin for output compare OCU7.
F
P42
16
18
IN6
RX1
F
IN7
TX1
Data sample input pin for input capture ICU6.
RX input pin for CAN1 Interface
External interrupt request input pin for INT9R.
P43
19
General purpose I/O ports
General purpose I/O port
INT9R
17
General purpose I/O port
The register can be set to select whether to use a pull-up
resistor.This function is enabled either in single-chip
mode or when the clock output is disabled.
Clock output pin. This function is enabled when both the
external bus and clock output are enabled.
CLK
11, 12
when the external ready function is disabled.
General purpose I/O port
F
Data sample input pin for input capture ICU7.
TX Output pin for CAN1
(Continued)
12
DS07-13752-4E
MB90950 Series
Pin No.
LQFP100*1
QFP100*2
Pin name
I/O
Circuit
type*3
P44
18
20
SDA0
General purpose I/O port
H
FRCK0
21
SCL0
General purpose I/O port
H
FRCK1
20
22
21
23
P46
SDA1
P47
SCL1
23
24
25
AN8
H
H
O
25
26
27
28
29
30, 31
Serial clock I/O pin for I2C 1
Analog input pin for the A/D converter
P51
General purpose I/O port
AN9
I
AN10
Analog input pin for the A/D converter
Serial data output pin for UART2
General purpose I/O port
I
Analog input pin for the A/D converter
SCK2
Clock I/O pin for UART2
P53
General purpose I/O port
AN11
I
Analog input pin for the A/D converter
TIN3
Event input pin for the reload timer 3
P54
General purpose I/O port
AN12
I
P55
AN13
AN14, AN15
DA0,DA1
Analog input pin for the A/D converter
Output pin for the reload timer 3
I
P56, P57
28, 29
General purpose I/O port
Serial data input pin for UART2
TOT3
27
Serial data I/O pin for I2C 1
SIN2
P52
26
General purpose I/O port
General purpose I/O port
SOT2
24
Serial clock I/O pin for I2C 0
Input pin for the 16-bit I/O Timer1
P50
22
Serial data I/O pin for I2C 0
Input pin for the 16-bit I/O Timer 0
P45
19
Function
General purpose I/O port
Analog input pin for the A/D converter
General purpose I/O ports
J
Analog input pins for the A/D converter
Analog output pins for the D/A converter
(Continued)
DS07-13752-4E
13
MB90950 Series
Pin No.
LQFP100*1
34 to 41
QFP100*2
36 to 43
Pin name
I/O
Circuit
type*3
P60 to P67
General purpose I/O ports
AN0 to AN7
Analog input pins for the A/D converter
PPG0,
PPG2,
PPG4,
PPG6,
PPG8,
PPGA,
PPGC,
PPGE
I
Output pins for PPGs
P70 to P77
43 to 48,
53, 54
45 to 50,
55, 56
AN16
to
AN23
General purpose I/O ports
I
INT0 to INT7
57
TIN0
ADTG
General purpose I/O port
F
INT12R
58
TOT0
CKOT
F
SIN0
TIN2
M
SOT0
F
SCK0
General purpose I/O port
F
INT15R
60
62
61
63
P85
SIN1
P86
SOT1
Serial data output pin for UART 0
Output pin for the reload timer 2
P84
61
Event input pin for the reload timer 2
General purpose I/O port
TOT2
59
Serial data input pin for UART0
External interrupt request input pin for INT14R
P83
60
Output pin for the clock monitor
General purpose I/O port
INT14R
58
Output pin for the reload timer 0
External interrupt request input pin for INT13R
P82
59
Trigger input pin for the A/D converter
General purpose I/O port
INT13R
57
Event input pin for the reload timer 0
External interrupt request input pin for INT12R
P81
56
Analog input pins for the A/D converter
External interrupt request input pins for INT0 to INT7
P80
55
Function
Clock I/O pin for UART0
External interrupt request input pin for INT15R
M
F
General purpose I/O port
Serial data input pin for UART1
General purpose I/O port
Serial data output pin for UART1
(Continued)
14
DS07-13752-4E
MB90950 Series
Pin No.
LQFP100*1
QFP100*2
62
64
Pin
name
P87
SCK1
I/O
Circuit
type*3
F
P90
65
66
67
68
PPG1
M
70
P91
General purpose I/O port
PPG3
F
PPG5
P93
PPG7
70
71
72
OUT0
General purpose I/O port
F
F
72
74
M
75
76
30
32
Waveform output pin for output compare for OCU0. This
function is enabled when the waveform output is enabled.
Serial data input pin for UART6
P95
General purpose I/O port
OUT1
F
OUT2
Waveform output pin for output compare for OCU1.This
function is enabled when the waveform output is enabled.
Serial data output pin for UART6
General purpose I/O port
F
Waveform output pin for output compare for OCU2. This
function is enabled when the waveform output is enabled.
SCK6
Clock I/O pin for UART6
P97
General purpose I/O port
OUT3
F
RX0
PA1
TX0
AVCC
Waveform output pin for output compare for OCU3. This
function is enabled when the waveform output is enabled.
General purpose I/O port
F
INT8R
74
Output pin for PPGs
SIN6
PA0
73
General purpose I/O port
General purpose I/O port
P96
73
Output pin for PPGs
Clock I/O pin for UART5
SOT6
71
Output pin for PPGs
Serial data output pin for UART5
P94
69
Output pin for PPGs
Serial data input pin for UART5
SCK5
68
Clock I/O pin for UART1
SIN5
P92
69
General purpose I/O port
General purpose I/O port
SOT5
67
Function
RX input pin for CAN0 Interface. Outputs generated by
other functions must be stopped when using the CAN
functions.
External interrupt request input pin for INT8R
F
K
General purpose I/O port
TX Output pin for CAN0
VCC power input pin for the Analog circuit
(Continued)
DS07-13752-4E
15
MB90950 Series
(Continued)
Pin No.
I/O
Circuit
type*3
LQFP100*1
QFP100*2
Pin
name
31
33
AVRH
L
Reference voltage input pin for the A/D Converter. This
power supply must be turned on or off while a voltage
higher than or equal to AVRH is applied to AVCC.
32
34
AVRL
K
Lower reference voltage input pin for the A/D Converter
33
35
AVSS
K
VSS power input pin for the Analog circuit
50, 51
52, 53
MD1,
MD0
C
Input pins for specifying the operating mode
49
51
MD2
D
Input pin for specifying the operating mode
13, 63, 88
15, 65, 90
VCC
⎯
Power (3.5 V to 5.5 V) input pins
VSS
⎯
Power (0 V) input pins
C
K
This is the power supply stabilization capacitor. This pin
should be connected to a ceramic capacitor with a
capacitance greater than or equal to 0.1 μF.
14, 42, 64, 89 16, 44, 66, 91
15
17
Function
*1 : FPT-100P-M20
*2 : FPT-100P-M06
*3 : For I/O circuit type, refer to “■ I/O CIRCUIT TYPES”.
16
DS07-13752-4E
MB90950 Series
■ I/O CIRCUIT TYPES
Type
A
Circuit
Remarks
X1
X out
Oscillation circuit
High-speed oscillation feedback
resistor = approx. 1 MΩ
(Flash memory product)
X0
Standby control signal
X1
X out
Oscillation circuit
High-speed oscillation feedback
resistor = approx. 1 MΩ
(Evaluation product)
X0
Standby control signal
B
X1A
Xout
Oscillation circuit
Low-speed oscillation feedback
resistor = approx. 10 MΩ
X0A
Standby control signal
C
CMOS hysteresis
inputs
Evaluation products:
CMOS hysteresis input
Flash memory products:
CMOS input pin
CMOS hysteresis
inputs
Evaluation products:
• CMOS hysteresis input
• Pull-down resistor value: approx. 50 kΩ
Flash memory products:
• CMOS input
• No pull-down
R
D
R
Pull-down
Resistor
(Continued)
DS07-13752-4E
17
MB90950 Series
Type
Circuit
Remarks
E
• CMOS hysteresis input
• Pull-up resistor value: approx. 50 kΩ
Pull-up
Resistor
R
CMOS hysteresis
inputs
F
P-ch
Pout
N-ch
Nout
R
CMOS hysteresis
input
• CMOS level output
(IOL = 4 mA, IOH = −4 mA)
• CMOS hysteresis input
(VIH 0.8 VCC VIL 0.2 VCC)
(with function to disconnect input during
standby)
• Automotive input
(with function to disconnect input during
standby)
Automotive input
Standby control for
input shutdown
G
Pull-up control
P-ch
P-ch
N-ch
Pout
Nout
R
CMOS hysteresis
input
Automotive input
TTL input
• CMOS level output
(IOL = 4 mA, IOH = −4 mA)
• CMOS hysteresis input
(VIH 0.8 VCC VIL 0.2 VCC)
(with function to disconnect input during
standby)
• Automotive input
(with function to disconnect input during
standby)
• TTL input
(with function to disconnect input during
standby)
• Programmable pull-up resistor: 50 kΩ
approx.
Standby control for
input shutdown
(Continued)
18
DS07-13752-4E
MB90950 Series
Type
Circuit
Remarks
H
P-ch
Pout
N-ch
Nout
R
CMOS hysteresis
input
Automotive input
Standby control for
input shutdown
I
P-ch
Pout
N-ch
Nout
R
CMOS hysteresis
input
Automotive input
• CMOS level output
(IOL = 3 mA, IOH = −3 mA)
• CMOS hysteresis input
(VIH 0.8 VCC VIL 0.2 VCC)
(with function to disconnect input during
standby)
• Automotive input (with function to
disconnect input during standby)
• CMOS hysteresis input
(VIH 0.7 VCC VIL 0.3 VCC)
(with function to disconnect input during
standby)
• CMOS level output
(IOL = 4 mA, IOH = −4 mA)
• CMOS hysteresis input
(VIH 0.8 VCC VIL 0.2 VCC)
(with function to disconnect input during
standby)
• Automotive input
(with function to disconnect input during
standby)
• A/D converter analog input
Standby control for
input shutdown
Analog input
J
P-ch
Pout
N-ch
Nout
R
CMOS hysteresis
input
Automotive input
Standby control for
input shutdown
• CMOS level output
(IOL = 4 mA, IOH = −4 mA)
• D/A analog output
• CMOS hysteresis input
(VIH 0.8 VCC VIL 0.2 VCC)
(with function to disconnect input during
standby)
• Automotive input
(with function to disconnect input during
standby)
• A/D converter analog input
• D/A converter analog output
Analog input
Analog output
(Continued)
DS07-13752-4E
19
MB90950 Series
Type
Circuit
Remarks
K
Power supply input protection circuit
P-ch
N-ch
L
ANE
P-ch
AVR
N-ch
ANE
M
P-ch
Pout
N-ch
Nout
R
CMOS hysteresis input
Automotive input
CMOS hysteresis input
A/D converter reference voltage power
supply input pin, with the protection circuit
Flash memory devices do not have
a protection circuit against VCC for
pin AVRH
• CMOS level output
(IOL = 4 mA, IOH = −4 mA)
• CMOS hysteresis input
(VIH 0.8 VCC VIL 0.2 VCC)
(with function to disconnect input during
standby)
• Automotive input
(with function to disconnect input during
standby)
• CMOS hysteresis input
(VIH 0.7 VCC VIL 0.3 VCC)
(with function to disconnect input during
standby)
Standby control for
input shutdown
N
Pull-up control
P-ch
P-ch
Pout
N-ch
Nout
R
CMOS hysteresis input
Automotive input
CMOS hysteresis input
TTL input
Standby control for
input shutdown
• CMOS level output
(IOL = 4 mA, IOH = −4 mA)
• CMOS hysteresis input
(VIH 0.8 VCC VIL 0.2 VCC)
(with function to disconnect input during
standby)
• Automotive input
(with function to disconnect input during
standby)
• TTL input
(with function to disconnect input during
standby)
• CMOS hysteresis input
(VIH 0.7 VCC VIL 0.3 VCC)
(with function to disconnect input during
standby)
• Programmable pull-up resistor: 50 kΩ
approx
(Continued)
20
DS07-13752-4E
MB90950 Series
(Continued)
Type
Circuit
Remarks
O
P-ch
Pout
N-ch
Nout
R
CMOS hysteresis input
Automotive input
CMOS hysteresis input
Standby control for
input shutdown
• CMOS level output
(IOL = 4 mA, IOH = −4 mA)
• CMOS hysteresis input
(VIH 0.8 VCC VIL 0.2 VCC)
(with function to disconnect input during
standby)
• Automotive input
(with function to disconnect input during
standby)
• CMOS hysteresis input
(VIH 0.7 VCC VIL 0.3 VCC)
(with function to disconnect input during
standby)
• A/D converter analog input
Analog input
DS07-13752-4E
21
MB90950 Series
■ HANDLING DEVICES
• Preventing latch-up
CMOS IC chips may suffer latch-up under the following conditions:
• A voltage higher than VCC or lower than VSS is applied to an input or output pin.
• A voltage higher than the rated voltage is applied between VCC and VSS pins.
• The AVCC power supply is applied before the VCC voltage.
Latch-up may increase the power supply current drastically, causing thermal damage to the device.
For the same reason, also be careful not to let the analog power-supply voltage (AVCC, AVRH) exceed the digital
power-supply voltage.
• Handling unused pins
Leaving unused input pins open may result in misbehavior or latch-up and possible permanent damage to the
device. Therefore they must be pulled up or pulled down through resistors. In this case those resistors should
be more than 2 kΩ.
Unused bidirectional pins should be set to the output state and can be left open, or the input state with the above
described connection.
• Power supply pins (VCC/VSS)
• If there are multiple VCC and VSS pins, that are designed to be set to the same potential are connected the
inside of the device to prevent malfunctions such as latch-up.
To reduce unnecessary radiation, prevent malfunctioning of the strobe signal due to the rise of ground level,
and observe the standard for total output current, be sure to connect the VCC and VSS pins to the power supply
and ground externally. Connect VCC and VSS pins to the device from the current supply source at a low impedance.
• As a measure against power supply noise, connect a capacitor of about 0.1 μF as a bypass capacitor between
VCC and VSS pins in the vicinity of VCC and VSS pins of the device
Vcc
Vss
Vcc
Vss
Vss
Vcc
MB90950
Series
Vcc
Vss
Vss
Vcc
• Mode Pins (MD0 to MD2)
Connect the mode pins directly to VCC or VSS pins. To prevent the device unintentionally entering test mode due
to noise, lay out the printed circuit board so as to minimize the distance from the mode pins to VCC or VSS pins
and to provide a low-impedance connection.
22
DS07-13752-4E
MB90950 Series
• Sequence for Turning On the Power Supply to the A/D Converter and Analog Inputs
Make sure to turn on the A/D converter power supply (AVCC, AVRH, AVRL) and analog inputs (AN0 to AN23)
after turning-on the digital power supply (VCC).
Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure
that the voltage does not exceed AVRH or AVCC (turning on/off the analog and digital power supplies simultaneously is acceptable).
• Pin connection when A/D converter is not used
Connect unused pins of A/D converter to AVCC = VCC, AVSS = AVRH = AVRL = VSS.
• Crystal Oscillator Circuit
The X0, X1 pins may be possible causes of abnormal operation. Make sure to provide bypass capacitors via
the shortest distance from X0, X1 pins and crystal oscillator (or ceramic oscillator) and ground lines, and make
sure, to the utmost effort, that the oscillation circuit lines do not cross the lines of other circuits. It is highly
recommended to provide a printed circuit board art work surrounding X0, X1 pins with a ground area for stabilizing
the operation.
For each of the mass-production products, request an oscillator evaluation from the manufacturer of the oscillator
you are using.
• Pull-up/down resistors
The MB90950 Series does not support internal pull-up/down resistors (except for the pull-up resistors built into
ports 0 to 3). Use external components where needed.
• Using external clock
The external clock inputs can not be used.
• Notes on operation in PLL clock mode
If PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even when
there is no external oscillator or the external clock input is stopped. Performance of this operation, however,
cannot be guaranteed.
• Notes on Power-On
To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during power-on to 50 μs
or more (0.2 V to 2.7 V) .
• Stabilization of power supply voltage
A sudden change in the supply voltage may cause the device to malfunction even within the specified VCC supply
voltage operating range. Therefore, the VCC supply voltage should be stabilized.
Stabilize the power supply voltage as follows as a standard level of stabilization.
• VCC ripple variations (peak-to-peak value) at commercial frequencies (50 Hz/60 Hz) fall below 10% of the
standard VCC supply voltage
• The coefficient of fluctuation does not exceed 0.1 V/ms at instantaneous power switching.
• Initialization
In the device, there are internal registers which are initialized only by a power-on reset. To initialize these registers,
turn on the power again.
DS07-13752-4E
23
MB90950 Series
• Port 0 to Port 3 Output During Power-on (External-bus Mode)
As shown below, when the power is turned on in External-Bus mode, there is a possibility that output signal of
Port 0 to Port 3 might be unstable irrespective of the reset input.
1/2VCC
VCC
Port0 to Port3
Port0 to Port3 outputs
might be unstable
Port0 to Port3 outputs = Hi-Z
• Notes on Using the CAN Function
To use the CAN function, please set the DIRECT bit of the CAN Direct Mode Register (CDMR) to 1.
If the DIRECT bit is set to '0' (initial value) only MB90V950AJAS and MB90V950AMAS, wait states will be
performed when accessing CAN registers.
Note : Please refer to the Hardware Manual of the MB90950 series for detail of CAN Direct Mode Register.
• Flash Security Function
A security bit is located in the area of the Flash memory.
If protection code 01H is written in the security bit, the Flash memory is in the protected state by security.
Therefore please do not write 01H in this address if you do not use the security function.
Refer to following table for the address of the security bit.
MB90F952JDS, MB90F952MDS
24
Flash memory size
Address of the security bit
Embedded 2 Mbits Flash Memory
FC0001H
DS07-13752-4E
MB90950 Series
■ BLOCK DIAGRAMS
MB90V950AJAS,MB90V950AMAS
X0,X1
Clock
RST
Controller
CR
oscillation
circuit*
16LX
CPU
Clock
calibration
unit*
I/O Timer 0
FRCK0
Input
Capture
8 channels
IN7 to IN0
RAM
30 Kbytes
Output
Compare
8 channels
OUT7 to OUT0
Prescaler
7 channels
I/O Timer 1
UART
7 channels
CAN
Controller
3 channels
CPU Operation
detection circuit*
AVCC
AVSS
AN23 to AN0
AVRH
AVRL
ADTG
DA01, DA00
16-bit
Reload Timer
4 channels
8/10-bit
A/D converter
24 channels
8-bit
D/A converter
2 channels
RX2 to RX0
TX2 to TX0
TIN3 to TIN0
TOT3 to TOT0
AD15 to AD00
F2MC-16 Bus
SOT6 to SOT0
SCK6 to SCK0
SIN6 to SIN0
FRCK1
A23 to A16
ALE
RD
External
Bus
Interface
WR/WRL
WRH
HRQ
PPGF to PPG0
SDA1, SDA0
SCL1, SCL0
HAK
8/16-bit
PPG
16 channels
I2C
Interface
2 channels
DMAC
RDY
CLK
DTP/External
Interrupt
16 channels
Clock
Monitor
INT15 to INT8
(INT15R to INT8R)
INT7 to INT0
CKOT
* : Only for MB90V950AJAS
DS07-13752-4E
25
MB90950 Series
MB90F952JDS, MB90F952MDS
X0,X1
Clock
Controller
RST
CR
oscillation
circuit*
16LX
CPU
Clock
calibration
unit*
Low voltage detection circuit
CPU operation detection circuit*
RAM
16 Kbytes
Flash
256 Kbytes
+32 Kbytes
I/O Timer 0
FRCK0
Input
Capture
8 channels
IN7 to IN0
Output
Compare
8 channels
OUT7 to OUT0
I/O Timer 1
FRCK1
Prescaler
7 channels
AVCC
AVSS
AN15 to AN0
AN23 to AN16
AVRH
AVRL
ADTG
DA01, DA00
PPGF to PPG0
SDA1, SDA0
SCL1, SCL0
UART
7 channels
16-bit
Reload Timer
4 channels
8/10-bit
A/D converter
16/24
channels
8-bit
D/A converter
2 channels
DMAC
TIN3 to TIN0
TOT3 to TOT0
A23 to A16
ALE
RD
External
Bus
Interface
WR/WRL
WRH
HRQ
HAK
8/16-bit
PPG
16 channels
I2C
Interface
2 channels
RX0, RX1
TX0, TX1
AD15 to AD00
F2MC-16 Bus
SOT6 to SOT0
SCK6 to SCK0
SIN6 to SIN0
CAN
Controller
2 channels
RDY
CLK
DTP/External
Interrupt
16 channels
Clock
Monitor
INT15 to INT8
(INT15R to INT8R)
INT7 to INT0
CKOT
* : Only for devices with a J suffix in the part number
26
DS07-13752-4E
MB90950 Series
■ MEMORY MAP
MB90V950AJAS,
MB90V950AMAS
MB90F952JDS,
MB90F952MDS
FFFFFFH
FFFFFFH
ROM (FF bank)
ROM (FF bank)
FF0000H
FEFFFFH
FF0000H
FEFFFFH
ROM (FE bank)
FE0000H
FDFFFFH
ROM (FE bank)
FE0000H
FDFFFFH
ROM (FD bank)
FD0000H
FCFFFFH
ROM (FD bank)
FD0000H
FCFFFFH
ROM (FC bank)
FC0000H
FBFFFFH
FB0000H
FAFFFFH
FA0000H
F9FFFFH
F90000H
F8FFFFH
ROM (FC bank)
FC0000H
ROM (FB bank)
ROM (FA bank)
ROM (F9 bank)
F77FFFH
ROM (Satellite)
F70000H
F6FFFFH
External access
area
ROM (F8 bank)
F80000H
00FFFFH
008000H
007FFFH
External access area
ROM
(image of FF bank)
00FFFFH
008000H
007FFFH
Peripheral
Peripheral
007900H
0078FFH
ROM
(image of FF bank)
007900H
RAM 30 Kbytes
003FFFH
RAM 16 Kbytes
000100H
000100H
External access area
External access area
0000EFH
000000H
Peripheral
0000EFH
000000H
Peripheral
: Not accessible
Note: An image of the data in the FF bank of ROM is visible in the upper part of bank 00, which makes it possible
for the C compiler to use the small memory model. The lower 16 bits of addresses in the FF bank are the
same as the lower 16 bits of addresses in the 00 bank so that tables stored in the ROM can be accessed
without using the far specifier in the pointer declaration.
For example, when the address 00C000H is accessed, the data at FFC000H in ROM is actually accessed.
The ROM area in bank FF exceeds 32 Kbytes, and its entire image cannot be shown in bank 00.
As a result, the image between FF8000H and FFFFFFH is visible in bank 00, while the image between FF0000H
and FF7FFFH is visible only in bank FF.
DS07-13752-4E
27
MB90950 Series
■ I/O MAP
Address
Register
Abbreviation
Access
Resource name
Initial value
000000H Port 0 Data Register
PDR0
R/W
Port 0
XXXXXXXXB
000001H Port 1 Data Register
PDR1
R/W
Port 1
XXXXXXXXB
000002H Port 2 Data Register
PDR2
R/W
Port 2
XXXXXXXXB
000003H Port 3 Data Register
PDR3
R/W
Port 3
XXXXXXXXB
000004H Port 4 Data Register
PDR4
R/W
Port 4
XXXXXXXXB
000005H Port 5 Data Register
PDR5
R/W
Port 5
XXXXXXXXB
000006H Port 6 Data Register
PDR6
R/W
Port 6
XXXXXXXXB
000007H Port 7 Data Register
PDR7
R/W
Port 7
XXXXXXXXB
000008H Port 8 Data Register
PDR8
R/W
Port 8
XXXXXXXXB
000009H Port 9 Data Register
PDR9
R/W
Port 9
XXXXXXXXB
00000AH Port A Data Register
PDRA
R/W
Port A
111111XXB
00000BH Analog Input Enable Register 5
ADER5
R/W
Port 5, A/D
11111111B
00000CH Analog Input Enable Register 6
ADER6
R/W
Port 6, A/D
11111111B
00000DH Analog Input Enable Register 7
ADER7
R/W
Port 7, A/D
11111111B
00000EH Input Level Select Register 0
ILSR0
R/W
Port 0 to 7
XXXXXXXXB
00000FH Input Level Select Register 1
ILSR1
R/W
Port 0 to 3,
Port 8 to A
XXXX0XXXB
000010H Port 0 Direction Register
DDR0
R/W
Port 0
00000000B
000011H Port 1 Direction Register
DDR1
R/W
Port 1
00000000B
000012H Port 2 Direction Register
DDR2
R/W
Port 2
00000000B
000013H Port 3 Direction Register
DDR3
R/W
Port 3
00000000B
000014H Port 4 Direction Register
DDR4
R/W
Port 4
00000000B
000015H Port 5 Direction Register
DDR5
R/W
Port 5
00000000B
000016H Port 6 Direction Register
DDR6
R/W
Port 6
00000000B
000017H Port 7 Direction Register
DDR7
R/W
Port 7
00000000B
000018H Port 8 Direction Register
DDR8
R/W
Port 8
00000000B
000019H Port 9 Direction Register
DDR9
R/W
Port 9
00000000B
00001AH Port A Direction Register
DDRA
R/W
Port A
00000100B
00001BH
Reserved
00001CH Port 0 Pull-up Control Register
PUCR0
R/W
Port 0
00000000B
00001DH Port 1 Pull-up Control Register
PUCR1
R/W
Port 1
00000000B
00001EH Port 2 Pull-up Control Register
PUCR2
R/W
Port 2
00000000B
00001FH Port 3 Pull-up Control Register
PUCR3
R/W
Port 3
00000000B
(Continued)
28
DS07-13752-4E
MB90950 Series
Abbreviation
Access
000020H Serial Mode Register 0
SMR0
W, R/W
00000000B
000021H Serial Control Register 0
SCR0
W, R/W
00000000B
000022H Reception/Transmission Data Register 0
RDR0/
TDR0
R/W
00000000B/
11111111B
000023H Serial Status Register 0
SSR0
R, R/W
ECCR0
R, W,
R/W
000025H Extended Status/Control Register 0
ESCR0
R/W
00000X00B
000026H Baud Rate Generator Register 00
BGR00
R, R/W
00000000B
000027H Baud Rate Generator Register 01
BGR01
R, R/W
00000000B
000028H Serial Mode Register 1
SMR1
W, R/W
00000000B
000029H Serial Control Register 1
SCR1
W, R/W
00000000B
00002AH Reception/Transmission Data Register 0
RDR1/
TDR1
R/W
00000000B/
11111111B
00002BH Serial Status Register 1
SSR1
R, R/W
ECCR1
R, W,
R/W
00002DH Extended Status/Control Register 1
ESCR1
R/W
00000X00B
00002EH Baud Rate Generator Register 10
BGR10
R, R/W
00000000B
00002FH Baud Rate Generator Register 11
BGR11
R, R/W
00000000B
000030H PPG0 Operation Mode Control Register
PPGC0
W, R/W
Address
000024H
00002CH
Register
Extended Communication Control
Register 0
Extended Communication Control
Register 1
000031H PPG1 Operation Mode Control Register
PPGC1
W, R/W
000032H PPG0/PPG1 Count Clock Select Register
PPG01
R/W
000033H
000034H PPG2 Operation Mode Control Register
PPGC2
W, R/W
000036H PPG2/PPG3 Count Clock Select Register
PPG23
R/W
UART1
00001000B
000000XXB
01000111B
16-bit
PPG0/PPG1
01000001B
00000010B
01000111B
16-bit
PPG2/PPG3
01000001B
00000010B
Reserved
PPGC4
W, R/W
000039H PPG5 Operation Mode Control Register
PPGC5
W, R/W
00003AH PPG4/PPG5 Clock Select Register
PPG45
R/W
00003BH Address Detect Control Register 1
PACSR1
R/W
00003CH PPG6 Operation Mode Control Register
PPGC6
W, R/W
00003DH PPG7 Operation Mode Control Register
PPGC7
W, R/W
00003EH PPG6/PPG7 Count Clock Select Register
PPG67
R/W
00003FH
00001000B
000000XXB
W, R/W
PPGC3
000038H PPG4 Operation Mode Control Register
UART0
Initial value
Reserved
000035H PPG3 Operation Mode Control Register
000037H
Resource name
01000111B
16-bit
PPG4/PPG5
01000001B
00000010B
Address Match
Detection 1
11000000B
01000111B
16-bit
PPG6/PPG7
01000001B
00000010B
Reserved
(Continued)
DS07-13752-4E
29
MB90950 Series
Address
Register
000040H PPG8 Operation Mode Control Register
Abbreviation
Access
PPGC8
W, R/W
000041H PPG9 Operation Mode Control Register
PPGC9
W, R/W
000042H PPG8/PPG9 Count Clock Select Register
PPG89
R/W
000043H
000044H PPGA Operation Mode Control Register
PPGCA
W, R/W
000046H PPGA/PPGB Count Clock Select Register
PPGAB
R/W
PPGCC
W, R/W
00004AH PPGC/PPGD Count Clock Select Register
PPGCD
R/W
01000001B
00000010B
01000111B
16-bit
PPGC/PPGD
01000001B
00000010B
Reserved
PPGCE
W, R/W
00004DH PPGF Operation Mode Control Register
PPGCF
W, R/W
00004EH PPGE/PPGF Count Clock Select Register
PPGEF
R/W
00004FH
01000111B
16-bit
PPGA/PPGB
W, R/W
PPGCD
00004CH PPGE Operation Mode Control Register
00000010B
Reserved
000049H PPGD Operation Mode Control Register
00004BH
01000001B
W, R/W
PPGCB
000048H PPGC Operation Mode Control Register
01000111B
16-bit
PPG8/PPG9
Reserved
000045H PPGB Operation Mode Control Register
000047H
Resource name Initial value
01000111B
16-bit
PPGE/PPGF
01000001B
00000010B
Reserved
000050H Input Capture Control Status 0/1
ICS01
R/W
000051H Input Capture Edge 0/1
ICE01
R/W, R
000052H Input Capture Control Status 2/3
ICS23
R/W
000053H Input Capture Edge 2/3
ICE23
R
000054H Input Capture Control Status 4/5
ICS45
R/W
000055H Input Capture Edge 4/5
ICE45
R
000056H Input Capture Control Status 6/7
ICS67
R/W
000057H Input Capture Edge 6/7
ICE67
R/W, R
000058H Output Compare Control Status 0
OCS0
R/W
000059H Output Compare Control Status 1
OCS1
R/W
00005AH Output Compare Control Status 2
OCS2
R/W
00005BH Output Compare Control Status 3
OCS3
R/W
00005CH Output Compare Control Status 4
OCS4
R/W
00005DH Output Compare Control Status 5
OCS5
R/W
00005EH Output Compare Control Status 6
OCS6
R/W
00005FH Output Compare Control Status 7
OCS7
R/W
000060H Timer Control Status 0
TMCSR0
R/W
000061H Timer Control Status 0
TMCSR0
R/W
000062H Timer Control Status 1
TMCSR1
R/W
000063H Timer Control Status 1
TMCSR1
R/W
Input Capture 0/1
Input Capture 2/3
Input Capture 4/5
Input Capture 6/7
Output Compare
0/1
Output Compare
2/3
Output Compare
4/5
Output Compare
6/7
16-bit reload
timer 0
16-bit reload
timer 1
00000000B
111010XXB
00000000B
111111XXB
00000000B
111100XXB
00000000B
111000XXB
00001100B
01100000B
00001100B
01100000B
00001100B
01100000B
00001100B
01100000B
00000000B
11110000B
00000000B
11110000B
(Continued)
30
DS07-13752-4E
MB90950 Series
Abbreviation
Access
Resource name
Initial value
000064H Timer Control Status 2
TMCSR2
R/W
00000000B
000065H Timer Control Status 2
TMCSR2
R/W
16-bit reload
timer 2
000066H Timer Control Status 3
TMCSR3
R/W
000067H Timer Control Status 3
TMCSR3
R/W
000068H A/D Control Status 0
ADCS0
R/W
00011110B
000069H A/D Control Status 1
ADCS1
R/W
00000001B
00006AH A/D Data 0
ADCR0
R
00006BH A/D Data 1
ADCR1
R
00006CH ADC Setting 0
ADSR0
R/W
00000000B
00006DH ADC Setting 1
ADSR1
R/W
00000000B
LVRC
R/W
Low Voltage/CPU
Operation
Detection Reset
00111000B
ROMM
W
ROM Mirror
11111101B
Address
00006EH
Register
Low Voltage/CPU OPeration Detection Reset Control Register
00006FH ROM Mirror Function Setting
000070H
to
00008FH
Reserved for CAN Controller
000090H
to
00009AH
Reserved
DMA Descriptor Channel Specified
Register
16-bit reload
timer 3
A/D Converter
11110000B
00000000B
11110000B
00000000B
11111100B
DCSR
R/W
00009CH DMA Status Register L
DSRL
R/W
00009DH DMA Status Register H
DSRH
R/W
PACSR0
R/W
Address Match
Detection 0
11000000B
DIRR
R/W
Delayed Interrupt
Generation
Module
11111110B
0000A0H Low-power Mode Control Register
LPMCR
W, R/W
Low Power
Control Circuit
00011000B
0000A1H Clock Selection Register
CKSCR
R, R/W
Low Power
Control Circuit
11111100B
0000A2H,
0000A3H
Reserved
DSSR
R/W
DMA
00000000B
00009BH
00009EH Address Detect Control Register 0
00009FH
Delayed Interrupt Trigger/Release
Register
0000A4H DMA Stop Status Register
0000A5H
Automatic Ready Function Select
Register
ARSR
W
0000A6H
External Address Output Control
Register
HACR
W
ECSR
W
0000A7H Bus Control Signal Selection Register
00000000B
DMA
00000000B
00000000B
00111100B
External Memory
Access
00000000B
00000001B
(Continued)
DS07-13752-4E
31
MB90950 Series
Address
Register
Abbreviation
Access Resource name Initial value
0000A8H Watchdog Control Register
WDTC
R, W
0000A9H Time Base Timer Control Register
TBTC
W, R/W
Time Base
Timer
11100100B
0000AAH Watch Timer Control Register
WTC
R, R/W
Watch Timer
1X001000B
0000ABH
Reserved
0000ACH DMA Enable Register L
DERL
R/W
0000ADH DMA Enable Register H
DERH
R/W
FMCS
R, R/W
0000AEH
Watchdog Timer X1XXX111B
Flash Control Status Register
(Flash memory devices only)
0000AFH
00000000B
DMA
00000000B
Flash Memory
000X0000B
Reserved
0000B0H Interrupt Control Register 00
ICR00
W, R/W
00000111B
0000B1H Interrupt Control Register 01
ICR01
W, R/W
00000111B
0000B2H Interrupt Control Register 02
ICR02
W, R/W
00000111B
0000B3H Interrupt Control Register 03
ICR03
W, R/W
00000111B
0000B4H Interrupt Control Register 04
ICR04
W, R/W
00000111B
0000B5H Interrupt Control Register 05
ICR05
W, R/W
00000111B
0000B6H Interrupt Control Register 06
ICR06
W, R/W
00000111B
0000B7H Interrupt Control Register 07
ICR07
W, R/W
0000B8H Interrupt Control Register 08
ICR08
W, R/W
0000B9H Interrupt Control Register 09
ICR09
W, R/W
00000111B
0000BAH Interrupt Control Register 10
ICR10
W, R/W
00000111B
0000BBH Interrupt Control Register 11
ICR11
W, R/W
00000111B
0000BCH Interrupt Control Register 12
ICR12
W, R/W
00000111B
0000BDH Interrupt Control Register 13
ICR13
W, R/W
00000111B
0000BEH Interrupt Control Register 14
ICR14
W, R/W
00000111B
0000BFH Interrupt Control Register 15
ICR15
W, R/W
00000111B
0000C0H D/A Converter Data 0
DAT0
R/W
XXXXXXXXB
0000C1H D/A Converter Data 1
DAT1
R/W
0000C2H D/A Control 0
DACR0
R/W
0000C3H D/A Control 1
DACR1
R/W
00000000B
00000000B
0000C4H,
0000C5H
Interrupt Control
D/A Converter
00000111B
00000111B
XXXXXXXXB
00000000B
Reserved
0000C6H External Interrupt Enable 0
ENIR0
R/W
0000C7H External Interrupt Source 0
EIRR0
R/W
0000C8H Detection Level Setting 0
ELVR0
R/W
0000C9H Detection Level Setting 0
ELVR0
R/W
DTP/External
Interrupt 0
XXXXXXXXB
00000000B
00000000B
(Continued)
32
DS07-13752-4E
MB90950 Series
Address
Register
0000CAH External Interrupt Enable 1
Abbreviation
Access
ENIR1
R/W
Resource name Initial value
00000000B
0000CBH External Interrupt Source 1
EIRR1
R/W
0000CCH Detection Level Setting 1
ELVR1
R/W
0000CDH Detection Level Setting 1
ELVR1
R/W
00000000B
0000CEH External Interrupt Source Select
EISSR
R/W
00000000B
0000CFH PLL/Sub clock Control Register
PSCCR
W
0000D0H DMA Buffer Address Pointer L Register
BAPL
R/W
XXXXXXXXB
0000D1H DMA Buffer Address Pointer M Register
BAPM
R/W
XXXXXXXXB
0000D2H DMA Buffer Address Pointer H Register
BAPH
R/W
XXXXXXXXB
DMACS
R/W
0000D4H I/O Register Address Pointer L Register
IOAL
R/W
0000D5H I/O Register Address Pointer H Register
IOAH
R/W
XXXXXXXXB
0000D6H Data Counter L Register
DCTL
R/W
XXXXXXXXB
0000D7H Data Counter H Register
DCTH
R/W
XXXXXXXXB
0000D8H Serial Mode Register 2
SMR2
W, R/W
00000000B
0000D9H Serial Control Register 2
SCR2
W, R/W
00000000B
RDR2/
TDR2
R/W
00000000B/
11111111B
SSR2
R, R/W
ECCR2
R, W,
R/W
0000DDH Extended Status Control Register 2
ESCR2
R/W
00000X00B
0000DEH Baud Rate Generator Register 20
BGR20
R, R/W
00000000B
0000DFH Baud Rate Generator Register 21
BGR21
R, R/W
00000000B
0000D3H DMA Control Register
0000DAH
Reception/Transmission Data
Register 2
0000DBH Serial Status Register 2
0000DCH
Extended Communication Control
Register 2
XXXXXXXXB
DTP/External
Interrupt 1
PLL
DMA
UART2
00000000B
11110000B
XXXXXXXXB
XXXXXXXXB
00001000B
000000XXB
0000E0H
to
0000EFH
Reserved for CAN Controller 2. Refer to “■ CAN CONTROLLERS”
0000F0H
to
0000FFH
External
007900H
Reload Register L0
PRLL0
R/W
007901H
Reload Register H0
PRLH0
R/W
007902H
Reload Register L1
PRLL1
R/W
007903H
Reload Register H1
PRLH1
R/W
XXXXXXXXB
007904H
Reload Register L2
PRLL2
R/W
XXXXXXXXB
007905H
Reload Register H2
PRLH2
R/W
007906H
Reload Register L3
PRLL3
R/W
007907H
Reload Register H3
PRLH3
R/W
DS07-13752-4E
XXXXXXXXB
16-bit
PPG0/PPG1
16-bit
PPG2/PPG3
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
(Continued)
33
MB90950 Series
Address
Register
Abbreviation
Access
Resource name
Initial value
007908H Reload Register L4
PRLL4
R/W
007909H Reload Register H4
PRLH4
R/W
00790AH Reload Register L5
PRLL5
R/W
00790BH Reload Register H5
PRLH5
R/W
XXXXXXXXB
00790CH Reload Register L6
PRLL6
R/W
XXXXXXXXB
00790DH Reload Register H6
PRLH6
R/W
00790EH Reload Register L7
PRLL7
R/W
00790FH Reload Register H7
PRLH7
R/W
XXXXXXXXB
007910H Reload Register L8
PRLL8
R/W
XXXXXXXXB
007911H Reload Register H8
PRLH8
R/W
007912H Reload Register L9
PRLL9
R/W
007913H Reload Register H9
PRLH9
R/W
XXXXXXXXB
007914H Reload Register LA
PRLLA
R/W
XXXXXXXXB
007915H Reload Register HA
PRLHA
R/W
007916H Reload Register LB
PRLLB
R/W
007917H Reload Register HB
PRLHB
R/W
XXXXXXXXB
007918H Reload Register LC
PRLLC
R/W
XXXXXXXXB
007919H Reload Register HC
PRLHC
R/W
00791AH Reload Register LD
PRLLD
R/W
00791BH Reload Register HD
PRLHD
R/W
XXXXXXXXB
00791CH Reload Register LE
PRLLE
R/W
XXXXXXXXB
00791DH Reload Register HE
PRLHE
R/W
00791EH Reload Register LF
PRLLF
R/W
00791FH Reload Register HF
PRLHF
R/W
XXXXXXXXB
007920H Input Capture 0
IPCP0
R
00000000B
007921H Input Capture 0
IPCP0
R
007922H Input Capture 1
IPCP1
R
007923H Input Capture 1
IPCP1
R
00000000B
007924H Input Capture 2
IPCP2
R
00000000B
007925H Input Capture 2
IPCP2
R
007926H Input Capture 3
IPCP3
R
007927H Input Capture 3
IPCP3
R
00000000B
007928H Input Capture 4
IPCP4
R
00000000B
007929H Input Capture 4
IPCP4
R
00792AH Input Capture 5
IPCP5
R
00792BH Input Capture 5
IPCP5
R
XXXXXXXXB
16-bit
PPG4/PPG5
16-bit
PPG6/PPG7
16-bit
PPG8/PPG9
16-bit
PPGA/PPGB
16-bit
PPGC/PPGD
16-bit
PPGE/PPGF
Input Capture 0/1*
Input Capture 2/3*
Input Capture 4/5*
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
* : The Initial values of MB90V950AJAS and MB90V950AMAS are XXXXXXXXB.
(Continued)
34
DS07-13752-4E
MB90950 Series
Address
Abbreviation
Access
00792CH Input Capture 6
IPCP6
R
00792DH Input Capture 6
IPCP6
R
00792EH Input Capture 7
IPCP7
R
00792FH Input Capture 7
IPCP7
R
00000000B
007930H Output Compare 0
OCCP0
R/W
XXXXXXXXB
007931H Output Compare 0
OCCP0
R/W
007932H Output Compare 1
OCCP1
R/W
007933H Output Compare 1
OCCP1
R/W
XXXXXXXXB
007934H Output Compare 2
OCCP2
R/W
XXXXXXXXB
007935H Output Compare 2
OCCP2
R/W
007936H Output Compare 3
OCCP3
R/W
007937H Output Compare 3
OCCP3
R/W
XXXXXXXXB
007938H Output Compare 4
OCCP4
R/W
XXXXXXXXB
007939H Output Compare 4
OCCP4
R/W
00793AH Output Compare 5
OCCP5
R/W
00793BH Output Compare 5
OCCP5
R/W
XXXXXXXXB
00793CH Output Compare 6
OCCP6
R/W
XXXXXXXXB
00793DH Output Compare 6
OCCP6
R/W
00793EH Output Compare 7
OCCP7
R/W
00793FH Output Compare 7
OCCP7
R/W
XXXXXXXXB
007940H Timer Data 0
TCDT0
R/W
00000000B
007941H Timer Data 0
TCDT0
R/W
007942H Timer Control Status 0
TCCSL0
R/W
007943H Timer Control Status 0
TCCSH0
R/W
01100000B
007944H Timer Data 1
TCDT1
R/W
00000000B
007945H Timer Data 1
TCDT1
R/W
007946H Timer Control Status 1
TCCSL1
R/W
007947H Timer Control Status 1
TCCSH1
R/W
007948H
Timer 0/Reload 0
TMR0/
TMRLR0
R/W
Timer 1/Reload 1
TMR1/
TMRLR1
Timer 2/Reload 2
TMR2/
TMRLR2
Timer 3/Reload 3
TMR3/
TMRLR3
007949H
00794AH
00794BH
00794CH
00794DH
00794EH
00794FH
Register
Resource name
Initial value
00000000B
Input Capture 6/7*
Output Compare 0/1
Output Compare 2/3
Output Compare 4/5
Output Compare 6/7
R/W
R/W
R/W
R/W
R/W
R/W
R/W
I/O Timer 0
I/O Timer 1
00000000B
00000000B
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
00000000B
00000000B
00000000B
00000000B
01100000B
16-bit Reload
Timer 0
XXXXXXXXB
16-bit Reload
Timer 1
XXXXXXXXB
16-bit Reload
Timer 2
XXXXXXXXB
16-bit Reload
Timer 3
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
* : The Initial values of MB90V950AJAS and MB90V950AMAS are XXXXXXXXB.
(Continued)
DS07-13752-4E
35
MB90950 Series
Address
Abbreviation
Access
007950H Serial Mode Register 3
SMR3
W, R/W
00000000B
007951H Serial Control Register 3
SCR3
W, R/W
00000000B
RDR3/TDR3
R/W
00000000B/
11111111B
SSR3
R, R/W
ECCR3
R, W,
R/W
007955H Extended Status Control Register 3
ESCR3
R/W
00000X00B
007956H Baud Rate Generator Register 30
BGR30
R, R/W
00000000B
007957H Baud Rate Generator Register 31
BGR31
R, R/W
00000000B
007958H Serial Mode Register 4
SMR4
W, R/W
00000000B
007959H Serial Control Register 4
SCR4
W, R/W
00000000B
RDR4/TDR4
R/W
00000000B/
11111111B
SSR4
R, R/W
ECCR4
R, W,
R/W
00795DH Extended Status Control Register 4
ESCR4
R/W
00000X00B
00795EH Baud Rate Generator Register 40
BGR40
R, R/W
00000000B
00795FH Baud Rate Generator Register 41
BGR41
R, R/W
00000000B
007960H Clock Supervisor Control Register
CSVCR
R/W
Clock Supervisor
00011100B
R/W
Clock Monitor
11110000 B
CDMR
R/W
CAN Clock Sync
11111110 B
CAN 0/1
11111100 B
007952H
Register
Reception/Transmission Data
Register 3
007953H Serial Status Register 3
007954H
00795AH
Extended Communication Control
Register 3
Reception/Transmission Data
Register 4
00795BH Serial Status Register 4
00795CH
Extended Communication Control
Register 4
007961H
to
00796BH
Resource name
UART3
Initial value
00001000B
000000XXB
UART4
00001000B
000000XXB
Reserved
00796CH Clock Output Enable Register
00796DH
CLKR
Reserved
00796EH CAN Direct Mode Register
00796FH CAN Switch Register
CANSWR
R/W
2
IBSR0
R
00000000B
2
007971H I C Bus Control Register 0
IBCR0
W, R/W
00000000B
007972H
ITBAL0
R/W
00000000B
ITBAH0
R/W
00000000B
ITMKL0
R/W
ITMKH0
R/W
00111111B
ISBA0
R/W
00000000B
ISMK0
R/W
01111111B
IDAR0
R/W
00000000B
007970H I C Bus Status Register 0
007973H
I2C 10-bit Slave Address Register 0
007974H I2C 10-bit Slave Address Mask
007975H Register 0
2
007976H I C 7-bit Slave Address Register 0
I2C Interface 0
11111111B
2
007977H
I C 7-bit Slave Address Mask
Register 0
007978H I2C Data Register 0
007979H,
00797AH
Reserved
(Continued)
36
DS07-13752-4E
MB90950 Series
Abbreviation
Access
Resource name
Initial value
00797BH I2C Clock Control Register 0
ICCR0
R/W
I2C Interface 0
00011111B
00797CH
to
00797FH
Reserved
Address
Register
007980H I2C Bus Status Register 1
IBSR1
R
00000000B
007981H I C Bus Control Register 1
IBCR1
W, R/W
00000000B
007982H
ITBAL1
R/W
00000000B
ITBAH1
R/W
2
007983H
I2C 10-bit Slave Address Register 1
007984H I C 10-bit Slave Address Mask
007985H Register 1
2
ITMKL1
R/W
00000000B
2
I C Interface 1
11111111B
ITMKH1
R/W
00111111B
2
ISBA1
R/W
00000000B
2
ISMK1
R/W
01111111B
2
007988H I C Data Register 1
IDAR1
R/W
00000000B
007989H,
00798AH
Reserved
00798BH I2C Clock Control Register 1
ICCR1
00798CH
to
00798FH
Reserved
007990H Serial Mode Register 5
SMR5
W, R/W
00000000B
007991H Serial Control Register 5
SCR5
W, R/W
00000000B
007992H Reception/Transmission Data Register 5
RDR5/
TDR5
R/W
00000000B/
11111111B
007993H Serial Status Register 5
SSR5
R, R/W
ECCR5
R, W,
R/W
007995H Extended Status Control Register 5
ESCR5
R/W
00000X00B
007996H Baud Rate Generator Register 50
BGR50
R, R/W
00000000B
007997H Baud Rate Generator Register 51
BGR51
R, R/W
00000000B
007998H Serial Mode Register 6
SMR6
W, R/W
00000000B
007999H Serial Control Register 6
SCR6
W, R/W
00000000B
00799AH Reception/Transmission Data Register 6
RDR6/
TDR6
R/W
00000000B/
11111111B
00799BH Serial Status Register 6
SSR6
R, R/W
ECCR6
R, W,
R/W
00799DH Extended Status Control Register 6
ESCR6
R/W
00000X00B
00799EH Baud Rate Generator Register 60
BGR60
R, R/W
00000000B
00799FH Baud Rate Generator Register 61
BGR61
R, R/W
00000000B
007986H I C 7-bit Slave Address Register 1
007987H I C 7-bit Slave Address Mask Register 1
007994H
00799CH
Extended Communication Control
Register 5
Extended Communication Control
Register 6
R/W
I2C Interface1
UART5
00011111B
00001000B
000000XXB
UART6
00001000B
000000XXB
(Continued)
DS07-13752-4E
37
MB90950 Series
Abbreviation
Access
Resource name
Initial value
0079A0H UART Input Level Setting Register
ILSR2
R/W
UART
11111100B
0079A1H
Reserved
0079A2H Flash Write Control Register 0
FWR0
R/W
Flash Memory
00000000B
0079A3H Flash Write Control Register 1
FWR1
R/W
Flash Memory
00000000B
0079A4H
to
0079B1H
Reserved
R/W
Low Voltage/
CPU Operation
Detection Reset
10000111B
Address
0079B2H
Register
Low Voltage/CPU Operation Detection
Setting Register
LVRS
0079B3H
to
0079B7H
Reserved
0079B8H Clock Calibration Unit Control
CUCR
R/W
00000000B
0079B9H CR Oscillation Trimming Setting
CRTR
R/W
11110111B
0079BAH
CUTDL
R/W
01010000B
CUTDH
R/W
CUTR1L
R
CUTR1H
R
00000000B
CUTR2L
R
00000000B
CUTR2H
R
00000000B
0079BBH
0079BCH
0079BDH
0079BEH
0079BFH
CR Oscillation Timer Data Register
Main Timer Data Register 1
Main Timer Data Register 2
0079C0H
to
0079DFH
Clock Calibration
Unit
11000011B
00000000B
Reserved
0079E0H Detect Address Setting 0
PADR0
R/W
XXXXXXXXB
0079E1H Detect Address Setting 0
PADR0
R/W
XXXXXXXXB
0079E2H Detect Address Setting 0
PADR0
R/W
0079E3H Detect Address Setting 1
PADR1
R/W
0079E4H Detect Address Setting 1
PADR1
R/W
XXXXXXXXB
0079E5H Detect Address Setting 1
PADR1
R/W
XXXXXXXXB
0079E6H Detect Address Setting 2
PADR2
R/W
0079E7H Detect Address Setting 2
PADR2
R/W
0079E8H Detect Address Setting 2
PADR2
R/W
Address Match
Detection 0
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Address Match
Detection 0
XXXXXXXXB
XXXXXXXXB
(Continued)
38
DS07-13752-4E
MB90950 Series
(Continued)
Address
Register
0079E9H
to
0079EFH
Abbreviation
Access
Resource name
Initial value
Reserved
0079F0H Detect Address Setting 3
PADR3
R/W
XXXXXXXXB
0079F1H Detect Address Setting 3
PADR3
R/W
XXXXXXXXB
0079F2H Detect Address Setting 3
PADR3
R/W
XXXXXXXXB
0079F3H Detect Address Setting 4
PADR4
R/W
XXXXXXXXB
Address Match
Detection 1
0079F4H Detect Address Setting 4
PADR4
R/W
0079F5H Detect Address Setting 4
PADR4
R/W
XXXXXXXXB
0079F6H Detect Address Setting 5
PADR5
R/W
XXXXXXXXB
0079F7H Detect Address Setting 5
PADR5
R/W
XXXXXXXXB
0079F8H Detect Address Setting 5
PADR5
R/W
XXXXXXXXB
0079F9H
to
0079FFH
Reserved
007A00H
to
007AFFH
Reserved for CAN Controller 0. Refer to “■ CAN CONTROLLERS”
007B00H
to
007BFFH
Reserved for CAN Controller 0. Refer to “■ CAN CONTROLLERS”
007C00H
to
007CFFH
Reserved for CAN Controller 1. Refer to “■ CAN CONTROLLERS”
007D00H
to
007DFFH
Reserved for CAN Controller 1. Refer to “■ CAN CONTROLLERS”
007E00H
to
007EFFH
Reserved for CAN Controller 2. Refer to “■ CAN CONTROLLERS”
007F00H
to
007FFFH
Reserved for CAN Controller 2. Refer to “■ CAN CONTROLLERS”
XXXXXXXXB
Notes : • Initial value of “X” represents unknown value.
• Any write access to reserved addresses in I/O map should not be performed. A read access to reserved
addresses results in reading “X”.
DS07-13752-4E
39
MB90950 Series
■ CAN CONTROLLERS
The CAN controller has the following features:
• Conforms to CAN Specification Version 2.0 Part A and B
• Supports transmission/reception in standard frame and extended frame formats
• Supports transmission of data frames by receiving remote frames
• 16 transmission/reception message buffers
• 29-bit ID and 8-byte data
• Multi-level message buffer configuration
• Provides full-bit comparison, full-bit mask, acceptance register 0/acceptance register 1 for each message
buffer as ID acceptance mask
• Two acceptance mask registers in either standard frame format or extended frame formats
• Bit rate programmable from 10 kbps to 2 Mbps (when input clock is at 16 MHz)
• List of Control Registers (1)
Address
CAN0
CAN1
CAN2
000070H
000080H
0000E0H
000071H
000081H
0000E1H
000072H
000082H
0000E2H
000073H
000083H
0000E3H
000074H
000084H
0000E4H
000075H
000085H
0000E5H
000076H
000086H
0000E6H
000077H
000087H
0000E7H
000078H
000088H
0000E8H
000079H
000089H
0000E9H
00007AH
00008AH
0000EAH
00007BH
00008BH
0000EBH
00007CH
00008CH
0000ECH
00007DH
00008DH
0000EDH
00007EH
00008EH
0000EEH
00007FH
00008FH
0000EFH
40
Register
Abbreviation
Access
Initial Value
Message Buffer
Valid Register
BVALR
R/W
00000000B
00000000B
Transmit Request
Register
TREQR
R/W
00000000B
00000000B
Transmit Cancel
Register
TCANR
W
00000000B
00000000B
Transmission
Complete Register
TCR
R/W
00000000B
00000000B
Receive Complete
Register
RCR
R/W
00000000B
00000000B
Remote Request
Receiving Register
RRTRR
R/W
00000000B
00000000B
Receive Overrun
Register
ROVRR
R/W
00000000B
00000000B
Reception Interrupt
Enable Register
RIER
R/W
00000000B
00000000B
DS07-13752-4E
MB90950 Series
• List of Control Registers (2)
Address
CAN0
CAN1
CAN2
007B00H
007D00H
007F00H
007B01H
007D01H
007F01H
007B02H
007D02H
007F02H
007B03H
007D03H
007F03H
007B04H
007D04H
007F04H
007B05H
007D05H
007F05H
007B06H
007D06H
007F06H
007B07H
007D07H
007F07H
007B08H
007D08H
007F08H
007B09H
007D09H
007F09H
007B0AH
007D0AH
007F0AH
007B0BH
007D0BH
007F0BH
007B0CH
007D0CH
007F0CH
007B0DH
007D0DH
007F0DH
007B0EH
007D0EH
007F0EH
007B0FH
007D0FH
007F0FH
007B10H
007D10H
007F10H
007B11H
007D11H
007F11H
007B12H
007D12H
007F12H
007B13H
007D13H
007F13H
007B14H
007D14H
007F14H
007B15H
007D15H
007F15H
007B16H
007D16H
007F16H
007B17H
007D17H
007F17H
007B18H
007D18H
007F18H
007B19H
007D19H
007F19H
007B1AH
007D1AH
007F1AH
007B1BH
007D1BH
007F1BH
DS07-13752-4E
Register
Abbreviation
Access
Initial Value
Control Status
Register
CSR
R/W, W
R/W, R
0XXXX0X1B
00XXX000B
Last Event
Indicator Register
LEIR
R/W
000X0000B
XXXXXXXXB
Receive And Transmit
Error Counter
RTEC
R
00000000B
00000000B
Bit Timing
Register
BTR
R/W
11111111B
X1111111B
IDE Register
IDER
R/W
XXXXXXXXB
XXXXXXXXB
Transmit RTR
Register
TRTRR
R/W
00000000B
00000000B
Remote Frame
Receive Waiting
Register
RFWTR
R/W
XXXXXXXXB
XXXXXXXXB
Transmit Interrupt
Enable Register
TIER
R/W
00000000B
00000000B
Acceptance Mask
Select Register
Acceptance Mask
Register 0
Acceptance Mask
Register 1
XXXXXXXXB
XXXXXXXXB
AMSR
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
AMR0
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
AMR1
R/W
XXXXXXXXB
XXXXXXXXB
41
MB90950 Series
• List of Message Buffers (ID Registers) (1)
Address
42
CAN0
CAN1
CAN2
007A00H
to
007A1FH
007C00H
to
007C1FH
007E00H
to
007E1FH
007A20H
007C20H
007E20H
007A21H
007C21H
007E21H
007A22H
007C22H
007E22H
007A23H
007C23H
007E23H
007A24H
007C24H
007E24H
007A25H
007C25H
007E25H
007A26H
007C26H
007E26H
007A27H
007C27H
007E27H
007A28H
007C28H
007E28H
007A29H
007C29H
007E29H
007A2AH
007C2AH
007E2AH
007A2BH
007C2BH
007E2BH
007A2CH
007C2CH
007E2CH
007A2DH
007C2DH
007E2DH
007A2EH
007C2EH
007E2EH
007A2FH
007C2FH
007E2FH
007A30H
007C30H
007E30H
007A31H
007C31H
007E31H
007A32H
007C32H
007E32H
007A33H
007C33H
007E33H
007A34H
007C34H
007E34H
007A35H
007C35H
007E35H
007A36H
007C36H
007E36H
007A37H
007C37H
007E37H
007A38H
007C38H
007E38H
007A39H
007C39H
007E39H
007A3AH
007C3AH
007E3AH
007A3BH
007C3BH
007E3BH
007A3CH
007C3CH
007E3CH
007A3DH
007C3DH
007E3DH
007A3EH
007C3EH
007E3EH
007A3FH
007C3FH
007E3FH
Register
Abbreviation
Access
Initial Value
GeneralPurpose Ram
⎯
R/W
XXXXXXXXB
to
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
ID Register 0
IDR0
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
ID Register 1
IDR1
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
ID Register 2
IDR2
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
ID Register 3
IDR3
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
ID Register 4
IDR4
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
ID Register 5
IDR5
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
ID Register 6
IDR6
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
ID Register 7
IDR7
R/W
XXXXXXXXB
XXXXXXXXB
DS07-13752-4E
MB90950 Series
• List of Message Buffers (ID Registers) (2)
Address
CAN0
CAN1
CAN2
007A40H
007C40H
007E40H
007A41H
007C41H
007E41H
007A42H
007C42H
007E42H
007A43H
007C43H
007E43H
007A44H
007C44H
007E44H
007A45H
007C45H
007E45H
007A46H
007C46H
007E46H
007A47H
007C47H
007E47H
007A48H
007C48H
007E48H
007A49H
007C49H
007E49H
007A4AH
007C4AH
007E4AH
007A4BH
007C4BH
007E4BH
007A4CH
007C4CH
007E4CH
007A4DH
007C4DH
007E4DH
007A4EH
007C4EH
007E4EH
007A4FH
007C4FH
007E4FH
007A50H
007C50H
007E50H
007A51H
007C51H
007E51H
007A52H
007C52H
007E52H
007A53H
007C53H
007E53H
007A54H
007C54H
007E54H
007A55H
007C55H
007E55H
007A56H
007C56H
007E56H
007A57H
007C57H
007E57H
007A58H
007C58H
007E58H
007A59H
007C59H
007E59H
007A5AH
007C5AH
007E5AH
007A5BH
007C5BH
007E5BH
007A5CH
007C5CH
007E5CH
007A5DH
007C5DH
007E5DH
007A5EH
007C5EH
007E5EH
007A5FH
007C5FH
007E5FH
DS07-13752-4E
Register
Abbreviation
Access
Initial Value
XXXXXXXXB
XXXXXXXXB
ID Register 8
IDR8
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
ID Register 9
IDR9
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
ID Register 10
IDR10
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
ID Register 11
IDR11
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
ID Register 12
IDR12
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
ID Register 13
IDR13
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
ID Register 14
IDR14
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
ID Register 15
IDR15
R/W
XXXXXXXXB
XXXXXXXXB
43
MB90950 Series
• List of Message Buffers (DLC Registers and Data Registers) (1)
Address
Register
Abbreviation
CAN0
CAN1
CAN2
44
007A60H
007C60H
007E60H
007A61H
007C61H
007E61H
007A62H
007C62H
007E62H
007A63H
007C63H
007E63H
007A64H
007C64H
007E64H
007A65H
007C65H
007E65H
007A66H
007C66H
007E66H
007A67H
007C67H
007E67H
007A68H
007C68H
007E68H
007A69H
007C69H
007E69H
007A6AH
007C6AH
007E6AH
007A6BH
007C6BH
007E6BH
007A6CH
007C6CH
007E6CH
007A6DH
007C6DH
007E6DH
007A6EH
007C6EH
007E6EH
007A6FH
007C6FH
007E6FH
007A70H
007C70H
007E70H
007A71H
007C71H
007E71H
007A72H
007C72H
007E72H
007A73H
007C73H
007E73H
007A74H
007C74H
007E74H
007A75H
007C75H
007E75H
007A76H
007C76H
007E76H
007A77H
007C77H
007E77H
007A78H
007C78H
007E78H
007A79H
007C79H
007E79H
007A7AH
007C7AH
007E7AH
007A7BH
007C7BH
007E7BH
007A7CH
007C7CH
007E7CH
007A7DH
007C7DH
007E7DH
007A7EH
007C7EH
007E7EH
007A7FH
007C7FH
007E7FH
Access
Initial Value
DLC Register 0
DLCR0
R/W
XXXXXXXXB
DLC Register 1
DLCR1
R/W
XXXXXXXXB
DLC Register 2
DLCR2
R/W
XXXXXXXXB
DLC Register 3
DLCR3
R/W
XXXXXXXXB
DLC Register 4
DLCR4
R/W
XXXXXXXXB
DLC Register 5
DLCR5
R/W
XXXXXXXXB
DLC Register 6
DLCR6
R/W
XXXXXXXXB
DLC Register 7
DLCR7
R/W
XXXXXXXXB
DLC Register 8
DLCR8
R/W
XXXXXXXXB
DLC Register 9
DLCR9
R/W
XXXXXXXXB
DLC Register 10
DLCR10
R/W
XXXXXXXXB
DLC Register 11
DLCR11
R/W
XXXXXXXXB
DLC Register 12
DLCR12
R/W
XXXXXXXXB
DLC Register 13
DLCR13
R/W
XXXXXXXXB
DLC Register 14
DLCR14
R/W
XXXXXXXXB
DLC Register 15
DLCR15
R/W
XXXXXXXXB
DS07-13752-4E
MB90950 Series
• List of Message Buffers (DLC Registers and Data Registers) (2)
Address
Register
Abbreviation
CAN0
CAN1
CAN2
Access
Initial Value
007A80H
to
007A87H
007C80H
to
007C87H
007E80H
to
007E87H
Data Register 0
(8 bytes)
DTR0
R/W
XXXXXXXXB
to
XXXXXXXXB
007A88H
to
007A8FH
007C88H
to
007C8FH
007E88H
to
007E8FH
Data Register 1
(8 bytes)
DTR1
R/W
XXXXXXXXB
to
XXXXXXXXB
007A90H
to
007A97H
007C90H
to
007C97H
007E90H
to
007E97H
Data Register 2
(8 bytes)
DTR2
R/W
XXXXXXXXB
to
XXXXXXXXB
007A98H
to
007A9FH
007C98H
to
007C9FH
007E98H
to
007E9FH
Data Register 3
(8 bytes)
DTR3
R/W
XXXXXXXXB
to
XXXXXXXXB
007AA0H
to
007AA7H
007CA0H
to
007CA7H
007EA0H
to
007EA7H
Data Register 4
(8 bytes)
DTR4
R/W
XXXXXXXXB
to
XXXXXXXXB
007AA8H
to
007AAFH
007CA8H
to
007CAFH
007EA8H
to
007EAFH
Data Register 5
(8 bytes)
DTR5
R/W
XXXXXXXXB
to
XXXXXXXXB
007AB0H
to
007AB7H
007CB0H
to
007CB7H
007EB0H
to
007EB7H
Data Register 6
(8 bytes)
DTR6
R/W
XXXXXXXXB
to
XXXXXXXXB
007AB8H
to
007ABFH
007CB8H
to
007CBFH
007EB8H
to
007EBFH
Data Register 7
(8 bytes)
DTR7
R/W
XXXXXXXXB
to
XXXXXXXXB
007AC0H
to
007AC7H
007CC0H
to
007CC7H
007EC0H
to
007EC7H
Data Register 8
(8 bytes)
DTR8
R/W
XXXXXXXXB
to
XXXXXXXXB
007AC8H
to
007ACFH
007CC8H
to
007CCFH
007EC8H
to
007ECFH
Data Register 9
(8 bytes)
DTR9
R/W
XXXXXXXXB
to
XXXXXXXXB
007AD0H
to
007AD7H
007CD0H
to
007CD7H
007ED0H
to
007ED7H
Data Register 10
(8 bytes)
DTR10
R/W
XXXXXXXXB
to
XXXXXXXXB
007AD8H
to
007ADFH
007CD8H
to
007CDFH
007ED8H
to
007EDFH
Data Register 11
(8 bytes)
DTR11
R/W
XXXXXXXXB
to
XXXXXXXXB
007AE0H
to
007AE7H
007CE0H
to
007CE7H
007EE0H
to
007EE7H
Data Register 12
(8 bytes)
DTR12
R/W
XXXXXXXXB
to
XXXXXXXXB
007AE8H
to
007AEFH
007CE8H
to
007CEFH
007EE8H
to
007EEFH
Data Register 13
(8 bytes)
DTR13
R/W
XXXXXXXXB
to
XXXXXXXXB
DS07-13752-4E
45
MB90950 Series
• List of Message Buffers (DLC Registers and Data Registers) (3)
Address
Register
Abbreviation
CAN0
CAN1
CAN2
46
Access
Initial Value
007AF0H
to
007AF7H
007CF0H
to
007CF7H
007EF0H
to
007EF7H
Data Register 14
(8 bytes)
DTR14
R/W
XXXXXXXXB
to
XXXXXXXXB
007AF8H
to
007AFFH
007CF8H
to
007CFFH
007EF8H
to
007EFFH
Data Register 15
(8 bytes)
DTR15
R/W
XXXXXXXXB
to
XXXXXXXXB
DS07-13752-4E
MB90950 Series
■ INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTER
Interrupt control
register
EI2OS
Support
DMA
channel
number
Number
Address
Number
Address
Reset
N
⎯
#08
FFFFDCH
⎯
⎯
INT9 instruction
N
⎯
#09
FFFFD8H
⎯
⎯
Exception
N
⎯
#10
FFFFD4H
⎯
⎯
CAN0 RX
N
⎯
#11
FFFFD0H
CAN0 TX/NS
N
⎯
#12
FFFFCCH
ICR00
0000B0H
CAN1 RX/Input Capture 6
Y1
⎯
#13
FFFFC8H
CAN1 TX/NS/Input Capture 7
Y1
⎯
#14
FFFFC4H
ICR01
0000B1H
CAN2 RX / I2C0
N
⎯
#15
FFFFC0H
CAN2 TX / NS / Clock Calibration Unit
N
⎯
#16
FFFFBCH
ICR02
0000B2H
16-bit Reload Timer 0
Y1
0
#17
FFFFB8H
16-bit Reload Timer 1
Y1
1
#18
FFFFB4H
ICR03
0000B3H
16-bit Reload Timer 2
Y1
2
#19
FFFFB0H
16-bit Reload Timer 3
Y1
⎯
#20
FFFFACH
ICR04
0000B4H
PPG0 / PPG1 / PPG4 / PPG5
N
⎯
#21
FFFFA8H
PPG2 / PPG3 / PPG6 / PPG7
N
⎯
#22
FFFFA4H
ICR05
0000B5H
PPG8 / PPG9 / PPGC / PPGD
N
⎯
#23
FFFFA0H
PPGA / PPGB / PPGE / PPGF
N
⎯
#24
FFFF9CH
ICR06
0000B6H
Time Base Timer
N
⎯
#25
FFFF98H
External Interrupt 0 to 3, 8 to 11
Y1
3
#26
FFFF94H
ICR07
0000B7H
Watch Timer
N
⎯
#27
FFFF90H
External Interrupt 4 to 7, 12 to 15
Y1
4
#28
FFFF8CH
ICR08
0000B8H
A/D Converter
Y1
5
#29
FFFF88H
I/O Timer 0/1
N
⎯
#30
FFFF84H
ICR09
0000B9H
Input Capture 4/5 / I2C1
Y1
6
#31
FFFF80H
Output Compare 0/1/4/5
Y1
7
#32
FFFF7CH
ICR10
0000BAH
Input Capture 0 to 3
Y1
8
#33
FFFF78H
Output Compare 2/3/6/7
Y1
9
#34
FFFF74H
ICR11
0000BBH
UART0 RX
Y2
10
#35
FFFF70H
UART0 TX
Y1
11
#36
FFFF6CH
ICR12
0000BCH
UART1 RX / UART3 RX / UART5 RX
Y2
12
#37
FFFF68H
UART1 TX / UART3 TX / UART5 TX
Y1
13
#38
FFFF64H
ICR13
0000BDH
Interrupt cause
Interrupt vector
(Continued)
DS07-13752-4E
47
MB90950 Series
(Continued)
EI2OS
Support
DMA
channel
number
Number
Address
UART2 RX / UART4 RX / UART6 RX
Y2
14
#39
FFFF60H
UART2 TX / UART4 TX / UART6 TX
Y1
15
#40
FFFF5CH
Flash Memory
N
⎯
#41
FFFF58H
Delayed Interrupt
N
⎯
#42
FFFF54H
Interrupt cause
Interrupt vector
Interrupt control
register
Number
Address
ICR14
0000BEH
ICR15
0000BFH
Y1 : Usable
Y2 : Usable, with EI2OS stop function
N : Unusable
Notes : • The peripheral resources sharing the ICR register have the same interrupt level.
• When two peripheral resources share the ICR register, only one can use Extended Intelligent I/O Service
at a time.
• When either of the two peripheral resources sharing the ICR register specifies Extended Intelligent I/O
Service, the other one cannot use interrupts.
48
DS07-13752-4E
MB90950 Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
Remarks
Min
Max
VCC
VSS − 0.3
VSS + 6.0
V
AVCC
VSS − 0.3
VSS + 6.0
V
VCC = AVCC*2
AVRH,
AVRL
VSS − 0.3
VSS + 6.0
V
AVCC ≥ AVRH, AVCC ≥ AVRL,
AVRH ≥ AVRL
Input voltage*1
VI
VSS − 0.3
VSS + 6.0
V
*3
Output voltage*1
VO
VSS − 0.3
VSS + 6.0
V
*3
ICLAMP
−4.0
+4.0
mA
*5
Σ|ICLAMP|
⎯
40
mA
*5
IOL
⎯
15
mA
*4
“L” level average output
current
IOLAV
⎯
4
mA
*4
“L” level maximum overall
output current
ΣIOL
⎯
100
mA
*4
ΣIOLAV
⎯
50
mA
*4
IOH
⎯
−15
mA
*4
“H” level average output
current
IOHAV
⎯
−4
mA
*4
“H” level maximum overall
output current
ΣIOH
⎯
−100
mA
*4
ΣIOHAV
⎯
−50
mA
*4
Power consumption
PD
⎯
430
mW
Operating temperature
TA
−40
+105
°C
−40
+125
°C
−55
+150
°C
Power supply voltage*1
Maximum Clamp Current
Total Maximum Clamp
Current
“L” level maximum output
current
“L” level average overall
output current
“H” level maximum output
current
“H” level average overall
output current
Storage temperature
TSTG
*6
*1: This parameter is based on VSS = AVSS = 0 V
*2: Set AVCC and VCC to the same voltage. Make sure that AVCC does not exceed VCC and that the voltage at the
analog inputs does not exceed AVCC when the power is switched on.
*3: VI and VO should not exceed VCC + 0.3 V. VI should not exceed the specified ratings. However if the maximum
current to/from an input is limited by some means with external components, the ICLAMP rating supersedes the VI
rating.
*4: Applicable to pins: P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67,
P70 to P77, P80 to P87, P90 to P97, PA0, PA1
(Continued)
DS07-13752-4E
49
MB90950 Series
(Continued)
*5: • Applicable to pins: P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47,
P50 to P55, P60 to P67, P70 to P77, P80 to P87, P90 to P97, PA0 to PA1
• Use within recommended operating conditions.
• Use with DC voltage (current)
• The +B signal should always be applied by using a limiting resistance placed between the +B signal and the
microcontroller.
• The value of the limiting resistance should be set so that when the +B signal is applied, the input current to
the microcontroller pin does not exceed the rated value, either instantaneously or for prolonged periods.
• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input
potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect
other devices.
• Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the power
supply is provided from the pins, so that incomplete operation may result.
• Note that if the +B input is applied during power-on, the power supply is provided from the pins and the
resulting supply voltage may not be sufficient to operate the power-on reset.
• Care must be taken not to leave the +B input pin open.
• Sample recommended circuits:
• Input/output equivalent circuits
Protective diode
VCC
Limiting
resistance
P-ch
+B input (0 V to 16 V)
N-ch
R
*6 : If used exceeding TA = + 105 °C, please consult with us due to the restricted reliability.
It is ensured to write/erase data to the Flash memory between TA = − 40 °C and + 105 °C.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
50
DS07-13752-4E
MB90950 Series
2. Recommended Operating Conditions
(VSS = AVSS = 0 V)
Parameter
Symbol
Power supply
voltage
VCC,
AVCC
Conditions
⎯
Smoothing
capacitor
CS
⎯
Operating
temperature
TA
⎯
Value
Unit
Remarks
Min
Typ
Max
3.0
5.0
5.5
V
Under normal operation
4.5
5.0
5.5
V
When External bus is used.
3.0
⎯
5.5
V
Maintains RAM data in stop mode
μF
Use a ceramic capacitor or capacitor
of better AC characteristics. Capacitor at the VCC should be greater than
this capacitor.
0.1
⎯
1.0
−40
⎯
+105
−40
⎯
+125
°C
MB90F952JDS, MB90F952MDS
*
* : If used exceeding TA = + 105 °C, please consult with us due to the restricted reliability.
It is ensured to write/erase data to the Flash memory between TA = − 40 °C and + 105 °C.
C Pin Connection Diagram
C
CS
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
representatives beforehand.
DS07-13752-4E
51
MB90950 Series
3. DC Characteristics
Parameter
Symbol
Pin name
Conditions
VIHS
⎯
VIHA
Value
Unit
Remarks
Min
Typ
Max
⎯
0.8 VCC
⎯
VCC + 0.3
V
Port inputs if CMOS
hysteresis input levels
are selected
⎯
⎯
0.8 VCC
⎯
VCC + 0.3
V
Port inputs if
Automotive input levels
are selected
VIHT
⎯
⎯
2.0
⎯
VCC + 0.3
V
Port inputs if TTL input
levels are selected
VIHS
P12,P15,
P44 to P47,
P50,P82,
P85,P90,
P94
⎯
0.7 VCC
⎯
VCC + 0.3
V
Port inputs if
CMOS hysteresis input
levels are selected
VIHR
RST
⎯
0.8 VCC
⎯
VCC + 0.3
V
RST input pin
(CMOS hysteresis)
VIHM
MD0 to MD2
⎯
VCC − 0.3
⎯
VCC + 0.3
V
MD input pins
VILS
⎯
⎯
VSS − 0.3
⎯
0.2 VCC
V
Port inputs if
CMOS hysteresis input
levels are selected
VILA
⎯
⎯
VSS − 0.3
⎯
0.5 VCC
V
Port inputs if
Automotive input levels
are selected
VILT
⎯
⎯
VSS − 0.3
⎯
0.8
V
Port inputs if TTL input
levels are selected
VILS
P12,P15,
P44 to P47,
P50,P82,
P85,P90,
P94
⎯
VSS − 0.3
⎯
0.3 VCC
V
Port inputs if
CMOS hysteresis input
levels are selected
VILR
RST
⎯
VSS − 0.3
⎯
0.2 VCC
V
RST input pin
(CMOS hysteresis)
VILM
MD0 to MD2
⎯
VSS − 0.3
⎯
VSS + 0.3
V
MD input pins
Output H
voltage
VOH
Normal
outputs
VCC = 4.5 V,
IOH = −4.0 mA
VCC − 0.5
⎯
⎯
V
Output H
voltage
VOHI
I2C outputs
VCC = 4.5 V,
IOH = −3.0 mA
VCC − 0.5
⎯
⎯
V
Output L
voltage
VOL
Normal
outputs
VCC = 4.5 V,
IOL = 4.0 mA
⎯
⎯
0.4
V
Output L
voltage
VOLI
I2C outputs
VCC = 4.5 V,
IOL = 3.0 mA
⎯
⎯
0.4
V
Input H
voltage
(At VCC =
5 V ± 10%)
Input L
voltage
(At VCC =
5 V ± 10%)
(Continued)
52
DS07-13752-4E
MB90950 Series
Symbol
Pin name
IIL
⎯
Pull-up
resistance
RUP
P00 to P07,
P10 to P17,
P20 to P27,
P30 to P37,
RST
Pull-down
resistance
RDOWN
MD2
Parameter
Conditions
Value
Unit
Remarks
Min
Typ
Max
−1
⎯
+1
μA
⎯
25
50
100
kΩ
⎯
25
50
100
kΩ
VCC = 5.0 V,
Internal frequency : 32 MHz,
At normal operation.
⎯
40
50
mA
VCC = 5.0 V,
Internal frequency : 32 MHz,
At writing Flash memory/erasing.
⎯
50
65
mA
ICCS
VCC = 5.0 V,
Internal frequency : 32 MHz,
In Sleep mode.
⎯
13
23
mA
ICTS
VCC = 5.0 V,
Internal frequency : 2 MHz,
In Main Timer mode
⎯
0.4
1.0
⎯
0.3
0.9
VCC = 5.0 V,
Internal frequency : 32 MHz,
In PLL Timer mode,
external frequency = 4 MHz
⎯
4
7
mA
ICCL
VCC = 5.0 V
Internal frequency : 12.5 kHz,
In CR sub operation
TA = +25°C
⎯
170
400
μA
MB90F952JDS
ICCLS
VCC = 5.0 V
Internal frequency : 12.5 kHz,
In CR sub sleep
TA = +25°C
⎯
130
250
μA
MB90F952JDS
ICCT
VCC = 5.0 V
Internal frequency : 12.5 kHz,
In CR watch mode
TA = +25°C
⎯
130
250
μA
MB90F952JDS
⎯
70
170
ICCH
VCC = 5.0 V,
In Stop mode,
TA = +25°C
Input leak
current
ICC
ICTSPLL6
Power
supply
current*
VCC
VCC = 5.5 V, VSS < VI < VCC
mA
Except
Flash memory
devices
MB90F952JDS,
MB90F952MDS
MB90F952JDS
MB90F952MDS
MB90F952JDS
μA
⎯
25
100
MB90F952MDS
(Continued)
DS07-13752-4E
53
MB90950 Series
(Continued)
Parameter
Input
capacitance
Symbol
Pin name
Conditions
CIN
Other than C,
AVCC, AVSS,
AVRH, AVRL,
VCC, VSS
⎯
Value
Min
Typ
Max
⎯
5
15
Unit
Remarks
pF
* : The power supply current is measured with an external clock.
54
DS07-13752-4E
MB90950 Series
4. AC Characteristics
(1) Clock Timing
(TA = −40 °C to +105 °C, VCC = 5.0 V ± 10%, fCP ≤ 32 MHz, VSS = AVSS = 0 V)
Parameter
Clock
frequency
Symbol
fC
Pin
name
X0, X1
Conditions
⎯
Value
Min
Typ
Max
Unit
Remarks
3
16
1/2 multiplied (PLL stopped)
When using an oscillation circuit
4
16
PLL multiplied by 1
When using an oscillation circuit
4
16
PLL multiplied by 2
When using an oscillation circuit
⎯
4
10
MHz
PLL multiplied by 3
When using an oscillation circuit
4
8
PLL multiplied by 4
When using an oscillation circuit
4
5
PLL multiplied by 6
When using an oscillation circuit
4
4
PLL multiplied by 8
When using an oscillation circuit
Clock cycle time
tCYL
X0, X1
⎯
62.5
⎯
333
Internal operating
clock frequency
(machine clock)
fCP
⎯
⎯
1.5
⎯
32
MHz When using main clock
fCPL
⎯
⎯
10.625
12.5
14.375
kHz When using CR clock
tCP
⎯
⎯
31.25
⎯
666
ns
When using main clock
tCPL
⎯
⎯
69.565
80
94.118
μs
When using CR clock
fCCR
⎯
⎯
85
100
115
kHz
Internal operating
clock cycle time
(machine clock)
Internal
CR oscillation
frequency
ns
When using an oscillation circuit
When trimming with the clock
calibration unit
• When oscillation circuit is used
tCYL
X0, X1
Amplitude:
It varies depending on the
external resistance, power
rating and the different kind of
device.
Reference values: 1 V to 2.5 V
Note: The amplitude of MB90V950AJAS and MB90V950AMAS are the same as VCC.
DS07-13752-4E
55
MB90950 Series
Power supply voltage VCC (V)
• Guaranteed PLL operation range
Guaranteed operation range
5.5
3.0
Guaranteed operation range
1.5
4
32
Internal clock fCP (MHz)
Note: When the power supply voltage is lower than the setting voltage of low voltage detection,
MB90F952JDS are reset.
Internal clock fCP ⎯ External clock fC
Guaranteed oscillation frequency range
×8
×6
×4
×3
×2
×1
Internal clock fCP (MHz)
32
24
×1/2
16
(PLL off)
12
8
4.0
1.5
3 4
8
12
16
24
32
External clock fC (MHz)*
* : When using a crystal oscillator or ceramic oscillator, the maximum oscillation clock frequency is 16 MHz
56
DS07-13752-4E
MB90950 Series
(2) Reset Standby Input
Parameter
Symbol
Reset input
time
Value
Pin Condiname tions
tRSTL
⎯
RST
Unit
Remarks
Min
Max
500
⎯
ns
Under normal operation
Oscillation time of oscillator*
+ 100 μs
⎯
μs
In Stop mode, Sub Clock
mode, Sub Sleep mode
and Watch mode
100
⎯
μs
In Time Base Timer mode
* : The oscillation time of the oscillator is the time it takes for the amplitude of the oscillations to reach 90%. For
crystal oscillators, this time is between several ms and several tens of ms, for ceramic oscillators the time is
between several hundred μs and several ms, and for an external clock, the time is 0 ms.
• Under normal operation:
tRSTL
RST
VILR
VILR
• In Stop mode, Sub Clock mode, Sub Sleep mode, Watch mode:
tRSTL
RST
VILR
X0
VILR
90% of
amplitude
Internal operation
clock
100 µs
Oscillation time
of oscillator
Oscillation stabilization
waiting time
Instruction execution
Internal reset
DS07-13752-4E
57
MB90950 Series
(3) Power On Reset
Parameter
Symbol
Pin
name
Power on rise time
tR
VCC
tOFF
VCC
Power off time
Value
Conditions
⎯
Unit
Min
Max
0.05
30
ms
1
⎯
ms
Remarks
Due to repetitive operation
tR
2.7 V
VCC
0.2 V
0.2 V
0.2 V
tOFF
Note: If you change the power supply voltage too rapidly, a power on reset may occur. We recommend that you
startup smoothly by restraining voltages when changing the power supply voltage during operation, as shown
in the figure below. Perform while not using the PLL clock. However, if voltage drops are within 1 V/s, you
can operate while using the PLL clock.
VCC
We recommend a rise of
50 mV/ms maximum.
3V
Holds RAM data
VSS
(4) Clock Output Timing
Symbol
Pin
name
Conditions
Cycle time
tCYC
CLK
⎯
CLK ↑ → CLK ↓
tCHCL
CLK
⎯
Parameter
Value
Unit
Remarks
Min
Max
tcp*
⎯
ns
tcp* / 2 − 15
tcp* / 2 + 15
ns
fCP = 25 MHz
tcp* / 2 − 20
tcp* / 2 + 20
ns
fCP = 16 MHz
* : tcp is the Internal clock cycle time. Refer to “ (1) Clock Timing”.
tCYC
tCHCL
CLK
2.4 V
2.4 V
0.8 V
58
DS07-13752-4E
MB90950 Series
(5) Bus Timing (Read)
Parameter
ALE pulse width
Symbol
tLHLL
Pin name
ALE
Conditions
⎯
Value
Unit
Remarks
⎯
ns
16MHz < fcp ≤
25 MHz
tcp*/ 2 − 20
⎯
ns
8 MHz < fcp ≤
16 MHz
tcp*/ 2 − 35
⎯
ns
fcp ≤ 8 MHz
tcp*/ 2 − 17
⎯
ns
tcp*/ 2 − 40
⎯
ns
Min
Max
tcp*/ 2 − 15
Valid address →
ALE ↓ time
tAVLL
Address,
ALE
⎯
ALE ↓ →
Address valid time
tLLAX
ALE ,
Address
⎯
tcp*/ 2 − 15
⎯
ns
Valid address →
RD ↓ time
tAVRL
RD ,
Address
⎯
tcp* − 25
⎯
ns
Valid address →
Valid data input
tAVDV
Address/
Data
⎯
⎯
tcp* / 2 − 55
ns
⎯
tcp* / 2 − 80
ns
fcp ≤ 8 MHz
3 tcp* / 2 −
25
⎯
ns
16 MHz < fcp ≤
25 MHz
3 tcp* / 2 −
20
⎯
ns
8 MHz < fcp ≤
16 MHz
3 tcp* / 2 − 55
ns
3 tcp* / 2 − 80
ns
RD pulse width
tRLRH
RD
⎯
RD ↓ →
Valid data input
tRLDV
RD ,
Data
⎯
RD ↑ →
Data hold time
tRHDX
RD ,
Data
⎯
0
⎯
ns
RD ↓ →
ALE ↑ time
tRHLH
RD , ALE
⎯
tcp* / 2 − 15
⎯
ns
RD ↑ →
Address valid time
tRHAX
Address,
RD
⎯
tcp* / 2 − 10
⎯
ns
Valid address →
CLK ↑ time
tAVCH
Address,
CLK
⎯
tcp* / 2 − 17
⎯
ns
RD ↓ →
CLK ↑ time
tRLCH
RD,CLK
⎯
tcp* / 2 − 17
⎯
ns
ALE ↓ →
RD ↓ time
tLLRL
RD,ALE
⎯
tcp* / 2 − 15
⎯
ns
fcp ≤ 8 MHz
fcp ≤ 8 MHz
* : tcp is the Internal cycle time. Refer to “(1) Clock Timing”.
DS07-13752-4E
59
MB90950 Series
tRLCH
tAVCH
2.4 V
CLK
2.4 V
tLLAX
tAVLL
ALE
2.4 V
tRHLH
2.4 V
2.4 V
0.8 V
tLHLL
tAVRL
tRLRH
2.4 V
RD
0.8 V
tLLRL
tRHAX
A23 to A16
2.4 V
2.4 V
0.8 V
0.8 V
tRLDV
tRHDX
tAVDV
AD15 to AD00
2.4 V
0.8 V
60
2.4 V
Address
0.8 V
VIHT
VILT
VIHT
Read data
VILT
DS07-13752-4E
MB90950 Series
(6) Bus Timing (Write)
Parameter
Valid address →
WR ↓ time
WR pulse width
Valid data output →
WR ↑ time
WR ↑ →
Data hold time
Symbol Pin name
Min
Max
⎯
tcp* − 15
⎯
ns
3 tcp* / 2 − 25
⎯
ns
16 MHz < fcp ≤
25 MHz
3 tcp* / 2 − 20
⎯
ns
8 MHz < fcp ≤
16 MHz
3 tcp* / 2 − 15
⎯
ns
10
⎯
ns
16 MHz < fcp ≤
25 MHz
20
⎯
ns
8 MHz < fcp ≤
16 MHz
30
⎯
ns
fcp ≤ 8 MHz
tAVWL
Address,
WR
tWLWH
WRL,
WRH
⎯
Data,
WR
⎯
tDVWH
tWHDX
WR ,
Data
Value
Conditions
⎯
Unit
WR ↑ → A
ddress valid time
tWHAX
WR ,
Address
⎯
tcp* / 2 − 10
⎯
ns
WR ↑ →
ALE ↑ time
tWHLH
WR , ALE
⎯
tcp* / 2 − 15
⎯
ns
WR ↓ →
CLK ↑ time
tWLCH
WR , CLK
⎯
tcp* / 2 − 17
⎯
ns
Remarks
*: tcp is the Internal operating clock cycle time. Refer to “(1) Clock Timing”.
DS07-13752-4E
61
MB90950 Series
tWLCH
CLK
2.4 V
tWHLH
ALE
2.4 V
tWLWH
2.4 V
WR (WRL, WRH)
0.8 V
tWHAX
tAVWL
A23 to A16
2.4 V
2.4 V
0.8 V
0.8 V
tDVWH
2.4 V
AD15 to AD00
62
0.8 V
Address
2.4 V
0.8 V
Write data
tWHDX
2.4 V
0.8 V
DS07-13752-4E
MB90950 Series
(7) Ready Input Timing
Symbol
Pin name
RDY setup time
tRYHS
RDY
RDY hold time
tRYHH
RDY
Parameter
Test
Condition
Rated Value
Unit
Min
Max
35
⎯
ns
70
⎯
ns
0
⎯
ns
⎯
Remarks
fCP = 8 MHz
Note : If the RDY setup time is insufficient, use the auto-ready function.
CLK
2.4 V
2.4 V
ALE
RD/WR
tRYHS
RDY
When WAIT
is not used.
RDY
When WAIT
is used.
(1 cycle)
DS07-13752-4E
tRYHH
VIHT
VILT
VIHT
VILT
tRYHS
63
MB90950 Series
(8) Hold Timing
Parameter
Symbol
Pin name
Pin floating → HAK ↓ time
tXHAL
HAK
HAK ↓ → time → Pin valid time
tHAHV
HAK
Conditions
⎯
Value
Unit
Min
Max
30
tCP*
ns
tCP*
2 tCP*
ns
* : tcp is the Internal operating clock cycle time. Refer to “(1) Clock Timing”.
Note : There is more than 1 cycle from when HRQ reads in until the HAK is changed.
2.4 V
HAK
0.8 V
tHAHV
tXHAL
Each pin
2.4 V
0.8 V
64
Hi-Z
2.4 V
0.8 V
DS07-13752-4E
MB90950 Series
(9) UART
ESCR : SCES = 0, ECCR : SCDE = 0
Parameter
Symbol
tSCYC
tSLOVI
tIVSHI
tSHIXI
tSLSH
tSHSL
tSLOVE
tIVSHE
tSHIXE
tF
tR
Serial clock cycle time
SCK ↓ → SOT delay time
SIN → SCK ↑ setup time
SCK ↑ → SIN hold time
Serial clock “H” pulse width
Serial clock “L” pulse width
SCK ↓ → SOT delay time
SIN → SCK ↑ setup time
SCK ↑ → SIN hold time
SCK fall time
SCK rise time
Conditions
Internal shift clock
operation
CL = 80 pF + 1
TTL.
External shift clock
operation
CL = 80 pF + 1
TTL.
Value
Unit
Min
Max
5 tcp*
⎯
ns
− 50
+ 50
ns
tcp* + 80
⎯
ns
0
⎯
ns
3 tcp* − tR
⎯
ns
tcp* + 10
⎯
ns
⎯
2 tcp* + 60
ns
30
⎯
ns
tcp* + 30
⎯
ns
⎯
10
ns
⎯
10
ns
*: tcp indicates the machine clock time
tSCYC
2.4 V
SCK
0.8 V
tSLOVI
2.4 V
SOT
0.8 V
tIVSHI
tSHIXI
VIH
SIN
VIL
Internal Clock Shift Operation
DS07-13752-4E
65
MB90950 Series
tSHSL
tSLSH
VIH
SCK
VIL
tR
tF
tSLOVE
2.4V
SOT
0.8V
tIVSHE
tSHIXE
VIH
SIN
VIL
External Clock Shift Operation
66
DS07-13752-4E
MB90950 Series
ESCR : SCES = 1, ECCR : SCDE = 0
Parameter
Symbol
tSCYC
tSHOVI
tIVSLI
tSLIXI
tSHSL
tSLSH
tSHOVE
tIVSLE
tSLIXE
tF
tR
Serial clock cycle time
SCK ↑ → SOT delay time
SIN → SCK ↓ setup time
SCK ↓ → SIN hold time
Serial clock “H” pulse width
Serial clock “L” pulse width
SCK ↑ → SOT delay time
SIN → SCK ↓ setup time
SCK ↓ → SIN hold time
SCK fall time
SCK rise time
Conditions
Internal shift clock
operation
CL = 80 pF + 1
TTL.
External shift clock
operation
CL = 80 pF + 1
TTL.
Value
Unit
Min
Max
5 tcp*
⎯
ns
− 50
+ 50
ns
tcp* + 80
⎯
ns
0
⎯
ns
3 tcp* − tR
⎯
ns
tcp* + 10
⎯
ns
⎯
2 tcp* + 60
ns
30
⎯
ns
tcp* + 30
⎯
ns
⎯
10
ns
⎯
10
ns
*: tcp indicates the machine clock time
tSCYC
2.4 V
SCK
0.8 V
tSHOVI
2.4 V
SOT
0.8 V
tIVSLI
tSLIXI
VIH
SIN
VIL
Internal Clock Shift Operation
DS07-13752-4E
67
MB90950 Series
tSLSH
tSHSL
VIH
SCK
VIL
tSHOVE
tF
tR
2.4 V
SOT
0.8 V
tIVSLE
tSLIXE
VIH
SIN
VIL
External Clock Shift Operation
68
DS07-13752-4E
MB90950 Series
ESCR : SCES = 0, ECCR : SCDE = 1
Value
Parameter
Symbol
Serial clock cycle time
tSCYC
SCK ↑ → SOT delay time
tSHOVI
SIN → SCK ↓ setup time
tIVSLI
SCK ↓ → SIN hold time
tSLIXI
SOT → SCK ↓ delay time
tSOVLI
Conditions
Unit
Internal shift clock
operation
CL = 80 pF + 1
TTL.
Min
Max
5 tcp*
⎯
ns
− 50
+ 50
ns
tcp* + 80
⎯
ns
0
⎯
ns
3 tcp* − 70
⎯
ns
*: tcp indicates the machine clock time
tSCYC
2.4 V
SCK
0.8 V
SOT
2.4 V
0.8 V
2.4 V
0.8 V
tIVSLI
SIN
DS07-13752-4E
VIH
VIL
0.8 V
tSHOVI
tSOVLI
tSLIXI
VIH
VIL
69
MB90950 Series
ESCR : SCES = 1, ECCR : SCDE = 1
Value
Parameter
Symbol
Serial clock cycle time
tSCYC
SCK ↓ → SOT delay time
tSLOVI
SIN → SCK ↑ setup time
tIVSHI
SCK ↑ → SIN hold time
tSHIXI
SOT → SCK ↑ delay time
tSOVHI
Conditions
Unit
Internal clock
operation
CL = 80 pF + 1
TTL.
Min
Max
5 tcp*
⎯
ns
− 50
+ 50
ns
tcp* + 80
⎯
ns
0
⎯
ns
3 tcp* − 70
⎯
ns
*: tcp indicates the machine clock time
tSCYC
2.4 V
SCK
2.4 V
0.8 V
tSLOVI
tSOVHI
SOT
2.4 V
2.4 V
0.8 V
0.8 V
tIVSHI
SIN
tSHIXI
VIH
VIH
VIL
VIL
(10) Trigger Input Timing
Parameter
Input pulse width
Symbol
Pin name
Conditions
tTRGH
tTRGL
INT0 to INT15,
INT8R to INT15R,
ADTG
⎯
70
Min
Max
5 tCP
⎯
Unit
ns
VIH
VIH
INT0 to INT15,
INT8R to INT15R,
ADTG
Value
VIL
VIL
tTRGH
tTRGL
DS07-13752-4E
MB90950 Series
(11) Timer Related Resource Input Timing
Parameter
Input pulse width
Symbol
Pin name
Conditions
tTIWH
TIN0 to TIN3,
IN0 to IN7
⎯
tTIWL
Min
Max
4 tCP
⎯
Unit
ns
VIH
VIH
TIN0 to TIN3,
IN0 to IN7
Value
VIL
VIL
tTIWH
tTIWL
(12) Timer Related Resource Output Timing
Parameter
CLK ↑ → TOUT change time
CLK
Symbol
Pin name
Conditions
tTO
TOT0 to TOT3,
PPG0 to PPGF
⎯
Value
Min
Max
30
⎯
Unit
ns
2.4 V
2.4 V
TOT0 to TOT3,
PPG0 to PPGF
0.8 V
tTO
DS07-13752-4E
71
MB90950 Series
(13) Low voltage detection
Value
Parameter
Symbol
Pin
name
Conditions
Min
Typ
Max
Detection voltage
initial value
VDL
VCC
⎯
3.8
4.0
4.2
V
During voltage drop
Hysteresis width
VHYS
VCC
⎯
169
173
177
mV
During voltage rise
− 0.1
⎯
+ 0.1
V/μs
dV/dt at low voltage
reset
Power supply
voltage change
rate
dV/dt
Detection delay
time
td
VCC
⎯
⎯
− 0.004
⎯
⎯
⎯
⎯
Unit
Remarks
dV/dt at standard
value of low voltage
+ 0.004 V/μs
detection/release
voltage
3.2
μs
When | dV/dt | ≤
0.004 V/μs
Note: The power supply voltage change rate is at 0.004 V/μs<|dv/dt|<0.1 V/μs, a reset may be generated or released
after the power supply voltage is passed the detection voltage range.
Internal reset
VCC
dV
dt
VHYS
VDL
td
72
td
DS07-13752-4E
MB90950 Series
(14) I2C Timing
Parameter
Symbol
Conditions
Standard-mode
Fast-mode*1
Unit
Min
Max
Min
Max
fSCL
0
100
0
400
kHz
tHDSTA
4.0
⎯
0.6
⎯
μs
“L” width of the SCL clock
tLOW
4.7
⎯
1.3
⎯
μs
“H” width of the SCL clock
tHIGH
4.0
⎯
0.6
⎯
μs
Set-up time (repeated) START condition
SCL ↑ → SDA ↓
tSUSTA
4.7
⎯
0.6
⎯
μs
Data hold time
SCL ↓ → SDA ↓ ↑
tHDDAT
0
3.45*3
0
0.9*4
μs
Data set-up time
SDA ↓ ↑ → SCL ↑
tSUDAT
250
⎯
100
⎯
ns
Set-up time for STOP condition
SCL ↑ → SDA ↑
tSUSTO
4.0
⎯
0.6
⎯
μs
tBUS
4.7
⎯
1.3
⎯
μs
SCL clock frequency
Hold time (repeated) START condition
SDA↓ → SCL ↓
Bus free time between a STOP and START
condition
R = 1.7 kΩ,
C = 50 pF*2
*1: For use at over 100 kHz, set the machine clock to at least 6 MHz.
*2: R,C: Pull-up resistor and load capacitor of the SCL and SDA lines.
*3: The maximum tHDDAT meets the requirement that it does not extend the “L” width (tLOW) of the SCL signal.
*4: A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement
tSUDAT ≥ 250 ns must then be met.
VIH
SDA
VIL
VIL
VIL VIL
tHDSTA
DS07-13752-4E
VIH
VIH
VIH
VIH
VIL
VIL
tSUDAT
VIH
tLOW
VIH
SCL
VIH
tHDSTA
VIH
tBUS
VIH
VIL
tHDDAT
tHIGH
tSUSTA
tSUSTO
73
MB90950 Series
(15) CAN PLL cycle jitter
Symbol
Parameter
CAN PLL cycle jitter
(When locked)
tPJ
Pin
name
Value
Condition
⎯
Min
⎯
Typ
− 10
⎯
Max
+ 10
Unit
Remarks
ns
FCP =
16 MHz
(4 MHz × multiplied by 4)
24 MHz
(4 MHz × multiplied by 6)
32 MHz
(4 MHz × multiplied by 8)
• CAN PLL cycle jitter
Deviation time from the ideal clock is assured per cycle out of 20, 000 cycles.
PLL output
t1
t2
tn-1
t3
tn
Ideal clock
Slow
Deviation
time
t1
t2
t3
tn-1
tn
Fast
74
DS07-13752-4E
MB90950 Series
5. A/D Converter
(3.0 V ≤ AVRH − AVRL)
Value
Symbol
Pin
name
Conditions
Min
Typ
Max
Resolution
⎯
⎯
⎯
⎯
⎯
10
bit
Total error
⎯
⎯
⎯
⎯
⎯
±3.0
LSB
Nonlinearity
error
⎯
⎯
⎯
⎯
⎯
±2.5
LSB
Differential
nonlinearity
error
⎯
⎯
⎯
⎯
⎯
±1.9
LSB
Zero reading
voltage
VOT
AN0
to
AN23
⎯
AVRL −
1.5 LSB
AVRL +
0.5 LSB
AVRL +
2.5 LSB
V
Full scale
reading voltage
VFST
AN0
to
AN23
⎯
AVRH −
3.5 LSB
AVRH −
1.5 LSB
AVRH +
0.5 LSB
V
Compare time
⎯
⎯
⎯
⎯
16500
μs
Sampling time
⎯
⎯
⎯
⎯
∞
μs
Analog port
input current
IAIN
AN0
to
AN23
⎯
−0.3
⎯
+0.3
μA
Analog input
voltage range
VAIN
AN0
to
AN23
⎯
AVRL
⎯
AVRH
V
Reference
voltage range
⎯
AVRH
⎯
AVRL + 2.7
⎯
AVCC
V
⎯
AVRL
⎯
0
⎯
AVRH − 2.7
V
Power supply
current
IA
AVCC
⎯
⎯
3.5
7.5
mA
IAH
AVCC
⎯
⎯
⎯
5
μA
Parameter
0.66
2.2
0.4
1.0
Unit
Reference
voltage current
IR
AVRH
⎯
⎯
600
900
μA
IRH
AVRH
⎯
⎯
⎯
5
μA
Offset between
input channels
⎯
AN0 to
AN23
⎯
⎯
⎯
4
LSB
Remarks
4.5 V ≤ AVCC ≤ 5.5 V
3.0 V ≤ AVCC < 4.5 V
4.5 V ≤ AVCC ≤ 5.5 V
3.0 V ≤ AVCC < 4.5 V
*
*
*: If the A/D convertor is not operating, a current when CPU is stopped is applicable (VCC = AVCC = AVRH = 5.0 V) .
Note: The accuracy gets worse as |AVRH − AVRL| becomes smaller.
DS07-13752-4E
75
MB90950 Series
6. Definition of A/D Converter Terms
Resolution
Non linearity
error
Differential
linearity error
Total error
: Analog variation that is recognized by the A/D converter.
: The deviation between the actual conversion characteristics and a line that joins the
zero-transition line ( “00 0000 0000” ← → “00 0000 0001” ) to the full-scale transition line
( “11 1111 1110” ← → “11 1111 1111” ) .
: Deviation of input voltage, which is required for changing output code by 1 LSB, from an
ideal value.
: Difference between the actual value and the ideal value. The total error includes zero
transition error, full-scale transition error, and linear error.
Total error
3FFH
3FEH
Actual conversion
characteristics
1.5 LSB
Digital output
3FDH
{1 LSB × (N − 1) + 0.5 LSB}
004H
VNT
(Actually-measured value)
003H
Actual conversion
characteristics
Ideal characteristics
002H
001H
0.5 LSB
AVRL
AVRH
Analog input
VNT − {1 LSB × (N − 1) + 0.5 LSB}
1 LSB
AVRH − AVRL
1 LSB (Ideal value) =
[V]
1024
Total error of digital output “N” =
[LSB]
N : Value of the digital output from the A/D converter
VOT (Ideal value) = AVRL + 0.5 LSB [V]
VFST (Ideal value) = AVRH − 1.5 LSB [V]
VNT : A voltage at which the digital output transitions from (N − 1) H to NH.
(Continued)
76
DS07-13752-4E
MB90950 Series
(Continued)
Non linearity error
Differential linearity error
Ideal
characteristics
3FFH
Actual conversion
characteristics
{1 LSB × (N − 1)
+ VOT }
Digital output
3FDH
(N + 1)H
VFST (actual
measurement
value)
VNT (actual
measurement value)
004H
Actual conversion
characteristics
003H
Digital output
3FEH
Actual conversion
characteristics
NH
V (N + 1) T
(actual measurement
value)
VNT
(actual measurement value)
(N − 1)H
002H
Ideal characteristics
Actual conversion
characteristics
(N − 2)H
001H
VOT (actual measurement value)
AVRL
AVRH
AVRL
AVRH
Analog input
Analog input
Non linearity error of digital output N =
Differential linearity error of digital output N =
1 LSB =
VNT − {1 LSB × (N − 1) + VOT}
1 LSB
V (N+1) T − VNT
1 LSB
VFST − VOT
1022
[LSB]
−1 LSB [LSB]
[V]
N : Value of the digital output from the A/D converter
VOT : Voltage at which digital output transits from “000H” to “001H.”
VFST : Voltage at which digital output transits from “3FEH” to “3FFH.”
DS07-13752-4E
77
MB90950 Series
7. Notes on A/D Converter Section
Use the device with external circuits of the following output impedance for analog inputs :
Recommended output impedance of external circuits are : Approx. 4.2 kΩ or lower (4.5 V ≤ AVCC ≤ 5.5 V,
sampling period = 0.4 μs)
If an external capacitor is used, in consideration of the capacitive voltage dividing effect between the external
capacitor and the internal on-chip capacitor, it is recommended that the capacitance of the external capacitor
be several thousand times greater than the capacitance of the internal capacitor.
If the output impedance of the external circuit is too high, a sampling period for an analog voltage may be
insufficient.
• Analog input circuit model
Analog input
R
Comparator
C
4.5 V ≤ AVCC ≤ 5.5 V : R =: 4.1 kΩ, C =: 8.5 pF
3.0 V ≤ AVCC < 4.5 V : R =: 10.33 kΩ, C =: 8.5 pF
MB90V950AJAS/V950AMAS 4.5 V ≤ AVCC ≤ 5.5 V : R =: 2.52 kΩ, C =: 10.7 pF
MB90F952JDS/F952MDS
Note : Use the values in the figure only as a guideline.
78
DS07-13752-4E
MB90950 Series
• The relationship between external impedance and minimum sampling time
• At 4.5 V ≤ AVCC ≤ 5.5 V
(External impedance = 0 kΩ to 100 kΩ)
(External impedance = 0 kΩ to 20 kΩ)
100
90
80
70
60
50
40
30
20
10
0
External impedance [kΩ]
External impedance [kΩ]
MB90F952MDS,
MB90F952JDS
MB90V950AJAS,MB90V950AMAS
0
1
2
3
4
5
6
7
8
MB90F952MDS,
MB90F952JDS
20
18
16
14
12
10
8
6
4
2
0
MB90V950AJAS,MB90V950AMAS
0
9 10
Minimum sampling time [μs]
1
2
3
4
5
Minimum sampling time [μs]
Minimum sampling time [μs] (4.5 V ≤ AVCC ≤ 5.5 V)
External impedance [kΩ]
5
10
50
MB90F952MDS,MB90F952JDS
0.54
0.84
3.22
MB90V950AJAS,MB90V950AMAS
0.56
0.94
3.93
(External impedance = 0 kΩ to 20 kΩ)
MB90F952MDS,
MB90F952JDS
100
90
80
70
60
50
40
30
20
10
0
External impedance [kΩ]
External impedance [kΩ]
• At 3.0 V ≤ AVCC < 4.5 V
(MB90V950 is at 4.0 V ≤ AVcc < 4.5 V)
(External impedance = 0 kΩ to 100 kΩ)
MB90V950AJAS,MB90V950AMAS
0
1
2
3
4
5
6
7
8
20
18
16
14
12
10
8
6
4
2
0
MB90F952MDS,
MB90F952JDS
MB90V950AJAS,MB90V950AMAS
0
9 10
Minimum sampling time [μs]
1
2
3
4
5
Minimum sampling time [μs]
Minimum sampling time [μs] (3.0 V ≤ AVCC<4.5 V)
External impedance [kΩ]
5
10
50
MB90F952MDS,MB90F952JDS
0.91
1.21
3.59
MB90V950AJAS,MB90V950AMAS
1.39
1.77
4.76
• About errors
As | AVR − AVSS | becomes smaller, values of relative errors grow larger.
DS07-13752-4E
79
MB90950 Series
8. Flash Memory Program/Erase Characteristics
Parameter
Value
Conditions
Unit
Remarks
Min
Typ
Max
⎯
0.9
3.6
s
Excludes programming
prior to erasure
⎯
7.2
28.8
s
Main Flash
⎯
3.6
14.4
s
Satellite Flash
Word (16-bit width)
programming time
⎯
15
240
μs
Except for the overhead
time of the system
Word (16-bit width)
programming time
⎯
23
370
μs
Except for the overhead
time of the system
TA > +85 °C
10000
⎯
⎯
cycle
TA ≤ +85 °C
100000
⎯
⎯
cycle
Average
TA = +85 °C
20
⎯
⎯
year
Sector erase time
Chip erase time
⎯
Program/Erase cycle
Flash Data Retention
Time
*
* : The value was converted into the normalized temperature at +85ÅãC from the results of evaluating the reliability
of the technology.
9. D/A Converter
Symbol
Pin
name
Conditions
Resolution
⎯
⎯
Non linearity
error
⎯
⎯
Conversion
time
⎯
⎯
Output
impedance
RO
Parameter
Power supply
current
80
Value
Unit
Min
Typ
Max
⎯
⎯
8
⎯
bit
⎯
-0.5
⎯
+0.5
LSB
⎯
0.773
0.787
1.078
⎯
2.490
2.535
3.474
DA0,
DA1
⎯
3.19
3.50
4.80
kΩ
IA
AVCC
⎯
⎯
476
920
μA
IAH
AVCC
⎯
⎯
⎯
5
μA
μs
Remarks
CL = 20 pF
CL = 100 pF
DS07-13752-4E
MB90950 Series
■ ORDERING INFORMATION
Part number
MB90F952JDSPF
MB90F952MDSPF
MB90F952JDSPFV
MB90F952MDSPFV
MB90V950AMASCR-ES
MB90V950AJASCR-ES
DS07-13752-4E
Package
Remarks
100-pin plastic QFP
(FPT-100P-M06)
100-pin plastic LQFP
(FPT-100P-M20)
299-pin ceramic PGA
(PGA-299C-A01)
For evaluation
81
MB90950 Series
■ PACKAGE DIMENSIONS
100-pin plastic QFP
Lead pitch
0.65 mm
Package width ×
package length
14.00 × 20.00 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
3.35 mm MAX
Code
(Reference)
P-QFP100-14×20-0.65
(FPT-100P-M06)
100-pin plastic QFP
(FPT-100P-M06)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
23.90±0.40(.941±.016)
* 20.00±0.20(.787±.008)
80
51
50
81
0.10(.004)
17.90±0.40
(.705±.016)
*14.00±0.20
(.551±.008)
INDEX
Details of "A" part
0.25(.010)
+0.35
3.00 –0.20
+.014
.118 –.008
(Mounting height)
0~8˚
31
100
1
30
0.65(.026)
0.32±0.05
(.013±.002)
0.13(.005)
M
"A"
©2002-2008
FUJITSU MICROELECTRONICS LIMITED F100008S-c-5-6
C
2002 FUJITSU LIMITED F100008S-c-5-5
0.17±0.06
(.007±.002)
0.80±0.20
(.031±.008)
0.88±0.15
(.035±.006)
0.25±0.20
(.010±.008)
(Stand off)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/
(Continued)
82
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MB90950 Series
(Continued)
100-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
14.0 mm × 14.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm Max
Weight
0.65 g
Code
(Reference)
P-LFQFP100-14×14-0.50
(FPT-100P-M20)
100-pin plastic LQFP
(FPT-100P-M20)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
16.00±0.20(.630±.008)SQ
* 14.00±0.10(.551±.004)SQ
75
51
76
50
0.08(.003)
Details of "A" part
+0.20
26
100
1
25
C
0.20±0.05
(.008±.002)
0.08(.003)
M
0.10±0.10
(.004±.004)
(Stand off)
0°~8°
"A"
0.50(.020)
+.008
1.50 –0.10 .059 –.004
(Mounting height)
INDEX
0.145±0.055
(.0057±.0022)
2005 -2008 FUJITSU MICROELECTRONICS LIMITED F100031S-c-3-3
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.25(.010)
Dimensions in mm (inches).
Note: The values in parentheses are reference values
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/
DS07-13752-4E
83
MB90950 Series
■ MAIN CHANGES IN THIS EDITION
Page
Section
⎯
⎯
74
■ ELECTRICAL CHARACTERISTICS
4. AC Characteristics
Change Results
Changed the part number;
MB90V950MAS→MB90V950AMAS
MB90V950JAS→MB90V950AJAS
Added the item “(15) CAN PLL cycle jitter”.
The vertical lines marked in the left side of the page show the changes.
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MEMO
DS07-13752-4E
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MEMO
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MB90950 Series
MEMO
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87
MB90950 Series
FUJITSU MICROELECTRONICS LIMITED
Shinjuku Dai-Ichi Seimei Bldg., 7-1, Nishishinjuku 2-chome,
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For further information please contact:
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