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AN706-00055-v11-E
32-BIT MICROCONTROLLER
FM3 family Application Note
Design of Low Power Systems
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AN706-00055-v11-E
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the use of information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for
general use, including without limitation, ordinary industrial use, general office use, personal use, and
household use, but are not designed, developed and manufactured as contemplated (1) for use
accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious
effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss
(i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport
control, medical life support system, missile launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages
arising in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or
loss from such failures by incorporating safety design measures into your facility and equipment such as
redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or technologies subject to certain restrictions on
export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese
government will be required for export of those products from Japan.
The company names and brand names herein are the trademarks or registered trademarks of their
respective owners.
Copyright© 2012 FUJITSU SEMICONDUCTOR LIMITED all rights reserved
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Revision History
Rev
Date
Remark
1.0
Oct. 15, 2012
MSc / SMa, First Edition
1.1
Mar. 09,2013
MSc, Energy harvesting added
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Table of Contents
Revision History...................................................................................................................... 2
Table of Contents.................................................................................................................... 3
Target products ....................................................................................................................... 5
1
Introduction ................................................................................................................... 6
2
Source Clock Selection ................................................................................................ 7
3
4
2.1
System Clock Mode Control Register ..................................................................... 8
2.2
PLL Unit ................................................................................................................... 8
Normal CPU Operation ............................................................................................... 10
3.1
Sub Run Mode ...................................................................................................... 10
3.2
Low-speed CR Run mode ..................................................................................... 10
3.3
High-speed CR Run mode .................................................................................... 10
3.4
Main Run mode ...................................................................................................... 11
3.5
PLL Run mode ....................................................................................................... 11
Low Power Operation ................................................................................................. 12
4.1
4.1.1
Standby Mode Control Register .................................................................... 12
4.1.2
RTC Mode Control Register .......................................................................... 12
4.1.3
Cortex-M3 System Control Register.............................................................. 13
4.2
Standby Sleep Mode ..................................................................................... 14
4.2.2
Standby Timer Mode ..................................................................................... 14
4.2.3
Standby RTC Mode ....................................................................................... 14
4.2.4
Standby STOP Mode ..................................................................................... 14
Deep Standby Modes............................................................................................ 15
4.3.1
Deep Standby RTC Mode ............................................................................. 15
4.3.2
Deep Standby Stop Mode ............................................................................. 16
4.4
6
Standby Modes ..................................................................................................... 13
4.2.1
4.3
5
Control Registers................................................................................................... 12
Deep Standby RAM Retention and Backup Registers ......................................... 16
Low Power Considerations ........................................................................................ 17
5.1
JTAG...................................................................................................................... 17
5.2
Low Voltage Detection .......................................................................................... 17
5.3
LCD Pins and Analog Inputs ................................................................................. 17
5.4
GPIO Pins ............................................................................................................. 18
Wake Up Times ............................................................................................................ 19
3
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6.1
Standby Modes ..................................................................................................... 19
6.2
Deep Standby Modes............................................................................................ 19
6.3
Wake up time scenarios ........................................................................................ 21
6.3.1
Executing the ISR, wait for the oscillators, then execute the first instruction.
21
6.3.2
Wait for the oscillators, execute the first instruction, and then execute ISR. 21
6.3.3
Executing the first instruction, then go to the ISR and wait for the oscillators.
23
7
8
9
Voltage Regulators and Super-capacitors ............................................................... 24
7.1
LDO and non-LDO regulators ............................................................................... 24
7.2
Super Capacitors................................................................................................... 24
7.3
Super Capacitors and voltage regulators ............................................................. 25
7.3.1
Decaying output voltage ................................................................................ 25
7.3.2
Fixed output voltage ...................................................................................... 28
Energy Harvester ........................................................................................................ 30
8.1
Piezo...................................................................................................................... 31
8.2
Electric Field .......................................................................................................... 32
8.3
Solar Panel ............................................................................................................ 32
8.4
Thermoelectric....................................................................................................... 33
Conclusions ................................................................................................................. 34
Appendix: Comparison table of clock operation states in all modes. ................................... 0
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Target products
This application note is described about below products;
•
All Series.
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1
Introduction
This Application-note describes the low power consumption modes of different devices and
also includes the basic code to switch between Run Mode (Normal Mode) and other.
Since there are several types of devices, also different low power modes and sub modes are
available according to each device type; Table 1.0 shows an overview.
Low Power
Sub Modes
TYPE
TYPE
TYPE
0, 1, 2, 4
3, 7
5, 6
Sleep mode
○
○
○
Timer mode
○
○
○
RTC mode
Not available
○
○
Stop mode
○
○
○
Deep Standby RTC mode
Not available
○
○
Deep Standby RTC mode
Not available
Not available
○
Modes
Standby
Modes
Deep
(On-chip SRAM retention)
Standby
Deep Standby Stop mode
Not available
○
○
Deep Standby Stop mode
Not available
Not available
○
Modes
(On-chip SRAM retention)
Table1.0: Low power consumption modes equipped in each TYPE.
Also five different clock sources are available for the CPU and peripherals (Sub, Low-speed
CR, High-speed CR, Main and PLL) and therefore the power consumption of each one is
different.
Depending on the group of the device, different low power modes are available, for example
the Ultra Low Leakage and the Low Power Groups are supporting Deep-Standby modes
while the High Performance Group only supports Sleep, Timer and Stop modes.
Therefore since not all devices support all low power modes, not everything described in this
application note applies to all devices. For example
the Deep-Stop mode with SRAM retention is only
available for Type 5 and 6 products. On the other
hand, Timer and Stop modes apply to all type of
devices.
6
The device TYPE can be found on
the first page of the corresponding
datasheet.
AN706-00055-v11-E
2
Source Clock Selection
To operate the MCU several options and power requirements are available
The following five types of clocks are source clocks:
•
Main clock (CLKMO)
•
Sub clock (CLKSO)
•
High-speed CR clock (CLKHC)
•
Low-speed CR clock (CLKLC)
•
Main PLL clock (CLKPLL)
Once one of these five clock sources is selected, it can be used as Master clock. The Master
clock is the source of the internal bus clocks used to operate the MCU.
Figure 2.0: Block Diagram of Clock Generation Unit (Peripheral manual, chapter: clock).
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Figure 2.0 depicts all clock sources, internal and external,as well as all the available bus
prescalers and PLL modules discussed later on.
2.1
System Clock Mode Control Register
As mentioned before, there are five options to select the Master Clock. It is also possible to
control which oscillators will be on or off depending on the Master clock selected. This is
done in the System Clock Mode Control Register (SCM_CTL).
The SCM_CTL is an 8 bit register; from those, only 6
The SCM_CTL register can be found
bits are used: 3 bits are dedicated to select the
in the Peripheral Manual, within the
source clock (RCS[2:0]) and 3 more to independently
Clock Chapter.
enable/disable the PLL (PLLE), Main (MOSCE) and
Sub (SOSCE) oscillators, see table 2.0.
7-5
4
3
2
1
0
RCS[2:0]
PLLE
SOSCE
Reserved
MOSCE
Reserved
Table 2.0: SCM_CTL register bits.
The internal oscillators (Low-speed CR and High-speed CR) cannot be manually turned on
and off. This is done automatically by the power mode selected.
2.2
PLL Unit
The PLL unit is very simple to use with the proper considerations; there are basically three
important concepts which are
•
,
is the frequency of the external main oscillator (also can be the internal
High-speed CR) divided by the factor
•
.
is the output frequency of the PLL module, and it is equal to
the factor
•
(see figure 2.1):
and
times
.
is the frequency that will act as Master Clock when selected as
oscillation source, equals to
divided by
.
The formulas below explain the PLL module in a simple way:
/
/
8
AN706-00055-v11-E
Figure 2.1: PLL module.
According to the device, some restrictions in the parameters vary, for example the factor
(PLL multiply rate) should be kept in the proper range. The same applies to
and
. These values can be found in the corresponding datasheet of the device,
section ELECTRICAL CHARACTERISTIS, sub section AC Characteristics. See figure 2.2
for an example.
Figure 2.2: PLL parameters from MB9AB40N Series.
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3
Normal CPU Operation
Five Run modes are available according to the selected Master Clock
Run mode refers to the normal operation of the CPU. The highest performance of the MCU
can be achieved and hence, highest power consumption. All or most of the peripheral
features are available in this mode, depending on the clock selected.
Run mode is defined by the clock selected as Master Clock. The base clocks, obtained by
dividing the Master Clock frequency, are supplied to CPU clock and Internal AHB bus clock,
and APB bus clock to run the CPU, buses, and most peripherals.
The source clock frequency can be changed dynamically. When not using the main or sub
oscillator, the source clock oscillator can be stopped.
Run mode is divided into the following sub modes depending on the source clock selected.
3.1
Sub Run Mode
In this mode the sub oscillator clock is used as Master Clock. The Low-speed CR oscillator
is always set to the active state. The main oscillator, High-speed CR oscillator, and PLL
Multiplier Circuit are not available in this mode.
3.2
Low-speed CR Run mode
In this mode the Low-speed CR oscillator clock is used as Master Clock. The status of the
sub oscillator varies depending on the setting of the SOSCE bit in the SCM_CTL register.
The main oscillator, High-speed CR oscillator, and PLL Multiplier Circuit are not available in
this mode.
3.3
High-speed CR Run mode
In this mode the High-speed CR oscillator clock is used as Master Clock. When not using
the main or sub oscillator, the respective oscillators can be stopped. The status of PLL
Multiplier Circuit varies depending on the setting of the PLLE bit in the SCM_CTL register.
The Low-speed CR oscillator is always set to the active state. It changes to this mode after a
reset has been released.
10
AN706-00055-v11-E
3.4
Main Run mode
In this mode the main oscillator clock is used as Master Clock. The status of the PLL
Multiplier Circuit or sub oscillator varies depending on the setting of the PLLE or SOSCE bit
in the SCM_CTL register. The High-speed CR and Low-speed CR oscillators are always
active.
3.5
PLL Run mode
In this mode the PLL clock is obtained by multiplying the Main oscillator clock or High-speed
CR oscillator clock and is used as Master Clock. The main, High-speed CR, and Low-speed
CR oscillators are always set to the active state. The status of the main or sub oscillator
varies depending on the setting of the MOSCE or SOSCE bit in the SCM_CTL register.
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4
Low Power Operation
To switch between power modes a few steps need to be followed
In general there are two different low power modes: Standby and Deep Standby mode.
Standby mode consists of 4 sub modes while in Deep Standby mode 2 sub modes are
accessible.
There are a lot of differences between these two general modes, but the main one is power
consumption. In Deep Standby modes all oscillations and buses are stopped, except for the
Sub oscillator in Deep RTC standby mode (further information can be found in chapter Low
Power Consumption Mode of the Peripheral Manual).
4.1
Control Registers
There are three registers to access all different sub-modes: The Standby Mode Control
Register (STB_CTL), the RTC Mode Control Register (PMD_CTL), and the Cortex-M3
System Control Register (SCR).
4.1.1
Standby Mode Control Register
To effectively change the value of this
In the STB_CTL register it is possible to configure the
register it is necessary to write
status of the pins (high impedance/retain value)
0x1ACC
during Standby and Deep Standby, to select which of
simultaneously with the new register
these modes to enter (Standby or Deep Standby) and
bit values.
to
the
key
bits
to select between Timer, STOP/RTC Standby and
stop/RTC Deep Standby modes.
31 - 16
15 - 5
4
3
2
1-0
KEY
Reserved
SPL
Reserved
DSTM
STM
Table 3.0: STB_CTL Register bits.
4.1.2
RTC Mode Control Register
With PMD_CTL register it is possible to select either Standby RTC mode or Standby STOP
mode and either deep standby RTC mode or deep standby STOP mode. This is an 8 bit
register, but only 1 bit is modifiable (bit 0), the other bits are reserved.
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AN706-00055-v11-E
7–1
0
Reserved
RTCE
Table 3.1: PMD_CTL Register bits.
4.1.3
Cortex-M3 System Control Register
The Cortex-M3 System Control Register is a 32 bit register, from which only 3 bits are
modifiable, and from those 3 only the SLEEPDEEP (bit 2) bit is important for this application
note. This bit indicates to the system that Cortex-M3 clock can be stopped.
31 - 5
4
3
2
1
0
Reserved
SEVONPEND
Reserved
SLEEPDEEP
SLEEPONEXIT
Reserved
Table 3.2: Cortex-M3 System Control Register bits.
4.2
Standby Modes
In Standbymode the following sub modes are available:
•
Standby Sleep mode
•
Standby Timer mode
•
Standby RTC mode
•
Standby STOP mode
To enter these sub modes specific instructions must be followed, after that the WFI (Wait for
an Interrupt) or WFE (Wait for an Event) instruction must be executed (examples below).
After the execution of this special instructions the system switches from Run mode to the
instructed mode.
To return from the Standby modes there are several options (further information can be
found in Operation of standby modes in chapter Low Power Consumption Mode of the
Peripheral Manual). In this application note only an External Interrupt will be used to return
from Standby modes. After returning from Standby, the CPU will switch to Run mode and
will select the source clock according to the last value of SCM_CTL register bits, this means
that it will return to the previous Master clock selected in Run mode. Also the CPU will
execute the corresponding Interrupt Service Routine (if returning by interrupt), and will
continue operating in Run mode.
For example if the CPU is being run by the Main clock (Main Run mode), then the __WFI();
instruction is executed (at this point the system is in Main standby mode) and when some
time an interrupt occurs, the system will return and start operating in Main Run mode.
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4.2.1
Standby Sleep Mode
To switch from any Run mode to Standby Sleep mode the following instructions should be
executed:
FM3_CRG->STB_CTL = 0x1ACC0010;
// Key value, DeepSleep disabled, pins to high impedance
SCB->SCR &= ~0x00000004;
// Reset SLEEPDEEP bit of Cortex-M3 System Control Reg
__WFI();
// Go to Standby Sleep mode (Wait For an Interrupt)
4.2.2
Standby Timer Mode
To switch from any Run mode to Standby Timer mode the following instructions should be
executed:
bFM3_DS_PMD_CTL_RTCE = 0;
// STOP mode and deep standby stop mode
FM3_CRG->STB_CTL = 0x1ACC0010;
// Key value, DeepSleep disabled, pins to high impedance
SCB->SCR |= 0x00000004;
// Set SLEEPDEEP bit of Cortex-M3 System Control Reg
__WFI();
// Go to Standby Timer mode (Wait For an Interrupt)
4.2.3
Standby RTC Mode
To switch from any Run mode to RTC Standby mode the following instructions should be
executed:
bFM3_DS_PMD_CTL_RTCE = 1;
// RTC mode and deep standby RTC mode
FM3_CRG->STB_CTL = 0x1ACC0012;
// Key value, DeepSleep disabled, pins to high impedance
SCB->SCR |= 0x00000004;
// Set SLEEPDEEP bit of Cortex-M3 System Control Reg
__WFI();
// Go to Standby RTC mode (Wait For an Interrupt)
4.2.4
Standby STOP Mode
To switch from any Run mode to Standby STOP mode the following instructions should be
executed:
bFM3_DS_PMD_CTL_RTCE = 0;
// STOP mode and deep standby stop mode
FM3_CRG->STB_CTL = 0x1ACC0012;
// Key value, DeepSleep disabled, pins to high impedance
SCB->SCR |= 0x00000004;
// Set SLEEPDEEP bit of Cortex-M3 System Control Reg
__WFI();
// Go to Standby Stop mode (Wait For an Interrupt)
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4.3
Deep Standby Modes
In Deep Standby the following sub modes are available:
•
Deep Standby RTC mode.
•
Deep Standby Stop mode.
To enter these sub modes, specific instructions must be followed, after that the __WFI();
(wait for an interrupt) or __WFE(); (wait for an event) instruction must be executed. After the
execution of this special instruction the system switches to the instructed mode.
To return from the Deep Standby modes there are duty few options, because these are the
lowest power consumption modes.
From Deep Standby RTC it is possible to return by
reset (INITX pin input reset or low-voltage detection
reset), by Remote Control Reception interrupt, by
low-voltage detection interrupt, and by WKUP pin
interrupt. In this application note only the WKUP0 pin
A return from deep standby mode by
WKUP0 pin input is always enabled
and
WKUP0
pin
input
always
requests a return in Low level. These
settings cannot be changed.
(Wake Up 0 input) will be used to return from the
Deep Standby modes.
After either a valid reset or interrupt occurs, the CPU returns from Deep Standby mode and
changes to High-speed CR Run mode regardless of the previous clock mode. It has to be to
mentioned that after returning from Deep Standby modes, the CPU will not execute the
interrupt service routine as before in Standby modes. It will start the code from the first line,
like a reset because the NVIC is initialized by Deep Standby transition reset.
4.3.1
Deep Standby RTC Mode
To switch from any Run mode to Deep Standby RTC mode the following instructions should
be executed.
bFM3_DS_PMD_CTL_RTCE = 1;
// RTC mode and deep standby RTC mode
FM3_CRG->STB_CTL = 0x1ACC0006;
// Key value, DeepSleep enabled, remember status on pins
SCB->SCR |= 0x00000004;
// Set SLEEPDEEP bit of Cortex-M3 System Control Reg
__WFI();
// Go to Deep-Standby RTC mode (Wait For an Interrupt)
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AN706-00055-v11-E
4.3.2
Deep Standby Stop Mode
To switch from any Run mode to Deep Standby STOP mode the following instructions
should be executed:
bFM3_DS_PMD_CTL_RTCE = 0;
// STOP mode and deep standby stop mode
FM3_CRG->STB_CTL = 0x1ACC0006;
// Key value, DeepSleep enabled, remember status on pins
SCB->SCR |= 0x00000004;
// Set SLEEPDEEP bit of Cortex-M3 System Control Reg
__WFI();
// Go to Deep-Standby Stop mode (Wait For an Interrupt)
4.4
Deep Standby RAM Retention and Backup Registers
In some devices retention of the on-chip SRAM contents in deep standby modes is
possible (Check Table 1.0). In Deep Standby modes the Back-up registers can be used
which are special sixteen 8-bit registers which store the value within them. When
available, Back-up registers are always enabled.
To enable on-chip SRAM retention, one control register is available. Execute the following
code before the WFI or WFE instruction to keep the contents of SRAM while in Deep
Standby mode.
FM3_DS->DSRAMR = 0x03;
// Retain on-chip SRAM contents in Deep-standby mode
To disable on-chip SRAM retention, just load the same register with “0” (clear the register).
16
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5
Low Power Considerations
Turn off active peripherals by default and general recommendations
5.1
JTAG
By default the JTAG interface is activated, even if the connector is unplugged. For example
in the MB9AFB44N the JTAG consumes around 200µA.
To disable the JTAG execute the following code:
FM3_GPIO->PFR0 = 0x00000000; //Disable JTAG interface, write 0x0000001F to enable it again
Note that right after executing this instruction, debugging and programming via JTAG is not
possible anymore. To enable the JTAG interface, erase the MCU memory and program it
again via UART/USB with the proper value (see comments on code above).
5.2
Low Voltage Detection
The Low-voltage Detection Circuit monitors the power supply voltage, and generates reset
and interrupt signals when the power supply voltage falls below the detection voltage. When
running by a Super-capacitor or battery the voltage might vary and a reset sometimes is not
desired.
To disable the LVD circuit execute the following code:
FM3_LVD->LVD_RLR = 0x1ACCE553;
// Enables writing the LVD Voltage Control Register
FM3_LVD->LVD_CTL = 0x0000;
// Disable the LVD
FM3_LVD->LVD_RLR = 0x0000000;
// Disables writing the LVD Voltage Control Register
5.3
LCD Pins and Analog Inputs
Although the LCD module does not influence directly the current consumption, the devices
equipped with this module by default configure the GPIO ports to LCD peripheral function,
and therefore if it is not deactivated, the shared GPIO pins will not work properly.
To disable the LCD module (if required) execute the following code:
FM3_LCDC->LCDCC3 = 0x80;
// Disable the LCD controller, Input from IO not cut off
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The same happens with the analog inputs, so if they are not used, it is better to set this pins
as digital GPIO.
To set the GPIO pins to digital instead of analog inputs execute the following code:
FM3_GPIO->ADE = 0x00000000;
5.4
// No Analog Inputs
GPIO Pins
The best to achieve the lowest power consumption is to set all unconnected ports as output,
because as input they will be floating and that could lead to unexpected behavior in current
consumption. Also depending on the circuitry on the board, is recommended to set the
output pins to low level (if possible).
18
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6
Wake Up Times
Time required to switch from Standby/Deep-Standby mode to Run mode
The time to return to Run mode depends on the previous master clock and the last Run
mode before going to Standby or Deep Standby. In Standby the device will return and
execute the ISR (if returning by interrupt) while in Deep Standby the device will return
always like a reset (even when returning by WKUPX interrupt) and executes the Startup
code. After that the MCU will continue with the Main function.
6.1
Standby Modes
The wake up time is measured from the moment the external interrupt is fired until the
execution of the first instruction (setting a bit) in the interrupt service routine (after waiting for
the corresponding oscillators, if required). Figure 3.0 shows the time sequence of events
(example for MB9AFB44N waking up from Sub-run mode executing the ISR first).
Figure 3.0: Wake up time line example.
6.2
Deep Standby Modes
The wake up time from Deep Standby modes is a bit different, because the ISR is not
executed; instead the start up code is executed (like a reset) and then the Main function.
Figure 3.1 shows the start up time from reset and from waking up from Deep Standby mode.
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AN706-00055-v11-E
Figure 3.2 shows the case when the device is woken up by WKUPX pin. Here the wake up
time refers to the time elapsed from the moment the WKUPX button is pressed until a bit is
set right at the beginning of the startup code. In the figure can be seen the startup code is
faster when coming back from Deep standby than when resetting the device.
Figure 3.1: Start up time example at hardware reset.
Figure 3.2: Start up time example when waking up from Deep Standby.
20
AN706-00055-v11-E
6.3
Wake up time scenarios
There are at least three possible scenarios when waking up because of an interrupt was
triggered in Standby modes:
1. Execute the ISR and wait for the oscillators, then execute the first instruction.
2. Wait for the oscillators, execute the first instruction and then execute the ISR.
3. Execute the first instruction, then go to the ISR and wait for the oscillators.
These three possible scenarios have different wake up times. Considering the time that
takes from pressing the external interrupt button to set a bit as the first instruction, the
longest wake up time will be the first case, while the shortest one will be the third case.
The next subsections show the code necessary to choose one of the previous mentioned
scenarios and a table with an example of the MB9AB40N wake up times for each case.
6.3.1
Executing the ISR, wait for the oscillators, then execute the first instruction.
It can be considered as the normal case, no special instructions or assembler code is
needed.
__WFI();
Mode / Clock
// Go to Standby mode and Wait For an Interrupt
Sub
Low-speed
High-speed
Main
PLL
clock
CR clock
CR clock
clock
clock
Sleep
1.39 ms
458 µs
11.44 µs
11 µs
1.2 µs
Timer
1.82 ms
715 µs
50 µs
45.6 µs
33.65 µs
RTC
3.184 ms
1.15 ms
265.2 µs
32.9 ms
33 ms
STOP
336 ms
1.15 ms
265.5 µs
32.88 ms
32.96 ms
Deep RTC and STOP
33.24 ms / 33.28 ms (SRAM on/off with Start up code)
Deep RTC and STOP
280 µs / 320 µs (SRAM on/off without Start up code)
Table 4.0: Wakeup times example from Standby and Deep Standby modes for
MB9AFB44N.
6.3.2
Wait for the oscillators, execute the first instruction, and then execute ISR.
In this case before executing the __WFI(); instruction, the interrupts are disabled with the
CMSIS instruction __disable_irq(); then by clearing P41 the register R0 is loaded with the
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address and finally “1” is preloaded in R1.
After the external interrupt is triggered and since the interrupts are disabled, the ISR is not
executed, instead the next instruction after __WFI(); is executed, in this case wait for the
external oscillator “X” to stabilize.
After the stabilization the next instruction will store the value that holds register R1 (“1” which
was already preloaded) to the address that R0 is pointing to, in this case P41.
__disable_irq();
// Disable jump to interrupts
bFM3_GPIO_PDOR4_P1 = 0;
// Reset P41 and load the address of P41 in R0
asm("MOVS
// Load R1 with "1"
R1, #1");
__WFI();
// Go to Standby-X mode
while (0 == bFM3_CRG_SCM_STR_X); // Wait for X oscillation stabilization
asm("STR
R1, [R0]");
__enable_irq();
Mode / Clock
// Set P41
// Enable interrrupts and therefore execute the ISR
Sub
Low-speed
High-speed
Main
PLL
clock
CR clock
CR clock
clock
clock
Sleep
808 µs
-
-
6.96 µs
0.938 µs
Timer
1.335 ms
-
-
44.16 µs
32.62 µs
RTC
-
-
-
32.88 ms
33 ms
STOP
334.4 ms
-
-
32.88 ms
33 ms
Deep RTC and STOP
33.24 ms / 33.28 ms (SRAM on/off with Start up code)
Deep RTC and STOP
280 µs / 320 µs (SRAM on/off without Start up code)
Table 4.1: Wakeup times example from Standby and Deep Standby modes for
MB9AFB44N.
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AN706-00055-v11-E
6.3.3
Executing the first instruction, then go to the ISR and wait for the oscillators.
The fastest scenario; the only difference between this one and the previous scenario is that
right after the “__WFI(); ” instruction, the bit P41 is set. Then the interrupts are activated and
waiting for the oscillators to stabilize is done within the ISR.
__disable_irq();
// Disable jump to interrupts
bFM3_GPIO_PDOR4_P1 = 0;
// Reset P41 and load the address of P41 in R0
asm("MOVS
// Load R1 with "1"
R1, #1");
__WFI();
asm("STR
// Go to Standby-X mode
R1, [R0]");
__enable_irq();
Mode / Clock
// Set P41
// Enable interrrupts and therefore execute the ISR
Sub
Low-speed
High-speed
Main
PLL
clock
CR clock
CR clock
clock
clock
Sleep
336 µs
113 µs
2.9 µs
3 µs
0.348 µs
Timer
604 µs
316 µs
40 µs
35 µs
31.36 µs
RTC
799 µs
422 µs
247 µs
32.68 ms
33 ms
STOP
333.6 ms
422 µs
248 µs
32.84 ms
32.98 ms
Deep RTC and STOP
33.24 ms / 33.28 ms (SRAM on/off with Start up code)
Deep RTC and STOP
280 µs / 320 µs (SRAM on/off without Start up code)
Table 4.2: Wakeup times example from Standby and Deep Standby modes for
MB9AFB44N.
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7
Voltage Regulators and Super-capacitors
Selection of the voltage regulator according to the application
When talking about low power applications it is important to consider all aspects of the
application, such as the voltage regulator. In most applications the two most important
parameters when selecting a linear voltage regulator are the output current and the output
voltage, but for low power devices the quiescent current (current flowing through the system
when no load is present) and the input–output differential voltage are also very important
parameters.
7.1
LDO and non-LDO regulators
LDO regulator means low dropout regulator. An LDO voltage regulator is just a DC linear
voltage regulator which can be operated with a very small input-output differential voltage.
This input-output voltage differential is called dropout voltage. In other words dropout
voltage is the voltage dropped by the regulator circuitry for its working. For example, an
LM2941 LDO voltage regulator has a dropout voltage of only around 0.5V, which means that
in order to get 5 volts at the output you need to input only 5.5 volts where an ordinary 7805
linear voltage regulator has a dropout voltage of around 2V. This means that, in order to get
5V at the output of 7805 you need to input at least 7V.
7.2
Super Capacitors
Another important topic in low power applications is also to have an energy storage. This
can be a battery or a super-capacitor (also known as double layer capacitor). Both of them
are different elements which are suitable for different applications, each of them have
advantages and disadvantages.
Table 5.0 summarizes the pros and cons of a super-capacitor.
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AN706-00055-v11-E
Super - Capacitor
Advantages
Disadvantages
Virtually unlimited life cycle; can be charged
and discharged millions of times
High specific power; low resistance enables
high load currents
Charges in seconds; no end-of-charge
termination required
Simple charging; draws only what it needs;
not subject to overcharge
Excellent low-temperature charge and
Low specific energy; holds a fraction of a
regular battery
Linear discharge voltage prevents using the
full energy spectrum
High self-discharge; higher than most
batteries
Low cell voltage; requires serial connections
with voltage balancing
High cost per watt
discharge performance
Table 5.0: Advantages and disadvantages of a Super-capacitor.
7.3
Super Capacitors and voltage regulators
When using a super-capacitor it has to be considered. if the application needs a fixed output
voltage for as long as possible or it can run within a decaying voltage range without
problems.
Also here is it very important to select the adequate voltage regulator and topology and if the
application requires a fix output voltage, then an LDO with a very low quiescent current will
be needed, as will be seen in the above examples.
7.3.1
Decaying output voltage
When it is possible to run the application within a voltage range, the easiest way is to place
the super-capacitor directly to the output of the regulator as figure 4.0 shows.
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AN706-00055-v11-E
Figure 4.0: Super-capacitor connected at the output of the voltage regulator.
This scheme has one special characteristic, the diodes D1 and D2; D2 prevents the
backward current from the super-capacitor, but at the same time D2 also creates the voltage
drop (the forward voltage of the diode itself). To balance this voltage drop, D1 is placed
between the IC’s ground terminal and ground to increase the output voltage (this increment
is again the forward voltage of the diode itself) and therefore D1 “cancels” the voltage drop
generated by D2 (Adding 2 diodes might not work for all voltage regulators).
If there is no power at the input, the remaining functional circuit is shown in the figure 4.1.
The resistor in series with the super-capacitor is placed to avoid a current surge when
charged. This resistor creates a simple charging circuit with a charge time of 5τ where τ is
the time constant in seconds and it is equal to the capacitance (in Farads) times the resistor
(in Ohms). For example, having a 1 Farad Capacitor and a 47 Ohms resistor, the charging
time will be: T = 5τ = 5 (1 x 47) = 235s which is approximately 4 min.
When discharging the resistor also serves as current limiter in case of a short circuit
between the output and ground.
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Figure 4.1: Resulting circuit when no input voltage is present.
Figure 4.2 shows an example of the discharging curve with the circuit proposed in figure 4.0.
First the input voltage is present and at some point the input is switched off. Since the
super-capacitor is connected to the output (3.3 V), the output voltage starts to decay
immediately. Assuming that the application cannot work properly with a voltage below 1.65 V,
the elapsed working time will be the time when Vout = 1.65 – time of input switched off.
Figure 4.2: Super-capacitor discharge graph when connected to the regulator output.
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AN706-00055-v11-E
7.3.2
Fixed output voltage
In some applications it is desired to maintain as long as possible the output voltage, for
example when using an LCD.
To obtain a fixed output voltage from a super-capacitor it is highly recommended to have a
good LDO regulator, this means with a very low quiescent current and also very low
input–output differential voltage. A good LDO regulator is important for one simple reason:
The supper-capacitor will be also powering the voltage regulator.
Figure 4.3 shows a proposed circuit using the LT1763S8-3.3 from (Quiescent Current of 30
µA and Dropout Voltage of 300 mV). Here one thing needs to be considered: The input LED.
If it remains connected, it will also consume power from the super-capacitor. Hence there is
need for a jumper (JP1) to disconnect the LED.
Figure 4.3: Super-capacitor connected at the input of the LDO regulator.
Also with the LT1763S8-3.3 it is possible to place the super-capacitor (and series resistor) at
the output without any additional diodes. This is possible because the quiescent current
drops to 0.1µA in shutdown (for more information check the LT1763 datasheet).
In figure 4.4 the two “stages” of the discharge of the super-capacitor can be seen: The first
stage when the output voltage remains at 3.3V because the capacitor is charged at 5V and
the second stage, similar to the previous, when the output voltage starts to decay.
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Figure 4.4: Super-capacitor discharge graph when connected to the regulator input.
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8
Energy Harvester
Selection of several energy harvesters according to the application
Especially for low power systems energy harvesters are helping to supply energy without
battery or accumulator. Harvesters can be piezoelectric, electro-mechanical, thermal, solar,
electric field and so on. The main problem: Energy harvesters do not operate at the
microcontroller’s operation voltage and current. There are three different cases:
1.) High voltage and low current
2.) High current and low voltage
3.) Wide voltage and current range
For case 1 an energy efficient step-down converter is needed, while for case 2 an energy
efficient step-up converter is needed. For case 3 there is mostly an energy efficient step-up
converter needed while for higher voltages an energy efficient low drop regulator is needed.
In some cases energy is created very shortly, so energy must be stored. At the end in most
energy harvesting applications transformers are needed to convert and store the generated
energy.
For this use cases several manufacturers offering one chip solutions with some external
components.
See following list of energy harvester:
Manufacturer
Piezo
Solar
Field
Product
Linear
Electric
Yes
Yes
Peltier
Vin min
Vin max
Element
Vout
Vout
Iout
min
max
max
Yes
Yes
(2.5V)
18V
1.8V
3.6V
100mA
Yes
Yes
0.25V
5V
1.5V
5.25V
400mA
1.5V
5.5V
2.5V
10V
30mA
0.5V
See
2.35V
5V
2.35V
5V
LTC3588
Linear
LTC3105
Linear
Yes
LTC3459
Linear
Yes
Yes
LTC3108
Linear
datasheet
Yes
Yes
0.5V
LTC3109
See
datasheet
30
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8.1
Piezo
In this case one or two piezo crystals are generating high voltage energy.
If a piezo is fast compressed, a short high voltage pulse with low current is generated. For
Example: This can be found at some cigarette lighters to fire the gas.
piezo
Vout+/Vout-/+
A second method is to use 2 piezo elements with a mass connected. If the mass vibrates,
the two piezo elements are generating energy.
mass
Vout+/-
piezo
Vout-/+
piezo
At Linear Technologies in the datasheet of LTC3588 can be found following schematic:
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8.2
Electric Field
This harvester uses some plates as electrodes and using the electric noise for energy
harvesting. Here a very high voltage with a very low current must be transformed into a low
voltage with higher current.
At Linear Technologies in the datasheet of LTC3588 can be found following schematic:
8.3
Solar Panel
Solar panels offering a wide voltage range from a few mV up to 20 Volts. An energy
harvesting circuit must operate in a wide voltage range.
At Linear Technologies in the datasheet of LTC3588 can be found following schematic:
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AN706-00055-v11-E
8.4
Thermoelectric
For harvesting energy via temperature, different temperatures are required. Two metals
between a hot and a cold side are generating a current flow.
At Linear Technologies in the datasheet of LTC3588 can be found following schematic:
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9
Conclusions
To make a robust and reliable low power system there are many things to be considered as
shown in this document; starting with the design of the voltage regulator circuit and followed
by the operating mode of the microcontroller, which also includes choosing the right clock
source for the desired application.
There is no general rule or a specific design that fits all applications requirements. A
thorough study of the application must be made in order to determine the optimal power
saving parameters.
The intention of this application note is to offer some guidelines to achieve the best
low-power design.
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Appendix: Comparison table of clock operation states in all modes.
Modes / Source Clocks
Sub
Sub
Low-speed
High-speed
Main
PLL
AHB and APB0
APB1 and APB2
CPU
clock
CR clock
CR clock
clock
clock
Bus clock
Bus clock
clock
Operating
Stopped
Stopped
Stopped
Low-speed CR
Run
mode
Main
MOSCE*1
Operating
High-speed CR
SOSCE*
1
Operating
PLL
Sub
Stopped
1
Stopped
mode
Main
MOSCE*1
Operating
High-speed CR
SOSCE*
1
Operating
PLL
Sub
Stopped
Low-speed CR
Low-speed CR*2
High-speed CR
High-speed CR*2
Operating
PLL
PLL*2
Stopped
Sub
Sub*2
Low-speed CR
Low-speed CR*2
High-speed CR
High-speed CR*2
PLLE*1
1
Operating
Stopped
Stopped
Timer
mode
Operating
High-speed CR
MOSCE*1
PLLE*1
Main
SOSCE*
1
Operating
Main*
PLL
PLL*2
Stopped
Operating
MOSCE*1
PLL
Operating
RTC mode and
Deep RTC mode
Operating
Stopped
STOP mode and
Deep Stop mode
2
Main
Low-speed CR
Stopped
*1: SOSCE, MOSCE and PLLE are the enable bits for the Sub, Main and PLL oscillators of the SCM_CTL register.
*2: Bus clock can be enabled or disabled by the APBC1EN or APBC2EN bit of the APBC1_PSR and APBC2_PSR register.
Operating
2
Main*
Operating
MOSCE*
Operating
Sub*
Main
Low-speed CR
Sleep
Sub
Operating
MOSCE*
Operating
PLLE*1
2
Stopped