DS07-13753-3E

The following document contains information on Cypress products.
FUJITSU MICROELECTRONICS
DATA SHEET
DS07-13753-3E
16-bit Microcontrollers
CMOS
F2MC-16LX MB90990 Series
MB90F997JBS/F997MBS/
MB90V950AJAS/V950AMAS
■ DESCRIPTION
The MB90990-series, loaded 1 channel FULL-CAN interface and Flash ROM, is general-purpose FUJITSU
16-bit microcontroller designing for automotive and industrial applications. Its main feature is the on-board CAN
Interfaces, which conform to Ver 2.0 Part A and Part B, while supporting a very flexible message buffer scheme
and so offering more functions than a normal FULL-CAN approach. With the new 0.18 μm CMOS technology,
Fujitsu now offers on-chip Flash ROM program memory up to 128 Kbytes.
The power supply (1.8 V) is supplied to the MCU core from an internal regulator circuit. This creates a major
advantage in terms of EMI and power consumption.
The internal PLL clock frequency multiplier provides an internal 31.25 ns instruction execution time from an
external 4 MHz clock. Also, the main clock can be monitored using the clock supervisor function.
The unit features a 4-channel input capture unit 1 channel 16-bit free-run timer, 2-channel LIN-UART,1 channel
UART, and 16-channel 8/10-bit A/D converter as the peripheral resource.
Note : F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
For the information for microcontroller supports, see the following web site.
http://edevice.fujitsu.com/micom/en-support/
Copyright©2008-2009 FUJITSU MICROELECTRONICS LIMITED All rights reserved
2009.6
MB90990 Series
■ FEATURES
• Clock
• Built-in PLL clock frequency multiplication circuit
• Selection of machine clocks (PLL clocks) is allowed among frequency division by 2 on oscillation clock and
multiplication of 1 to 8 times of oscillation clock (for 4 MHz oscillation clock, 4 MHz to 32 MHz)
• Minimum execution time of instruction : 31.25 ns (when operating with 4-MHz oscillation clock and 8-time
multiplied PLL clock)
• Clock supervisor (only for devices with J-suffix)
• Main clock is monitored
• Internal CR oscillation clock (100 kHz typical) can be used as sub clock
• 16 Mbytes CPU memory space
24-bit internal addressing
• Instruction system best suited to controller
• Wide choice of data types (bit, byte, word, and long word)
• Wide choice of addressing modes (23 types)
• Enhanced multiply-divide instructions with sign and RETI instructions
• Enhanced high-precision computing with 32-bit accumulator
• Instruction system compatible with high-level language (C language) and multitask
• Employing system stack pointer
• Enhanced various pointer indirect instructions
• Barrel shift instructions
• Increased processing speed
4-byte instruction queue
• Powerful interrupt function
• Powerful 8-level, 34-condition interrupt feature
• 8 channels external interrupts are supported
• CPU-independent automatic data transfer function
Expanded intelligent I/O service function (EI2OS) : up to 16 channels
• Low power consumption (standby) mode
Sleep mode (a mode that halts CPU operating clock)
• Timebase timer mode
• Main timer mode (timebase timer mode that is transferred from main clock mode)
• PLL timer mode (timebase timer mode that is transferred from PLL clock mode)
• Watch mode (a mode that operates sub clock and watch timer only)
• Stop mode (a mode that stops oscillation clock and sub clock)
• CPU blocking operation mode
• Process
CMOS technology
• I/O port
General purpose input/output port (CMOS output) :36 ports
(Continued)
2
DS07-13753-3E
MB90990 Series
(Continued)
• Timer
• Timebase timer, watch timer, watchdog timer : 1 channel
• 8/16-bit PPG timer : 8-bit × 6 channels or 16-bit × 3 channels
• 16-bit reload timer : 2 channels
• 16- bit input/output timer
- 16-bit free-run timer : 1 channel (FRT0 : ICU 0/1/2/3)
- 16- bit input capture : (ICU) : 4 channels
• FULL-CAN interface : 1 channel
• Compliant with CAN specifications Version 2.0 A and B
• 16 message buffers are built in
• CAN wake-up function
• UART (LIN/SCI) : LIN-UART × 2 channels, UART × 1 channel
• Equipped with full-duplex double buffer
• Clock-asynchronous or clock-synchronous serial transmission is available
• DTP/External interrupt : up to 8 channels, CAN wakeup : up to 1 channel
Module for activation of expanded intelligent I/O service (EI2OS) and generation of external interrupt by external
input
• Delay interrupt generator module
Generates interrupt request for task switching
• 8/10-bit A/D converter : 16 channels
• Resolution is selectable between 8-bit and 10-bit
• Activation by external trigger input is allowed
• Conversion time : 3 μs (at 32-MHz machine clock, including sampling time)
• Program patch function
Address matching detection for 6 address pointers
• Low voltage/CPU operation detection reset (devices with J-suffix)
• Detects low voltage (Set the voltage 2.8 V to 4.2 V.) and resets automatically
• Resets automatically when program is runaway and counter is not cleared within interval time
(Set in the programming approx.16.4 ms to approx.524 ms for external 4 MHz operation.)
• Clock calibration unit (products with J-suffix)
Capable of improving precision of CR oscillation circuit by calculating calibration value from measurement and
performing trimming.
• Capable of changing input voltage for port
Automotive/CMOS-Schmitt input level (initial level is Automotive in single-chip mode)
• Flash memory security function
Protects the content of Flash memory
• 8-bit D/A converter : 1 channel
DS07-13753-3E
3
MB90990 Series
■ PRODUCT LINEUP
Part number
MB90V950AMAS
MB90V950AJAS
MB90F997JBS
MB90F997MBS
Parameter
Type
Evaluation product
Flash memory product
2
F MC-16LX CPU
CPU
System clock
On-chip PLL clock multiplier (×1, ×2, ×3, ×4, ×6, ×8, 1/2 when PLL stops)
Minimum instruction execution time : 31.25 ns (Oscillation clock 4 MHz PLL ×8)
Main
128 Kbytes
Satellite 32 Kbytes
ROM
External
RAM
30 Kbytes
8 Kbytes
Yes
⎯
Rev 050617
⎯
MB2147-20 Rev.04C or later
⎯
Emulator-specific
power supply*1
FPGA data*2
Adaptor board*2
Clock supervisor
No
Yes
Yes
No
Clock calibration
unit
No
Yes
Yes
No
No
Yes
(Corresponds to CPU
operation detection
reset only)
Yes
No
Low-voltage/CPU
operation detection
reset
0.35 μm CMOS with
built-in power supply regulator
0.18 μm CMOS with
built-in power supply regulator +
Flash memory with charge pump for
programming voltage
Operation voltage
range
5 V ± 10 %
3.0 V to 5.5 V : When normal operating
Operation ambient
temperature
⎯
−40 °C to +105 °C
PGA-299
LQFP-48
7 channels
LIN-UART × 2 channels, UART × 1 channel
Technology
Package
UART
I2C (400 kbps)
A/D converter
16-bit
Reload timer
Wide range of baud rate settings using a dedicated reload timer
Special synchronous options for adapting to different synchronous serial protocols
LIN functionality working either as master or slave LIN device (Supported by LIN-UART only)
2 channels
⎯
24 channels
16 channels
10-bit or 8-bit resolution
Conversion time : Min 3 μs include sample time (per one channel)
4 channels
2 channels
Operation clock frequency : fsys/2 , fsys/2 , fsys/2 (fsys = Machine clock frequency)
Supports External Event Count function
1
3
5
(Continued)
4
DS07-13753-3E
MB90990 Series
Part number
MB90V950AMAS
MB90V950AJAS
MB90F997JBS
MB90F997MBS
Parameter
2 channels
16-bit
I/O timer
1 channel
Generates an interrupt signal on overflow
Operation clock freq. :
fsys, fsys/21, fsys/22, fsys/23, fsys/24, fsys/25, fsys/26, fsys/27 (fsys = Machine clock freq.)
I/O Timer 0 (clock input FRCK0) corresponds to ICU0/1/2/3, OCU 0/1/2/3
I/O Timer 1 (clock input FRCK1) corresponds to ICU4/5/6/7, OCU 4/5/6/7
⎯
8 channels
16-bit
Output compare
16-bit
Input capture
8/16-bit
PPG
Generates an interrupt signal when one of the 16-bit I/O timer matches the output compare
register
A pair of compare registers can be used to generate an output signal.
8 channels
4 channels
Rising edge, falling edge or rising & falling edge sensitive
Signals an interrupt upon external event
8 channels (16-bit) /16 channels (8-bit)
Sixteen 8-bit reload counters
Sixteen 8-bit reload registers for L pulse width
Sixteen 8-bit reload registers for H pulse width
3 channels (16-bit) /6 channels (8-bit)
Six 8-bit reload counters
Six 8-bit reload registers for L pulse width
Six 8-bit reload registers for H pulse width
Supports 8-bit and 16-bit operation modes
A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as
8-bit prescaler plus 8-bit reload counter
Operating clock freq. : fsys, fsys/21, fsys/22, fsys/23, fsys/24 or 128 [email protected] = 4 MHz
(fsys = Machine clock frequency, fosc = Oscillation clock frequency)
3 channels
CAN
Interface
External interrupt
(8 channels)
Conforms to CAN Specification Version 2.0 Part A and B
Automatic re-transmission in case of error
Automatic transmission in response to Remote Frames
Prioritized 16 message buffers for data and ID’s
Supports multiple messages
Flexible configuration of acceptance filtering :
Full bit compare/Full bit mask/Two partial bit masks
Supports up to 1 Mbps
Can be used rising edge, falling edge, starting up by H/L level input, external interrupt,
expanded intelligent I/O services (EI2OS)
D/A Converter
Sub clock
1 channel
2 channels
No
1 channel
Yes
Yes
No
(Continued)
DS07-13753-3E
5
MB90990 Series
(Continued)
Part number
MB90V950AMAS
MB90V950AJAS
MB90F997JBS
MB90F997MBS
Parameter
I/O Ports
Virtually all external pins can be used as general purpose I/O port
All ports are push-pull outputs
Bit-wise settable as input/output or peripheral signal
Can be configured 8 as CMOS schmitt trigger/ automotive inputs (in blocks of 8 pins)
TTL input level settable for external bus (32-pin only for external bus)
Flash memory
(Flash memory
product only)
Supports automatic programming, Embedded Algorithm
Write/Erase/Erase-Suspend/Resume commands
A flag indicating completion of the algorithm
Boot block configuration
Erase can be performed on each block
Flash Security
*1: It is setting of Jumper switch (TOOL VCC) when emulator (MB2147-01) is used. Please refer to the Emulator
hardware manual for the details.
*2: Customers considering the use of other FPGA data and the adaptor boards should consult with sales representatives.
6
DS07-13753-3E
MB90990 Series
■ PIN ASSIGNMENT
• MB90F997MBS, MB90F997JBS
P43/TX1
P86/SOT1
P87/SCK1
P85/SIN1
39
38
37
P84/SCK0/INT15R
43
40
P82/SIN0/INT14R/TIN2
44
P83/SOT0/TOT2
P44/FRCK0
45
P42/RX1/INT9R
P40
46
41
P41
47
42
AVss
48
(TOP VIEW)
AVcc
1
36
P20 *
AVR
2
35
P21/PPGB(A) *
P60/AN0
3
34
P22/PPGD(C) *
P61/AN1
4
33
P23/PPGF(E) *
P62/AN2
5
32
P24/IN0
P63/AN3
6
31
P25/IN1
30
P26/IN2
LQFP-48
20
21
22
23
24
MD2
MD1
MD0
RST
Vcc
Vss
P57/AN15/INT13
C
25
19
26
12
18
11
P50/AN8/SIN2
P56/AN14/INT11/DA0
P80/ADTG/INT12R
P55/AN13/INT10
X0
17
27
16
10
P54/AN12/TOT3/INT8
X1
P67/AN7/PPGE(F)
15
P66/AN6/PPGC(D)
28
14
P27/IN3
9
P53/AN11/TIN3
29
P52/AN10/SCK2
8
13
P65/AN5/PPGA(B)
P51/AN9/SOT2
P64/AN4
7
(FPT-48P-M26)
* : High current output port
DS07-13753-3E
7
MB90990 Series
■ PIN DESCRIPTION
Pin No.
Pin name
I/O circuit
type*
1
AVCC
I
2
AVR
⎯
3 to 7
P60 to P64
AN0 to AN4
H
P65 to P67
PPGA (B) ,
PPGC (D) ,
PPGE (F)
ADTG
13
General-purpose I/O port.
F
General-purpose I/O port.
L
16
17
Analog input pin for A/D converter.
SIN2
Serial data input pin for UART2.
P51
General-purpose I/O port.
AN9
H
AN10
Analog input pin for A/D converter.
Serial data output pin for UART2.
P52
15
Trigger input pin for A/D converter.
External interrupt request input pin for INT12R.
SOT2
14
Analog input pins for A/D converter.
Output pins for PPG.
P50
AN8
General-purpose I/O ports.
Analog input pins for A/D converter.
INT12R
12
Power (Vref+) input pin for A/D converter.
It should be below VCC.
H
P80
11
VCC power input pin for analog circuit.
General-purpose I/O ports.
AN5 to AN7
8 to 10
Function
General-purpose I/O port.
H
Analog input pin for A/D converter.
SCK2
Clock I/O pin for UART2.
P53
General-purpose I/O port.
AN11
H
Analog input pin for A/D converter.
TIN3
Event input pin for reload timer 3.
P54
General-purpose I/O port.
AN12
TOT3
H
Analog input pin for A/D converter.
Output pin for reload timer 3.
INT8
External interrupt request input pin for INT8.
P55
General-purpose I/O port.
AN13
INT10
H
Analog input pin for A/D converter.
External interrupt request input pin for INT10.
(Continued)
8
DS07-13753-3E
MB90990 Series
Pin No.
Pin name
I/O circuit
type*
P56
AN14
18
INT11
Function
General-purpose I/O port.
M
Analog input pin for A/D converter.
External interrupt request input pin for INT11.
DA0
Analog output pin for D/A converter.
P57
General-purpose I/O port.
(Different I/O circuit type from those in MB90V950AJAS,
MB90V950AMAS).
19
H
AN15
Analog input pin for A/D converter.
INT13
External interrupt request input pin for INT13.
20
MD2
D
Input pin for operation mode specification.
21, 22
MD1,
MD0
C
Input pins for operation mode specification.
23
RST
E
Reset input pin.
24
VCC
⎯
Power input pin (3.5 V to 5.5 V) .
25
VSS
⎯
Power input pin (0 V) .
26
C
I
27
X0
28
X1
29 to 32
P27 to P24
A
G
Power supply stabilization capacitor pin. It should be connected to a higher than or equal to 0.1 μF ceramic condenser.
Oscillation input pin.
Oscillation output pin.
General-purpose I/O ports.
The register can be set to select whether to use a pull-up resistor. This
function is enabled in single-chip mode.
IN3 to IN0
Event input pins for input capture 0 to 3.
P23 to P21
General-purpose I/O ports.
The register can be set to select whether to use a pull-up resistor. This
function is enabled in single-chip mode.
High current output port.
(Different I/O circuit type from those in
MB90V950AJAS,MB90V950AMAS).
33 to 35
J
PPGF (E) ,
PPGD (C) ,
PPGB(A)
36
37
38
P20
P85
SIN1
P87
SCK1
Output pins for PPG.
J
K
F
General-purpose I/O port.
The register can be set to select whether to use a pull-up
resistor. This function is enabled in single-chip mode.
High current output port.
(Different I/O circuit type from those in
MB90V950AJAS,MB90V950AMAS).
General-purpose I/O port.
Serial data input pin for UART1.
General-purpose I/O port.
Clock I/O pin for UART1.
(Continued)
DS07-13753-3E
9
MB90990 Series
(Continued)
Pin No.
39
40
Pin name
P86
SOT1
P43
TX1
I/O circuit
type*
F
F
P42
41
RX1
F
F
F
45
INT14R
Serial data output pin for UART0.
Clock I/O pin for UART0.
External interrupt request input pin for INT15R.
P82
SIN0
RX input pin for CAN1 interface.
General-purpose I/O port.
INT15R
44
TX output pin for CAN1 interface.
Output pin for reload timer 2.
P84
SCK0
General-purpose I/O port.
General-purpose I/O port.
TOT2
43
Serial data output pin for UART1.
External interrupt request input pin for INT9R.
P83
SOT0
General-purpose I/O port.
General-purpose I/O port.
INT9R
42
Function
General-purpose I/O port.
K
Serial data input pin for UART0.
External interrupt request input pin for INT14R.
TIN2
Event input pin for reload timer 2.
P44
General-purpose I/O port
(Different I/O circuit type from those in MB90V950AJAS,
MB90V950AMAS) .
F
FRCK0
Free-run timer 0 clock input pin.
46, 47
P40, P41
F
General-purpose I/O ports.
48
AVSS
I
VSS power input pin for analog circuit.
* : For the I/O circuit type, refer to “■ I/O CIRCUIT TYPE”.
10
DS07-13753-3E
MB90990 Series
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
A
X1
Oscillation circuit :
High-speed oscillation feedback resistor =
approx. 1 MΩ
(Flash memory product)
Xout
X0
Standby control signal
X1
Oscillation circuit :
High-speed oscillation feedback resistor =
approx. 1 MΩ
(Evaluation product)
Xout
X0
Standby control signal
B
X1A
Oscillation circuit :
Low-speed oscillation feedback resistor =
approx. 10 MΩ
Xout
X0A
Standby control signal
C
CMOS hysteresis
inputs
• Evaluation product :
CMOS hysteresis input
• Flash memory product
CMOS input
CMOS hysteresis
inputs
• Evaluation product :
CMOS hysteresis input
• Flash memory product
- CMOS input
- No Pull-down
R
D
R
Pull-down
resistor
E
CMOS hysteresis input
Pull-up
resistor
R
CMOS hysteresis
inputs
(Continued)
DS07-13753-3E
11
MB90990 Series
Type
Circuit
F
P-ch
Pout
N-ch
Nout
R
CMOS hysteresis inputs
Remarks
• CMOS level output
(IOL = 4 mA, IOH = − 4 mA)
• CMOS hysteresis inputs
(VIH 0.8Vcc VIL 0.2Vcc)
(With the standby-time input shutdown
function)
• Automotive input (With the
standby-time input shutdown function)
Automotive inputs
Standby control for
input shutdown
G
Pull-up control
Pull-up
resistor
P-ch
P-ch
Pout
N-ch
Nout
R
• CMOS level output
(IOL = 4 mA, IOH = − 4 mA)
• CMOS hysteresis inputs
(VIH 0.8Vcc VIL 0.2Vcc)
(With the standby-time input shutdown
function)
• Automotive input (With the
standby-time input shutdown function)
CMOS hysteresis inputs
Automotive inputs
Standby control for
input shutdown
H
P-ch
Pout
N-ch
Nout
R
CMOS hysteresis inputs
• CMOS level output
(IOL = 4 mA, IOH = − 4 mA)
• CMOS hysteresis inputs
(VIH 0.8Vcc VIL 0.2Vcc)
(With the standby-time input shutdown
function)
• Automotive input (With the
standby-time input shutdown function)
• A/D analog input
Automotive inputs
Standby control for
input shutdown
Analog input
(Continued)
12
DS07-13753-3E
MB90990 Series
Type
Circuit
I
Remarks
Protection circuit for power supply input
P-ch
N-ch
J
Pull-up control
Pull-up
resistor
P-ch
P-ch
Pout high current output
N-ch
Nout high current output
R
• CMOS level output
(IOL = 20 mA, IOH = − 14 mA)
(MB90V950 IOL = 4 mA, IOH = − 4 mA)
• CMOS hysteresis inputs
(VIH 0.8Vcc VIL 0.2Vcc)
(With the standby-time input shutdown
function)
• Automotive input (With the standbytime input shutdown function)
CMOS hysteresis inputs
Automotive inputs
Standby control for
input shutdown
K
P-ch
N-ch
Pout
Nout
R
CMOS hysteresis inputs
Automotive input
CMOS hysteresis
inputs
• CMOS level output
(IOL = 4 mA, IOH = − 4 mA)
• CMOS hysteresis inputs
(VIH 0.7Vcc VIL 0.3Vcc)
(With standby-time input shutdown
function)
• Automotive input (With standby-time
input shutdown function)
• CMOS hysteresis inputs
(VIH 0.8Vcc VIL 0.2Vcc)
(With the standby-time input shutdown
function)
Standby control for
input shutdown
(Continued)
DS07-13753-3E
13
MB90990 Series
(Continued)
Type
Circuit
Remarks
L
P-ch
N-ch
Pout
Nout
R
CMOS hysteresis
inputs
Automotive input
CMOS hysteresis
inputs
Standby control for
input shutdown
Analog input
M
P-ch
N-ch
Pout
Nout
R
CMOS hysteresis
inputs
Automotive input
Standby control for
input shutdown
Analog input
• CMOS level output
(IOL = 4 mA, IOH = − 4 mA)
• CMOS hysteresis inputs
(VIH 0.8Vcc VIL 0.2Vcc)
(With the standby-time input shutdown
function)
• Automotive input
(With the standby-time input shutdown
function)
• CMOS hysteresis inputs
(VIH 0.7Vcc VIL 0.3Vcc)
(With the standby-time input shutdown
function)
• A/D analog input
• CMOS level output
(IOL = 4 mA, IOH = − 4 mA)
• CMOS hysteresis inputs
(VIH 0.8Vcc VIL 0.2Vcc)
(With the standby-time input shutdown
function)
• Automotive input
(With the standby-time input shutdown
function)
• A/D analog input
• D/A analog output
Analog output
14
DS07-13753-3E
MB90990 Series
■ HANDLING DEVICES
• Preventing latch-up
CMOS IC chips may suffer latch-up under the following conditions :
• A voltage higher than VCC pin or lower than VSS pin is applied to an input or output pin.
• A voltage higher than the rated voltage is applied between VCC pin and VSS pin.
• The AVCC power supply is applied before the VCC voltage.
Latch-up may increase the power supply current drastically, causing thermal damage to the device.
Use meticulous care not to exceed the rating.
For the same reason, also be careful not to let the analog power-supply voltage (AVCC, AVR) exceed the digital
power-supply voltage.
• Treatment of unused pins
Leaving unused input pins open may result in permanent damage of the device due to misbehavior or latch-up.
Therefore, they must be pulled up or pulled down through resistors. In this case, those resistors should be more
than 2 kΩ.
Unused bidirectional pins should be set to the output state and can be left open, or the input state with the above
described connection.
• Using external clock
The high-speed oscillator pins (X0, X1) can not be used for external clock inputs.
• Notes on during operation of PLL clock mode
On this microcontroller, if in case the crystal oscillator breaks off or an external reference clock input stops while
the PLL clock mode is selected, a self-oscillator circuit contained in the PLL may continue its operation at its
self-running frequency. However, Fujitsu will not guarantee results of operations if such failure occurs.
• Power supply pins (VCC/VSS)
• If there are multiple VCC and VSS pins, from the point of view of device design, pins to be of the same potential
are connected the inside of the device to prevent malfunction such as latch-up.
To reduce unnecessary radiation, prevent malfunctioning of the strobe signal due to the rise of ground level,
and observe the standard for total output current, be sure to connect the VCC and VSS pins to the power supply
and ground externally.
• Connect VCC and VSS pins to the device from the current supply source at a low impedance.
DS07-13753-3E
15
MB90990 Series
• As a measure against power supply noise, connect a capacitor of about 0.1 μF as a bypass capacitor between
VCC pin and VSS pin in the vicinity of VCC and VSS pins of the device.
VCC
VSS
VCC
VSS
VSS
VCC
MB90990
Series
VCC
VSS
VSS
VCC
• Pull-up/down resistors
The MB90990 series does not support internal pull-up/down resistors (Port 2 : built-in pull-up resistors) . Use
external components where needed.
• Crystal oscillator circuit
Noises around X0 or X1 pins may be possible causes of malfunctions. Make sure to provide bypass capacitors
via shortest distance from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and make sure,
that lines of oscillation circuit do not cross the lines of other circuits.
It is highly recommended to provide a printed circuit board artwork surrounding X0 and X1 pins with a ground
area for stabilizing the operation. Please ask the crystal maker to evaluate the oscillational characteristics of the
crystal and this device.
• Turning-on sequence of power supply to A/D converter and analog inputs
Make sure to turn on the A/D converter power supply (AVCC and AVR) and analog inputs (AN0 to AN15) after
turning-on the digital power supply (VCC) .
Turn-off the digital power after turning off the A/D converter power supply and analog inputs. In this case, make
sure that the voltage does not exceed AVRH or AVCC.
• Connection of unused pins of A/D converter if A/D converter is not used
Connect unused pins of A/D converter to AVCC = VCC, AVSS = AVR = VSS.
• Notes on energization
To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at
50 μs or more (0.2 V to 2.7 V) .
• Stabilization of power supply voltage
A sudden change in the power supply voltage may cause the device to malfunction even within the specified
VCC power supply voltage operating guarantee range. Therefore, the VCC power supply voltage should be
stabilized.
For reference, the power supply voltage should be controlled so that VCC ripple variations (peak-to-peak value)
at commercial frequencies (50 Hz/60 Hz) fall below 10% of the standard VCC power supply voltage and the
coefficient of transient fluctuation does not exceed 0.1 V/ms at instantaneous power switching.
16
DS07-13753-3E
MB90990 Series
• Initialization
In the device, there are internal registers which are initialized only by a power-on reset. To initialize these registers,
turn on the power again.
• Notes on using CAN function
To use CAN function, please set “1” to DIRECT bit of CAN direct mode register (CDMR) .
If DIRECT bit is set to “0” (initial value) , wait states will be performed when accessing CAN registers.
Note : Please refer to Hardware Manual of “MB90990 series for detail of CAN Direct Mode Register”.
• Flash security function
The security bit is located in the area of the Flash memory.
If protection code 01H is written in the security bit, the Flash memory is in the protected state by security.
Therefore, please do not write 01H in this address if you do not use the security function.
Please refer to following table for the address of the security bit.
MB90F997
Flash memory size
Address for security bit
Embedded 1 Mbit Flash Memory
FE0001H
• Correspondence with TA = +105 °C or more
If used exceeding TA = +105 °C, please consult with us due to the restricted reliability.
It is ensured to write/erase data to the Flash memory between TA = − 40 °C and +105 °C.
DS07-13753-3E
17
MB90990 Series
■ BLOCK DIAGRAMS
• MB90V950AMAS
X0, X1
Clock
controller
F2MC-16LX
core
RST
16-bit
free-run
timer 0
Input
capture
8 channels
RAM
30 Kbytes
Output
compare
8 channels
16-bit
free-run
timer 1
Prescaler
(5 channels)
AVCC
AVSS
AN23 to AN0
AVRH
AVRL
ADTG
UART
7 channels
8/10-bit
A/D
converter
24 channels
Internal data bus
SOT6 to SOT0
SCK6 to SCK0
SIN6 to SIN0
FRCK0
IN7 to IN0
OUT7 to OUT0
FRCK1
CAN
controller
3 channels
RX2 to RX0
TX2 to TX0
16-bit
reload timer
4 channels
TIN3 to TIN0
TOT3 to TOT0
AD15 to AD00
A23 to A16
ALE
DA01, DA00
PPGF to PPG0
SDA1, SDA0
SCL1, SCL0
8-bit
D/A converter
2 channels
I2C
interface
2 channels
RD
WRL
WRH
HRQ
HAK
RDY
CLK
8/16-bit
PPG
16 channels
DMA
18
External
bus
DTP/
External
interrupt
INT15 to INT8
(INT15R to INT8R)
INT7 to INT0
Clock
monitor
CKOT
DS07-13753-3E
MB90990 Series
• MB90V950AJAS
X0, X1
Clock
controller/
monitor
RST
F2MC-16LX
Core
Clock
calibration unit
CR oscillation
circuit
16-bit
free-run
timer 0
Input
capture
8 channels
CPU
operation detection
RAM
30 Kbytes
Output
compare
8 channels
16-bit
free-run
timer 1
Prescaler
(5 channels)
AVCC
AVSS
AN23 to AN0
AVRH
AVRL
ADTG
UART
7 channels
8/10-bit
A/D
converter
24 channels
Internal data bus
SOT6 to SOT0
SCK6 to SCK0
SIN6 to SIN0
FRCK0
IN7 to IN0
OUT7 to OUT0
FRCK1
CAN
controller
3 channels
RX2 to RX0
TX2 to TX0
16-bit
reload timer
4 channels
TIN3 to TIN0
TOT3 to TOT0
AD15 to AD00
A23 to A16
ALE
DA01, DA00
PPGF to PPG0
SDA1, SDA0
SCL1, SCL0
8-bit
D/A converter
2 channels
I2C
interface
2 channels
RD
WRL
WRH
HRQ
HAK
RDY
CLK
8/16-bit
PPG
16 channels
DMA
DS07-13753-3E
External
bus
DTP/
External
interrupt
INT15 to INT8
(INT15R to INT8R)
INT7 to INT0
Clock
monitor
CKOT
19
MB90990 Series
• MB90F997JBS, MB90F997MBS
X0, X1
Clock
control
RST
F2MC-16LX
Core
Clock
calibration unit*
CR oscillation
circuit*
Input
capture
4 channels
Low voltage detection*
CPU operation detection*
RAM
Satellite
Flash
Prescaler
3 channels
SOT0 to SOT2
SCK0 to SCK2
SIN0 to SIN2
AVCC
AVSS
DA0
AVCC
AVSS
AN0 to AN15
AVR
ADTG
PPGA(B), PPGB(A),
PPGF(E), PPGD(C),
PPGC(D), PPGE(F)
LIN-UART
2 channels
UART
1 channel
Internal data bus
Main
Flash
IN0 to IN3
16-bit
free-run
timer 0
FRCK0
CAN
controller
1 channel
RX1
TX1
16-bit
Reload
timer
2 channels
TIN2, TIN3
TOT2, TOT3
8-bit
D/A
converter
1 channel
8/10-bit
A/D
converter
16 channels
8/16-bit
PPG
3 channels
DTP/
External
interrupt
INT8, INT9R
INT10, INT11
INT12R, INT13
INT14R, INT15R
* : Only for devices with J-suffix
20
DS07-13753-3E
MB90990 Series
■ MEMORY MAP
MB90V950AJAS
MB90V950AMAS
FFFFFFH
FF0000H
FEFFFFH
FE0000H
FDFFFFH
FD0000H
FCFFFFH
FC0000H
FBFFFFH
FB0000H
FAFFFFH
FA0000H
F9FFFFH
F90000H
F8FFFFH
ROM (FF bank)
ROM (FE bank)
007900H
0078FFH
ROM (FF bank)
FF0000H
FEFFFFH
ROM (FE bank)
ROM (FD bank)
ROM (FC bank)
ROM (FB bank)
ROM (FA bank)
ROM (F9 bank)
F77FFFH
ROM (F8 bank)
F70000H
External access area
008000H
007FFFH
FFFFFFH
FE0000H
F80000H
00FFFFH
MB90F997JBS
MB90F997MBS
ROM
(image of FF bank)
Peripheral
RAM 30 Kbytes
010000H
00FFFFH
008000H
007FFFH
ROM
(Satellite)
ROM
(image of FF bank)
Peripheral
007900H
0020FFH
RAM 8 Kbytes
000100H
External access area
0000EFH
000000H
Peripheral
000100H
0000FFH
0000F0H
0000EFH
000000H
Peripheral
: Not accessible
Note : The high-order portion of bank 00 gives the image of the FF bank ROM to make the small model of the C
compiler effective. Since the low-order 16 bits are the same, the table in ROM can be referred without using
the far specification in the pointer declaration.
For example, an attempt to access 00C000H practically accesses the value at FFC000H in ROM.
The ROM area in bank FF exceeds 32 Kbytes, and its entire image cannot be shown in bank 00.
The image between FF8000H and FFFFFFH is visible in bank 00, while the image between FF0000H and
FF7FFFH is visible only in bank FF.
DS07-13753-3E
21
MB90990 Series
■ I/O MAP
Address
Register
Abbreviation
Access
Resource name
Initial value
R/W
Port 2
XXXXXXXXB
000000H,
000001H
Reserved
000002H Port 2 Data Register
PDR2
000003H
Reserved
000004H Port 4 Data Register
PDR4
R/W
Port 4
XXXXXXXXB
000005H Port 5 Data Register
PDR5
R/W
Port 5
XXXXXXXXB
000006H Port 6 Data Register
PDR6
R/W
Port 6
XXXXXXXXB
000007H
Reserved
000008H Port 8 Data Register
PDR8
R/W
Port 8
XXXXXXXXB
000009H,
00000AH
Reserved
00000BH Port 5 Analog Input Enable Register
ADER5
R/W
Port 5, A/D
11111111B
00000CH Port 6 Analog Input Enable Register
ADER6
R/W
Port 6, A/D
11111111B
00000DH
Reserved
00000EH Input Level Select Register
ILSR0
R/W
00000FH Input Level Select Register
ILSR1
R/W
000010H,
000011H
Reserved
000012H Port 2 Direction Register
DDR2
000013H
Reserved
000014H Port 4 Direction Register
Ports
XXXXXXXXB
XXXX0XXXB
R/W
Port 2
00000000B
DDR4
R/W
Port 4
00000000B
000015H Port 5 Direction Register
DDR5
R/W
Port 5
00000000B
000016H Port 6 Direction Register
DDR6
R/W
Port 6
00000000B
000017H
Reserved
000018H Port 8 Direction Register
DDR8
R/W
Port 8
00000000B
000019H
Reserved
W
Port A
00000111B
R/W
Port 2
00000000B
00001AH Port A Direction Register
00001BH
to
00001DH
00001EH Port 2 Pull-up Control Register
00001FH
DDRA
Reserved
PUCR2
Reserved
(Continued)
22
DS07-13753-3E
MB90990 Series
Abbreviation
Access
000020H Serial Mode Register 0
SMR0
W, R/W
00000000B
000021H Serial Control Register 0
SCR0
W, R/W
00000000B
000022H Reception/Transmission Data Register 0
RDR0/
TDR0
R/W
00000000B/
11111111B
000023H Serial Status Register 0
SSR0
R, R/W
ECCR0
R, W,
R/W
000025H Extended Status/Control Register 0
ESCR0
R/W
00000X00B
000026H Baud Rate Generator Register 00
BGR00
R/W, R
00000000B
000027H Baud Rate Generator Register 01
BGR01
R/W, R
00000000B
000028H Serial Mode Register 1
SMR1
W, R/W
00000000B
000029H Serial Control Register 1
SCR1
W, R/W
00000000B
00002AH Reception/Transmission Data Register 1
RDR1/
TDR1
R/W
00000000B/
11111111B
00002BH Serial Status Register 1
SSR1
R, R/W
ECCR1
R, W,
R/W
00002DH Extended Status/Control Register 1
ESCR1
R/W
00000X00B
00002EH Baud Rate Generator Register 10
BGR10
R/W, R
00000000B
00002FH Baud Rate Generator Register 11
BGR11
R/W, R
00000000B
Address
000024H
00002CH
Register
Extended Communication Control
Register 0
Extended Communication Control
Register 1
000030H
to
00003AH
Resource name
UART0
Initial value
00001000B
000000XXB
UART1
00001000B
000000XXB
Reserved
00003BH Address Detect Control Register 1
00003CH
to
000043H
PACSR1
R/W
Address Match
Detection 1
11000000B
Reserved
000044H PPGA Operation Mode Control Register
PPGCA
W, R/W
000045H PPGB Operation Mode Control Register
PPGCB
W, R/W
000046H PPGA/B Count Clock Select Register
PPGAB
R/W
00000010B
01000111B
16-bit PPG A/B
01000001B
Reserved
000047H
000048H PPG C Operation Mode Control Register
PPGCC
W, R/W
000049H PPG D Operation Mode Control Register
PPGCD
W, R/W
PPGCD
R/W
00004AH
01000111B
PPG C/PPG D Count Clock Select
Register
00004BH
16-bit PPG C/D
01000001B
00000010B
Reserved
(Continued)
DS07-13753-3E
23
MB90990 Series
Address
Register
Abbreviation
Access
00004CH
PPG E Operation Mode Control
Register
PPGCE
W, R/W
00004DH
PPG F Operation Mode Control
Register
PPGCF
W, R/W
00004EH
PPG E/PPG F Count Clock Select
Register
PPGEF
R/W
00004FH
Resource name
Initial value
01000111B
01000001B
16-bit PPG E/F
00000010B
Reserved
000050H Input Capture Control Status 0/1
ICS01
R/W
000051H Input Capture Edge 0/1
ICE01
R/W, R
000052H Input Capture Control Status 2/3
ICS23
R/W
000053H Input Capture Edge 2/3
ICE23
R
000054H
to
000063H
00000000B
Input Capture 0/1
111010XXB
00000000B
Input Capture 2/3
111111XXB
Reserved
000064H Timer Control Status 2
TMCSR2
R/W
000065H Timer Control Status 2
TMCSR2
R/W
000066H Timer Control Status 3
TMCSR3
R/W
000067H Timer Control Status 3
TMCSR3
R/W
000068H A/D Control Status 0
ADCS0
R/W
00011110B
000069H A/D Control Status 1
ADCS1
R/W, W
00000001B
00006AH A/D Data 0
ADCR0
R
00006BH A/D Data 1
ADCR1
R
00006CH A/D Converter Setting 0
ADSR0
R/W
00000000B
00006DH A/D Converter Setting 1
ADSR1
R/W
00000000B
LVRC
R/W, W
Low Voltage/CPU
Operation Detection
Reset
00111000B
ROMM
W
ROM Mirror
11111101B
00006EH
Low Voltage/CPU Operation
Detection Reset Control Register
00006FH ROM Mirror Function Select
16-bit Reload Timer 2
16-bit Reload Timer 3
A/D Converter
000070H
to
00007FH
Reserved
000080H
to
00008FH
Reserved for CAN Interface 1. Refer to “■ CAN CONTROLLERS”
000090H
to
00009DH
Reserved
00009EH Address Detect Control Register 0
PACSR0
R/W
Address Match
Detection 0
00000000B
11110000B
00000000B
11110000B
00000000B
11111100B
11000000B
(Continued)
24
DS07-13753-3E
MB90990 Series
Address
Register
00009FH Delayed Interrupt/Release Register
0000A0H
Low-power Consumption Mode
Control Register
0000A1H Clock Selection Register
0000A2H
to
0000A7H
Abbreviation
Access
Resource name
Initial value
DIRR
R/W
Delayed Interrupt
Generation module
11111110B
LPMCR
W, R/W
CKSCR
R, R/W
Low-Power
Consumption
Control Circuit
00011000B
11111100B
Reserved
0000A8H Watchdog Control Register
WDTC
R, W
Watchdog Timer
XXXXX111B
0000A9H Timebase Timer Control Register
TBTC
W, R/W
Timebase Timer
11100100B
0000AAH Watch Timer Control register
WTC
R, R/W
Watch Timer
1X001000B
Flash Memory
000X0000B
0000ABH
to
0000ADH
0000AEH
Reserved
Flash Control Status
(Flash Devices only.
Otherwise reserved)
0000AFH
FMCS
R, R/W
Reserved
0000B0H Interrupt Control Register 00
ICR00
W, R/W
00000111B
0000B1H Interrupt Control Register 01
ICR01
W, R/W
00000111B
0000B2H Interrupt Control Register 02
ICR02
W, R/W
00000111B
0000B3H Interrupt Control Register 03
ICR03
W, R/W
00000111B
0000B4H Interrupt Control Register 04
ICR04
W, R/W
00000111B
0000B5H Interrupt Control Register 05
ICR05
W, R/W
00000111B
0000B6H Interrupt Control Register 06
ICR06
W, R/W
00000111B
0000B7H Interrupt Control Register 07
ICR07
W, R/W
0000B8H Interrupt Control Register 08
ICR08
W, R/W
0000B9H Interrupt Control Register 09
ICR09
W, R/W
00000111B
0000BAH Interrupt Control Register 10
ICR10
W, R/W
00000111B
0000BBH Interrupt Control Register 11
ICR11
W, R/W
00000111B
0000BCH Interrupt Control Register 12
ICR12
W, R/W
00000111B
0000BDH Interrupt Control Register 13
ICR13
W, R/W
00000111B
0000BEH Interrupt Control Register 14
ICR14
W, R/W
00000111B
0000BFH Interrupt Control Register 15
ICR15
W, R/W
00000111B
0000C0H D/A Converter Data 0
DAT0
R/W
Interrupt Control
D/A
Converter
00000111B
00000111B
XXXXXXXXB
(Continued)
DS07-13753-3E
25
MB90990 Series
Address
Register
Abbreviation
Access
0000C2H D/A Control 0
0000C3H
to
0000C9H
DACR0
R/W
D/A
Converter
00000000B
Reserved
0000CAH External Interrupt Enable 1
ENIR1
R/W
0000CBH External Interrupt Source 1
EIRR1
R/W
ELVR1
R/W
0000CEH External Interrupt Source Select
EISSR
R/W
0000CFH PLL/Sub clock Control Register
PSCCR
W
0000CDH
Initial value
Reserved
0000C1H
0000CCH
Resource name
Detection Level Setting 1
0000D0H
to
0000D7H
00000000B
XXXXXXXXB
DTP/
External Interrupt
00000000B
00000000B
00000000B
PLL
11110000B
Reserved
0000D8H Serial Mode Register 2
SMR2
W, R/W
00000000B
0000D9H Serial Control Register 2
SCR2
W, R/W
00000000B
RDR2/
TDR2
R/W
00000000B/
11111111B
SSR2
R, R/W
ECCR2
R, W,
R/W
0000DDH Extended Status/Control Register 2
ESCR2
R/W
00000X00B
0000DEH Baud Rate Generator Register 20
BGR20
R/W, R
00000000B
0000DFH Baud Rate Generator Register 21
BGR21
R/W, R
00000000B
0000DAH
Reception/Transmission Data Register
2
0000DBH Serial Status Register 2
0000DCH
Extended Communication Control
Register 2
0000E0H
to
0000FFH
Reserved
007900H
to
007913H
Reserved
UART2
00001000B
000000XXB
007914H Reload Register LA
PRLLA
R/W
XXXXXXXXB
007915H Reload Register HA
PRLHA
R/W
007916H Reload Register LB
PRLLB
R/W
007917H Reload Register HB
PRLHB
R/W
XXXXXXXXB
007918H Reload Register LC
PRLLC
R/W
XXXXXXXXB
007919H Reload Register HC
PRLHC
R/W
00791AH Reload Register LD
PRLLD
R/W
00791BH Reload Register HD
PRLHD
R/W
16-bit PPG A/B
16-bit PPG C/D
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
(Continued)
26
DS07-13753-3E
MB90990 Series
Abbreviation
Access
00791CH Reload Register LE
PRLLE
R/W
00791DH Reload Register HE
PRLHE
R/W
00791EH Reload Register LF
PRLLF
R/W
00791FH Reload Register HF
PRLHF
R/W
XXXXXXXXB
007920H Input Capture 0
IPCP0
R
00000000B
007921H Input Capture 0
IPCP0
R
007922H Input Capture 1
IPCP1
R
007923H Input Capture 1
IPCP1
R
00000000B
007924H Input Capture 2
IPCP2
R
00000000B
007925H Input Capture 2
IPCP2
R
007926H Input Capture 3
IPCP3
R
007927H Input Capture 3
IPCP3
R
00000000B
00000000B
Address
Register
007928H
to
00793FH
TCDT0
R/W
007941H Timer Data 0
TCDT0
R/W
007942H Timer Control Status 0
TCCSL0
R/W
007943H Timer Control Status 0
TCCSH0
R/W
007944H
to
00794BH
00794DH
00794EH
00794FH
Initial value
XXXXXXXXB
16-bit PPG E/F
Input Capture 0/1*
Input Capture 2/3*
XXXXXXXXB
XXXXXXXXB
00000000B
00000000B
00000000B
00000000B
Reserved
007940H Timer Data 0
00794CH
Resource name
I/O Timer 0
00000000B
00000000B
01100000B
Reserved
Timer 2/Reload 2
TMR2/
TMRLR2
Timer 3/Reload 3
TMR3/
TMRLR3
007950H
to
00795FH
007960H Clock Supervisor Control Register
007961H
to
00796DH
00796EH CAN Direct Mode Register
00796FH
to
0079A1H
R/W
16-bit Reload
Timer 2
XXXXXXXXB
XXXXXXXXB
R/W
16-bit Reload
Timer 3
R, R/W
Clock supervisor
00011100B
CAN clock sync
11111110B
R/W
R/W
XXXXXXXXB
XXXXXXXXB
Reserved
CSVCR
Reserved
CDMR
R/W
Reserved
* : The initial value of the evaluation product is XXXXXXXXB.
(Continued)
DS07-13753-3E
27
MB90990 Series
Abbreviation
Access
0079A2H Flash Write Control Register 0
FWR0
R/W
0079A3H Flash Write Control Register 1
FWR1
R/W
Address
Register
0079A4H
to
0079B1H
0079B2H
Resource name
Flash
Initial value
00000000B
00000000B
Reserved
Low Voltage/CPU Operation Detection
Setting Register
0079B3H
to
0079B7H
LVRS
R/W
Low Voltage/CPU
Operation Detection
Reset
10000000B
Reserved
0079B8H Clock Calibration Unit Control Register
CUCR
R/W
00000000B
0079B9H CR Trimming Register
CRTR
R/W
11110111B
0079BAH CR Oscillation Timer Deta Register
CUTDL
R/W
01010000B
0079BBH CR Oscillation Timer Deta Register
CUTDL
R/W
0079BCH Main Oscillation Timer Deta Register 1
CUTR1L
R
Main Oscillation Timer Deta Register 1
CUTR1H
R
00000000B
0079BEH Main Oscillation Timer Deta Register 2
CUTR2L
R
00000000B
0079BFH Main Oscillation Timer Deta Register 2
CUTR2H
R
00000000B
0079BDH
0079C0H
to
0079DFH
Clock Calibration
Unit
11000011B
00000000B
Reserved
0079E0H Detect Address Setting 0
PADR0
R/W
XXXXXXXXB
0079E1H Detect Address Setting 0
PADR0
R/W
XXXXXXXXB
0079E2H Detect Address Setting 0
PADR0
R/W
XXXXXXXXB
0079E3H Detect Address Setting 1
PADR1
R/W
XXXXXXXXB
Address Match
Detection 0
0079E4H Detect Address Setting 1
PADR1
R/W
0079E5H Detect Address Setting 1
PADR1
R/W
XXXXXXXXB
0079E6H Detect Address Setting 2
PADR2
R/W
XXXXXXXXB
0079E7H Detect Address Setting 2
PADR2
R/W
XXXXXXXXB
0079E8H Detect Address Setting 2
PADR2
R/W
XXXXXXXXB
0079E9H
to
0079EFH
XXXXXXXXB
Reserved
(Continued)
28
DS07-13753-3E
MB90990 Series
(Continued)
Abbreviation
Access
0079F0H Detect Address Setting 3
PADR3
R/W
XXXXXXXXB
0079F1H Detect Address Setting 3
PADR3
R/W
XXXXXXXXB
0079F2H Detect Address Setting 3
PADR3
R/W
XXXXXXXXB
0079F3H Detect Address Setting 4
PADR4
R/W
Address
Register
Resource name
Initial value
XXXXXXXXB
Address Match
Detection 1
0079F4H Detect Address Setting 4
PADR4
R/W
0079F5H Detect Address Setting 4
PADR4
R/W
XXXXXXXXB
0079F6H Detect Address Setting 5
PADR5
R/W
XXXXXXXXB
0079F7H Detect Address Setting 5
PADR5
R/W
XXXXXXXXB
0079F8H Detect Address Setting 5
PADR5
R/W
XXXXXXXXB
0079F9H
to
007BFFH
Reserved
007C00H
to
007CFFH
Reserved for CAN Interface 1. Refer to “■ CAN CONTROLLERS”
007D00H
to
007DFFH
Reserved for CAN Interface 1. Refer to “■ CAN CONTROLLERS”
007E00H
to
007FFFH
Reserved
XXXXXXXXB
Notes : • Initial value of “X” represents undefined value.
• Do not write to reserved address in I/O map. A read access to reserved addresses results in reading “X”.
DS07-13753-3E
29
MB90990 Series
■ CAN CONTROLLERS
• Conforms to CAN Specification Ver 2.0 A and B
• Supports transmission/reception in standard frame and extended frame formats
• Supports transmitting of data frames by receiving remote frames
• 16 transmitting/receiving message buffers
• 29-bit ID and 8-byte data
• Multi-level message buffer configuration
• Provides full-bit comparison, full-bit mask, acceptance register 0/acceptance register 1 for each message
buffer as ID acceptance mask
• 2 acceptance mask registers in either standard frame format or extended frame formats
• Bit rate programmable from 10 kbps to 1 Mbps (when input clock is at 16 MHz)
List of Control Registers (1)
Address
CAN1
000080H
000081H
000082H
000083H
000084H
000085H
000086H
000087H
000088H
000089H
00008AH
00008BH
00008CH
00008DH
00008EH
00008FH
30
Register
Abbreviation
Access
Initial Value
Message buffer valid register
BVALR
R/W
00000000 00000000B
Transmit request register
TREQR
R/W
00000000 00000000B
Transmit cancel register
TCANR
W
00000000 00000000B
Transmission complete register
TCR
R/W
00000000 00000000B
Receive complete register
RCR
R/W
00000000 00000000B
Remote request receiving
register
RRTRR
R/W
00000000 00000000B
Receive overrun register
ROVRR
R/W
00000000 00000000B
Reception interrupt enable
register
RIER
R/W
00000000 00000000B
DS07-13753-3E
MB90990 Series
List of Control Registers (2)
Address
CAN1
007D00H
007D01H
007D02H
007D03H
007D04H
007D05H
007D06H
007D07H
007D08H
007D09H
007D0AH
007D0BH
007D0CH
007D0DH
007D0EH
007D0FH
Register
Abbreviation
Access
Initial Value
Control status register
CSR
R/W, W
R/W, R
0XXXX0X1 00XXX000B
Last event indicator register
LEIR
R/W
000X0000 XXXXXXXXB
Receive and transmit error
counter
RTEC
R
00000000 00000000B
Bit timing register
BTR
R/W
11111111 X1111111B
IDE register
IDER
R/W
XXXXXXXX XXXXXXXXB
Transmit RTR register
TRTRR
R/W
00000000 00000000B
Remote frame receive
waiting register
RFWTR
R/W
XXXXXXXX XXXXXXXXB
Transmit interrupt enable
register
TIER
R/W
00000000 00000000B
007D10H
007D11H
007D12H
XXXXXXXX XXXXXXXXB
Acceptance mask select
register
AMSR
R/W
XXXXXXXX XXXXXXXXB
007D13H
007D14H
007D15H
007D16H
XXXXXXXX XXXXXXXXB
Acceptance mask register 0
AMR0
R/W
XXXXXXXX XXXXXXXXB
007D17H
007D18H
007D19H
007D1AH
007D1BH
DS07-13753-3E
XXXXXXXX XXXXXXXXB
Acceptance mask register 1
AMR1
R/W
XXXXXXXX XXXXXXXXB
31
MB90990 Series
List of Message Buffers (ID Registers)
Address
CAN1
007C00H
to
007C1FH
Register
Abbreviation
Access
Initial Value
General-purpose RAM
⎯
R/W
XXXXXXXXB
to
XXXXXXXXB
007C20H
007C21H
007C22H
XXXXXXXX XXXXXXXXB
ID register 0
IDR0
R/W
XXXXXXXX XXXXXXXXB
007C23H
007C24H
007C25H
007C26H
XXXXXXXX XXXXXXXXB
ID register 1
IDR1
R/W
XXXXXXXX XXXXXXXXB
007C27H
007C28H
007C29H
007C2AH
XXXXXXXX XXXXXXXXB
ID register 2
IDR2
R/W
XXXXXXXX XXXXXXXXB
007C2BH
007C2CH
007C2DH
007C2EH
XXXXXXXX XXXXXXXXB
ID register 3
IDR3
R/W
XXXXXXXX XXXXXXXXB
007C2FH
007C30H
007C31H
007C32H
XXXXXXXX XXXXXXXXB
ID register 4
IDR4
R/W
XXXXXXXX XXXXXXXXB
007C33H
007C34H
007C35H
007C36H
XXXXXXXX XXXXXXXXB
ID register 5
IDR5
R/W
XXXXXXXX XXXXXXXXB
007C37H
007C38H
007C39H
007C3AH
XXXXXXXX XXXXXXXXB
ID register 6
IDR6
R/W
XXXXXXXX XXXXXXXXB
007C3BH
007C3CH
007C3DH
007C3EH
007C3FH
XXXXXXXX XXXXXXXXB
ID register 7
IDR7
R/W
XXXXXXXX XXXXXXXXB
(Continued)
32
DS07-13753-3E
MB90990 Series
(Continued)
Address
CAN1
Register
Abbreviation
Access
007C40H
007C41H
007C42H
XXXXXXXX XXXXXXXXB
ID register 8
IDR8
R/W
XXXXXXXX XXXXXXXXB
007C43H
007C44H
007C45H
007C46H
XXXXXXXX XXXXXXXXB
ID register 9
IDR9
R/W
XXXXXXXX XXXXXXXXB
007C47H
007C48H
007C49H
007C4AH
XXXXXXXX XXXXXXXXB
ID register 10
IDR10
R/W
XXXXXXXX XXXXXXXXB
007C4BH
007C4CH
007C4DH
007C4EH
XXXXXXXX XXXXXXXXB
ID register 11
IDR11
R/W
XXXXXXXX XXXXXXXXB
007C4FH
007C50H
007C51H
007C52H
XXXXXXXX XXXXXXXXB
ID register 12
IDR12
R/W
XXXXXXXX XXXXXXXXB
007C53H
007C54H
007C55H
007C56H
XXXXXXXX XXXXXXXXB
ID register 13
IDR13
R/W
XXXXXXXX XXXXXXXXB
007C57H
007C58H
007C59H
007C5AH
XXXXXXXX XXXXXXXXB
ID register 14
IDR14
R/W
XXXXXXXX XXXXXXXXB
007C5BH
007C5CH
007C5DH
007C5EH
007C5FH
DS07-13753-3E
Initial Value
XXXXXXXX XXXXXXXXB
ID register 15
IDR15
R/W
XXXXXXXX XXXXXXXXB
33
MB90990 Series
List of Message Buffers (DLC Registers and Data Registers)
Address
CAN1
007C60H
007C61H
007C62H
007C63H
007C64H
007C65H
007C66H
007C67H
007C68H
007C69H
007C6AH
007C6BH
007C6CH
007C6DH
007C6EH
007C6FH
007C70H
007C71H
007C72H
007C73H
007C74H
007C75H
007C76H
007C77H
007C78H
007C79H
007C7AH
007C7BH
007C7CH
007C7DH
007C7EH
007C7FH
Register
Abbreviation
Access
Initial Value
DLC register 0
DLCR0
R/W
XXXXXXXXB
DLC register 1
DLCR1
R/W
XXXXXXXXB
DLC register 2
DLCR2
R/W
XXXXXXXXB
DLC register 3
DLCR3
R/W
XXXXXXXXB
DLC register 4
DLCR4
R/W
XXXXXXXXB
DLC register 5
DLCR5
R/W
XXXXXXXXB
DLC register 6
DLCR6
R/W
XXXXXXXXB
DLC register 7
DLCR7
R/W
XXXXXXXXB
DLC register 8
DLCR8
R/W
XXXXXXXXB
DLC register 9
DLCR9
R/W
XXXXXXXXB
DLC register 10
DLCR10
R/W
XXXXXXXXB
DLC register 11
DLCR11
R/W
XXXXXXXXB
DLC register 12
DLCR12
R/W
XXXXXXXXB
DLC register 13
DLCR13
R/W
XXXXXXXXB
DLC register 14
DLCR14
R/W
XXXXXXXXB
DLC register 15
DLCR15
R/W
XXXXXXXXB
(Continued)
34
DS07-13753-3E
MB90990 Series
Address
Register
Abbreviation
Access
Initial Value
007C80H
to
007C87H
Data register 0
(8 bytes)
DTR0
R/W
XXXXXXXXB
to
XXXXXXXXB
007C88H
to
007C8FH
Data register 1
(8 bytes)
DTR1
R/W
XXXXXXXXB
to
XXXXXXXXB
007C90H
to
007C97H
Data register 2
(8 bytes)
DTR2
R/W
XXXXXXXXB
to
XXXXXXXXB
007C98H
to
007C9FH
Data register 3
(8 bytes)
DTR3
R/W
XXXXXXXXB
to
XXXXXXXXB
007CA0H
to
007CA7H
Data register 4
(8 bytes)
DTR4
R/W
XXXXXXXXB
to
XXXXXXXXB
007CA8H
to
007CAFH
Data register 5
(8 bytes)
DTR5
R/W
XXXXXXXXB
to
XXXXXXXXB
007CB0H
to
007CB7H
Data register 6
(8 bytes)
DTR6
R/W
XXXXXXXXB
to
XXXXXXXXB
007CB8H
to
007CBFH
Data register 7
(8 bytes)
DTR7
R/W
XXXXXXXXB
to
XXXXXXXXB
007CC0H
to
007CC7H
Data register 8
(8 bytes)
DTR8
R/W
XXXXXXXXB
to
XXXXXXXXB
007CC8H
to
007CCFH
Data register 9
(8 bytes)
DTR9
R/W
XXXXXXXXB
to
XXXXXXXXB
007CD0H
to
007CD7H
Data register 10
(8 bytes)
DTR10
R/W
XXXXXXXXB
to
XXXXXXXXB
007CD8H
to
007CDFH
Data register 11
(8 bytes)
DTR11
R/W
XXXXXXXXB
to
XXXXXXXXB
007CE0H
to
007CE7H
Data register 12
(8 bytes)
DTR12
R/W
XXXXXXXXB
to
XXXXXXXXB
007CE8H
to
007CEFH
Data register 13
(8 bytes)
DTR13
R/W
XXXXXXXXB
to
XXXXXXXXB
CAN1
(Continued)
DS07-13753-3E
35
MB90990 Series
(Continued)
Address
Register
Abbreviation
Access
Initial Value
007CF0H
to
007CF7H
Data register 14
(8 bytes)
DTR14
R/W
XXXXXXXXB
to
XXXXXXXXB
007CF8H
to
007CFFH
Data register 15
(8 bytes)
DTR15
R/W
XXXXXXXXB
to
XXXXXXXXB
CAN1
36
DS07-13753-3E
MB90990 Series
■ INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTER
Interrupt cause
EI2OS
corresponding
Interrupt vector
Interrupt control
register
Number
Address
Number
Address
Reset
N
#08
FFFFDCH
⎯
⎯
INT9 instruction
N
#09
FFFFD8H
⎯
⎯
Exception
N
#10
FFFFD4H
⎯
⎯
Reserved
N
#11
FFFFD0H
Reserved
N
#12
FFFFCCH
ICR00
0000B0H
CAN 1 reception
N
#13
FFFFC8H
CAN 1 transmission/node status
N
#14
FFFFC4H
ICR01
0000B1H
Reserved
N
#15
FFFFC0H
Clock calibration unit
N
#16
FFFFBCH
ICR02
0000B2H
Reserved
N
#17
FFFFB8H
Reserved
N
#18
FFFFB4H
ICR03
0000B3H
16-bit reload timer 2
Y1
#19
FFFFB0H
16-bit reload timer 3
Y1
#20
FFFFACH
ICR04
0000B4H
Reserved
N
#21
FFFFA8H
Reserved
N
#22
FFFFA4H
ICR05
0000B5H
PPG C/D
N
#23
FFFFA0H
PPG A/B/E/F
N
#24
FFFF9CH
ICR06
0000B6H
Timebase timer
N
#25
FFFF98H
External interrupt 8 to 11
Y1
#26
FFFF94H
ICR07
0000B7H
Watch timer
N
#27
FFFF90H
External interrupt 12 to 15
Y1
#28
FFFF8CH
ICR08
0000B8H
A/D converter
Y1
#29
FFFF88H
I/O timer 0
N
#30
FFFF84H
ICR09
0000B9H
Reserved
N
#31
FFFF80H
Reserved
N
#32
FFFF7CH
ICR10
0000BAH
Input capture 0 to 3
Y1
#33
FFFF78H
Reserved
N
#34
FFFF74H
ICR11
0000BBH
UART 0 reception
Y2
#35
FFFF70H
UART 0 transmission
Y1
#36
FFFF6CH
ICR12
0000BCH
UART 1 reception
Y2
#37
FFFF68H
UART 1 transmission
Y1
#38
FFFF64H
ICR13
0000BDH
(Continued)
DS07-13753-3E
37
MB90990 Series
(Continued)
Interrupt cause
EI2OS
corresponding
Interrupt vector
Number
Address
UART 2 reception
Y2
#39
FFFF60H
UART 2 transmission
Y1
#40
FFFF5CH
Flash memory
N
#41
FFFF58H
Delayed interrupt generation module
N
#42
FFFF54H
Interrupt control
register
Number
Address
ICR14
0000BEH
ICR15
0000BFH
Y1 : Usable
Y2 : Usable, with EI2OS stop function
N : Unusable
Notes : • The peripheral resources sharing the ICR register have the same interrupt level.
• When the peripheral resources sharing the ICR register use extended intelligent I/O service, only one
can use extended intelligent I/O service at a time.
• When either of the 2 peripheral resources sharing the ICR register specifies extended intelligent I/O
service, the other one cannot use interrupts.
38
DS07-13753-3E
MB90990 Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter
Power supply voltage*1
Input voltage*1
Output voltage*
1
Maximum clamp current
Total Maximum clamp current
“L” level maximum output current
“L” level average output current
“L” level maximum overall output current
Symbol
“H” level average output current
“H” level maximum overall output current
VCC
VSS − 0.3
VSS + 6.0
V
AVCC
VSS − 0.3
VSS + 6.0
V
VCC = AVCC*2
AVR
VSS − 0.3
VSS + 6.0
V
AVCC ≥ AVR*2
VI
VSS − 0.3
VSS + 6.0
V
*3
VO
VSS − 0.3
VSS + 6.0
V
*3
ICLAMP
−2.0
+2.0
mA
*6
Σ|ICLAMP|
⎯
40
mA
*6
IOL1
⎯
15
mA
*4
IOL2
⎯
40
mA
*5
IOLAV1
⎯
4
mA
*4
IOLAV2
⎯
30
mA
*5
ΣIOL1
⎯
125
mA
*4
ΣIOL2
⎯
160
mA
*5
⎯
40
mA
⎯
40
mA
IOH1
⎯
−15
mA
*4
IOH2
⎯
−40
mA
*5
IOHAV1
⎯
−4
mA
*4
IOHAV2
⎯
−30
mA
*5
ΣIOH1
⎯
−125
mA
*4
ΣIOH2
⎯
−160
mA
*5
⎯
−40
mA
⎯
−40
mA
⎯
420
mW
−40
+105
°C
−40
+125
°C
−55
+150
°C
ΣIOLAV2
ΣIOLAV1
ΣIOHAV1
“H” level average overall output current
ΣIOHAV2
ΣIOHAV1
ΣIOHAV2
Power consumption
PD
Operating temperature
TA
Storage temperature
Remarks
Max
ΣIOLAV2
“H” level maximum output current
Unit
Min
ΣIOLAV1
“L” level average overall output current
Rating
TSTG
*4
*5
*4
*5
*4
*5
*4
*5
*7
(Continued)
DS07-13753-3E
39
MB90990 Series
(Continued)
*1 : This parameter is based on VSS = AVSS = 0 V.
*2 : Set AVCC and VCC to the same voltage. Make sure that AVCC does not exceed VCC and that the voltage at the
analog inputs does not exceed AVCC when the power is switched on.
*3 : VI and VO should not exceed VCC + 0.3 V. VI should not exceed the specified ratings. However, if the maximun
current to/from an input is limited by some means with external components, the ICLAMP rating supersedes the
VI rating.
*4 : Applicable to pins : P24 to P27, P40 to P44, P50 to P57, P60 to P67, P80, P82 to P87
*5 : Applicable to pins : P20 to P23
*6 : Applicable to pins : P20 to P27, P40 to P44, P50 to P57, P60 to P67, P80, P82 to P87
• Use within recommended operating conditions.
• Use at DC voltage (current) .
• The +B signal should always be applied a connecting limit resistance between the +B signal and the
microcontroller.
• The value of the limiting resistance should be set so that when the +B signal is applied the input current to
the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input
potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect
other devices.
• Note that if a +B signal is inputted when the microcontroller power supply is off (not fixed at 0 V) , the power
supply is provided from the pins, so that incomplete operation may result.
• Note that if the +B input is applied during power-on, the power supply is provided from the pins and the
resulting power supply voltage may not be sufficient to operate the power-on reset.
• Care must be taken not to leave the +B input pin open.
• Recommended circuit sample :
• Input/output equivalent circuits
Protective diode
VCC
Limiting
resistance
P-ch
+B input (0 V to 16 V)
N-ch
R
*7 : If used exceeding TA = +105 °C, please consult with us due to the restricted reliability.
It is ensured to write/erase data to the Flash memory between TA = − 40 °C and +105 °C.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
40
DS07-13753-3E
MB90990 Series
2. Recommended Conditions
(VSS = AVSS = 0 V)
Parameter
Power supply voltage
Symbol
VCC,
AVCC
Smoothing capacitor
CS
Operating temperature
TA
Value
Unit
Remarks
Min
Typ
Max
3.0
5.0
5.5
V
Under normal operation
2.6
⎯
5.5
V
Maintains RAM data in stop mode
Use a ceramic capacitor or comparable capacitor of the AC characteristics. Bypass capacitor at the
VCC pin should be greater than this
capacitor.
0.1
⎯
1.0
μF
−40
⎯
+105
°C
−40
⎯
+125
°C
*
* : For the restricted reliability, contact us if use the devices over Ta=+105 °C.
It is ensured to write/erase data to the Flash memory between TA = − 40 °C and +105 °C.
• C Pin Connection Diagram
C
CS
WARNING: The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented
on the data sheet. Users considering application outside the listed conditions are advised to contact
their representatives beforehand.
DS07-13753-3E
41
MB90990 Series
3. DC Characteristics
Parameter
Symbol
Pin name
Condition
VIHS
⎯
VIHA
Value
Unit
Remarks
VCC + 0.3
V
Pin inputs if CMOS
hysteresis input levels
are selected
⎯
VCC + 0.3
V
Pin inputs if
Automotive input
levels are selected
0.7 VCC
⎯
VCC + 0.3
V
P50, P82, P85 inputs if
CMOS input levels are
selected
⎯
0.8 VCC
⎯
VCC + 0.3
V
RST input pin
(CMOS hysteresis)
⎯
⎯
VCC − 0.3
⎯
VCC + 0.3
V
MD input pin
VILS
⎯
⎯
VSS − 0.3
⎯
0.2 VCC
V
Pin inputs if CMOS
hysteresis input levels
are selected
VILA
⎯
⎯
VSS − 0.3
⎯
0.5 VCC
V
Pin inputs if
Automotive input
levels are selected
VILS
⎯
⎯
VSS − 0.3
⎯
0.3 VCC
V
P50, P82, P85 inputs if
CMOS input levels are
selected
VILR
⎯
⎯
VSS − 0.3
⎯
0.2 VCC
V
RST input pin (CMOS
hysteresis)
VILM
⎯
⎯
VSS − 0.3
⎯
VSS + 0.3
V
MD input pin
VCC − 0.5
⎯
⎯
V
VCC = 4.5 V,
VCC − 0.5
IOH = −14.0 mA
⎯
⎯
V
⎯
⎯
0.4
V
Min
Typ
Max
⎯
0.8 VCC
⎯
⎯
⎯
0.8 VCC
VIHS
⎯
⎯
VIHR
⎯
VIHM
Input “H”
voltage
Input “L”
voltage
VOH
Other than VCC = 4.5 V,
P20 to P23 IOH = −4.0 mA
VOHI
P20 to P23
VOL
Other than VCC = 4.5 V,
P20 to P23 IOL = 4.0 mA
VOLI
P20 to P23
VCC = 4.5 V,
IOL = 20.0 mA
⎯
⎯
0.4
V
Input leak
current
IIL
⎯
VCC = 5.5 V,
VSS < VI < VCC
−1
⎯
+1
μA
Pull-up
resistance
RUP
P20 to P27,
RST
⎯
25
50
100
kΩ
Pull-down
resistance
RDOWN
MD2
⎯
25
50
100
kΩ
Output “H”
voltage
Output “L”
voltage
Evaluation products
only
(Continued)
42
DS07-13753-3E
MB90990 Series
(Continued)
Parameter
Symbol
Pin
name
Unit
Remarks
Typ
Max
VCC = 5.0 V,
Internal frequency : 32 MHz,
At normal operation.
⎯
30
40
mA
VCC = 5.0 V,
Internal frequency : 24 MHz,
At normal operation.
⎯
22.5
30
mA
VCC = 5.0 V,
Internal frequency : 2 MHz,
At normal operation.
⎯
3
7
mA
VCC = 5.0 V,
Internal frequency : 32 MHz,
At writing Flash memory.
⎯
50
65
mA
VCC = 5.0 V,
Internal frequency : 32 MHz,
At erasing Flash memory.
⎯
50
65
mA
VCC = 5.0 V,
Internal frequency : 32 MHz,
At sleep mode.
⎯
13
23
mA
⎯
0.4
1.0
⎯
0.3
0.9
ICTSPLL8
VCC = 5.0 V,
Internal frequency : 24 MHz,
At PLL timer mode,
External frequency = 4 MHz
⎯
4
7
mA
ICCL
VCC = 5.0 V,
Internal frequency : 12.5 kHz
At CR sub operation,
TA = +25°C
⎯
170
400
μA
MB90F997JBS
ICCLS
VCC = 5.0 V,
Internal frequency : 12.5 kHz
At CR sub sleep,
TA = +25°C
⎯
130
250
μA
MB90F997JBS
ICCT
VCC = 5.0 V,
Internal frequency : 12.5 kHz
At CR watch mode,
TA = +25°C
⎯
130
250
μA
MB90F997JBS
ICCH
VCC = 5.0 V,
At stop mode, TA = +25°C
⎯
70
170
μA
MB90F997JBS
⎯
25
100
μA
MB90F997MBS
⎯
5
15
pF
ICCS
Input capacity
Value
Min
ICC
Power supply
current*
Condition
ICTS
CIN
VCC
Other
than AVCC,
AVSS,
AVR, VCC,
VSS, C
VCC = 5.0 V,
Internal frequency : 2 MHz,
At main timer mode
⎯
MB90F997JBS
mA
MB90F997MBS
* : The power supply current is measured with an external clock.
DS07-13753-3E
43
MB90990 Series
4. AC Characteristics
(1) Clock Timing
Parameter
Clock frequency
Symbol
fC
Clock cycle time
tCYL
Internal operating clock
frequency (machine
clock)
fCP
Internal operating clock
cycle time (machine
clock)
tCP
Internal CR oscillation
frequency
fCCR
Pin
name
Value
Unit
Remarks
16
MHz
1/2 when PLL stops,
When using an oscillation circuit
⎯
16
MHz
PLL × 1,
When using an oscillation circuit
4
⎯
16
MHz
PLL × 2,
When using an oscillation circuit
4
⎯
10
MHz
PLL × 3,
When using an oscillation circuit
4
⎯
8
MHz
PLL × 4,
When using an oscillation circuit
4
⎯
5
MHz
PLL × 6,
When using an oscillation circuit
4
⎯
4
MHz
PLL × 8,
When using an oscillation circuit
X0, X1
62.5
⎯
333
ns
When using an oscillation circuit
⎯
1.5
⎯
32
⎯
10.625
12.5
14.375
kHz
⎯
31.25
⎯
666
ns
When using main clock
⎯
69.565
80
94.118
μs
When using CR clock
⎯
85
100
115
kHz
X0, X1
Min
Typ
Max
3
⎯
4
MHz When using main clock
When using CR clock
When trimming with clock
calibration unit.
• When using an oscillation circuit
tCYL
X0, X1
Amplitude:
It varies depending on the
external resistance, power
rating and the different kind of
device.
Reference values: 1 V to 2.5 V
Note: The amplitude of MB90V950AJAS and MB90V950AMAS are the same as VCC.
44
DS07-13753-3E
MB90990 Series
• Guaranteed PLL Operation Range
Guaranteed operation range
Power supply voltage
VCC (V)
5.5
4.0
3.5
Guaranteed PLL operation range
1.5
4
32
Internal clock fCP (MHz)
Guaranteed operation range of MB90990 series
Guaranteed oscillation frequency range
×8
×6
Internal clock fCP (MHz)
32
×4
×3
×2
×1
24
×1/2
16
(PLLoff)
12
8
4.0
1.5
3 4
8
12
16
24
32
External clock fC (MHz)*
* : When using the oscillation circuit, the maximum oscillation clock frequency is 16 MHz.
Note: MB90F997JBS will be at a reset state under the power supply voltage of less than low-voltage
detection voltage.
DS07-13753-3E
45
MB90990 Series
(2) Reset Standby Input
Parameter
Reset input
time
Symbol
tRSTL
Value
Pin
name
RST
Unit
Remarks
Min
Max
500
⎯
ns
Under normal operation
Oscillation time of oscillator*
+ 100 μs
⎯
μs
In stop mode, sub clock
mode, sub sleep mode,
and watch mode
100
⎯
μs
In timebase timer mode
* : Oscillation time of oscillator is the time that the amplitude reaches 90%. In the crystal oscillator, the oscillation
time is between several ms and tens of ms. In ceramic oscillators, the oscillation time is between hundreds of μs
and several ms. An External clock of oscillation time is 0 ms.
• Under normal operation :
tRSTL
RST
VILR
VILR
• In stop mode, sub clock mode, sub sleep mode, and watch mode :
tRSTL
RST
VILR
X0
VILR
90% of
amplitude
Internal operation
clock
100 µs
Oscillation time
of oscillator
Oscillation stabilization
waiting time
Instruction execution
Internal reset
46
DS07-13753-3E
MB90990 Series
(3) Power-on Reset
Parameter
Symbol
Pin
name
Power on rise time
tR
VCC
tOFF
VCC
Power off time
Condition
⎯
Value
Unit
Min
Max
0.05
30
ms
1
⎯
ms
Remarks
Due to repetitive operation
tR
VCC
2.7 V
0.2 V
0.2 V
0.2 V
tOFF
Note : If you change the power supply voltage too rapidly, a power-on reset may occur. We recommend that you
start up smoothly by restraining voltages when changing the power supply voltage during operation, as
shown in the figure below. Perform while not using the PLL clock. However, if voltage drops are within
1 V/s, you can operate while using the PLL clock.
VCC
We recommend a rise of
50 mV/ms maximum.
3V
VSS
DS07-13753-3E
Holds RAM data
47
MB90990 Series
(4) UART
ESCR : SCES = 0, ECCR : SCDE = 0
Parameter
Symbol
tSCYC
tSLOVI
tIVSHI
tSHIXI
tSLSH
tSHSL
tSLOVE
tIVSHE
tSHIXE
tF
tR
Serial clock cycle time
SCK ↓ → SOT delay time
SIN → SCK ↑ setup time
SCK↑ → SIN hold time
Serial clock “L” pulse width
Serial clock “H” pulse width
SCK ↓ → SOT delay time
SIN → SCK ↑ setup time
SCK↑ → SIN hold time
SCK fall time
SCK rise time
Condition
Internal shift clock
operation
CL = 80pF + 1
TTL.
External shift clock
operation
CL = 80pF + 1
TTL.
Value
Unit
Min
Max
5 tcp*
⎯
ns
− 50
+ 50
ns
tcp + 80
⎯
ns
0
⎯
ns
3 tcp − tR
⎯
ns
tcp + 10
⎯
ns
⎯
2 tcp + 60
ns
30
⎯
ns
tcp + 30
⎯
ns
⎯
10
ns
⎯
10
ns
*: The tcp indicates machine clock
tSCYC
2.4 V
SCK
0.8 V
tSLOVI
2.4 V
SOT
0.8 V
tIVSHI
tSHIXI
VIH
SIN
VIL
Internal Clock Shift Operation
48
DS07-13753-3E
MB90990 Series
tSHSL
tSLSH
VIH
SCK
VIL
tR
tF
tSLOVE
2.4 V
SOT
0.8 V
tIVSHE
tSHIXE
VIH
SIN
VIL
External Clock Shift Operation
DS07-13753-3E
49
MB90990 Series
ESCR : SCES = 1, ECCR : SCDE = 0
Parameter
Symbol
tSCYC
tSHOVI
tIVSLI
tSLIXI
tSHSL
tSLSH
tSHOVE
tIVSLE
tSLIXE
tF
tR
Serial clock cycle time
SCK ↑ → SOT delay time
SIN → SCK ↓ setup time
SCK ↓ → SIN hold time
Serial clock “H” pulse width
Serial clock “L” pulse width
SCK ↑ → SOT delay time
SIN → SCK ↓ setup time
SCK ↓ → SIN hold time
SCK fall time
SCK rise time
Condition
Internal shift clock
operation
CL = 80pF + 1
TTL.
External shift clock
operation
CL = 80pF + 1
TTL.
Value
Unit
Min
Max
5 tcp*
⎯
ns
− 50
+ 50
ns
tcp + 80
⎯
ns
0
⎯
ns
3 tcp − tR
⎯
ns
tcp + 10
⎯
ns
⎯
2 tcp + 60
ns
30
⎯
ns
tcp + 30
⎯
ns
⎯
10
ns
⎯
10
ns
*: The tcp indicates machine clock
tSCYC
2.4 V
SCK
0.8 V
tSHOVI
2.4 V
SOT
0.8 V
tIVSLI
tSLIXI
VIH
SIN
VIL
Internal Clock Shift Operation
50
DS07-13753-3E
MB90990 Series
tSLSH
tSHSL
VIH
SCK
VIL
tF
tR
tSHOVE
2.4 V
SOT
0.8 V
tIVSLE
tSLIXE
VIH
SIN
VIL
External Clock Shift Operation
DS07-13753-3E
51
MB90990 Series
ESCR : SCES = 0, ECCR : SCDE = 1
Value
Parameter
Symbol
Serial clock cycle time
tSCYC
SCK ↑ → SOT delay time
tSHOVI
SIN → SCK ↓ setup time
tIVSLI
SCK ↓ → SIN hold time
tSLIXI
SOT → SCK ↓ delay time
tSOVLI
Condition
Unit
Internal shift clock
operation
CL = 80pF + 1
TTL.
Min
Max
5 tcp*
⎯
ns
− 50
+ 50
ns
tcp + 80
⎯
ns
0
⎯
ns
3 tcp − 70
⎯
ns
*: The tcp indicates machine clock
tSCYC
2.4 V
SCK
0.8 V
0.8 V
tSHOVI
tSOVLI
SOT
2.4 V
2.4 V
0.8 V
0.8 V
tIVSLI
SIN
52
tSLIXI
VIH
VIH
VIL
VIL
DS07-13753-3E
MB90990 Series
ESCR : SCES = 1, ECCR : SCDE = 1
Value
Parameter
Symbol
Serial clock cycle time
tSCYC
SCK ↓ → SOT delay time
tSLOVI
SIN → SCK ↑ setup time
tIVSHI
SCK ↑ → SIN hold time
tSHIXI
SOT → SCK ↑ delay time
tSOVHI
Condition
Unit
Internal clock
operation
CL = 80pF + 1
TTL.
Min
Max
5 tcp*
⎯
ns
− 50
+ 50
ns
tcp + 80
⎯
ns
0
⎯
ns
3 tcp − 70
⎯
ns
*: The tcp indicates machine clock
tSCYC
2.4 V
SCK
2.4 V
0.8 V
tSLOVI
tSOVHI
SOT
2.4 V
2.4 V
0.8 V
0.8 V
tIVSHI
SIN
tSHIXI
VIH
VIH
VIL
VIL
(5) Trigger Input Timing
Parameter
Input pulse width
Symbol
Pin name
Condition
tTRGH
tTRGL
INT8, INT9R
INT10, INT11
INT12R, INT13
INT14R, INT15R
ADTG
⎯
Value
Min
Max
5 tCP
⎯
Unit
ns
Note : tCP is internal operating clock cycle time (machine clock) . Refer to “ (1) Clock Timing”.
INT8, INT9R
INT10, INT11
INT12R, INT13
INT14R, INT15R
ADTG
DS07-13753-3E
VIH
VIH
VIL
VIL
tTRGH
tTRGL
53
MB90990 Series
(6) Timer Related Resource Input Timing
Parameter
Symbol
Pin name
Condition
tTIWH
TIN2, TIN3
IN0 to IN3
⎯
Input pulse width
tTIWL
Value
Min
Max
4 tCP
⎯
Unit
ns
Note : tCP is internal operating clock cycle time (machine clock) . Refer to “ (1) Clock Timing”.
VIH
VIH
TIN2, TIN3
IN0 to IN3
VIL
VIL
tTIWH
tTIWL
(7) Timer Related Resource Output Timing
Parameter
CLK ↑ → TOUT change time
CLK
Symbol
Pin name
Condition
tTO
TOT2, TOT3
PPGA to PPGF
⎯
Value
Min
Max
30
⎯
Unit
ns
2.4 V
2.4 V
TOT2, TOT3
PPGA to PPGF
0.8 V
tTO
54
DS07-13753-3E
MB90990 Series
(8) Low Voltage Detection
Symbol
Pin
name
Condition
Detection voltage
initial value
VDL
VCC
Hysteresis width
VHYS
VCC
Parameter
Power supply
voltage change
rate
dV/dt
Detection delay
time
td
VCC
⎯
Value
Unit
Remarks
Min
Typ
Max
⎯
3.8
4.0
4.2
V
During voltage drop
⎯
169
173
177
mV
During voltage rise
− 0.1
⎯
+ 0.1
V/μs
dV/dt at low voltage
reset
⎯
⎯
− 0.004
⎯
⎯
⎯
dV/dt at standard
value of low voltage
+ 0.004 V/μs
detection/release
voltage
3.2
μs
When |dV/dt| ≤
0.004 V/μs
Note: When the change ratio of the power supply voltage is 0.004 V/μs < | dV/dt | ≤ 0.1 V/μs, reset may be generated
or released after the power supply voltage has exceeded the detection voltage range.
Internal reset
VCC
dV
dt
VHYS
VDL
td
DS07-13753-3E
td
55
MB90990 Series
(9) CAN PLL cycle jitter
Symbol
Parameter
CAN PLL cycle jitter
(When locked)
tPJ
Pin
name
Value
Condition
⎯
Min
⎯
Typ
− 10
⎯
Max
+ 10
Unit
Remarks
ns
FCP =
16 MHz
(4 MHz × multiplied by 4)
24 MHz
(4 MHz × multiplied by 6)
32 MHz
(4 MHz × multiplied by 8)
• CAN PLL cycle jitter
Deviation time from the ideal clock is assured per cycle out of 20, 000 cycles.
PLL output
t1
t2
tn-1
t3
tn
Ideal clock
Slow
Deviation
time
t1
t2
t3
tn-1
tn
Fast
56
DS07-13753-3E
MB90990 Series
5. A/D Converter
(3.0 V ≤ AVR = AVSS)
Parameter
Symbol
Pin name
Resolution
⎯
Total error
Value
Unit
Min
Typ
Max
⎯
⎯
⎯
10
bit
⎯
⎯
⎯
⎯
±3.0
LSB
Nonlinearity error
⎯
⎯
⎯
⎯
±2.5
LSB
Differential
nonlinearity error
⎯
⎯
⎯
⎯
±1.9
LSB
Zero reading voltage
VOT
AN0 to AN15
AVSS −
1.5 LSB
AVSS +
0.5 LSB
AVSS +
2.5 LSB
V
Full scale reading
voltage
VFST
AN0 to AN15
AVR −
3.5 LSB
AVR −
1.5 LSB
AVR +
0.5 LSB
V
Compare time
⎯
⎯
⎯
16500
μs
Sampling time
⎯
⎯
⎯
∞
μs
Analog port input
current
IAIN
AN0 to AN15
−0.3
⎯
+0.3
μA
Analog input
voltage range
VAIN
AN0 to AN15
AVSS
⎯
AVR
V
Reference
voltage range
⎯
AVR
AVSS + 2.7
⎯
AVCC
V
IA
AVCC
⎯
3.5
7.5
mA
IAH
AVCC
⎯
⎯
5
μA
Power supply current
0.66
2.2
0.4
1.0
Reference
voltage supply current
IR
AVR
⎯
600
900
μA
IRH
AVR
⎯
⎯
5
μA
Offset between
input channels
⎯
AN0 to AN15
⎯
⎯
4
LSB
Remarks
4.5 V ≤ AVCC ≤ 5.5 V
3.0 V ≤ AVCC < 4.5 V
4.5 V ≤ AVCC ≤ 5.5 V
3.0 V ≤ AVCC < 4.5 V
*
*
* : If A/D converter is not operating, a current when CPU is stopped is applicable (VCC = AVCC = AVR = 5.0 V) .
DS07-13753-3E
57
MB90990 Series
• About the external impedance of analog input and its sampling time
A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling
time, the analog voltage changed to the internal sample and hold capacitor is insufficient, adversely affecting A/
D conversion precision. Therefore, to satisfy the A/D conversion precision standard, consider the relationship
between the external impedance and minimum sampling time and either adjust the resistor value and operating
frequency or decrease the external impedance so that the sampling time is longer than the minimum value. And,
if the sampling time cannot be sufficient, connect a capacitor of about 0.1 μF to the analog input pin.
• Analog input equivalent circuit model
Analog input
R
Comparator
C
MB90V950AMAS 4.5 V ≤ AVCC ≤ 5.5 V : R =: 2.52 kΩ, C =: 10.7 pF
MB90V950AJAS 4.0 V ≤ AVCC < 4.5 V : R =: 13.6 kΩ, C =: 10.7 pF
MB90F997MBS
MB90F997JBS
4.5 V ≤ AVCC ≤ 5.5 V : R =: 4.1 kΩ, C =: 8.5 pF
3.0 V ≤ AVCC < 4.5 V : R =: 10.33 kΩ, C =: 8.5 pF
Note : The values are reference values.
58
DS07-13753-3E
MB90990 Series
6. Definition of A/D Converter Terms
Resolution
Non linearity
error
Differential
linearity error
Total error
: Analog variation that is recognized by an A/D converter.
: Deviation between a line across zero-transition line ( “00 0000 0000B” ← → “00 0000 0001B” )
and full-scale transition line ( “11 1111 1110B” ← → “11 1111 1111B” ) and actual conversion
characteristics.
: Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal
value.
: Difference between an actual value and an theoretical value. A total error includes zero transition error, full-scale transition error, and linear error.
Total error
3FFH
3FEH
1.5 LSB
Actual conversion
characteristics
Digital output
3FDH
{1 LSB × (N − 1) + 0.5 LSB}
004H
VNT
(Actually-measured value)
003H
Actual conversion
characteristics
Ideal characteristics
002H
001H
0.5 LSB
AVSS
AVR
Analog input
VNT − {1 LSB × (N − 1) + 0.5 LSB}
1 LSB
AVR − AVSS
[V]
1024
Total error of digital output “N” =
1 LSB (Ideal value) =
[LSB]
N : A/D converter digital output value
VOT (Ideal value) = AVSS + 0.5 LSB [V]
VFST (Ideal value) = AVR − 1.5 LSB [V]
VNT : A voltage at which digital output transits from (N − 1) H to NH.
(Continued)
DS07-13753-3E
59
MB90990 Series
(Continued)
Non linearity error
Differential linearity error
Ideal
characteristics
3FFH
Digital output
3FDH
Actual conversion
characteristics
{1 LSB × (N − 1)
+ VOT }
(N + 1)H
VFST (actual
measurement
value)
VNT (actual
measurement value)
004H
003H
Actual conversion
characteristics
Digital output
3FEH
Actual conversion
characteristics
NH
V (N + 1) T
(actual measurement
value)
VNT
(actual measurement value)
(N − 1)H
002H
Ideal characteristics
Actual conversion
characteristics
(N − 2)H
001H
VOT (actual measurement value)
AVSS
AVR
AVSS
AVR
Analog input
Analog input
Non linearity error of digital output N =
Differential linearity error of digital output N =
1 LSB =
VNT − {1 LSB × (N − 1) + VOT}
1 LSB
V (N+1) T − VNT
1 LSB
VFST − VOT
1022
[LSB]
−1 LSB [LSB]
[V]
N
: A/D converter digital output value
VOT : Voltage at which digital output transits from “000H” to “001H.”
VFST : Voltage at which digital output transits from “3FEH” to “3FFH.”
60
DS07-13753-3E
MB90990 Series
• The relationship between external impedance and minimum sampling time
• At 4.5 V ≤ AVCC ≤ 5.5 V
(External impedance = 0 kΩ to 100 kΩ)
(External impedance = 0 kΩ to 20 kΩ)
100
90
80
70
60
50
40
30
20
10
0
External impedance [kΩ]
External impedance [kΩ]
MB90F997MBS,
MB90F997JBS
MB90V950AJAS,MB90V950AMAS
0
1
2
3
4
5
6
7
8
MB90F997MBS,
MB90F997JBS
20
18
16
14
12
10
8
6
4
2
0
MB90V950AJAS,MB90V950AMAS
0
9 10
Minimum sampling time [μs]
1
2
3
4
5
Minimum sampling time [μs]
Minimum sampling time [μs] (4.5 V ≤ AVCC ≤ 5.5 V)
External impedance [kΩ]
5
10
50
MB90F997MBS, MB90F997JBS
0.54
0.84
3.22
MB90V950AJAS,MB90V950AMAS
0.56
0.94
3.93
(External impedance = 0 kΩ to 20 kΩ)
MB90F997MBS,
MB90F997JBS
100
90
80
70
60
50
40
30
20
10
0
External impedance [kΩ]
External impedance [kΩ]
• At 3.0 V ≤ AVCC < 4.5 V
(External impedance = 0 kΩ to 100 kΩ)
MB90V950AJAS,MB90V950AMAS
0
1
2
3
4
5
6
7
8
MB90F997MBS,
MB90F997JBS
20
18
16
14
12
10
8
6
4
2
0
MB90V950AJAS,MB90V950AMAS
0
9 10
Minimum sampling time [μs]
1
2
3
4
5
Minimum sampling time [μs]
Minimum sampling time [μs] (3.0 V ≤ AVCC < 4.5 V)
External impedance [kΩ]
5
10
50
MB90F997MBS, MB90F997JBS
0.91
1.21
3.59
MB90V950AJAS,MB90V950AMAS
1.39
1.77
4.76
• About errors
As | AVR − AVSS | becomes smaller, values of relative errors grow larger.
DS07-13753-3E
61
MB90990 Series
7. Flash Memory Program/Erase Characteristics
Parameter
Value
Conditions
Sector erase time
⎯
Chip erase time
Unit
Typ
Max
⎯
0.9
3.6
s
Excludes programming
prior to erasure
⎯
5.4
21.6
s
Main Flash
⎯
3.6
14.4
s
Satellite Flash
Byte (8-bit width)
programming time
⎯
⎯
15
240
μs
Word (16-bit width)
programming time
⎯
⎯
23
370
μs
TA > +85 °C
10000
⎯
⎯
cycle
TA ≤ +85 °C
100000
⎯
⎯
cycle
Average
TA = +85 °C
20
⎯
⎯
year
Program/Erase cycle
Flash memory data
retention time
Remarks
Min
Except for the overhead
time of the system level
*
* : Corresponding value comes from the technology reliability evaluation result (using Arrhenius equation to translate
high temperature measurements into normalized value at +85 °C) .
8. D/A Converter
Parameter
Symbol
Pin name
Resolution
⎯
Non linearity error
Value
Unit
Min
Typ
Max
⎯
⎯
8
⎯
bit
⎯
⎯
− 0.5
⎯
+ 0.5
LSB
Conversion time
⎯
⎯
0.773
0.787
1.078
2.490
2.535
3.474
Output impedance
Ro
DA0
3.19
3.50
4.80
kΩ
IA
AVCC
⎯
476
920
μA
IAH
AVCC
⎯
⎯
5
μA
Power supply current
62
μs
Remarks
CL = 20pF
CL = 100pF
DS07-13753-3E
MB90990 Series
■ ORDERING INFORMATION
Part number
MB90F997JBSPMC
MB90F997MBSPMC
MB90V950AMASCR-ES
MB90V950AJASCR-ES
DS07-13753-3E
Package
Remarks
48-pin plastic LQFP
(FPT-48P-M26)
299-pin ceramic PGA
(PGA-299C-A01)
For evaluation
63
MB90990 Series
■ PACKAGE DIMENSION
48-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
7 × 7 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Weight
0.17 g
Code
(Reference)
P-LFQFP48-7×7-0.50
(FPT-48P-M26)
48-pin plastic LQFP
(FPT-48P-M26)
Note 1) * : These dimensions include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
9.00±0.20(.354±.008)SQ
+0.40
+.016
* 7.00 –0.10 .276 –.004 SQ
36
0.145±0.055
(.006±.002)
25
37
24
0.08(.003)
Details of "A" part
+0.20
1.50 –0.10
+.008
48
13
"A"
0˚~8˚
LEAD No.
0.50(.020)
1
(Mounting height)
.059 –.004
INDEX
0.10±0.10
(.004±.004)
(Stand off)
12
0.20±0.05
(.008±.002)
0.08(.003)
0.25(.010)
M
0.60±0.15
(.024±.006)
©2003-2008
FUJITSU
LIMITED F48040S-c-2-3
C
2003 FUJITSU
LIMITEDMICROELECTRONICS
F48040S-c-2-2
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/
64
DS07-13753-3E
MB90990 Series
■ MAIN CHANGES IN THIS EDITION
Page
Section
⎯
⎯
56
Change Results
Changed the part number.
MB90V950MAS → MB90V950AMAS
MB90V950JAS → MB90V950AJAS
■ ELECTRICAL CHARACTERISTICS Added the item “(9) CAN PLL cycle jitter”.
4. AC Characteristics
The vertical lines marked in the left side of the page show the changes.
DS07-13753-3E
65
MB90990 Series
MEMO
66
DS07-13753-3E
MB90990 Series
MEMO
DS07-13753-3E
67
MB90990 Series
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