DS07-12626-3E

The following document contains information on Cypress products.
FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-12626-3E
8-bit Microcontroller
CMOS
F2MC-8FX MB95220H Series
MB95F222H/F223H
MB95F222K/F223K
■ DESCRIPTION
MB95220H are a series of general-purpose, single-chip microcontrollers. In addition to a compact instruction set,
the microcontrollers of these series contain a variety of peripheral resources.
Note: F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
■ FEATURES
• F2MC-8FX CPU core
Instruction set optimized for controllers
• Multiplication and division instructions
• 16-bit arithmetic operations
• Bit test branch instructions
• Bit manipulation instructions, etc.
• Clock
• Selectable main clock source
External clock (up to 32.5 MHz, maximum machine clock frequency: 16.25 MHz)
Main internal CR clock (1/8/10 MHz ±3%, maximum machine clock frequency: 10 MHz)
• Selectable subclock source
External clock (32.768 kHz)
Sub-internal CR clock (Typ: 100 kHz, Min: 50 kHz, Max: 200 kHz)
• Timer
• 8/16-bit composite timer
• Timebase timer
• Watch prescaler
• LIN-UART (MB95F222H/F222K/F223H/F223K)
• Full duplex double buffer
• Capable of clock-synchronized serial data transfer and clock-asynchronized serial data transfer
(Continued)
For the information for microcontroller supports, see the following web site.
http://edevice.fujitsu.com/micom/en-support/
Copyright©2008-2010 FUJITSU SEMICONDUCTOR LIMITED All rights reserved
2010.7
MB95220H Series
(Continued)
• External interrupt
• Interrupt by edge detection (rising edge, falling edge, and both edges can be selected)
• Can be used to wake up the device from different low power consumption (standby) modes
• 8/10-bit A/D converter
• 8-bit or 10-bit resolution can be selected.
• Low power consumption (standby) modes
• Stop mode
• Sleep mode
• Watch mode
• Timebase timer mode
• I/O port (Max: 13) (MB95F222K/F223K)
• General-purpose I/O ports (Max):
CMOS I/O: 11, N-ch open drain: 2
• I/O port (Max: 12) (MB95F222H/F223H)
• General-purpose I/O ports (Max):
CMOS I/O: 11, N-ch open drain: 1
• On-chip debug
• 1-wire serial control
• Serial writing supported (asynchronous mode)
• Hardware/software watchdog timer
• Built-in hardware watchdog timer
• Low-voltage detection reset circuit
• Built-in low-voltage detector
• Clock supervisor counter
• Built-in clock supervisor counter function
• Programmable port input voltage level
• CMOS input level / hysteresis input level
• Flash memory security function
• Protects the contents of flash memory
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DS07-12626-3E
MB95220H Series
■ PRODUCT LINE-UP
Part number
MB95F223H
MB95F222H
MB95F223K
MB95F222K
Parameter
Type
Flash memory product
Clock
supervisor
It supervises the main clock oscillation.
counter
ROM capacity
8 KB
4 KB
8 KB
4 KB
RAM capacity
496 B
240 B
496 B
240 B
Low-voltage
No
Yes
detection reset
Reset input
Dedicated
Selected by software
Number of basic instructions
: 136
Instruction bit length
: 8 bits
Instruction length
: 1 to 3 bytes
CPU functions
Data bit length
: 1, 8, and 16 bits
Minimum instruction execution time : 61.5 ns (with machine clock = 16.25 MHz)
Interrupt processing time
: 0.6 µs (with machine clock = 16.25 MHz)
I/O ports (Max): 12
I/O ports (Max): 13
GeneralCMOS: 11,
CMOS: 11,
purpose I/O
N-ch: 1
N-ch: 2
Timebase timer Interrupt cycle : 0.256 ms - 8.3 s (when external clock = 4 MHz)
Hardware/
Reset generation cycle
software
Main oscillation clock at 10 MHz : 105 ms (Min)
watchdog timer The sub-CR clock can be used as the source clock of the hardware watchdog timer.
Wild register
It can be used to replace three bytes of data.
A wide range of communication speed can be selected by a dedicated reload timer.
It has a full duplex double buffer.
LIN-UART
Clock-synchronized serial data transfer and clock-asynchronized serial data transfer is
enabled.
The LIN function can be used as a LIN master or a LIN slave.
5 ch.
8/10-bit A/D
converter
8-bit or 10-bit resolution can be selected.
1 ch.
8/16-bit
The timer can be configured as an "8-bit timer x 2 channels" or a "16-bit timer x 1 channel".
composite
It has built-in timer function, PWC function, PWM function and input capture function.
timer
Count clock: it can be selected from internal clocks (seven types) and external clocks.
It can output square wave.
6 ch.
External
Interrupt by edge detection (The rising edge, falling edge, or both edges can be selected.)
interrupt
It can be used to wake up the device from standby modes.
1-wire serial control
On-chip debug
It supports serial writing. (asynchronous mode)
(Continued)
DS07-12626-3E
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MB95220H Series
(Continued)
Part number
MB95F223H
MB95F222H
MB95F223K
MB95F222K
Parameter
Watch
prescaler
Eight different time intervals can be selected.
It supports automatic programming, Embedded Algorithm,
write/erase/erase-suspend/erase-resume commands.
It has a flag indicating the completion of the operation of Embedded Algorithm.
Flash memory Number of write/erase cycles: 100000
Data retention time: 20 years
For write/erase, external Vpp(+10 V) input is required.
Flash security feature for protecting the contents of the flash
Standby mode Sleep mode, stop mode, watch mode, timebase timer mode
Package
4
DIP-16P-M06
FPT-16P-M06
DS07-12626-3E
MB95220H Series
■ PACKAGES AND CORRESPONDING PRODUCTS
Part number
MB95F223H MB95F222H MB95F223K MB95F222K
Package
DIP-16P-M06
O
O
O
O
FPT-16P-M06
O
O
O
O
O: Available
DS07-12626-3E
5
MB95220H Series
■ DIFFERENCES AMONG PRODUCTS AND NOTES ON PRODUCT SELECTION
• Current consumption
When using the on-chip debug function, take account of the current consumption of flash erase/program.
For details of current consumption, see “■ ELECTRICAL CHARACTERISTICS”.
• Package
For details of information on each package, see “■ PACKAGES AND CORRESPONDING PRODUCTS” and
“■ PACKAGE DIMENSIONS”.
• Operating voltage
The operating voltage varies, depending on whether the on-chip debug function is used or not.
For details of the operating voltage, see “■ ELECTRICAL CHARACTERISTICS”.
• On-chip debug function
The on-chip debug function requires that VCC, VSS and 1 serial-wire be connected to an evaluation tool. In addition,
if the flash memory data has to be updated, the RST/PF2 pin must also be connected to the same evaluation tool.
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MB95220H Series
■ PIN ASSIGNMENT
X0/PF0
X1/PF1
Vss
X1A/PG2
X0A/PG1
Vcc
RST/PF2
C
DS07-12626-3E
1
2
3
4
5
6
7
8
(TOP VIEW)
16 pins
16
15
14
13
12
11
10
9
P12/EC0/DBG
P07/INT07
P06/INT06/TO01
P05/INT05/AN05/TO00/HCLK2
P04/INT04/AN04/SIN/HCLK1/EC0
P03/INT03/AN03/SOT
P01/AN01
P02/INT02/AN02/SCK
7
MB95220H Series
■ PIN DESCRIPTION (MB95220H Series)
Pin no.
1
2
3
4
5
6
Pin name
PF0
X0
PF1
X1
VSS
PG2
X1A
PG1
X0A
VCC
I/O
circuit
type*
B
B
—
C
C
—
PF2
7
8
RST
C
INT02
AN02
P01
AN01
12
INT03
AN03
General-purpose I/O port
Main clock I/O oscillation pin
Power supply pin (GND)
General-purpose I/O port
Subclock I/O oscillation pin
General-purpose I/O port
Subclock input oscillation pin
Power supply pin
Reset pin
This pin is a dedicated reset pin in MB95F222H/F223H.
—
Capacitor connection pin
General-purpose I/O port
E
External interrupt input pin
A/D converter analog input pin
LIN-UART clock I/O pin
E
P03
11
Main clock input oscillation pin
A
SCK
10
General-purpose I/O port
General-purpose I/O port
P02
9
Function
General-purpose I/O port
A/D converter analog input pin
General-purpose I/O port
E
External interrupt input pin
A/D converter analog input pin
SOT
LIN-UART data output pin
P04
General-purpose I/O port
INT04
External interrupt input pin
AN04
SIN
HCLK1
EC0
F
A/D converter analog input pin
LIN-UART data input pin
External clock input pin
8/16-bit composite timer ch. 0 clock input pin
(Continued)
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DS07-12626-3E
MB95220H Series
(Continued)
Pin no.
Pin name
I/O
circuit
type*
General-purpose I/O port
High-current port
P05
INT05
13
AN05
External interrupt input pin
E
TO00
External clock input pin
General-purpose I/O port
High-current port
P06
INT06
G
TO01
15
P07
INT07
EC0
DBG
External interrupt input pin
8/16-bit composite timer ch. 0 clock input pin
G
P12
16
A/D converter analog input pin
8/16-bit composite timer ch. 0 clock input pin
HCLK2
14
Function
General-purpose I/O port
External interrupt input pin
General-purpose I/O port
H
8/16-bit composite timer ch. 0 clock input pin
DBG input pin
*: For the I/O circuit types, see "■ I/O CIRCUIT TYPE".
DS07-12626-3E
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MB95220H Series
■ I/O CIRCUIT TYPE
Type
Circuit
A
Remarks
Reset input / Hysteresis output
Reset output / Digital output
N-ch
B
P-ch
• N-ch open drain output
• Hysteresis input
• Reset output
Port select
Digital output
N-ch
Digital output
Standby control
Hysteresis input
Clock input
X1
X0
• CMOS output
• Hysteresis input
Standby control / Port select
P-ch
• Oscillation circuit
• High-speed side
Feedback resistance: approx. 1 MΩ
Port select
Digital output
N-ch
Digital output
Standby control
Hysteresis input
C
Port select
R
P-ch
Pull-up control
P-ch
Digital output
N-ch
Digital output
Standby control
Hysteresis input
Clock input
X1A
X0A
Standby control / Port select
Port select
R
• Oscillation circuit
• Low-speed side
Feedback resistance: approx. 10 MΩ
• CMOS output
• Hysteresis input
• Pull-up control available
Pull-up control
Digital output
P-ch
Digital output
N-ch
Digital output
Standby control
Hysteresis input
(Continued)
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MB95220H Series
(Continued)
Type
Circuit
D
Remarks
P-ch
Digital output
Digital output
N-ch
• CMOS output
• Hysteresis input
Standby control
Hysteresis input
E
Pull-up control
R
P-ch
Digital output
P-ch
Digital output
N-ch
• CMOS output
• Hysteresis input
• Pull-up control available
Analog input
A/D control
Standby control
Hysteresis input
F
Pull-up control
R
P-ch
Digital output
P-ch
Digital output
N-ch
Analog input
•
•
•
•
CMOS output
Hysteresis input
CMOS input
Pull-up control available
A/D control
Standby control
Hysteresis input
CMOS input
G
Pull-up control
R
P-ch
Digital output
P-ch
Digital output
N-ch
• Hysteresis input
• CMOS output
• Pull-up control available
Standby control
Hysteresis input
H
Standby control
Hysteresis input
• N-ch open drain output
• Hysteresis input
Digital output
N-ch
DS07-12626-3E
11
MB95220H Series
■ NOTES ON DEVICE HANDLING
• Preventing latch-ups
When using the device, ensure that the voltage applied does not exceed the maximum voltage rating.
In a CMOS IC, if a voltage higher than VCC or a voltage lower than VSS is applied to an input/output pin that is
neither a medium-withstand voltage pin nor a high-withstand voltage pin, or if a voltage out of the rating range
of power supply voltage mentioned in 1. Absolute Maximum Ratings of ■ ELECTRICAL CHARACTERISTICS”
is applied to the VCC pin or the VSS pin, a latch-up may occur.
When a latch-up occurs, power supply current increases significantly, which may cause a component to be
thermally destroyed.
• Stabilizing supply voltage
Supply voltage must be stabilized.
A malfunction may occur when power supply voltage fluctuates rapidly even though the fluctuation is within the
guaranteed operating range of the VCC power supply voltage.
As a rule of voltage stabilization, suppress voltage fluctuation so that the fluctuation in VCC ripple (p-p value) at
the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the standard VCC value, and the transient
fluctuation rate does not exceed 0.1 V/ms at a momentary fluctuation such as switching the power supply.
• Notes on using the external clock
When an external clock is used, oscillation stabilization wait time is required for power-on reset, wake-up from
subclock mode or stop mode.
■ PIN CONNECTION
• Treatment of unused pins
If an unused input pin is left unconnected, a component may be permanently damaged due to malfunctions or
latch-ups. Always pull up or pull down an unused input pin through a resistor of at least 2 kΩ. Set an unused
input/output pin to the output state and leave it unconnected, or set it to the input state and treat it the same as
an unused input pin. If there is an unused output pin, leave it unconnected.
• Power supply pins
To reduce unnecessary electro-magnetic emission, prevent malfunctions of strobe signals due to an increase
in the ground level, and conform to the total output current standard, always connect the VCC pin and the VSS pin
to the power supply and ground outside the device. In addition, connect the current supply source to the VCC pin
and the VSS pin with low impedance.
It is also advisable to connect a ceramic capacitor of approximately 0.1 µF as a bypass capacitor between the
VCC pin and the VSS pin at a location close to this device.
• DBG pin
Connect the DBG pin directly to an external pull-up resistor.
To prevent the device from unintentionally entering the debug mode due to noise, minimize the distance between
the DBG pin and the VCC or VSS pin when designing the layout of the printed circuit board.
The DBG pin should not stay at “L” level after power-on until the reset output is released.
• RST pin
Connect the RST pin directly to an external pull-up resistor.
To prevent the device from unintentionally entering the reset mode due to noise, minimize the distance between
the RST pin and the VCC or VSS pin when designing the layout of the printed circuit board.
The RST/PF2 pin functions as the reset input/output pin after power-on. In addition, the reset output of the RST/
PF2 pin can be enabled by the RSTOE bit of the SYSC register, and the reset input function and the general
purpose I/O function can be selected by the RSTEN bit of the SYSC register.
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MB95220H Series
• C pin
Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. The bypass capacitor for the
VCC pin must have a capacitance larger than CS. For the connection to a smoothing capacitor CS, see the diagram
below. To prevent the device from unintentionally entering a mode to which the device is not set to transit due
to noise, minimize the distance between the C pin and CS and the distance between CS and the VSS pin when
designing the layout of a printed circuit board.
• DBG/RST/C pin connection diagram
DBG
C
RST
Cs
DS07-12626-3E
13
MB95220H Series
■ BLOCK DIAGRAM (MB95220H Series)
F2MC-8FX CPU
PF2*1/RST*2
Flash with security function
(8/4 KB)
Reset with LVD
PF1/X1*2
RAM (496/240 B)
PF0/X0*2
PG2/X1A*2
Oscillator
circuit
CR
oscillator
Interrupt controller
PG1/X0A*2
(P05*3/TO00)
(P04/HCLK1)
8/16-bit composite timer (0)
Clock control
(P06*3/TO01)
(P05*3/HCLK2)
P12*1/EC0, (P04/EC0)
(P12/DBG)
On-chip debug
P02/INT02-P07/INT07
External interrupt
Internal Bus
(P01/AN01-P05*3/AN05)
Wild register
8/10-bit A/D converter
(P02/SCK)
(P03/SOT)
LIN-UART
(P04/SIN)
C
Port
VCC
*1: PF2 and P12 are Nch open drain pins.
VSS
*2: Software option
Port
*3: P05 and P06 are high-current ports.
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MB95220H Series
■ CPU CORE
• Memory Space
The memory space of the MB95220H Series is 64 KB in size, and consists of an I/O area, a data area, and a
program area. The memory space includes areas intended for specific purposes such as general-purpose
registers and a vector table. The memory maps of the MB95220H Series are shown below.
• Memory Maps
MB95F223H/F223K
0000H
I/O
0080H
Access prohibited
0090H
RAM 496 B
0100H
Register
0200H
0280H
Access prohibited
0F80H
Extension I/O
1000H
MB95F222H/F222K
0000H
I/O
0080H
Access prohibited
0090H
RAM 240 B
0100H
Register
0180H
Access prohibited
0F80H
Access prohibited
E000H
Access prohibited
Flash 8 KB
F000H
FFFFH
DS07-12626-3E
Extension I/O
1000H
Flash 4 KB
FFFFH
15
MB95220H Series
■ I/O MAP (MB95220H Series)
Address
Register
abbreviation
Register name
R/W
Initial value
0000H
PDR0
Port 0 data register
R/W
00000000B
0001H
DDR0
Port 0 direction register
R/W
00000000B
0002H
PDR1
Port 1 data register
R/W
00000000B
0003H
DDR1
Port 1 direction register
R/W
00000000B
0004H
—
—
—
0005H
WATR
R/W
11111111B
0006H
—
—
—
0007H
SYCC
System clock control register
R/W
0000X011B
0008H
STBC
Standby control register
R/W
00000XXXB
0009H
RSRR
Reset source register
R
XXXXXXXXB
000AH
TBTC
Timebase timer control register
R/W
00000000B
000BH
WPCR
Watch prescaler control register
R/W
00000000B
000CH
WDTC
Watchdog timer control register
R/W
00000000B
000DH
SYCC2
System clock control register 2
R/W
XX100011B
000EH
to
0015H
—
(Disabled)
—
—
0016H
—
(Disabled)
—
—
0017H
—
(Disabled)
—
—
0018H
to
0027H
—
(Disabled)
—
—
0028H
PDRF
Port F data register
R/W
00000000B
0029H
DDRF
Port F direction register
R/W
00000000B
002AH
PDRG
Port G data register
R/W
00000000B
002BH
DDRG
Port G direction register
R/W
00000000B
002CH
PUL0
Port 0 pull-up register
R/W
00000000B
002DH
to
0034H
—
—
—
(Disabled)
Oscillation stabilization wait time setting register
(Disabled)
(Disabled)
0035H
PULG
Port G pull-up register
R/W
00000000B
0036H
T01CR1
8/16-bit composite timer 01 status control register 1 ch. 0
R/W
00000000B
0037H
T00CR1
8/16-bit composite timer 00 status control register 1 ch. 0
R/W
00000000B
0038H
—
(Disabled)
—
—
0039H
—
(Disabled)
—
—
003AH
to
0048H
—
(Disabled)
—
—
0049H
EIC10
R/W
00000000B
External interrupt circuit control register ch. 2/ch. 3
(Continued)
16
DS07-12626-3E
MB95220H Series
Address
Register
abbreviation
004AH
EIC20
004BH
EIC30
004CH
to
004FH
—
0050H
SCR
0051H
Register name
R/W
Initial value
External interrupt circuit control register ch. 4/ch. 5
R/W
00000000B
External interrupt circuit control register ch. 6/ch. 7
R/W
00000000B
—
—
LIN-UART serial control register
R/W
00000000B
SMR
LIN-UART serial mode register
R/W
00000000B
0052H
SSR
LIN-UART serial status register
R/W
00001000B
0053H
RDR/TDR
LIN-UART receive/transmit data register
R/W
00000000B
0054H
ESCR
LIN-UART extended status control register
R/W
00000100B
0055H
ECCR
LIN-UART extended communication control register
R/W
000000XXB
0056H
to
006BH
—
—
—
006CH
ADC1
8/10-bit A/D converter control register 1
R/W
00000000B
006DH
ADC2
8/10-bit A/D converter control register 2
R/W
00000000B
006EH
ADDH
8/10-bit A/D converter data register (Upper)
R/W
00000000B
006FH
ADDL
8/10-bit A/D converter data register (Lower)
R/W
00000000B
0070H,
0071H
—
—
—
0072H
FSR
R/W
000X0000B
0073H
to
0075H
—
—
—
0076H
WREN
Wild register address compare enable register
R/W
00000000B
0077H
WROR
Wild register data test setting register
R/W
00000000B
0078H
—
—
—
0079H
ILR0
Interrupt level setting register 0
R/W
11111111B
007AH
ILR1
Interrupt level setting register 1
R/W
11111111B
007BH
ILR2
Interrupt level setting register 2
R/W
11111111B
007CH
—
—
—
007DH
ILR4
Interrupt level setting register 4
R/W
11111111B
007EH
ILR5
Interrupt level setting register 5
R/W
11111111B
007FH
—
—
—
0F80H
WRARH0
R/W
00000000B
(Disabled)
(Disabled)
(Disabled)
Flash memory status register
(Disabled)
Mirror of register bank pointer (RP) and direct bank pointer
(DP)
(Disabled)
(Disabled)
Wild register address setting register (Upper) ch. 0
(Continued)
DS07-12626-3E
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MB95220H Series
Address
Register
abbreviation
0F81H
WRARL0
0F82H
WRDR0
0F83H
Register name
R/W
Initial value
Wild register address setting register (Lower) ch. 0
R/W
00000000B
Wild register data setting register ch. 0
R/W
00000000B
WRARH1
Wild register address setting register (Upper) ch. 1
R/W
00000000B
0F84H
WRARL1
Wild register address setting register (Lower) ch. 1
R/W
00000000B
0F85H
WRDR1
Wild register data setting register ch. 1
R/W
00000000B
0F86H
WRARH2
Wild register address setting register (Upper) ch. 2
R/W
00000000B
0F87H
WRARL2
Wild register address setting register (Lower) ch. 2
R/W
00000000B
0F88H
WRDR2
Wild register data setting register ch. 2
R/W
00000000B
0F89H
to
0F91H
—
—
—
0F92H
T01CR0
8/16-bit composite timer 01 status control register 0 ch. 0
R/W
00000000B
0F93H
T00CR0
8/16-bit composite timer 00 status control register 0 ch. 0
R/W
00000000B
0F94H
T01DR
8/16-bit composite timer 01 data register ch. 0
R/W
00000000B
0F95H
T00DR
8/16-bit composite timer 00 data register ch. 0
R/W
00000000B
0F96H
TMCR0
8/16-bit composite timer 00/01 timer mode control register
ch. 0
R/W
00000000B
0F97H
—
(Disabled)
—
—
0F98H
—
(Disabled)
—
—
0F99H
—
(Disabled)
—
—
0F9AH
—
(Disabled)
—
—
0F9BH
—
(Disabled)
—
—
0F9CH
to
0FBBH
—
(Disabled)
—
—
0FBCH
BGR1
LIN-UART baud rate generator register 1
R/W
00000000B
0FBDH
BGR0
LIN-UART baud rate generator register 0
R/W
00000000B
0FBEH
to
0FC2H
—
—
—
0FC3H
AIDRL
R/W
00000000B
0FC4H
to
0FE3H
—
—
—
0FE4H
CRTH
Main CR clock trimming register (Upper)
R/W 1XXXXXXXB
0FE5H
CRTL
Main CR clock trimming register (Lower)
R/W
(Disabled)
(Disabled)
A/D input disable register (Lower)
(Disabled)
000XXXXXB
(Continued)
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MB95220H Series
(Continued)
Address
Register
abbreviation
0FE6H,
0FE7H
—
0FE8H
SYSC
0FE9H
Register name
R/W
Initial value
—
—
System configuration register
R/W
11000011B
CMCR
Clock monitoring control register
R/W
00000000B
0FEAH
CMDR
Clock monitoring data register
R/W
00000000B
0FEBH
WDTH
Watchdog timer selection ID register (Upper)
R/W XXXXXXXXB
0FECH
WDTL
Watchdog timer selection ID register (Lower)
R/W XXXXXXXXB
0FEDH
—
0FEEH
ILSR
0FEFH
to
0FFFH
—
(Disabled)
(Disabled)
Input level select register
(Disabled)
—
—
R/W
00000000B
—
—
• R/W access symbols
R/W : Readable / Writable
R
: Read only
W
: Write only
• Initial value symbols
0
: The initial value of this bit is “0”.
1
: The initial value of this bit is “1”.
X
: The initial value of this bit is undefined.
Note: Do not write to an address that is “(Disabled)”. If a “(Disabled)” address is read, an undefined value is returned.
DS07-12626-3E
19
MB95220H Series
■ INTERRUPT SOURCE TABLE (MB95220H Series)
Vector table address
Priority order of
Bit name of
interrupt sourcinterrupt level es of the same
setting register level (occurring
simultaneously)
Interrupt
request
number
Upper
Lower
External interrupt ch. 4
IRQ0
FFFAH
FFFBH
L00 [1:0]
External interrupt ch. 5
IRQ1
FFF8H
FFF9H
L01 [1:0]
IRQ2
FFF6H
FFF7H
L02 [1:0]
IRQ3
FFF4H
FFF5H
L03 [1:0]
—
IRQ4
FFF2H
FFF3H
L04 [1:0]
8/16-bit composite timer ch. 0
(Lower)
IRQ5
FFF0H
FFF1H
L05 [1:0]
8/16-bit composite timer ch. 0
(Upper)
IRQ6
FFEEH
FFEFH
L06 [1:0]
LIN-UART (reception)
IRQ7
FFECH
FFEDH
L07 [1:0]
LIN-UART (transmission)
IRQ8
FFEAH
FFEBH
L08 [1:0]
—
IRQ9
FFE8H
FFE9H
L09 [1:0]
—
IRQ10
FFE6H
FFE7H
L10 [1:0]
—
IRQ11
FFE4H
FFE5H
L11 [1:0]
—
IRQ12
FFE2H
FFE3H
L12 [1:0]
—
IRQ13
FFE0H
FFE1H
L13 [1:0]
—
IRQ14
FFDEH
FFDFH
L14 [1:0]
—
IRQ15
FFDCH
FFDDH
L15 [1:0]
—
IRQ16
FFDAH
FFDBH
L16 [1:0]
—
IRQ17
FFD8H
FFD9H
L17 [1:0]
8/10-bit A/D converter
IRQ18
FFD6H
FFD7H
L18 [1:0]
Timebase timer
IRQ19
FFD4H
FFD5H
L19 [1:0]
Watch prescaler
IRQ20
FFD2H
FFD3H
L20 [1:0]
—
IRQ21
FFD0H
FFD1H
L21 [1:0]
—
IRQ22
FFCEH
FFCFH
L22 [1:0]
Flash memory
IRQ23
FFCCH
FFCDH
L23 [1:0]
Interrupt source
External interrupt ch. 2
External interrupt ch. 6
External interrupt ch. 3
External interrupt ch. 7
20
High
Low
DS07-12626-3E
MB95220H Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter
Symbol
Power supply voltage*1
Input voltage*1
Output voltage*
1
Maximum clamp current
Total maximum clamp
current
“L” level maximum
output current
Rating
VCC
VSS−0.3
VSS + 6
V
VI1
VSS−0.3
VCC + 0.3
V
Other than PF2*2
VI2
VSS−0.3
10.5
V
PF2
VO
VSS−0.3
VSS + 6
V
*2
ICLAMP
-2
+2
mA
Applicable to specific pins*3
Σ|ICLAMP|
—
20
mA
Applicable to specific pins*3
IOL1
IOL2
“L” level average current
—
“H” level maximum
output current
15
—
mA
mA
12
ΣIOL
—
100
mA
ΣIOLAV
—
50
mA
IOH1
IOH2
—
IOHAV1
“H” level average
current
-15
-15
mA
-4
—
IOHAV2
“H” level total maximum
output current
15
4
IOLAV2
“L” level total average
output current
mA
-8
ΣIOH
—
-100
mA
ΣIOHAV
—
-50
mA
Power consumption
Pd
—
320
mW
Operating temperature
TA
-40
+ 85
°C
Tstg
-55
+ 150
°C
“H” level total average
output current
Storage temperature
Remarks
Max
IOLAV1
“L” level total maximum
output current
Unit
Min
Other than P05, P06
P05, P06
Other than P05, P06
Average output current =
operating current × operating ratio
(1 pin)
P05, P06
Average output current =
operating current × operating ratio
(1 pin)
Total average output current =
operating current × operating ratio
(Total number of pins)
Other than P05, P06
P05, P06
Other than P05, P06
Average output current =
operating current × operating ratio
(1 pin)
P05, P06
Average output current =
operating current × operating ratio
(1 pin)
Total average output current =
operating current × operating ratio
(Total number of pins)
(Continued)
DS07-12626-3E
21
MB95220H Series
(Continued)
*1: The parameter is based on VSS = 0.0 V.
*2: VI and VO must not exceed VCC+0.3 V. VI must not exceed the rated voltage. However, if the maximum current
to/from an input is limited by means of an external component, the ICLAMP rating is used instead of the VI rating.
*3: Applicable to the following pins: P01 to P07, PG1, PG2, PF0, PF1
• Use under recommended operating conditions.
• Use with DC voltage (current).
• The HV (High Voltage) signal is an input signal exceeding the VCC voltage. Always connect a limiting resistor
between the HV (High Voltage) signal and the microcontroller before applying the HV (High Voltage) signal.
• The value of the limiting resistor should be set to a value at which the current to be input to the microcontroller
pin when the HV (High Voltage) signal is input is below the standard value, irrespective of whether the current
is transient current or stationary current.
• When the microcontroller drive current is low, such as in low power consumption modes, the HV (High Voltage)
input potential may pass through the protective diode to increase the potential of the VCC pin, affecting other
devices.
• If the HV (High Voltage) signal is input when the microcontroller power supply is off (not fixed at 0 V), since
power is supplied from the pins, incomplete operations may be executed.
• If the HV (High Voltage) input is input after power-on, since power is supplied from the pins, the voltage of
power supply may not be sufficient to enable a power-on reset.
• Do not leave the HV (High Voltage) input pin unconnected.
• Example of a recommended circuit:
• Input/Output equivalent circuit
Protective diode
VCC
P-ch
Limiting
resistor
HV(High Voltage) input (0 V to 16 V)
N-ch
R
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
22
DS07-12626-3E
MB95220H Series
2. Recommended Operating Conditions
(VSS = 0.0 V)
Parameter
Power supply
voltage
Symbol
VCC
Smoothing
capacitor
CS
Operating
temperature
TA
Value
Min
Max
2.4*1*2
5.5*1
2.3
5.5
2.9
5.5
2.3
5.5
0.022
1
-40
+85
+5
+35
Unit
Remarks
In normal operation
Other than on-chip debug
Hold condition in stop mode mode
V
In normal operation
Hold condition in stop mode
µF
°C
On-chip debug mode
*3
Other than on-chip debug mode
On-chip debug mode
*1: The value varies depending on the operating frequency, the machine clock and the analog guaranteed range.
*2: The value is 2.88 V when the low-voltage detection reset is used.
*3: Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. The bypass capacitor for the
VCC pin must have a capacitance larger than CS. For the connection to a smoothing capacitor CS, see the diagram
below. To prevent the device from unintentionally entering an unknown mode due to noise, minimize the distance
between the C pin and CS and the distance between CS and the VSS pin when designing the layout of a printed
circuit board.
• DBG / RST / C pin connection diagram
*
DBG
C
RST
Cs
*: Since the DBG pin becomes a communication pin in on-chip debug mode,
set a pull-up resistor value suiting the input/output specifications of P12/DBG.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented
on the data sheet. Users considering application outside the listed conditions are advised to contact
their representatives beforehand.
DS07-12626-3E
23
MB95220H Series
3. DC Characteristics
(VCC = 5.0 V±10%, VSS = 0.0 V, TA = -40°C to +85°C)
Parameter
"H" level
input voltage
“L” level
input voltage
Open-drain
output
application
voltage
Symbol
Pin name
Condition
Value
Min
Typ
Max
Unit
Remarks
VIHI
P04
*1
0.7 VCC
—
VCC+0.3
V
When CMOS input
level (hysteresis
input) is selected
VIHS
P01 to P07,
P12,
PF0, PF1,
PG1, PG2
*1
0.8 VCC
—
VCC+0.3
V
Hysteresis input
VIHM
PF2
—
0.7 VCC
—
10.5
V
Hysteresis input*3
VIL
P04
*1
VSS−0.3
—
0.3 VCC
V
When CMOS input
level (hysteresis
input) is selected
VILS
P01 to P07,
P12,
PF0, PF1,
PG1, PG2
*1
VSS−0.3
—
0.2 VCC
V
Hysteresis input
VILM
PF2
—
VSS−0.3
—
0.3 VCC
V
Hysteresis input
VD
PF2, P12
—
VSS−0.3
—
VSS + 5.5
V
“H” level
output
voltage
VOH1
Output pins
other than P05, IOH = -4 mA
P06, P12, PF2
VCC−0.5
—
—
V
VOH2
P05, P06
VCC−0.5
—
—
V
“L” level
output
voltage
VOL1
Output pins
other than P05, IOL = 4 mA
P06
—
—
0.4
V
VOL2
P05, P06
IOL = 12 mA
—
—
0.4
V
ILI
All input pins
0.0 V < VI < VCC
-5
—
+5
µA
When pull-up
resistance is
disabled
RPULL
P01 to P07,
PG1, PG2
VI = 0 V
25
50
100
kΩ
When pull-up
resistance is
enabled
Other than VCC
and VSS
f = 1 MHz
—
5
15
pF
Input leak
current (Hi-Z
output leak
current)
Pull-up
resistance
Input
capacitance
CIN
IOH = -8 mA
(Continued)
24
DS07-12626-3E
MB95220H Series
(VCC = 5.0 V±10%, VSS = 0.0 V, TA = -40°C to +85°C)
Parameter
Symbol
Pin name
Condition
Value
Min
Typ
Max
Unit
Remarks
Flash memory
product (except
mA
writing and
erasing)
—
13
17
—
33.5
39.5
Flash memory
mA product (at writing
and erasing)
—
15
21
mA At A/D conversion
VCC = 5.5 V
FCH = 32 MHz
FMP = 16 MHz
Main sleep mode
(divided by 2)
—
5.5
9
mA
VCC = 5.5 V
FCL = 32 kHz
FMPL = 16 kHz
Subclock mode
(divided by 2)
TA = +25°C
—
65
153
µA
ICCLS
VCC = 5.5 V
FCL = 32 kHz
FMPL = 16 kHz
Subsleep mode
(divided by 2)
TA = +25°C
—
10
84
µA
ICCT
VCC = 5.5 V
FCL = 32 kHz
Watch mode
Main stop mode
TA = +25°C
—
5
30
µA
VCC = 5.5 V
FCRH = 10 MHz
FMP = 10 MHz
Main CR clock
mode
—
8.6
—
mA
VCC = 5.5 V
Sub-CR clock
mode
(divided by 2)
TA = +25°C
—
110
410
µA
VCC = 5.5 V
FCH = 32 MHz
FMP = 16 MHz
Main clock mode
(divided by 2)
ICC
ICCS
ICCL
VCC
(External clock
operation)
Power
supply
current*2
ICCMCR
VCC
ICCSCR
(Continued)
DS07-12626-3E
25
MB95220H Series
(Continued)
Parameter
Symbol
Pin name
VCC = 5.5 V
FCH = 32 MHz
Timebase timer
mode
TA = +25°C
—
1.1
3
mA
ICCH
VCC = 5.5 V
Substop mode
TA = +25°C
—
3.5
22.5
µA
ILVD
Current
consumption for
low-voltage
detection circuit
only
—
37
54
µA
ICRH
Current
consumption for
the internal main
CR oscillator
—
0.5
0.6
mA
Current
consumption for
the internal sub-CR
oscillator
oscillating at
100 kHz
—
20
72
µA
ICCTS
VCC
(External clock
operation)
Power
supply
current*2
Condition
(VCC = 5.0 V±10%, VSS = 0.0 V, TA = -40°C to +85°C)
Value
Unit
Remarks
Min
Typ
Max
ICRL
VCC
Main stop mode
for single clock
selection
*1: The input level of P04 can be switched between “CMOS input level” and “hysteresis input level”. The input level
selection register (ILSR) is used to switch between the two input levels.
*2: • The power supply current is determined by the external clock. When the low-voltage detection option is
selected, the power-supply current will be the sum of adding the current consumption of the low-voltage
detection circuit (ILVD) to one of the value from ICC to ICCH. In addition, when both the low-voltage detection option
and the CR oscillator are selected, the power supply current will be the sum of adding up the current consumption of the low-voltage detection circuit, the current consumption of the CR oscillators (ICRH, ICRL) and a
specified value. In on-chip debug mode, the CR oscillator (ICRH) and the low-voltage detection circuit are always
enabled, and current consumption therefore increases accordingly.
• See "4. AC Characteristics: (1) Clock Timing" for FCH and FCL.
• See "4. AC Characteristics: (2) Source Clock/Machine Clock" for FMP and FMPL.
*3: PF2 act as high voltage supply for the flash memory during program and erase. It can tolerate high voltage
input. For details, see section "6. Flash Memory Program/Erase Characteristics".
26
DS07-12626-3E
MB95220H Series
4. AC Characteristics
(1) Clock Timing
(VCC = 2.4 V to 5.5 V, VSS = 0.0 V, TA = -40°C to +85°C)
Parameter
Symbol Pin name Condition
FCH
FCL
FCRL
Clock cycle time
tHCYL
tLCYL
Min
Typ
X0, X1
—
1
—
X0,
HCLK1,
HCLK2
X1 open
1
—
X0, X1,
HCLK1,
HCLK2
—
—
X0A, X1A
Max
Unit
16.25 MHz
12
Remarks
When the main oscillation
circuit is used
MHz
When the main external
clock is used
Clock frequency
FCRH
Value
—
1
—
32.5
MHz
9.7
10
10.3
MHz
7.76
8
8.24
When the main CR clock is
MHz used
0.97
1
1.03
MHz
9.5
10
10.5
7.6
8
8.4
MHz When the main CR clock is
MHz used
0.95
1
1.05
MHz
—
32.768
—
kHz
When the sub oscillation
circuit is used
—
32.768
—
kHz
When the sub-external
clock is used
—
2.4 V ≤ Vcc < 5.5 V(0 °C ≤ TA ≤ 40 °C)
2.4 V ≤ Vcc < 5.5 V
(-40 °C ≤ TA < 0 °C, 40 °C < TA ≤ 85 °C)
—
—
50
100
200
kHz
When the sub-CR clock is
used
X0, X1
—
61.5
—
1000
ns
When the main oscillation
circuit is used
X0,
HCLK1,
HCLK2
X1 open
83.4
—
1000
ns
X0, X1,
HCLK1,
HCLK2
—
30.8
—
1000
ns
X0A, X1A
—
—
30.5
—
µs
When the external clock is
used
When the subclock is used
(Continued)
DS07-12626-3E
27
MB95220H Series
(Continued)
(VCC = 2.4 V to 5.5 V, VSS = 0.0 V, TA = -40°C to +85°C)
Parameter
Input clock pulse
width
Symbol Pin name Condition
CR oscillation
start time
28
Min
Typ
Max
33.4
—
—
Unit
Remarks
X0,
HCLK1,
HCLK2
X1 open
X0, X1,
HCLK1,
HCLK2
—
12.4
—
—
ns
X0A
—
—
15.2
—
µs
X0,
HCLK1,
HCLK2
X1 open
—
—
5
ns
X0, X1,
HCLK1,
HCLK2
—
—
—
5
ns
tCRHWK
—
—
—
—
80
µs
When the main CR clock is
used
tCRLWK
—
—
—
—
10
µs
When the sub-CR clock is
used
tWH1
tWL1
tWH2
tWL2
Input clock rise
time and fall time
Value
tCR
tCF
ns
When the external clock is
used, the duty ratio should
range between 40% and
60%.
When the external clock is
used
DS07-12626-3E
MB95220H Series
tHCYL
tWH1
tWL1
tCR
tCF
X0, X1, HCLK1, HCLK2
0.8 VCC 0.8 VCC
0.2 VCC
0.2 VCC
0.2 VCC
• Figure of main clock input port external connection
When a crystal oscillator or When the external clock is used When the external clock is
a ceramic oscillator is used
(X1 is open)
used
X0
X0
X1
X1
X0
When the external clock is
used
X1
HCLK1/HCLK2
Open
FCH
FCH
FCH
FCH
tLCYL
tWH2
tCR
X0A
tWL2
tCF
0.8 VCC 0.8 VCC
0.2 VCC
0.2 VCC
0.2 VCC
• Figure of subclock input port external connection
When a crystal oscillator or
a ceramic oscillator is used
X0A
X1A
FCL
When the external clock is used
X0A
X1A
Open
FCL
DS07-12626-3E
29
MB95220H Series
(2) Source Clock/Machine Clock
(VCC = 5.0 V±10%, VSS = 0.0 V, TA = -40°C to +85°C)
Parameter
Source clock
cycle time*1
Symbol
tSCLK
Pin
name
—
FSP
Source clock
frequency
—
FSPL
Machine clock
cycle time*2
(minimum
instruction
execution time)
tMCLK
—
FMPL
Unit
Remarks
Min
Typ
Max
61.5
—
2000
ns
When the main external clock is used
Min: FCH = 32.5 MHz, divided by 2
Max: FCH = 1 MHz, divided by 2
100
—
1000
ns
When the main CR clock is used
Min: FCRH = 10 MHz
Max: FCRH = 1 MHz
—
61
—
µs
When the sub-CR clock is used
FCL = 32.768 kHz, divided by 2
—
20
—
µs
When the sub-oscillation clock is used
FCRL = 100 kHz, divided by 2
0.5
⎯
16.25
1
⎯
10
MHz When the main CR clock is used
—
16.384
—
kHz When the sub-oscillation clock is used
—
50
—
kHz
61.5
—
32000
ns
When the main oscillation clock is used
Min: FSP = 16.25 MHz, no division
Max: FSP = 0.5 MHz, divided by 16
100
—
16000
ns
When the main CR clock is used
Min: FSP = 10 MHz
Max: FSP = 1 MHz, divided by 16
61
—
976.5
µs
When the sub-oscillation clock is used
Min: FSPL = 16.384 kHz, no division
Max: FSPL = 16.384 kHz, divided by 16
20
—
320
µs
When the sub-CR clock is used
Min: FSPL = 50 kHz, no division
Max: FSPL = 50 kHz, divided by 16
0.031
—
16.25
0.0625
—
10
1.024
—
16.384
3.125
—
50
MHz When the main oscillation clock is used
—
FMP
Machine clock
frequency
Value
When the sub-CR clock is used
FCRL = 100 kHz, divided by 2
MHz When the main oscillation clock is used
MHz When the main CR clock is used
kHz When the sub-oscillation clock is used
kHz
When the sub-CR clock is used
FCRL = 100 kHz
*1: This is the clock before it is divided according to the division ratio set by the machine clock division ratio selection
bits (SYCC : DIV1 and DIV0) . This source clock is divided to become a machine clock according to the division
ratio set by the machine clock division ratio selection bits (SYCC : DIV1 and DIV0) . In addition, a source clock
can be selected from the following.
• Main clock divided by 2
• Main CR clock
• Subclock divided by 2
• Sub-CR clock divided by 2
(Continued)
30
DS07-12626-3E
MB95220H Series
(Continued)
*2: This is the operating clock of the microcontroller. A machine clock can be selected from the following.
• Source clock (no division)
• Source clock divided by 4
• Source clock divided by 8
• Source clock divided by 16
DS07-12626-3E
31
MB95220H Series
• Schematic diagram of the clock generation block
Divided
by 2
FCH
(main oscillation)
FCRH
(Internal main
CR clock)
FCL
(sub-oscillation)
FCRL
(Internal subCR clock)
Divided
by 2
Division
circuit
x 1
x 1/4
x 1/8
x1/16
SCLK
(source clock)
Divided
by 2
MCLK
(machine clock)
Machine clock division
ratio select bits
(SYCC : DIV1, DIV0)
Clock mode select bits
(SYCC2: RCS1, RCS0)
• Operating voltage - Operating frequency (When TA = -40°C to +85°C)
MB95220H (without the on-chip debug function)
5.5
Operating voltage (V)
5.0
A/D converter operation range
4.0
3.5
3.0
2.4
16 kHz
3 MHz
10 MHz
16.25 MHz
Source clock frequency (FSP/FSPL)
• Operating voltage - Operating frequency (When TA = -40°C to +85°C)
MB95220H (with the on-chip debug function)
5.5
Operating voltage (V)
5.0
A/D converter operation range
4.0
3.5
2.9
3.0
16 kHz
12.5 MHz
3 MHz
16.25 MHz
Source clock frequency (FSP)
32
DS07-12626-3E
MB95220H Series
(3) External Reset
(VCC = 5.0 V±10%, VSS = 0.0 V, TA = -40°C to +85°C)
Parameter
Value
Symbol
RST “L” level pulse
width
tRSTL
Unit
Remarks
Min
Max
2 tMCLK*1
—
ns
In normal operation
Oscillation time of the
oscillator*2+100
—
µs
In stop mode, subclock mode,
sub-sleep mode, watch mode,
and power on
100
—
µs
In timebase timer mode
*1: See “ (2) Source Clock/Machine Clock” for tMCLK.
*2: The oscillation time of an oscillator is the time for it to reach 90% of its amplitude. The crystal oscillator has an
oscillation time of between several ms and tens of ms. The ceramic oscillator has an oscillation time of between
hundreds of µs and several ms. The external clock has an oscillation time of 0 ms. The CR oscillator clock has
an oscillation time of between several µs and several ms.
• In normal operation
tRSTL
RST
0.2 VCC
0.2 VCC
• In stop mode, subclock mode, subsleep mode, watch mode and power-on
tRSTL
RST
X0
0.2 VCC
0.2 VCC
90% of
amplitude
Internal
operating
clock
Oscillation
time of
oscillator
Internal reset
DS07-12626-3E
100 μs
Oscillation stabilization wait time
Execute instruction
33
MB95220H Series
(4) Power-on Reset
(VSS = 0.0 V, TA = -40°C to +85°C)
Parameter
Symbol
Condition
Power supply rising time
tR
Power supply cutoff time
tOFF
tR
Value
Unit
Min
Max
—
—
50
ms
—
1
—
ms
Remarks
Wait time until power-on
tOFF
2.5 V
VCC
0.2 V
0.2 V
0.2 V
Note: A sudden change of power supply voltage may activate the power-on reset function. When changing the
power supply voltage during the operation, set the slope of rising to a value below within 30 mV/ms as shown
below.
VCC
2.3 V
Set the slope of rising to
a value below 30 mV/ms.
Hold condition in stop mode
VSS
34
DS07-12626-3E
MB95220H Series
(5) Peripheral Input Timing
(VCC = 5.0 V±10%, VSS = 0.0 V, TA = -40°C to +85°C)
Parameter
Symbol
Peripheral input “H” pulse width
tILIH
Peripheral input “L” pulse width
tIHIL
Value
Pin name
INT02 to INT07, EC0
Unit
Min
Max
2 tMCLK*
—
ns
2 tMCLK*
—
ns
* See “(2) Source Clock/Machine Clock” for tMCLK.
tILIH
INT02 to INT07,
EC0
DS07-12626-3E
0.8 VCC
tIHIL
0.8 VCC
0.2 VCC
0.2 VCC
35
MB95220H Series
(6) LIN-UART Timing (Available only in MB95F222H/F222K/F223H/F223K)
Sampling is executed at the rising edge of the sampling clock*1, and serial clock delay is disabled*2.
(ESCR register:SCES bit = 0, ECCR register:SCDE bit = 0)
(VCC = 5.0 V±10%, AVSS = VSS = 0.0 V, TA = -40°C to +85°C)
Parameter
Serial clock cycle time
Symbol Pin name
tSCYC
SCK
tSLOVI
t
Valid SIN → SCK ↑
tIVSHI
SCK ↑→ valid SIN hold time
tSHIXI
Internal clock
SCK, SOT
operation output pin:
SCK, SIN
CL = 80 pF+1 TTL
SCK, SIN
Serial clock “L” pulse width
tSLSH
SCK
SCK ↓→ SOT delay time
Serial clock “H” pulse width
Value
Condition
tSHSL
SCK
SCK ↓→ SOT delay time
tSLOVE
SCK, SOT
Valid SIN → SCK ↑
tIVSHE
SCK, SIN
SCK ↑→ valid SIN hold time
tSHIXE
SCK, SIN
Max
5 tMCLK*3
—
ns
-95
+95
ns
MCLK 3
* +190
—
ns
0
—
ns
3 tMCLK*3−tR
—
ns
* +95
—
ns
t
External clock
operation output pin:
CL = 80 pF+1 TTL
Unit
Min
MCLK 3
—
2t
* +95
MCLK 3
ns
190
—
ns
tMCLK*3+95
—
ns
SCK fall time
tF
SCK
—
10
ns
SCK rise time
tR
SCK
—
10
ns
*1: There is a function used to choose whether the sampling of reception data is performed at a rising edge or a
falling edge of the serial clock.
*2: The serial clock delay function is a function used to delay the output signal of the serial clock for half the clock.
*3: See “(2) Source Clock/Machine Clock” for tMCLK.
36
DS07-12626-3E
MB95220H Series
• Internal shift clock mode
tSCYC
2.4 V
SCK
0.8 V
0.8 V
tSLOVI
2.4 V
SOT
0.8 V
tIVSHI
tSHIXI
0.8 VCC 0.8 VCC
SIN
0.2 VCC 0.2 VCC
• External shift clock mode
tSLSH
tSHSL
0.8 VCC
0.8 VCC
0.8 VCC
SCK
0.2 VCC
tF
0.2 VCC
tR
tSLOVE
2.4 V
SOT
0.8 V
tIVSHE
tSHIXE
0.8 VCC 0.8 VCC
SIN
0.2 VCC 0.2 VCC
DS07-12626-3E
37
MB95220H Series
Sampling is executed at the falling edge of the sampling clock*1, and serial clock delay is disabled*2.
(ESCR register:SCES bit = 1, ECCR register:SCDE bit = 0)
(VCC = 5.0 V±10%, VSS = 0.0 V, TA = -40°C to +85°C)
Parameter
Symbol Pin name
Serial clock cycle time
tSCYC
SCK
SCK ↑→ SOT delay time
tSHOVI
SCK, SOT
Value
Condition
Internal clock
operation output pin:
CL = 80 pF+1 TTL
Unit
Min
Max
5 tMCLK*3
—
ns
-95
+95
ns
MCLK 3
* +190
—
ns
0
—
ns
Valid SIN → SCK ↓
tIVSLI
SCK, SIN
SCK ↓→ valid SIN hold time
tSLIXI
SCK, SIN
Serial clock “H” pulse width
tSHSL
SCK
3 tMCLK*3−tR
—
ns
Serial clock “L” pulse width
tSLSH
SCK
tMCLK*3+95
—
ns
SCK ↑→ SOT delay time
tSHOVE
SCK, SOT
Valid SIN → SCK ↓
tIVSLE
SCK, SIN
SCK ↓→ valid SIN hold time
tSLIXE
SCK, SIN
External clock
operation output pin:
CL = 80 pF+1 TTL
t
—
2t
* +95
MCLK 3
ns
190
—
ns
tMCLK*3+95
—
ns
SCK fall time
tF
SCK
—
10
ns
SCK rise time
tR
SCK
—
10
ns
*1: There is a function used to choose whether the sampling of reception data is performed at a rising edge or a
falling edge of the serial clock.
*2: The serial clock delay function is a function used to delay the output signal of the serial clock for half the clock.
*3: See “(2) Source Clock/Machine Clock” for tMCLK.
38
DS07-12626-3E
MB95220H Series
• Internal shift clock mode
tSCYC
2.4 V
2.4 V
SCK
0.8 V
tSHOVI
2.4 V
SOT
0.8 V
tIVSLI
tSLIXI
0.8 VCC 0.8 VCC
SIN
0.2 VCC 0.2 VCC
• External shift clock mode
tSHSL
0.8 VCC
tSLSH
0.8 VCC
SCK
0.2 VCC
tR
tF
0.2 VCC
0.2 VCC
tSHOVE
2.4 V
SOT
0.8 V
tIVSLE
tSLIXE
0.8 VCC 0.8 VCC
SIN
0.2 VCC 0.2 VCC
DS07-12626-3E
39
MB95220H Series
Sampling is executed at the rising edge of the sampling clock*1, and serial clock delay is enabled*2.
(ESCR register:SCES bit = 0, ECCR register:SCDE bit = 1)
(VCC = 5.0 V±10%, VSS = 0.0 V, TA = -40°C to +85°C)
Parameter
Symbol Pin name
Serial clock cycle time
tSCYC
SCK
SCK ↑→ SOT delay time
tSHOVI
SCK, SOT
Valid SIN → SCK ↓
tIVSLI
SCK, SIN
SCK ↓→ valid SIN hold time
tSLIXI
SCK, SIN
SOT → SCK ↓ delay time
tSOVLI
SCK, SOT
Value
Condition
Internal clock
operation output pin:
CL = 80 pF+1 TTL
t
Unit
Min
Max
5 tMCLK*3
—
ns
-95
+95
ns
MCLK 3
* +190
—
ns
0
—
ns
—
4 tMCLK*3
ns
*1: There is a function used to choose whether the sampling of reception data is performed at a rising edge or a
falling edge of the serial clock.
*2: The serial clock delay function is a function that delays the output signal of the serial clock for half clock.
*3: See “(2) Source Clock/Machine Clock” for tMCLK.
tSCYC
2.4 V
SCK
0.8 V
SOT
2.4 V
2.4 V
0.8 V
0.8 V
tIVSLI
SIN
40
0.8 V
tSHOVI
tSOVLI
tSLIXI
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
DS07-12626-3E
MB95220H Series
Sampling is executed at the falling edge of the sampling clock*1, and serial clock delay is enabled*2.
(ESCR register:SCES bit = 1, ECCR register:SCDE bit = 1)
(VCC = 5.0 V±10%, VSS = 0.0 V, TA = -40°C to +85°C)
Parameter
Symbol Pin name
Serial clock cycle time
tSCYC
SCK
SCK ↓→ SOT delay time
tSLOVI
SCK, SOT
Valid SIN → SCK ↑
tIVSHI
SCK, SIN
SCK ↑→ valid SIN hold time
tSHIXI
SCK, SIN
SOT → SCK ↑ delay time
tSOVHI
SCK, SOT
Value
Condition
Internal clock
operation output pin:
CL = 80 pF+1 TTL
t
Unit
Min
Max
5 tMCLK*3
—
ns
-95
+95
ns
MCLK 3
* +190
—
ns
0
—
ns
—
4 tMCLK*3
ns
*1:There is a function used to choose whether the sampling of reception data is performed at a rising edge or a
falling edge of the serial clock.
*2: The serial clock delay function is a function that delays the output signal of the serial clock for half clock.
*3: See “(2) Source Clock/Machine Clock” for tMCLK.
tSCYC
2.4 V
SCK
2.4 V
0.8 V
tSOVHI
SOT
2.4 V
2.4 V
0.8 V
0.8 V
tIVSHI
SIN
DS07-12626-3E
tSLOVI
tSHIXI
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
41
MB95220H Series
(7) Low-voltage Detection
(VSS = 0.0 V, TA = -40°C to +85°C)
Parameter
Symbol
Value
Min
Typ
Max
Unit
Remarks
Release voltage
VDL+
2.52
2.7
2.88
V
At power supply rise
Detection voltage
VDL−
2.42
2.6
2.78
V
At power supply fall
Hysteresis width
VHYS
70
100
—
mV
Power supply start voltage
Voff
—
—
2.3
V
Power supply end voltage
Von
4.9
—
—
V
1
—
—
µs
Slope of power supply that the reset
release signal generates
—
3000
—
µs
Slope of power supply that the reset
release signal generates within the
rating (VDL+)
300
—
—
µs
Slope of power supply that the reset
detection signal generates
—
300
—
µs
Slope of power supply that the reset
detection signal generates within the
rating (VDL-)
Power supply voltage
change time
(at power supply rise)
tr
Power supply voltage
change time
(at power supply fall)
tf
Reset release delay time
td1
—
—
300
µs
Reset detection delay time
td2
—
—
20
µs
42
DS07-12626-3E
MB95220H Series
VCC
Von
Voff
time
tf
tr
VDL+
VHYS
VDL-
Internal reset signal
time
td2
DS07-12626-3E
td1
43
MB95220H Series
5. A/D Converter
(1) A/D Converter Electrical Characteristics
(VCC = 4.0 V to 5.5 V, VSS = 0.0 V, TA = -40°C to +85°C)
Parameter
Symbol
Value
Unit
Min
Typ
Max
Resolution
—
—
10
bit
Total error
-3
—
+3
LSB
-2.5
—
+2.5
LSB
-1.9
—
+1.9
LSB
Linearity error
—
Differential linear
error
Remarks
Zero transition
voltage
VOT
VSS−1.5 LSB
VSS+0.5 LSB
VSS+2.5 LSB
V
Full-scale transition
voltage
VFST
VCC−4.5 LSB
VCC−2 LSB
VCC+0.5 LSB
V
0.9
—
16500
µs
4.5 V ≤ VCC ≤ 5.5 V
1.8
—
16500
µs
4.0 V ≤ VCC < 4.5 V
0.6
—
∞
µs
4.5 V ≤ VCC ≤ 5.5 V,
with external
impedance < 5.4 kΩ
1.2
—
∞
µs
4.0 V ≤ VCC ≤ 4.5 V,
with external
impedance < 2.4 kΩ
Compare time
Sampling time
—
—
Analog input current
IAIN
-0.3
—
+0.3
µA
Analog input voltage
VAIN
VSS
—
VCC
V
44
DS07-12626-3E
MB95220H Series
(2) Notes on Using the A/D Converter
• External impedance of analog input and its sampling time
• The A/D converter has a sample and hold circuit. If the external impedance is too high to keep sufficient
sampling time, the analog voltage charged to the capacitor of the internal sample and hold circuit is insufficient,
adversely affecting A/D conversion precision. Therefore, to satisfy the A/D conversion precision standard,
considering the relationship between the external impedance and minimum sampling time, either adjust the
register value and operating frequency or decrease the external impedance so that the sampling time is longer
than the minimum value. In addition, if sufficient sampling time cannot be secured, connect a capacitor of
about 0.1 µF to the analog input pin.
• Analog input equivalent circuit
Analog input
Comparator
R
C
During sampling: ON
~ 1.95 kΩ (Max), C ~
4.5 V <
~ 17 pF (Max)
= VCC <
= 5.5 V : R ~
4.0 V <
~ 8.98 kΩ (Max), C ~
~ 17 pF (Max)
= VCC < 4.5 V : R ~
Note: The values are reference values.
• Relationship between external impedance and minimum sampling time
[External impedance = 0 kΩ to 20 kΩ]
[External impedance = 0 kΩ to 100 kΩ]
20
External impedance [kΩ]
External impedance [kΩ]
100
90
80
70
60
(VCC >
= 4.5 V)
50
(VCC >
= 4.0 V)
40
30
20
10
18
16
14
12
(VCC >
= 4.5 V)
10
(VCC >
= 4.0 V)
8
6
4
2
0
0
0
2
4
6
8
10
12
Minimum sampling time [μs]
14
0
1
2
3
4
Minimum sampling time [μs]
• A/D conversion error
As |VCC−VSS| decreases, the A/D conversion error increases proportionately.
DS07-12626-3E
45
MB95220H Series
(3) Definitions of A/D Converter Terms
• Resolution
It indicates the level of analog variation that can be distinguished by the A/D converter.
When the number of bits is 10, analog voltage can be divided into 210 = 1024.
• Linearity error (unit: LSB)
It indicates how much an actual conversion value deviates from the straight line connecting
the zero transition point (“00 0000 0000” ← → “00 0000 0001”) of a device to
the full-scale transition point (“11 1111 1111“ ← → “11 1111 1110”) of the same device.
• Differential linear error (unit : LSB)
It indicates how much the input voltage required to change the output code by 1 LSB deviates from an ideal
value.
• Total error (unit: LSB)
It indicates the difference between an actual value and a theoretical value. The error can be caused by a zero
transition error, a full-scale transition errors, a linearity error, a quantum error, or noise.
Ideal I/O characteristics
3FF
Total error
3FF
VFST
3FE
3FE
2 LSB
3FD
Digital output
Digital output
3FD
004
VOT
003
Actual conversion
characteristic
{1 LSB x (N-1) + 0.5 LSB}
004
VNT
003
1 LSB
002
Actual conversion
characteristic
002
Ideal characteristic
001
001
0.5 LSB
VSS
Analog input
1 LSB =
VCC
VCC - VSS
(V)
1024
VSS
Analog input
VCC
VNT - {1 LSB x (N - 1) + 0.5 LSB}
Total error of
=
[LSB]
digital output N
1 LSB
N : A/D converter digital output value
VNT: Voltage at which the digital output transits from (N - 1) to N
(Continued)
46
DS07-12626-3E
MB95220H Series
(Continued)
Zero transition error
Full-scale transition error
004
Ideal characteristic
Actual conversion
characteristic
3FF
Actual conversion
characteristic
Digital output
Digital output
003
002
Ideal
characteristic
Actual conversion
characteristic
3FE
VFST
(measurement
value)
3FD
Actual conversion
characteristic
001
3FC
VOT (measurement value)
VSS
VCC
Analog input
VSS
Linearity error
Differential linearity error
Ideal characteristic
Actual conversion
characteristic
3FF
N+1
3FE
Actual conversion
characteristic
Digital output
3FD
VFST
(measurement
value)
VNT
004
Actual conversion
characteristic
Digital output
{1 LSB x N + VOT}
003
V(N+1)T
N
VNT
N-1
Ideal
characteristic
002
VCC
Analog input
Actual conversion
characteristic
N-2
001
VOT (measurement value)
VSS
Analog input
VCC
VNT - {1 LSB x N + VOT}
Linearity error
=
of digital output N
1 LSB
VSS
Analog input
VCC
V(N+1)T - VNT
Differential linear error
=
- 1
of digital output N
1 LSB
N : A/D converter digital output value
VNT: Voltage at which the digital output transits from (N - 1) to N
VOT (ideal value) = VSS + 0.5 LSB [V]
VFST (ideal value) = VCC - 2 LSB [V]
DS07-12626-3E
47
MB95220H Series
6. Flash Memory Program/Erase Characteristics
Parameter
Value
Unit
Remarks
Min
Typ
Max
Chip erase time
—
1*1
15*2
s
00H programming time prior to erasure is
excluded.
Byte programming time
—
32
3600
µs
System-level overhead is excluded.
Erase/program voltage
9.5
10
10.5
V
The erase/program voltage must be
applied to the PF2 pin in erase/program.
Current drawn on PF2
—
—
5.0
mA
Erase/program cycle
—
100000
—
cycle
Power supply voltage at erase/
program
3.0
—
5.5
V
Flash memory data retention
time
20*3
—
—
year
Current consumption of PF2 pin during
flash memory program/erase
Average TA = +85°C
*1: TA = +25°C, VCC = 5.0 V, 100000 cycles
*2: TA = +85°C, VCC = 4.5 V, 100000 cycles
*3: This value is converted from the result of a technology reliability assessment. (The value is converted from the
result of a high temperature accelerated test by using the Arrhenius equation with the average temperature being
+85°C) .
48
DS07-12626-3E
MB95220H Series
■ SAMPLE ELECTRICAL CHARACTERISTICS
• Power supply current•temperature
ICC - VCC
TA=+25°C, FMP=2, 4, 8, 10, 16 MHz (divided by 2)
Main clock mode with the external clock operating
ICC - TA
VCC=5.5 V, FMP=10, 16 MHz (divided by 2)
Main clock mode with the external clock operating
20
20
15
15
FMP=16 MHz
10
FMP=10 MHz
FMP=8 MHz
5
ICC[mA]
ICC[mA]
FMP=16 MHz
10
FMP=10 MHz
5
FMP=4 MHz
FMP=2 MHz
0
0
2
3
4
5
6
-50
7
0
+50
+100
+150
TA[°C]
ICCS - VCC
TA=+25°C, FMP=2, 4, 8, 10, 16 MHz (divided by 2)
Main sleep mode with the external clock operating
ICCS - TA
VCC=5.5 V, FMP=10, 16 MHz (divided by 2)
Main sleep mode with the external clock operating
20
20
15
15
ICCS[mA]
ICCS[mA]
VCC[V]
10
FMP=16 MHz
FMP=10 MHz
FMP=8 MHz
FMP=4 MHz
FMP=2 MHz
5
0
3
4
5
6
FMP=16 MHz
5
FMP=10 MHz
0
-50
7
0
+50
+100
+150
VCC[V]
TA[°C]
ICCL - VCC
TA=+25°C, FMPL=16 kHz (divided by 2)
Subclock mode with the external clock operating
ICCL - TA
VCC=5.5 V, FMPL=16 kHz (divided by 2)
Subclock mode with the external clock operating
100
100
75
75
ICCL[µA]
ICCL[µA]
2
10
50
50
25
25
0
0
2
3
4
5
VCC[V]
6
7
-50
0
+50
+100
+150
TA[°C]
(Continued)
DS07-12626-3E
49
MB95220H Series
ICCLS - VCC
TA=+25°C, FMPL=16 kHz (divided by 2)
Subsleep mode with the external clock operating
ICCLS - TA
VCC=5.5 V, FMPL=16 kHz (divided by 2)
Subsleep mode with the external clock operating
75
75
ICCLS[µA]
100
ICCLS[µA]
100
50
50
25
25
0
0
2
3
4
5
6
-50
7
0
+50
100
100
75
75
ICCT[µA]
ICCT[µA]
+150
ICCT - TA
V=5.5 V, FMPL=16 kHz (divided by 2)
Clock mode with the external clock operating
ICCT - VCC
TA=+25°C, FMPL=16 kHz (divided by 2)
Clock mode with the external clock operating
50
25
50
25
0
0
2
3
4
5
6
7
-50
0
VCC[V]
+50
+100
+150
TA[°C]
ICTS - VCC
TA=+25°C, FMP=2, 4, 8, 10, 16 MHz (divided by 2)
Timebase timer mode with the external clock operating
ICTS - TA
V=5.5 V, FMP=10, 16 MHz (divided by 2)
Timebase timer mode with the external clock operating
2.0
2.0
1.5
1.5
1.0
FMP=16 MHz
0.5
FMP=10 MHz
FMP=8 MHz
ICTS[mA]
ICTS[mA]
+100
TA[°C]
VCC[V]
FMP=16 MHz
1.0
FMP=10 MHz
0.5
FMP=4 MHz
FMP=2 MHz
0.0
0.0
2
3
4
5
VCC[V]
6
7
-50
0
+50
+100
+150
TA[°C]
(Continued)
50
DS07-12626-3E
MB95220H Series
ICCH - VCC
TA=+25°C, FMPL=(stop)
Substop mode wtih the external clock stopping
ICCH - TA
V=5.5 V, FMPL=(stop)
Substop mode with the external clock stopping
20
20
15
15
ICCH[µA]
ICCH[µA]
(Continued)
10
10
5
5
0
0
2
3
4
5
6
7
-50
0
VCC[V]
ICCMCR - VCC
TA=+25°C, FMP=1, 8, 10 MHz (no division)
Main clock mode with the internal main CR clock operating
+100
+150
ICCMCR - TA
V=5.5 V, FMPL=1, 8, 10 MHz (no division)
Main clock mode with the internal main CR clock operating
20
20
15
15
10
FMP=10 MHz
FMP=8 MHz
ICCMCR[mA]
ICCMCR[mA]
+50
TA[°C]
5
10
FMP=10 MHz
FMP=8 MHz
5
FMP=1 MHz
FMP=1 MHz
0
0
2
3
4
5
6
7
-50
0
+50
+100
+150
TA[°C]
ICCSCR - VCC
TA=+25°C, FMPL=50 kHz (divided by 2)
Subclock mode with the internal sub-CR clock operating
ICCSCR - TA
VCC=5.5 V, FMPL=50 kHz (divided by 2)
Subclock mode with the internal sub-CR clock operating
200
200
150
150
FMPL=50 kHz
100
50
ICCSCR[µA]
ICCSCR[µA]
VCC[V]
FMPL=50 kHz
100
50
0
0
2
3
4
5
VCC[V]
DS07-12626-3E
6
7
-50
0
+50
+100
+150
TA[°C]
51
MB95220H Series
• Input voltage
VIHS - VCC and VILS - VCC
TA=+25°C
5
5
4
4
VIHI
3
VIHS
VIHS/VILS[V]
VIHI/VILI[V]
VIHI - VCC and VILI - VCC
TA=+25°C
VILI
2
3
VILS
2
1
1
0
0
2
3
4
5
6
7
2
3
VCC[V]
4
5
6
7
VCC[V]
VIHM - VCC and VILM - VCC
TA=+25°C
5
VIHM/VILM[V]
4
3
VIHM
VILM
2
1
0
2
3
4
5
6
7
VCC[V]
52
DS07-12626-3E
MB95220H Series
• Output voltage
(VCC-VOH2) - IOH
TA=+25°C
(VCC-VOH1) - IOH
TA=+25°C
1.0
1.0
0.8
VCC-VOH2[V]
VCC-VOH1[V]
0.8
0.6
0.4
0.6
0.4
0.2
0.2
0.0
0.0
0
-2
-4
-6
-8
0
-10
-2
-4
-8
-10
VCC=2.4 V
VCC=2.7 V
VCC=3.5 V
VCC=4.5 V
VCC=5.0 V
VCC=5.5 V
VOL2 - IOL
TA=+25°C
VOL1 - IOL
TA=+25°C
1.0
1.0
0.8
0.8
0.6
0.6
VOL2[V]
VOL1[V]
-6
IOH[mA]
IOH[mA]
VCC=2.4 V
VCC=2.7 V
VCC=3.5 V
VCC=4.5 V
VCC=5.0 V
VCC=5.5 V
0.4
0.2
0.4
0.2
0.0
0.0
0
DS07-12626-3E
2
4
6
8
10
0
2
4
6
IOL[mA]
IOL[mA]
VCC=2.4 V
VCC=2.7 V
VCC=3.5 V
VCC=4.5 V
VCC=5.0 V
VCC=5.5 V
VCC=2.4 V
VCC=2.7 V
VCC=3.5 V
VCC=4.5 V
VCC=5.0 V
VCC=5.5 V
8
10
12
53
MB95220H Series
• Pull-up
RPULL - VCC
TA=+25°C
250
RPULL[kΩ]
200
150
100
50
0
2
3
4
5
6
VCC[V]
54
DS07-12626-3E
MB95220H Series
■ MASK OPTIONS
No.
Part Number
MB95F222H
MB95F223H
MB95F222K
MB95F223K
Selectable/Fixed
Fixed
Fixed
1
Low-voltage detection reset
Without low-voltage detection
• With low-voltage detection reset
reset
• Without low-voltage detection reset
With low-voltage detection
reset
2
Reset
• With dedicated reset input
• Without dedicated reset input
Without dedicated reset input
With dedicated reset input
■ ORDERING INFORMATION
Part Number
Package
MB95F222HPH-G-SNE2
MB95F222KPH-G-SNE2
MB95F223HPH-G-SNE2
MB95F223KPH-G-SNE2
16-pin plastic DIP
(DIP-16P-M06)
MB95F222HPF-G-SNE1
MB95F222KPF-G-SNE1
MB95F223HPF-G-SNE1
MB95F223KPF-G-SNE1
16-pin plastic SOP
(FPT-16P-M06)
DS07-12626-3E
55
MB95220H Series
■ PACKAGE DIMENSIONS
16-pin plastic DIP
Lead pitch
2.54 mm
Sealing method
Plastic mold
(DIP-16P-M06)
16-pin plastic DIP
(DIP-16P-M06)
19.55
.770
+0.20
–0.30
+.008
–.012
INDEX
6.35±0.25
(.250±.010)
7.62(.300)
TYP.
0.50(.020)
MIN
4.36(.172)MAX
0.25±0.05
(.010±.002)
3.00(.118)MIN
1.52 –0
MAX
.060 –0
+.012
+0.30
0.99 –0
+.012
.039 –0
C
+0.30
1.27(.050)
0.46±0.08
(.018±.003)
2.54(.100)
TYP.
2006-2010 FUJITSU SEMICONDUCTOR LIMITED D16125S-c-1-3
15° MAX
Dimensions in mm (inches).
Note: The values in parentheses are reference values
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
(Continued)
56
DS07-12626-3E
MB95220H Series
(Continued)
16-pin plastic SOP
Lead pitch
1.27 mm
Package width ×
package length
5.3 × 10.15 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
2.25 mm MAX
Weight
0.20 g
Code
(Reference)
P-SOP16-5.3×10.15-1.27
(FPT-16P-M06)
16-pin plastic SOP
(FPT-16P-M06)
Note 1) *1 : These dimensions include resin protrusion.
Note 2) *2 : These dimensions do not include resin protrusion.
Note 3) Pins width and pins thickness include plating thickness.
Note 4) Pins width do not include tie bar cutting remainder.
+0.25
+.010
+0.03
*110.15 –0.20 .400 –.008
0.17 –0.04
+.001
16
.007 –.002
9
*2 5.30±0.30
7.80±0.40
(.209±.012) (.307±.016)
INDEX
Details of "A" part
+0.25
2.00 –0.15
+.010
.079 –.006
1
"A"
8
1.27(.050)
0.47±0.08
(.019±.003)
0.13(.005)
(Mounting height)
0.25(.010)
0~8°
M
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
+0.10
0.10 –0.05
+.004
.004 –.002
(Stand off)
0.10(.004)
C
2002-2010 FUJITSU SEMICONDUCTOR LIMITED F16015S-c-4-9
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
DS07-12626-3E
57
MB95220H Series
■ MAIN CHANGES IN THIS EDITION
Page
21
Section
■ ELECTRICAL CHARACTERISTICS Changed the characteristics of Input voltage.
1. Absolute Maximum Ratings
3. DC Characteristics
24
Added the footnote *3.
4. AC Characteristics
(1) Clock Timing
Added a figure of HCLK1/HCLK2.
(2) Source Clock/Machine Clock
Corrected the graph of Operating voltage - Operating frequency
(with the on-chip debug function).
(Corrected the pitch)
(3) External Reset
Added and power on to the remarks column.
6. Flash Memory Program/
Erase Characteristics
Added the row of Current drawn on PF2.
32
33
48
Corrected the maximum value of “H” level input voltage for PF2
pin.
VCC + 0.3 → 10.5
Corrected the maximum value of Open-drain output application
voltage.
0.2Vcc → Vss + 5.5
26
29
Change Results
Corrected the minimum value of Power supply voltage at erase/
program.
4.5 → 3.0
The vertical lines marked in the left side of the page show the changes.
58
DS07-12626-3E
MB95220H Series
MEMO
DS07-12626-3E
59
MB95220H Series
FUJITSU SEMICONDUCTOR LIMITED
Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome,
Kohoku-ku Yokohama Kanagawa 222-0033, Japan
Tel: +81-45-415-5858
http://jp.fujitsu.com/fsl/en/
For further information please contact:
North and South America
FUJITSU SEMICONDUCTOR AMERICA, INC.
1250 E. Arques Avenue, M/S 333
Sunnyvale, CA 94085-5401, U.S.A.
Tel: +1-408-737-5600 Fax: +1-408-737-5999
http://us.fujitsu.com/micro/
Asia Pacific
FUJITSU SEMICONDUCTOR ASIA PTE. LTD.
151 Lorong Chuan,
#05-08 New Tech Park 556741 Singapore
Tel : +65-6281-0770 Fax : +65-6281-0220
http://www.fujitsu.com/sg/services/micro/semiconductor/
Europe
FUJITSU SEMICONDUCTOR EUROPE GmbH
Pittlerstrasse 47, 63225 Langen, Germany
Tel: +49-6103-690-0 Fax: +49-6103-690-122
http://emea.fujitsu.com/semiconductor/
FUJITSU SEMICONDUCTOR SHANGHAI CO., LTD.
Rm. 3102, Bund Center, No.222 Yan An Road (E),
Shanghai 200002, China
Tel : +86-21-6146-3688 Fax : +86-21-6335-1605
http://cn.fujitsu.com/fmc/
Korea
FUJITSU SEMICONDUCTOR KOREA LTD.
206 Kosmo Tower Building, 1002 Daechi-Dong,
Gangnam-Gu, Seoul 135-280, Republic of Korea
Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
http://kr.fujitsu.com/fmk/
FUJITSU SEMICONDUCTOR PACIFIC ASIA LTD.
10/F., World Commerce Centre, 11 Canton Road,
Tsimshatsui, Kowloon, Hong Kong
Tel : +852-2377-0226 Fax : +852-2376-3269
http://cn.fujitsu.com/fmc/en/
Specifications are subject to change without notice. For further information please contact each office.
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose
of reference to show examples of operations and uses of FUJITSU SEMICONDUCTOR device; FUJITSU SEMICONDUCTOR does not
warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device
based on such information, you must assume any responsibility arising out of such use of the information.
FUJITSU SEMICONDUCTOR assumes no liability for any damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use
or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU SEMICONDUCTOR or
any third party or does FUJITSU SEMICONDUCTOR warrant non-infringement of any third-party's intellectual property right or other
right by using such information. FUJITSU SEMICONDUCTOR assumes no liability for any infringement of the intellectual property
rights or other rights of third parties which would result from the use of information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured
as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to
the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear
facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon
system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that FUJITSU SEMICONDUCTOR will not be liable against you and/or any third party for any claims or damages arising in
connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current
levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of
the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Edited: Sales Promotion Department