The following document contains information on Cypress products. FUJITSU SEMICONDUCTOR DATA SHEET DS04–21379–2E ASSP Single Serial Input PLL Frequency Synthesizer On-chip 3.0 GHz Prescaler MB15E06SR ■ DESCRIPTION The Fujitsu Semiconductor MB15E06SR is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 3.0 GHz prescaler. The 3.0 GHz prescaler has a dual modulus division ratio of 64/65 or 128/129 enabling pulse swallowing operation. The supply voltage range is between 2.7 V and 4.0 V. A refined charge pump supplies well-balanced output currents of 4.0 mA. The phase noise of MB15E06SR was drastically improved comparing with the former single PLL, MB15E06. The data format of serial data and the pin assignments except for φP and φR pins are same as the former one, so it is easy to replace the former one. MB15E06SR is ideally suited for the high frequency wireless system such as ETC (Electronic Toll Collection System). ■ FEATURES • • • • • • • • • • • High frequency operation: 3.0 GHz Max Low power supply voltage: VCC = 2.7 V to 4.0 V Ultra Low power supply current: ICC = 8.0 mA Typ (VCC = Vp = 3.0 V, Ta = +25°C, in locking state) Direct power saving function:Power supply current in power saving mode Typ 0.1 μA (VCC = Vp = 3.0 V, Ta = +25°C) Dual modulus prescaler: 64/65 or 128/129 Serial input 14-bit programmable reference divider: R = 3 to 16,383 Serial input programmable divider consisting of: - Binary 7-bit swallow counter: 0 to 127 - Binary 11-bit programmable counter: 3 to 2,047 Software selectable charge pump current On-chip phase control for phase comparator Built-in digital locking detector circuit to detect PLL locking and unlocking. Operating temperature: Ta = –40 °C to +85 °C Copyright©2004-2011 FUJITSU SEMICONDUCTOR LIMITED All rights reserved 2011.10 MB15E06SR ■ PIN ASSIGNMENTS 16-pin TSSOP OSCIN 1 16 NC OSCout 2 15 NC VP 3 14 LD/fout VCC 4 13 NC Top view DO 5 12 PS GND 6 11 LE Xfin 7 10 Data fin 8 9 Clock (FPT-16P-M07) 2 DS04–21379–2E MB15E06SR ■ PIN DESCRIPTIONS Pin no. TSSOP Pin name I/O 1 OSCIN I Programmable reference divider input. Connection to a TCXO. 2 OSCOUT O Oscillator output. 3 VP – Power supply voltage input for the charge pump. 4 VCC – Power supply voltage input. 5 DO O Charge pump output. Phase of the charge pump can be selected via programming of the FC bit. 6 GND – Ground. 7 Xfin I Prescaler complementary input, which should be grounded via a capacitor. 8 fin I Prescaler input. Connection to an external VCO should be done via AC coupling. 9 Clock I Clock input for the 19-bit shift register. Data is shifted into the shift register on the rising edge of the clock. (Open is prohibited.) 10 Data I Serial data input using binary code. The last bit of the data is a control bit. (Open is prohibited.) 11 LE I Load enable signal input. (Open is prohibited.) When LE is set high, the data in the shift register is transferred to a latch according to the control bit in the serial data. Descriptions 12 PS I Power saving mode control. This pin must be set at “L” at Power-ON. (Open is prohibited.) PS = “H”; Normal mode PS = “L”; Power saving mode 13 NC – No connection. 14 LD/fout O Lock detect signal output (LD)/phase comparator monitoring output (fout). The output signal is selected via programming of the LDS bit. LDS = “H”; outputs fout (fr/fp monitoring output) LDS = “L”; outputs LD (“H” at locking, “L” at unlocking.) 15 NC – No connection. 16 NC – No connection. DS04–21379–2E 3 MB15E06SR ■ BLOCK DIAGRAM OSCIN OSCOUT 1 2 Reference oscillator circuit Binary 14-bit reference couter SW FC LDS 3-bit latch Phase comparator 14-bit latch PS 12 LE 11 Intermittent mode control (power save) C N T Lock detector 19-bit shift register LD/fr/fp selector 1-bit control latch 7-bit latch Data Binary 7-bit swallow counter 10 Clock 9 Xfin 7 fin GND VCC 4 8 11-bit latch Charge pump 14 LD/fout 3 VP 5 DO Binary 11-bit programmable counter fp Prescaler 64/65 128/129 SW 6 4 DS04–21379–2E MB15E06SR ■ ABSOLUTE MAXIMUM RATINGS Parameter Power supply voltage Input voltage Output voltage Storage temperature Symbol Condition VCC Rating Unit Min Max – –0.5 5.0 V VP – VCC 6.0 V VI – –0.5 VCC +0.5 V VO Except Do GND VCC V VO Do GND VP V Tstg – –55 +125 °C Remark WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. ■ RECOMMENDED OPERATING CONDITIONS Parameter Symbol Value Unit Min Typ Max VCC 2.7 3.0 4.0 V VP VCC – 5.5 V Input voltage VI GND – VCC V Operating temperature Ta –40 – +85 °C Power supply voltage Remark WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand. DS04–21379–2E 5 MB15E06SR ■ ELECTRICAL CHARACTERISTICS (VCC = 2.7 V to 4.0 V, Ta = –40 °C to +85 °C) Parameter Symbol Power supply current*1 ICC fin = 3000 MHz, VCC = VP = 3.0 V Power saving current IPS PS = “L” Operating frequency Input sensitivity “H” level input voltage “L” level input voltage “H” level input current “L” level input current “H” level input current “L” level input current “H” level output voltage “L” level output voltage “H” level output voltage “H” level output current “L” level output current “H” level output current “L” level output current Typ Max 6.0 8.0 11.5 mA – 0.1*2 20 μA fIN – 700 – 3000 MHz OSCIN fosc – 3 – 40 MHz fin*3 Pfin –10 – +2 dBm OSCIN*3 VOSC – 0.5 – VCC Vp-p Data, Clock, LE, PS VIH – VCC × 0.7 – – VIL – – – VCC × 0.3 Data, Clock, LE, PS IIH*4 – –1.0 – +1.0 IL*4 I – –1.0 – +1.0 IIH – 0 – +100 I – –100 – 0 OSCIN 50 Ω system (Refer to the measurement circuit.) IL*4 V μA μA VOH VCC = VP = 3.0 V, IOH = –1 mA VCC – 0.4 – – VOL VCC = VP = 3.0 V, IOL = 1 mA – – 0.4 VDOH VCC = VP = 3.0 V, IDOH = –0.5 mA VP – 0.4 – – VDOL VCC = VP = 3.0 V, IDOL = 0.5 mA – – 0.4 IOFF VCC = VP = 3.0 V, VOFF = 0.5 V to VP – 0.5 V – – 2.5 IOH VCC = VP = 3.0 V – – –1.0 IOL VCC = VP = 3.0 V 1.0 – – VCC = VP = 3.0 V, VDO = VP/2, Ta = +25°C –5.2 –4.0 –2.8 2.8 4.0 5.2 IDOMT*5 VDO = VP/2 – 5 – % vs VDO IDOVD*6 0.5 V ≤ VDO ≤ VP – 0.7 V – 10 – % vs Ta IDOTA*7 – 5 – % LD/fout Do Do LD/fout Do IDOL/ IDOH Charge pump current rate Unit Min fin “L” level output voltage High impedance cutoff current Value Condition IDOH*4 IDOL – 40°C ≤ Ta ≤ +85°C, VDO = VP/2 V V nA mA mA *1: Conditions; fosc = 13 MHz, Vosc = 1.2 VPP, Ta = +25°C, in locking state. *2: VCC = VP = 3.0 V, fosc = 13 MHz, Vosc = 1.2 VPP, Ta = +25°C, in power saving mode *3: AC coupling. 1000 pF capacitor is connected under the condition of min. operating frequency. *4: The symbol “–” (minus) means direction of current flow. *5: VCC = VP = 3.0 V, Ta = +25°C (||I3| – |I4||) / [(|I3| + |I4|) /2] × 100(%) *6: VCC = VP = 3.0 V, Ta = +25°C [(||I2| – |I1||) /2] / [(|I1| + |I2|) /2] × 100(%) (Applied to each IDOL, IDOH) (Continued) 6 DS04–21379–2E MB15E06SR (Continued) *7: VCC = VP = 3.0 V, VDO = VP/2 (||IDO(+85°C)| – |IDO(–40°C)| |/2) / (||IDO(+85°C)| + |IDO(–40°C)|| /2) × 100(%) (Applied to each IDOL, IDOH) I1 I3 I2 IDOL IDOH I4 I2 I1 0.5 VP/2 VP − 0.7 VP Charge Pump Output Voltage (V) DS04–21379–2E 7 MB15E06SR ■ FUNCTIONAL DESCRIPTION 1. Pulse Swallow Function The divide ratio can be calculated using the following equation: fVCO = [(P × N) + A] × fOSC ÷ R (A < N) fVCO : Output frequency of external voltage controlled oscillator (VCO) N : Preset divide ratio of binary 11-bit programmable counter (3 to 2,047) A : Preset divide ratio of binary 7-bit swallow counter (0 ≤ A ≤ 127) fOSC : Output frequency of the reference frequency oscillator R : Preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383) P : Preset divide ratio of modulus prescaler (64 or 128) 2. Serial Data Input Serial data is processed using the Data, Clock, and LE pins. Serial data controls the programmable reference divider and the programmable divider separately. Binary serial data is entered through the Data pin. One bit of data is shifted into the shift register on the rising edge of the Clock. When the LE signal pin is taken high, stored data is latched according to the control bit data as follows: Table 1. Control Bit Control bit (CNT) Destination of serial data H For the programmable reference divider L For the programmable divider (1) Shift Register Configuration Programmable Reference Counter MSB LSB Data Flow 1 2 3 4 5 6 7 8 9 CNT R1 R2 R3 R4 R5 R6 R7 R8 CNT R1 to R14 SW FC LDS 10 11 12 13 14 15 16 R9 R10 R11 R12 R13 R14 SW : Control bit : Divide ratio setting bit for the programmable reference counter (3 to 16,383) : Divide ratio setting bit for the prescaler (64/65 or 128/129) : Phase control bit for the phase comparator : LD/fOUT signal select bit 17 18 FC LDS [Table 1] [Table 2] [Table 5] [Table 7] [Table 6] Note: Start data input with MSB first. 8 DS04–21379–2E MB15E06SR Programmable Counter MSB LSB Data Flow 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 CNT A1 A2 A3 A4 A5 A6 A7 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 CNT : Control bit N1 to N11: Divide ratio setting bits for the programmable counter (3 to 2,047) A1 to A7 : Divide ratio setting bits for the swallow counter (0 to 127) 18 19 [Table 1] [Table 3] [Table 4] Note: Data input with MSB first. Table 2. Binary 14-bit Programmable Reference Counter Data Setting Divide ratio(R) R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 3 0 0 0 0 0 0 0 0 0 0 0 0 1 1 4 0 0 0 0 0 0 0 0 0 0 0 1 0 0 ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ 16383 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Note: Divide ratio less than 3 is prohibited. Table 3. Binary 11-bit Programmable Counter Data Setting Divide ratio(N) N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 3 0 0 0 0 0 0 0 0 0 1 1 4 0 0 0 0 0 0 0 0 1 0 0 ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ 2047 1 1 1 1 1 1 1 1 1 1 1 Note: Divide ratio less than 3 is prohibited. Table 4. Binary 7-bit Swallow Counter Data Setting Divide ratio (A) A7 A6 A5 A4 A3 A2 A1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ 127 1 1 1 1 1 1 1 DS04–21379–2E 9 MB15E06SR Table 5. Prescaler Data Setting SW Prescaler divide ratio 1 64/65 0 128/129 Table 6. LD/fout Output Select Data Setting LDS LD/fout output signal 1 fout signal 0 LD signal (2) Relation between the FC Input and Phase Characteristics The FC bit changes the phase characteristics of the phase comparator. The internal charge pump output level (DO) is reversed according to the FC bit. Also, the monitor pin (fout) output is controlled by the FC bit. The relationship between the FC bit and DO is shown below. Table 7. FC Bit Data Setting (LDS = “1”) FC = 1 DO fr > fP H fr < fP L FC = 0 LD/fout DO LD/fout L fout = fr Z fr = fP Z : High impedance H fout = fp Z When designing a synthesizer, the FC pin setting depends on the VCO and LPF characteristics. • When the LPF and VCO characteristics are similar to (1), set FC bit high. • When the VCO characteristics are similar to (2), set FC bit low. PLL LPF VCO (1) VCO Output Frequency (2) LPF Output Voltage Note : Give attention to the polarity for using active type LPF. 10 DS04–21379–2E MB15E06SR 3. Power Saving Mode (Intermittent Mode Control Circuit) Table 10. PS Pin Setting PS pin Status H Normal mode L Power saving mode The intermittent mode control circuit reduces the PLL power consumption. By setting the PS pin low, the device enters into the power saving mode, reducing the current consumption. See the Electrical Characteristics chart for the specific value. The phase detector output, Do, becomes high impedance. For the signal PLL, the lock detector, LD, remains high, indicating a locked condition. Setting the PS pin high, releases the power saving mode, and the device works normally. The intermittent mode control circuit also ensures a smooth startup when the device returns to normal operation. When the PLL is returned to normal operation, the phase comparator output signal is unpredictable. This is because of the unknown relationship between the comparison frequency (fp) and the reference frequency (fr) which can cause a major change in the comparator output, resulting in a VCO frequency jump and an increase in lockup time. To prevent a major VCO frequency jump, the intermittent mode control circuit limits the magnitude of the error signal from the phase detector when it returns to normal operation. Notes : • When power (VCC) is first applied, the device must be in standby mode, PS = Low. • The serial data input after the power supply becomes stable and the the power saving mode is released after completed the data input.. OFF ON tV ≥ 1 μs VCC Clock Data LE tPS ≥ 100 ns PS (1) (2) (3) (1) PS = L (power saving mode) at Power ON (2) Set serial data 1 μs later after power supply remains stable (VCC > 2.2 V). (3) Release power saving mode (PS: “L” → “H”) 100 ns later after setting serial data. DS04–21379–2E 11 MB15E06SR ■ SERIAL DATA INPUT TIMING 1st data 2nd data Control bit Invalid data ∼ Data MSB LSB ∼ ∼ Clock t2 t1 t3 t6 t0 LE ∼ t4 t5 On the rising edge of the clock, one bit of data is transferred into the shift register. Parameter Min Typ Max Unit Parameter Min Typ Max Unit t1 20 – – ns t5 100 – – ns t2 20 – – ns t6 20 – – ns t3 30 – – ns t7 100 – – ns t4 30 – – ns Note: LE should be “L” when the data is transferred into the shift register. 12 DS04–21379–2E MB15E06SR ■ PHASE COMPARATOR OUTPUT WAVEFORM fr fp t WU t WL LD [FC = “1”] DO [FC = “0”] DO Notes: • Phase error detection range: –2π to +2π • Pulses on Do signal during locked state are output to prevent dead zone. • LD output becomes low when phase is tWU or more. LD output becomes high when phase error is tWL or less and continues to be so for three cycles or more. • tWU and tWL depend on OSCIN input frequency. tWU > 2/fosc (s) (e. g. tWU > 153.8 ns, fosc = 13 MHz) tWU < 4/fosc (s) (e. g. tWL < 307.7 ns, fosc = 13 MHz) • LD becomes high during the power saving mode (PS = “L”). DS04–21379–2E 13 MB15E06SR ■ MEASURMENT CIRCUIT (for Measuring Input Sensitivity fin/OSCIN) 1000 pF 0.1 F 1000 pF 0.1 F 1000 pF S.G. S.G. 50 fin Xfin GND DO VCC VP OSCOUT OSCIN 8 7 6 5 4 3 2 1 9 10 11 12 13 14 15 16 Clock Data LE PS NC LD/fout NC VCC 50 NC Oscilloscope Controller (setting divide ratio) 14 DS04–21379–2E MB15E06SR ■ TYPICAL CHARACTERISTICS 1. fin input sensitivity Input sensitivity - Input frequency Input sensitivity Pfin (dBm) Ta = +25 °C 10 5 0 Catalog guaranteed range −5 −10 −15 −20 VCC = 2.7 V −25 VCC = 3.0 V −30 VCC = 4.0 V SPEC −35 0 500 1000 1500 2000 2500 3000 3500 4000 4500 Input frequency fIN (MHz) 2. OSCIN input sensitivity Input sensitivity - Input frequency Ta = +25 °C 10.0 Catalog guaranteed range Input sensitivity VOSC (dBm) 0.0 −10.0 −20.0 −30.0 VCC = 2.7 V VCC = 3.0 V −40.0 VCC = 3.75 V SPEC −50.0 0 20 40 60 80 100 120 140 160 180 Input frequency fOSC (MHz) DS04–21379–2E 15 MB15E06SR 3. Do output current • 4.0 mA VDO - IDO Charge pump output current IDO (mA) 2.00 mA/div 10.00 Ta = +25˚C, VCC = VP = 3.0 V 0.00 −10.00 0 1 2 3 4 5 7 6 Charge pump output voltage VDO (V) 4. fin input impedance 4: 75.418 Ω 63.625 Ω 3.3754 nH 3 000.000 000 MHz 1 : 27.688 Ω −105.31 Ω 700 MHz 2 : 18.004 Ω −64.969 Ω 1 GHz 4 3 : 18.395 Ω 1.0674 Ω 2 GHz 3 1 2 START 16 700.000 000 MHz STOP 3 000.000 000 MHz DS04–21379–2E MB15E06SR 5. OSCIN input impedance 4: 56.25 Ω −1.3356 kΩ 2.979 pF 40.000 000 MHz 1 : 5.771 kΩ −15.199 kΩ 3 MHz 2 : 133.63 Ω −2.5508 kΩ 20 MHz 4 3 : 56.25 Ω −1.3956 kΩ 40 MHz 1 32 START DS04–21379–2E 3.000 000 MHz STOP 40.000 000 MHz 17 MB15E06SR ■ REFERENCE INFORMATION Test Circuit S.G. OSCIN fin LPF Do fVCO = 1619 MHz KV = 44 MHz/V fr = 100 kHz fOSC = 10 MHz (1.2 VPP) LPF 27 kΩ 2200 pF Spectrum Analyzer VCO 3.3 kΩ VCC =VP = 3.0 V VVCO = 3.0 V Ta = +25 °C CP : 4 mA 120 pF 15000 pF • PLL Reference Leakage ATTEN 10 dB RL −10.0 dBm VAVG 16 10 dB/ ΔMKR −77.67 dB 100.0 kHz ΔMKR 100.0 kHz −77.67 dB CENTER 1.6190000 GHz VBW 3.0 kHz RBW 3.0 kHz SPAN 300.0 kHz SWP 84.0 ms • PLL Phase Noise ATTEN 10 dB RL −10.0 dBm VAVG 16 10 dB/ ΔMKR −78.84 dB/Hz 1.000 kHz ΔMKR 1.000 kHz −78.84 dB/Hz CENTER 1.619000000 GHz VBW 30 Hz RBW 30 Hz SPAN 5.000 kHz SWP 969 ms (Continued) 18 DS04–21379–2E MB15E06SR (Continued) • PLL Lock Up time 1597.2 MHz Lch x : −289.99777 μs y : −23.8776 MHz ΔMkr 1672 MHz ± 1 kHz Hch 1.06 ms 1.672003384 GHz 1.671999384 GHz 1.671995384 GHz 0.00 s 2.500 ms 5.000 ms • PLL Lock Up time 1672 MHz Hch x : −300.00071 μs y : −23.8754 MHz ΔMkr 1597.2 MHz ±1kHz Lch 0.9 ms 1.597203471 GHz 1.597199471 GHz 1.597195471 GHz 0.00 s DS04–21379–2E 2.500 ms 5.000 ms 19 MB15E06SR ■ APPLICATION EXAMPLE OUTPUT VCO LPF Lock Det. From a controller NC NC LD/fout NC PS LE Data Clock 16 15 14 13 12 11 10 9 MB15E06SR 1 2 3 4 5 6 7 8 OSCIN OSCOUT VP VCC DO GND Xfin fin 1000 pF 1000 pF 1000 pF 0.1 F 0.1 F TCXO VP: 5.5 V Max ■ USAGE PRECAUTIONS To protect against damage by electrostatic discharge, note the following handling precautions: -Store and transport devices in conductive containers. -Use properly grounded workstations, tools, and equipment. -Turn off power before inserting device into or removing device from a socket. -Protect leads with a conductive sheet when transporting a board-mounted device. 20 DS04–21379–2E MB15E06SR ■ ORDERING INFORMATION Part number MB15E06SRPFT DS04–21379–2E Package Remarks 16-pin, Plastic TSSOP (FPT-16P-M07) 21 MB15E06SR ■ PACKAGE DIMENSIONS 16-pin plastic TSSOP (FPT-16P-M07) 16-pin plastic TSSOP (FPT-16P-M07) Lead pitch 0.65 mm Package width × package length 4.40 × 5.00 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.10mm MAX Weight 0.06g Code (Reference) P-TSSOP16-4.4×5.0-0.65 Note 1) *1 : Resin protrusion. (Each side : +0.15 (.006) Max). Note 2) *2 : These dimensions do not include resin protrusion. Note 3) Pins width and pins thickness include plating thickness. Note 4) Pins width do not include tie bar cutting remainder. *1 5.00±0.10(.197±.004) 0.17±0.05 (.007±.002) 9 16 *2 4.40±0.10 6.40±0.20 (.173±.004) (.252±.008) INDEX Details of "A" part 1.05±0.05 (Mounting height) (.041±.002) LEAD No. 1 8 0.65(.026) "A" 0.24±0.08 (.009±.003) 0.13(.005) M 0~8° +0.03 (0.50(.020)) 0.10(.004) C 22 2003-2010 FUJITSU SEMICONDUCTOR LIMITED F16020S-c-3-5 0.60±0.15 (.024±.006) +.001 0.07 –0.07 .003 –.003 (Stand off) 0.25(.010) Dimensions in mm (inches). Note: The values in parentheses are reference values. DS04–21379–2E MB15E06SR MEMO DS04–21379–2E 23 MB15E06SR FUJITSU SEMICONDUCTOR LIMITED Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome, Kohoku-ku Yokohama Kanagawa 222-0033, Japan Tel: +81-45-415-5858 http://jp.fujitsu.com/fsl/en/ For further information please contact: North and South America FUJITSU SEMICONDUCTOR AMERICA, INC. 1250 E. Arques Avenue, M/S 333 Sunnyvale, CA 94085-5401, U.S.A. Tel: +1-408-737-5600 Fax: +1-408-737-5999 http://us.fujitsu.com/micro/ Asia Pacific FUJITSU SEMICONDUCTOR ASIA PTE. LTD. 151 Lorong Chuan, #05-08 New Tech Park 556741 Singapore Tel : +65-6281-0770 Fax : +65-6281-0220 http://sg.fujitsu.com/semiconductor/ Europe FUJITSU SEMICONDUCTOR EUROPE GmbH Pittlerstrasse 47, 63225 Langen, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://emea.fujitsu.com/semiconductor/ FUJITSU SEMICONDUCTOR SHANGHAI CO., LTD. Rm. 3102, Bund Center, No.222 Yan An Road (E), Shanghai 200002, China Tel : +86-21-6146-3688 Fax : +86-21-6335-1605 http://cn.fujitsu.com/fss/ Korea FUJITSU SEMICONDUCTOR KOREA LTD. 902 Kosmo Tower Building, 1002 Daechi-Dong, Gangnam-Gu, Seoul 135-280, Republic of Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 http://kr.fujitsu.com/fsk/ FUJITSU SEMICONDUCTOR PACIFIC ASIA LTD. 10/F., World Commerce Centre, 11 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel : +852-2377-0226 Fax : +852-2376-3269 http://cn.fujitsu.com/fsp/ Specifications are subject to change without notice. For further information please contact each office. All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with sales representatives before ordering. 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