Errata - Spansion

MDD1)12-010-01
Errata
This errata sheet is for MB91520 Series Hardware Manual 1st edition (MN705-00010-1v0-E).
FR81S
32-BIT MICROCONTROLLER
MB91520 series
HARDWARE MANUAL
*
Date
2012/
02/29
Page
54
Item
1.9
2012/02/29
: Correction part
Description
"Table 9-1 List of Pin Functions" was corrected as shown below.
(Error)
62
78
98
116
137
167
P006
D22
SCS2_0
ADTG1_1
INT2_1
-
167
P006
D22
SCS2_0
ADTG1_1
INT2_1
-
B
General-purpose I/O port
External Bus data bit22 I/O pin(0)
Serial chip select 2 I/O pin(0)
A/D converter external trigger input pin
1(1)
INT2 external interrupt input pin(1)
A
General-purpose I/O port
External Bus data bit22 I/O pin(0)
Serial chip select 2 I/O pin(0)
A/D converter external trigger input pin
1(1)
INT2 external interrupt input pin(1)
(Correct)
62
2012/
02/29
292
7.5.5
78
98
116
137
"Figure 5-5 Reset Sequence" was corrected as shown below.
(Error)
Generate reset source (iii)
External reset
External low-voltage detection reset
Illegal standby mode transition detection reset
Software reset
Flash security violation reset
(Correct)
Generate reset source (iii)
External reset
External low-voltage detection reset
Illegal standby mode transition detection reset
Software reset
Flash security violation reset
Clock supervisor reset
1/42
Date
2012/
02/29
Page
353
Item
9.4
Description
The Register function of the address 0x040C of "Table 0-1 Registers Map" was corrected as shown below.
(Error)
DMA clear request register 12 (for vector number #47)
DMA clear request register 13 (for vector number #52)
DMA clear request register 14 (for vector number #53)
DMA clear request register 15 (for vector number #54)
(Correct)
DMA clear request register 13 (for vector number #52)
DMA clear request register 14 (for vector number #53)
DMA clear request register 15 (for vector number #54)
2012/
02/29
359
9.4.5
The description of bit2 to bit0 was corrected as shown below.
(Error)
Interrupt clear selection bits for sound generator ch.1 / LIN-UART ch.7 transmission completion
(Correct)
Interrupt clear selection bits for 16-bit free-run timer 0 zero detection, compare clear, multi-function serial ch.7
transmission completion
2012/
02/29
360
9.4.6
The description of bit3 to bit0 was corrected as shown below.
(Error)
Interrupt clear selection bits for PPG0, 1, 10, 11, 20, 21
(Correct)
Interrupt clear selection bits for PPG0, 1, 10, 11, 20, 21, 16-bit free-run timer 1 zero detection, compare clear
2012/
02/29
361
9.4.7
The description of bit3 to bit0 was corrected as shown below.
(Error)
Interrupt clear selection bits for PPG2, 3, 12, 13, 22, 23
(Correct)
Interrupt clear selection bits for PPG2, 3, 12, 13, 22, 23, 16-bit free-run timer 2 zero detect, compare clear
2012/
02/29
361
9.4.7
The description of Note was corrected as shown below.
(Error)
Setting PPGSEL1[3:0]= "0110", "0111" and "1011" to "1111" are prohibited. During this setting, no interrupt clear
will be selected.
(Correct)
Setting PPGSEL1[3:0]= "0110", "0111" and "1010" to "1111" are prohibited. During this setting, no interrupt clear
will be selected.
2/42
Date
2012/
02/29
Page
365
Item
9.4.11
Description
The description of bit2 to bit0 was corrected as shown below.
(Error)
Interrupt clear selection for main timer / sub timer / PLL timer
(Correct)
Interrupt clear selection for main timer / sub timer / PLL timer, multi-function serial ch.8 transmission completion,
16-bit ICU2, ICU3
2012/
02/29
366
9.4.12
The description of bit1, bit0 was corrected as shown below.
(Error)
Interrupt clear selection for ICU ch.6
(Correct)
Interrupt clear selection for ICU ch.6, multi-function serial ch.10 reception completion
2012/
02/29
367
9.4.13
The description of bit1, bit0 was corrected as shown below.
(Error)
Interrupt clear selection for ICU ch.7
(Correct)
Interrupt clear selection for ICU ch.7, multi-function serial ch.10 transmission completion
2012/
02/29
368
9.4.14
The description of bit1, bit0 was corrected as shown below.
(Error)
Interrupt clear selection for ICU ch.8
(Correct)
Interrupt clear selection for ICU ch.8, multi-function serial ch.11 reception completion
2012/
02/29
369
9.4.15
The description of bit3 to bit0 was corrected as shown below.
(Error)
Interrupt clear selection for ICU ch.9
(Correct)
Interrupt clear selection for ICU ch.9, WG dead timer underflow 0, 1, 2, WG dead timer reload 0, 1, 2, WG DTTI0
3/42
Date
2012/
02/29
Page
370
Item
9.4.16
Description
The description of bit1, bit0 was corrected as shown below.
(Error)
Interrupt clear selection for ICU ch.4
(Correct)
Interrupt clear selection for ICU ch.4, multi-function serial ch.11 transmission completion
2012/
02/29
371
9.4.17
The description of bit4 to bit0 was corrected as shown below.
(Error)
Interrupt clear selection for ICU ch.5
(Correct)
Interrupt clear selection for ICU ch.5, A/D converter ch.32 to ch.47
2012/
02/29
374
9.4.20
The description of bit1, bit0 was corrected as shown below.
(Error)
Interrupt clear selection bits for Base Timer0 IRQ0, IRQ1/ SG2
(Correct)
Interrupt clear selection bits for Base Timer0 IRQ0, IRQ1
2012/
02/29
375
9.4.21
The description of bit1, bit0 was corrected as shown below.
(Error)
Interrupt clear selection bits for Base Timer1 IRQ0, IRQ1/ SG3
(Correct)
Interrupt clear selection bits for Base Timer1 IRQ0, IRQ1
2012/
02/29
377
9.4.23
The clear target of MFS_SEL1[1:0]=00 was corrected as shown below.
(Error)
Multi-function serial ch.9 reception completion
(Correct)
Multi-function serial ch.9 transmission completion
4/42
Date
2012/
02/29
Page
378
Item
9.4.24
Description
The attribute of bit4, bit3, bit2 of "DMA Request Clear Register 25 : ICSEL25" was corrected as shown below.
(Error)
bit7
bit6
bit5
bit4
bit3
Reserved
Initial value
Attribute
bit2
bit1
bit0
AD_SEL[4:0]
0
0
0
0
0
0
0
0
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
(Correct)
Reserved
Initial value
Attribute
2012/
02/29
399
11.2
AD_SEL[4:0]
0
0
0
0
0
0
0
0
R0,WX
R0,WX
R0,WX
R/W
R/W
R/W
R/W
R/W
The following register was added to" Key code function".
· Port input enable register
2012/
02/29
423
11.4.6.5 The operation of TRGnE[1:0]=1x was corrected as shown below.
(Error)
Input from the PPGn_1 pin
(Correct)
Input from the TRGn_2 pin
5/42
Date
2012/
02/29
Page
425
Item Description
11.4.6.7 The operation of TIAnE was corrected as shown below.
(Error)
TIAnE[1:0]
(n=0, 1)
Operation
00
Base timer TIOAn_0 output disabled, Input from the base timer TIOAn_0
( Initial value )
01
Base timer TIOAn_0 output enabled, Input from the base timer TIOAn_0
1x
Base timer TIOAn_1 output enabled, Input from the base timer TIOAn_1
TIAnE[1:0]
(n=0, 1)
Operation
00
Base timer TIOAn_0 output disabled, Input from the base timer TIOA1_0
( Initial value )
01
Base timer TIOAn_0 output enabled, Input from the base timer TIOA1_0
1x
Base timer TIOAn_1 output enabled, Input from the base timer TIOA1_1
(Correct)
2012/
02/29
437
11.4.6.17 The description of bit1, bit0 of "Extended Port Function Register 87 : EPFR87" was corrected as shown below.
(Error)
ADTG0E[1:0] : AD converter external trigger ch.0 input pin select
ADTG1E[1:0] : AD converter external trigger ch.1 input pin select
(Correct)
ADTG0E
ADTG1E
2012/
02/29
439
11.4.7
: AD converter external trigger ch.0 input pin select
: AD converter external trigger ch.1 input pin select
The following sentence was added to the description of "Port Input Enable Register: PORTEN".
The PORTEN is the target key code register.
6/42
Date
2012/
02/29
Page
540
Item Description
16.4.30 The attribute of bit0 of "Interrupt Request Batch Read Register 15 lower-order : IRPR15L" was corrected as shown
below.
(Error)
Initial value
Attribute
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
CANIR1
XBTC
XBIC
XBTE
BRTC
BRIC
BRTE
Reserved
0
0
0
0
0
0
0
0
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
CANIR1
XBTC
XBIC
XBTE
BRTC
BRIC
BRTE
Reserved
0
0
0
0
0
0
0
0
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
R0,WX
(Correct)
Initial value
Attribute
2012/
02/29
606
17.6
The description of " PPG is operating" was corrected as shown below.
(Error)
5. If the timer operation enable bit (PCN:CNTE) is set to "0" to disable the PPG during the PPG operation, the PPG
stops with its state (count and output level) maintained.
(Correct)
5. If the timer operation enable bit (PCN:CNTE) is set to "0" to disable the PPG during the PPG operation, the PPG
down counter value will be maintained and the PPG output will be changed to "L" and will be stopped
2012/
02/29
606
17.6
The following description was added to " PPG is operating".
7. When the PPG output waveform selection (OWFS) is rewritten during the PPG communication operation, the
setting will be reflected at the next cycle.
8. To change the PPG output mask (PCN.PGMS) from "1" to "0" to cancel mask during the PPG communication
operation, perform the setting within the period between the beginning of cycle and the duty match.
7/42
Date
2012/
02/29
Page
607
Item
17.6
Description
The description of " Cycle value (PCSR) and Duty (PDUT) Settings" was corrected as shown below.
(Error)
8. The duty value (PDUT) must be equal to or smaller than the cycle value (PCSR). If the duty value is set larger than
the cycle value (PCSR), disable PPG operation before changing the duty value (PDUT) to a smaller value. If PPG
operation is not disabled, the following will occur:
(1) If the Normal Wave Form is selected (PCN.OWFS=0), the output level will be "H" or "L" depending on the
cycle value (PCSR)/duty value (PDUT) setting.
(2) If the Center Aligned Wave Form is selected (PCN.OWFS=1), the output level is always "L".
(Correct)
8. When you set the PPG duty setting register (PDUT), use values smaller than the PPG cycle setting register (PCSR).
2012/
02/29
607
17.6
The description of " Others" was corrected as shown below.
(Error)
 Others
13. If the interrupt request flag is set to "0" when interrupt request flag (PCN:IRQF) is "1", the flag clear request is
overwrited, and the interrupt request flag becomes "1".
14. The PPG cycle setting register (PCSR) and the PPG duty setting register (PDUT) are only for writing.
15. If the activation trigger selection bits (GTRS0 to GTRS11:TSELii[6:0]) are set to a value out of the specifiable
ranges (001_1000 to 001_1111, 010_0010 to 011_1111, and 101_1000 to 111_1111), once disable PPG operation
and write a correct value within specifiable ranges in order to restore the registers to normalcy.
(Correct)
 Interrupts
13. If the interrupt request flag is set to "0" when interrupt request flag (PCN:IRQF) is "1", the flag clear request is
overwrited, and the interrupt request flag becomes "1".
14. The performance while the PPG output mask is set (PCN.PGMS='1') is shown below.
The interrupt flag will not be set to "1" because of interrupt factor caused by duty match.
The interrupt flag will be set to "1" because of interrupt factor caused by counter borrow occurrence.
The interrupt flag will be set to "1" because of interrupt factor caused by triggers (software trigger, external trigger or
trigger caused by GATE signal).
8/42
Date
2012/
02/29
Page
608
and
609
Item
17.6
Description
The description of " PPG Communication Mode Function" was corrected as shown below.
(Error)
26. The activation of the PPG communication starts the PPG communication by setting the PPG communication
enable (CMD), the cycle setting (PHCDR/PLCSR), the duty setting (PHDUT/PLDUT), the PPG communication
mode data (PCMDDT), and the PPG communication data bit length (PCMDWD), and then set the activation trigger
at the end.
Be sure to write the setting in the register when the PPG communication is activated.
(Similar when GATE function is used)
27. In the PPG communication mode, the register that becomes valid or invalid as follows.
Valid registers: Software trigger (STRG)

Interrupt factor selection (IRS1, IRS0)
PPG output enable (OE)

PPG communication data register Empty flag (REMP)
PPG communication data shift register Empty flag (SREMP)

Invalid registers: Timer operation enable (CNTE)

Timing Point Capture value setting (PTPC)
(Correct)
26. The activation of the PPG communication starts the PPG communication by setting the PPG communication
enable (CMD), the cycle setting (PHCSR/PLCSR), the duty setting (PHDUT/PLDUT), the PPG communication
mode data (PCMDDT), and the PPG communication data bit length (PCMDWD), and then set the activation trigger
at the end. Be sure to write the setting in the register when the PPG communication is activated. Also, set the other
registers before the start triggers are set.
However, PPG communication will not be started if the activation triggers are generated before the settings above are
not completed. Perform setting again after disabling the PPG communication (PCN2.CMD='0').
(similar when GATE function is used)
27. In the PPG communication mode, the register that becomes valid or invalid as follows.
Valid registers: Software trigger (STRG)
Interrupt factor selection (IRS1, IRS0)
Interrupt request flag (IRQF) (*1)
PPG output enable (OE)

PPG communication data register Empty flag (REMP) (*2)
PPG communication data shift register Empty flag (SREMP) (*2)

Invalid registers: Timer operation enable (CNTE)

Timing Point Capture value setting (PTPC)
(*1) IRS[2:0]=000b to 100b of the interrupt selection cannot be set during the PPG communication; however,
the registers are enabled.
(*2) Cannot be set because this is a read only register.
9/42
Date
2012/
02/29
Page
609
Item
17.6
Description
The description of " PPG Communication Mode Function" was corrected as shown below.
(Error)
28. During the PPG communication operation, do not change any of the following: the count clock selection (CKS1,
CKS0), the trigger input edge selection (EGS1, EGS0), the PPG output polarity selection (OSEL), the PPG
communication mode data reading selection (CMDSEL), and the communication mode data bit length setting
(PCMDWD) If any of the above bits is changed during the PPG communication operation, disable PPG
communication operation before reconfiguring the register.
(Correct)
28. During the PPG communication operation, do not change any of the following: the count clock selection (CKS1,
CKS0), the interrupt selection (IRS2 to IRS0), the trigger input edge selection (EGS1, EGS0), the PPG output polarity
selection (OSEL), the GATE function enable (STGR), the activation effective edge selection (EDGE), the PPG
communication mode data reading selection (CMDSEL), the High/Low format pulse selection (HFPR/LFPR) and the
communication mode data bit length setting (PCMDWD) If any of the above bits is changed during the PPG
communication operation, disable PPG communication operation before reconfiguring the register.
2012/
02/29
610
17.6
The following description was added to " PPG Communication Mode Function".
32. When the PPG output mask selection (PGMS) is rewritten during the PPG communication operation, the setting
will be reflected at the next cycle.
10/42
Description
The channel number in "Figure 3-2 Configuration Diagram of the free-run timer selector" was corrected as shown
below.
(Error)
#0 (for OCU)
(FRS8)
OS01 to OS00
32-bit free-run timer 5
Slretce
32-bit free-run timer 3
32-bit free-run timer 4
#1 to 5 (for OCU)
32-bit output compare 6
32-bit output compare 7 to11
#0 (for ICU)
(FRS9)
IS01 to IS00
Sretcel
Item
21.3.2
#1 to 5 (for ICU)
32-bit input compare 4
32-bit intput compare 5 to 9
(Correct)
#6 (for OCU)
(FRS8)
OS61 to OS60
32-bit free-run timer 3
32-bit free-run timer 4
32-bit free-run timer 5
Slretce
Page
804
#7 to 11 (for OCU)
32-bit output compare 6
32-bit output compare 7 to11
#4 (for ICU)
(FRS9)
IS41 to IS40
Sretcel
Date
2012/
02/29
#5 to 9 (for ICU)
32-bit input compare 4
32-bit intput compare 5 to 9
11/42
Date
2012/
02/29
Page
831
Item
21.7.2
Description
The pin name of the free-run timer 5 was corrected as shown below.
(Error)
To set to
external
clock
input
Free-run
timer 3
Free-run
timer 4
Free-run
timer 5
Configuration
Set the
clock
selection bit
(ECKE) to
"1".
Pin
Set the FRCK3 pin for peripheral input.
(See "CHAPTER: I/O PORTS".)
FRCK3
Set the FRCK4 pin for peripheral input.
(See "CHAPTER: I/O PORTS".)
FRCK4
Set the FRCK2 pin for peripheral input.
(See "CHAPTER: I/O PORTS".)
FRCK2
Pulse
width
(H width,
L width)
4/FPCLK
or higher
(Correct)
To set to
external
clock
input
Free-run
timer 3
Free-run
timer 4
Free-run
timer 5
Configuration
Set the
clock
selection bit
(ECKE) to
"1".
Pin
Set the FRCK3 pin for peripheral input.
(See "CHAPTER: I/O PORTS".)
FRCK3
Set the FRCK4 pin for peripheral input.
(See "CHAPTER: I/O PORTS".)
FRCK4
Set the FRCK5 pin for peripheral input.
(See "CHAPTER: I/O PORTS".)
FRCK5
12/42
Pulse
width
(H width,
L width)
4/FPCLK
or higher
Date
2012/
02/29
Page
843
Item
22.3
Description
The channel number in "Figure 3-1 Configuration Diagram (Detail)" was corrected as shown below.
(Error)
CH6
OMS0
Compare register 0
OCCP0
compare
OLS0
from 32bit free-run timer
Level
Control
circuit
IOE0
External pin
OCU6
OCU6
interrupt
IOP0
OMS1
CH7
OLS1
Compare register 1
OCCP1
CMOD
compare
Level
Control
circuit
External pin
OCU7
from 32bit free-run timer
Same as ch.8 to ch.11
IOE1
OCU7
interrupt
IOP1
(Correct)
CH6
OMS6
Compare register 6
OCCP6
compare
OLS6
from 32bit free-run timer
Level
Control
circuit
IOE6
External pin
OCU6
OCU6
interrupt
IOP6
OMS7
CH7
OLS7
Compare register 7
OCCP7
CMOD
compare
Level
Control
circuit
External pin
OCU7
from 32bit free-run timer
Same as ch.8 to ch.11
IOE7
IOP7
13/42
OCU7
interrupt
Date
2012/
02/29
Page
844
Item
22.4
Description
The channel number in "Table 4-2 Registers Map" was corrected as shown below.
(Error)
0x0F98
Reserved
Reserved
OCSH1011
Output control register
45 upper
OCSL1011
Output control register
45 lower
OCSH1011
Output control register
1011 upper
OCSL1011
Output control register
1011 lower
(Correct)
0x0F98
2012/
02/29
1097
30.4.2
Reserved
Reserved
The description of bit3 of PMUCTLR was corrected as shown below.
(Error)
 PMUCTLR : Address 0591H (Access: Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
SHDE
Initial value
Attribute
0
R/W
Reserved IOCTMD
0
R0,W0
0
R/W
IOCT
0
R/W
bit2
bit1
bit0
Reserved
0
R0,W0
0
R0,W0
0
R0,W0
0
R0,W0
bit2
bit1
bit0
[bit3 to bit0] Reserved
The read value is always "0". Be sure to write these bits to "0".
(Correct)
 PMUCTLR : Address 0591H (Access: Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
SHDE
Initial value
Attribute
0
R/W
Reserved IOCTMD
0
R0,W0
0
R/W
IOCT
BRAMSC
0
R/W
0
R/W
Reserved
0
R0,W0
0
R0,W0
[bit3]
BRAMSC
0
1
Backup RAM sleep control in standby mode
Backup RAM does not sleep in standby mode
Backup RAM sleeps in standby mode
[bit2 to bit0] Reserved
The read value is always "0". Be sure to write these bits to "0".
14/42
0
R0,W0
Date
2012/
02/29
Page
1316
Item
40.1
Description
The description of overview was corrected as shown below.
(Error) This module provides, UART (Asynchronous Serial Interface), CSIO (SPI supported, Clock Synchronous
Serial Interface), LIN-UART (LIN Processing Hardware Attached Serial Interface) and I2C serial communication
function.
(Correct) This module provides, UART (Asynchronous Serial Interface), CSIO (SPI supported, Clock Synchronous
Serial Interface), LIN Interface (v2.1)(LIN Communication Control Interface(v2.1)) and I2C serial communication
function.
2012/
02/29
1317
40.2
The description of features was corrected as shown below.
(Error)
This product is equipped with 12-channel multi-function serial interface communication module. To use this device,
you will select UART, CSIO, LIN-UART, or I2C using the serial mode register (SMR).
(Correct)
This product is equipped with 12-channel multi-function serial interface communication module. To use this device,
you will select UART, CSIO, LIN Interface (v2.1), or I2C using the serial mode register (SMR).
2012/
02/29
1318
40.2
The table in " UART" was corrected as shown below.
(Error)
Reception error
detection
Hardware flow control
Synchronous
transmission feature
· Framing error
· Overrun error
· Parity error*
Automatic transmission and reception control with CTS/RTS
Synchronizes serial timer and is capable of automatic data transmission
periodically
(Correct)
Reception error
detection
2012/
02/29
1318
40.2
· Framing error
· Overrun error
· Parity error*
The function of "Timer feature" in " UART" was corrected as shown below.
(Error)
· Employs 16-bit serial timer
· Dividing ratio of operating clock is selectable (1/1 to 1/256)
· External trigger available
(Correct)
· Employs 16-bit serial timer
· Dividing ratio of operating clock is selectable (1/1 to 1/256)
15/42
Date
2012/
02/29
Page
1318
Item
40.2
Description
The function of "Interrupt request" in " UART" was corrected as shown below.
(Error)
· Both transmission and reception employ extended intelligent I/O service (EI2OS) and DMA function
(Correct)
· Both transmission and reception employ DMA function
2012/
02/29
1319
40.2
The table in " CSIO" was corrected as shown below.
(Error)
4-ch control (single control, round control)*
Variable setup/hold/deselect times can be set
Active level can be select for each channel
Synchronous
Synchronizes serial timer and is capable of automatic data transmission
transmission feature
periodically
* : 4-ch control function is incorporated only for ch.4
Serial chip select
·
·
·
·
(Correct)
Serial chip select
Synchronous
transmission feature
2012/
02/29
1319
40.2
·
·
·
·
·
·
Ch.0: Serial chip select function invalid
Ch.1,2,3,8,9,10,11: 1-ch control (single control)
Ch.4,5,6,7: 4-ch control (single control, round control)
Variable setup/hold/deselect times can be set
Active level can be select for each channel
Synchronizes serial timer and is capable of automatic data transmission
periodically
The function of Interrupt request in " CSIO" was corrected as shown below.
(Error)
· Both transmission and reception employ extended intelligent I/O service (EI2OS) and DMA function
(Correct)
· Both transmission and reception employ DMA function
2012/
02/29
1319
40.2
The function of Timer feature in " CSIO" was corrected as shown below.
(Error)
· Employs 16-bit serial timer
· Dividing ratio of operating clock is selectable (1/1 to 1/256)
· External trigger available
(Correct)
· Employs 16-bit serial timer
· Dividing ratio of operating clock is selectable (1/1 to 1/256)
16/42
Date
2012/
02/29
Page
1320
Item
40.2
Description
The description of " Manual Mode" in " LIN-UART" was corrected as shown below.
(Error)
 LIN-UART
 Manual Mode
LIN-UART (LIN Communication Control UART) provides specific functions to support LIN bus.
(Correct)
 LIN Interface (v2.1)(LIN Communication Control Interface (v2.1))
 Manual Mode
LIN interface (v2.1)(LIN Communication Control Interface (v2.1)) provides
2012/
02/29
1320
40.2
functions to support LIN bus.
The Function of Timer feature in " LIN-UART" was corrected as shown below.
(Error)
· Employs 16-bit serial timer
· Dividing ratio of operating clock is selectable (1/1 to 1/256)
· External trigger available
(Correct)
· Employs 16-bit serial timer
· Dividing ratio of operating clock is selectable (1/1 to 1/256)
2012/
02/29
1320
40.2
The following description of table of " Manual Mode" in " LIN-UART" was deleted.
Synchronous
Synchronizes serial timer and is capable of automatic data transmission periodically
transmission feature
2012/
02/29
1320
40.2
The Function of Interrupt request of " Manual Mode" in " LIN-UART" was corrected as shown below.
(Error)
· Both transmission and reception employ extended intelligent I/O service (EI2OS) and DMA function
(Correct)
· Both transmission and reception employ DMA function
2012/
02/29
1321
40.2
The description of " Assist Mode" in " LIN-UART" was corrected as shown below.
(Error)
 Assist Mode
LIN-UART (LIN Communication Control UART) provides specific functions to support LIN bus.
(Correct)
 Assist Mode
LIN Interface (v2.1)(LIN Communication Control Interface (v2.1)) provides
17/42
functions to support LIN bus.
Date
2012/
02/29
Page
1321
Item
40.2
Description
The function of Timer feature of " Assist Mode" in " LIN-UART" was corrected as shown below.
(Error)
· Employs 16-bit serial timer
· Dividing ratio of operating clock is selectable (1/1 to 1/256)
· External trigger available
(Correct)
· Employs 16-bit serial timer
· Dividing ratio of operating clock is selectable (1/1 to 1/256)
2012/
02/29
1321
40.2
The Function of Interrupt request of " Assist Mode" in " LIN-UART" was corrected as shown below.
(Error)
· Both transmission and reception employ extended intelligent I/O service (EI2OS) and DMA function
(Correct)
· Both transmission and reception employ DMA function
2012/
02/29
1323
40.2
The function of Timer feature in " I2C" was corrected as shown below.
(Error)
· Employs 16-bit serial timer
· Dividing ratio of operating clock is selectable (1/1 to 1/256)
· External trigger available
(Correct)
· Employs 16-bit serial timer
· Dividing ratio of operating clock is selectable (1/1 to 1/256)
2012/
02/29
1323
40.2
The function of Interrupt request in " I2C" was corrected as shown below.
(Error)
· Both transmission and reception employ extended intelligent I/O service (EI2OS) and DMA function
(Correct)
· Both transmission and reception employ DMA function
18/42
Date
2012/
02/29
Page
1323
Item
40.2
Description
The description in " I2C" was corrected as shown below.
(Error)
 I2C
I2C interface supports buses among ICs, and runs as a master/slave device on the I2C bus.
(Correct)
 I2C
I2C interface (I2C Communication Control Interface) supports I2C bus, and runs as a master/slave device on the I2C
bus.
2012/
02/29
1330
40.4
Table 4-2 Registers Map
The "Register +3" of "Address Base+18h" was corrected as shown below.
(Error)
[UART] TBYTE0n
[CSIO] TBYTE0n
[LIN-UART] LAMTIDn/LAMRIDn
[I2C] Reserved
(Correct)
[UART] Reserved
[CSIO] TBYTE0n
[LIN-UART] LAMTIDn/LAMRIDn
[I2C] Reserved
2012/
02/29
1332
40.4.1.1 The attribute and description of bit4 of "Serial Mode Register: SMR" were corrected as shown below.
(Error)
7
6
5
0
0
0
0
3
SBL/
SCINV/
RIE
0
R/W
R/W
R/W
R/W
R/W
R/W
2
BDS/TIE
R/W
MD[2:0]
4
Reserved
2
BDS/TIE
0
1
0
bit
SOE/
SCKE/
(Reserved) (Reserved)
0
R/W
(R/W0)
0
R/W
(R/W0)
Initial value
1
0
bit
Attribute
[bit4] Reserved
Writing/reading does not affect the operation.
(Correct)
7
6
5
0
0
0
0
3
SBL/
SCINV/
RIE
0
R/W
R/W
R/W
R/W0
R/W
MD[2:0]
4
Reserved
[bit4] Reserved
Always set this bit to "0".
19/42
0
SOE/
SCKE/
(Reserved) (Reserved)
0
R/W
(R/W0)
0
R/W
(R/W0)
Initial value
Attribute
Date
2012/
02/29
Page
1333
Item Description
40.4.1.1 The notes of bit3 of "Serial Mode Register: SMR" was corrected as shown below.
(Error)
· This bit is used in one of cases below.
· When chip select pin is disabled (SCSCR:CSEN3-0="0000"b)
· While in slave mode (SCR:MS=0)
(Correct)
· This bit is used in one of cases below.
· When chip select pin is disabled (SCSCR:CSEN3-0="0000"b)
· While in slave mode (SCR:MS=1)
2012/
02/29
1335
40.4.1.2 The attribute and description of bit7, bit6, bit5 of "FIFO Control Register 1: FCR1" were corrected as shown below.
(Error)
7
6
Reserved
5
4
3
2
1
0
-
FLSTE
FRIIE
FDRQ
FTIE
FSEL
1
R(RM1),
W
0
0
Initial value
R/W
R/W
Attribute
bit
0
0
-
0
0
R/W0
R/W0
R0,WX
R/W
R/W
bit
[bit7, bit6] Reserved
These bits must always be written to "0".
[bit5] Undefined
Always reads "0". No effect for writing operations.
(Correct)
7
6
5
Reserved
4
3
2
1
0
FLSTE
FRIIE
FDRQ
FTIE
FSEL
1
R(RM1),
W
0
0
Initial value
R/W
R/W
Attribute
0
0
0
0
0
R/W0
R/W0
R,W0
R/W
R/W
[bit7 to bit5] Reserved
Always set this bit to "0".
20/42
Date
2012/
02/29
Page
1349
Item Description
40.4.2.3 The bit name, attribute, and function of bit7of "Extended Serial Control Register: ESCR" were corrected as shown
below.
(Error)
7
6
5
4
3
FLWEN
ESBL
INV
PEN
P
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
2
1
0
bit
0
R/W
Initial value
Attribute
L[2:0]
0
R/W
0
R/W
bit7 FLWEN:
This bit enables or disables hardware flow control operation.
Flow control enable bit · "0" disables the hardware flow control.
· "1" enables the hardware flow control.
Notes:
· This bit must be set while transmission and reception are disabled
(SCR:TXE=0, RXE=0).
· Set this bit to "1" only when you use hardware flow control.
(Correct)
7
6
5
4
3
Reserved
ESBL
INV
PEN
P
0
R/W0
0
R/W
0
R/W
0
R/W
0
R/W
bit7 Reserved bit
2012/
02/29
1353
2
1
0
bit
0
R/W
Initial value
Attribute
L[2:0]
0
R/W
0
R/W
Always set this bit to "0".
40.4.2.5 The description of "Serial Aid Control Status Register: SACSR" was corrected as shown below.
(Error)
Serial Aid Control Status Register (SACSR) has setups for serial test operation control, serial timer startup selection,
timer interrupt enable/disable, synchronous transmission enable/disable, operating clock division rate of serial timer,
and serial timer enable/disable.
(Correct)
Serial Aid Control Status Register (SACSR) has setups for serial test operation control, timer interrupt enable/disable,
synchronous transmission enable/disable, operating clock division rate of serial timer, and serial timer enable/disable.
21/42
Date
2012/
02/29
Page
1353
Item Description
40.4.2.5 The bit name, attribute, and function of bit14 to bit9 of "Serial Aid Control Status Register: SACSR" were corrected
as shown below.
(Error)
15
14
13
12
11
10
9
8
bit
STST
-
-
-
-
TRG1
TRG0
TINT
0
R/W
0
RX,WX
0
RX,WX
0
RX,WX
0
RX,WX
0
R/W
0
R/W
0
R/W
Initial value
Attribute
8
bit
[bit14 to bit11] Undefined
Read value is undefined. No effect for writing operations.
[bit10, bit9] TRG1-0: Trigger Selection Bits
These bits select how to detect external trigger edge used for starting serial timer.
TRG1
TRG0
0
0
Trailing edge detection
How to detect external trigger edge
0
1
Rising edge detection
1
0
Both edges detection
1
1
Prohibited to set
Note:
Invalid when external trigger enable bit (TRGE) is "0".
(Correct)
15
14
13
STST
0
R/W
12
11
10
9
Reserved
0
RX,W0
0
RX,W0
0
RX,W0
[bit14 to bit9] Reserved
Always set this bit to "0".
22/42
0
RX,W0
TINT
0
RX,W0
0
RX,W0
0
R/W
Initial value
Attribute
Date
2012/
02/29
Page
1353
and
1354
Item Description
40.4.2.5 The bit name, attribute, and function of bit6, bit5 of "Serial Aid Control Status Register: SACSR" were corrected as
shown below.
(Error)
7
6
5
4
3
2
1
0
TINTE
TSYNE
TRGE
TDIV3
TDIV2
TDIV1
TDIV0
TMRE
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
bit
Initial value
Attribute
[bit6] TSYNE: Synchronous Transmission Enable Bit
This bit enables/disables synchronous transmission.
When this bit is "1" and Serial Timer Register (STMR) matches Serial Timer Comparison Register
(STMCR), transmission will be started.
TSYNE
0
1
Description
Disables synchronous transmission
Serial timer is used as a timer.
Enables synchronous transmission
Serial timer is not used as a timer.
Notes:
· This bit can be changed only when serial timer enable bit (TMRE) is "0".
· When no valid data is present in the transmission data register (SSR:TDRE="1") while synchronous
transmission is enabled (SSR:TSYNE="1"), no transmission will be started even if Serial Timer Register
(STMR) matched Serial Timer Comparison Register (STMCR).
· When synchronous transmission is enabled (TSYNE="1") and transmission is disabled (SCR:TXE="0"),
no transmission will be started even if Serial Timer Register (STMR) matched Serial Timer Comparison
Register (STMCR).
· When Serial Timer Register (STMR) matched Serial Timer Comparison Register (STMCR) while in
transmission with synchronous transmission enabled (TSYNE="1"), it will be ignored and the transmission
will be continued.
[bit5] TRGE: External Trigger Enable Bit
This bit selects how to start the serial timer.
TRGE
0
1
Description
When serial timer enable bit (TMRE) is changed from "0" to "1", serial timer will be
started.
Any of external trigger edges set at the trigger selection bit (TRG1, 0) is detected
while serial timer enable bit (TMRE) is set to "1", serial timer will be started.
Notes:
· This bit can be changed only when serial timer enable bit (TMRE) is "0".
· The serial timer will not be started even if any of external trigger edges set at the trigger selection bit
(TRG1, 0) is detected while serial timer enable bit (TMRE) is set to "0".
(Correct)
7
TINTE
0
R/W
6
5
Reserved
0
RX,W0
0
RX,W0
4
3
2
1
0
TDIV3
TDIV2
TDIV1
TDIV0
TMRE
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
[bit6 to bit5] Reserved
Always set this bit to "0".
23/42
bit
Initial value
Attribute
Date
2012/
02/29
Page
1355
Item Description
40.4.2.5 The notes of "[bit0] TMRE: Serial timer enable Bit" was corrected as shown below.
(Error)
Notes:
· Even if this bit is set to “1” while external trigger is enabled (TRGE="1"), serial timer will not be started
until any of external trigger edges set at the trigger selection bit (SAGSR:TRG1, 0) is detected.
· When you make synchronous transmission with serial timer or transmission with external trigger, change
this bit when any of following condition is met.
· Transmission is disabled (SCR:TXE="0")
· Transmission bus is idling (SSR:TBI="1")
(Correct)
Notes:
· When you make synchronous transmission with serial timer, change this bit when any of following
condition is met.
· Transmission is disabled (SCR:TXE="0")
· Transmission bus is idling (SSR:TBI="1")
2012/
02/29
1357
40.4.2.7 The notes of "4.2.7 Serial timer Comparison Register: STMCR" was corrected as shown below.
(Error)
· When (0000)H is set to this register, the Serial Timer Register still indicates "0".
· With "0000"H set to this register while synchronous transmission is disabled (SACSR:TSYNE="0"), the
timer interrupt flag (SACSR:TINT) will be fixed to “1” when the timer operating clock division value
(SACSR:TDIV) is set to "0000"b while the timer is running.
· With synchronous transmission enabled (SACSR:TSYNE="1"), external trigger enabled
(SACSR:TRGE="1"), this register set with (0000)H, and when transmission data is present
(SSR:TDRE="0") while transmission is enabled(SCR:TXE="1"), the transmission will immediately be
started when any of external trigger edges set at the trigger selection bit (SACSR:TRG1, 0) is detected.
· This register can be changed only when serial timer is disabled (SACSR:TMRE="0").
(Correct)
· When (0000)H is set to this register, the Serial Timer Register still indicates "0".
· With "0000"H set to this register while synchronous transmission is disabled (SACSR:TSYNE="0"), the
timer interrupt flag (SACSR:TINT) will be fixed to “1” when the timer operating clock division value
(SACSR:TDIV) is set to "0000"b while the timer is running.
· This register can be changed only when serial timer is disabled (SACSR:TMRE="0").
2012/
02/29
1358
40.4.2.8 This section ("Transfer Byte Register: TBYTE") was deleted.
24/42
Date
2012/
02/29
Page
1361
Item Description
40.4.3.1 The attribute of bit5 of "Serial Control Register: SCR" was corrected as shown below.
(Error)
7
6
5
4
3
2
1
0
bit
UPCL
MS
SPI
RIE
TIE
TBIE
RXE
TXE
0
R0,W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Initial value
Attribute
7
6
5
4
3
2
1
0
bit
UPCL
MS
SPI
RIE
TIE
TBIE
RXE
TXE
0
R0,W
0
R/W
0
R,W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
(Correct)
2012/
02/29
1363
Initial value
Attribute
40.4.3.2 The bit name, initial value, attribute and function of bit6, bit5, bit4 of "Serial Status Register: SSR" were corrected as
shown below.
(Error)
7
6
5
4
3
2
1
0
REC
Reserved
ES
AWC
ORE
RDRF
TDRE
TBI
0
R0,W
RX,W0
0
RX,WX
0
RX,WX
0
R,WX
0
R,WX
1
R,WX
1
R,WX
bit6 Reserved bit
bit
Initial value
Attribute
When read: Reads "0".
When written: Always write "0".
In the cases below, select whether access is made from lower bit of
transmission/reception data or from upper bit.
· Access width for transmission data register (TDR) and reception data
register (RDR) is 16 bits (AWC=0)
· Data length is 20, 24, or 32 bits
· "0" is set: Access from lower bit
· "1" is set: Access from upper bit
Note:
This bit can be changed only if transmission/reception is disabled
(SCR:TXE=RXE=0) and TDR and RDR are empty (SSR:TDRE=1,
SSR:RDRF=0).
bit5 ES:
Endian selection bit
(Correct)
7
REC
0
R0,W
6
5
Reserved
0
R0,W0
bit6, bit5 Reserved bit
0
R/W0
4
3
2
1
0
AWC
ORE
RDRF
TDRE
TBI
0
R/W
0
R,WX
0
R,WX
1
R,WX
1
R,WX
Always set this bit to "0".
25/42
bit
Initial value
Attribute
Date
2012/
02/29
Page
1366
Item Description
40.4.3.3 The notes of bit6, bit2 to bit0 of "Extended Serial Control Register: ESCR" was corrected as shown below.
(Error)
Notes:
· Settings other than those listed above are prohibited.
· This bit is used in one of cases below.
· When chip select pin is disabled (SCSCR:CSEN3-0="0000"b)
· While in slave mode (SCR:MS=0)
(Correct)
Notes:
· Settings other than those listed above are prohibited.
· This bit is used in one of cases below.
· When chip select pin is disabled (SCSCR:CSEN3-0="0000"b)
· While in slave mode (SCR:MS=1)
2012/
02/29
1371
40.4.3.5 The description of "Serial Aid Control Status Register: SACSR" was corrected as shown below.
(Error)
The serial aid control status register (SACSR) allows you to control serial test operations, select how to
activate the serial timer, enable/disable timer interrupts, enable/disable synchronous transmission, set the
division value of the operating clock of the serial timer, and enable/disable the serial timer.
(Correct)
The serial aid control status register (SACSR) allows you to control serial test operations, enable/disable timer
interrupts, enable/disable synchronous transmission, set the division value of the operating clock of the serial
timer, and enable/disable the serial timer.
26/42
Date
2012/
02/29
Page
1371
and
1372
Item Description
40.4.3.5 The bit name, attribute and function of bit10, bit9 and the attribute of bit15, bit14, bit11, bit8 of "Serial Aid Control
Status Register: SACSR" were corrected as shown below.
(Error)
15
14
13
12
11
10
9
8
STST
Reserved
TBEEN
CSEIE
CSE
TRG1
TRG0
TINT
0
R/W
0
R0,W0
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
bit
Initial value
Attribute
[bit10,bit9] TRG1-0: Trigger select bits
These bits are used to select how to detect an edge of an external trigger for activating the serial timer.
TRG1
0
0
1
1
TRG0
0
1
0
1
How to detect an edge of an external trigger
Falling edge detected
Rising edge detected
Both edges detected
Setting prohibited
Note:
These bits have no effect when the external trigger enable bit (TRGE) is set to "0".
(Correct)
15
14
13
12
11
STST
Reserved
TBEEN
CSEIE
CSE
0
R,W
0
RX,W0
0
R/W
0
R/W
10
9
Reserved
0
0
R(RM1),W RX,W0
8
TINT
0
0
Initial value
RX,W0 R(RM1),W Attribute
[bit10,bit9] Reserved bit
Always set this bit to "0".
2012/
02/29
1371
40.4.3.5 Serial Aid Control Status Register: SACSR
The description of "[bit13] TBEEN: Transfer byte error enable bit" was corrected as shown below.
(Error)
· Chip select is used
· Synchronous transmission of the serial timer is used
· Transmission activated by an external trigger is used
(Correct)
· Chip select is used
· Synchronous transmission of the serial timer is used
27/42
bit
Date
2012/
02/29
Page
1371
and
1373
Item Description
40.4.3.5 The bit name, attribute and function of bit5 and the attribute of bit6, bit4, bit3, bit2, bit1 of "Serial Aid Control Status
Register: SACSR" were corrected as shown below.
(Error)
7
6
5
4
3
2
1
0
TINTE
TSYNE
TRGE
TDIV3
TDIV2
TDIV1
TDIV0
TMRE
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
bit
Initial value
Attribute
[bit5] TRGE: External trigger enable bit
This bit is used to select how to activate the serial timer.
TRGE
0
1
Description
When the serial timer enable bit (TMRE) is changed from
"0" to "1", the serial timer will start operation.
When the serial timer enable bit (TMRE) is set to "1", and an
edge of the external trigger set by the trigger select bits
(TRG1, 0) is detected, the serial timer will start operation.
Notes:
· This bit can be changed only when the serial timer enable bit (TMRE) is set to "0".
· When the serial timer enable bit (TMRE) is set to "0", the serial timer will not start operation, even if an
edge of the external trigger set by the trigger select bits (TRG1, 0) is detected.
(Correct)
7
6
5
4
3
2
1
0
TINTE
TSYNE
Reserved
TDIV3
TDIV2
TDIV1
TDIV0
TMRE
0
R/W
0
R,W
0
RX,W0
0
R,W
0
R,W
0
R,W
0
R,W
0
R/W
bit
Initial value
Attribute
[bit5] Reserved bit
Always set this bit to "0".
2012/
02/29
1374
40.4.3.5 Serial Aid Control Status Register: SACSR
The notes of "[bit0] TMRE: Serial timer enable bit" was corrected as shown below.
(Error)
Notes:
· When an external trigger is enabled (TRGE="1"), the serial timer will not start operation until an edge of
the external trigger set by the trigger select bits (SAGSR:TRG1, 0) is detected, even if this bit is set to "1".
· To perform synchronous transmission by the serial timer, or perform transmission by an external trigger,
change this bit under one of the following conditions:
· Transmission disabled (SCR:TXE="0")
· Transmission bus idle (SSR:TBI="1")
(Correct)
Notes:
· To perform synchronous transmission by the serial timer, or perform transmission by an external trigger,
change this bit under one of the following conditions:
· Transmission disabled (SCR:TXE="0")
· Transmission bus idle (SSR:TBI="1")
28/42
Date
2012/
02/29
Page
1375
Item Description
40.4.3.6 The attribute of bit15 to bit0 of "Serial Timer Register: STMR" was corrected as shown below.
(Error)
15
TM15
0
R
14
TM14
0
R
13
TM13
0
R
12
TM12
0
R
11
TM11
0
R
10
TM10
0
R
9
TM9
0
R
8
TM8
0
R
7
TM7
0
R
6
TM6
0
R
5
TM5
0
R
4
TM4
0
R
3
TM3
0
R
2
TM2
0
R
1
TM1
0
R
0
TM0
0
R
15
TM15
0
R,WX
14
TM14
0
R,WX
13
TM13
0
R,WX
12
TM12
0
R,WX
11
TM11
0
R,WX
10
TM10
0
R,WX
9
TM9
0
R,WX
8
TM8
0
R,WX
7
TM7
0
R,WX
6
TM6
0
R,WX
5
TM5
0
R,WX
4
TM4
0
R,WX
3
TM3
0
R,WX
2
TM2
0
R,WX
1
TM1
0
R,WX
0
TM0
0
R,WX
bit
Initial value
Attribute
bit
Initial value
Attribute
(Correct)
2012/
02/29
1376
bit
Initial value
Attribute
bit
Initial value
Attribute
40.4.3.7 The attribute of bit15 to bit0 of "Serial Timer Compare Register: STMCR" was corrected as shown below.
(Error)
15
TC15
0
R/W
14
TC14
0
R/W
13
TC13
0
R/W
12
TC12
0
R/W
11
TC11
0
R/W
10
TC10
0
R/W
9
TC9
0
R/W
8
TC8
0
R/W
7
TC7
0
R/W
6
TC6
0
R/W
5
TC5
0
R/W
4
TC4
0
R/W
3
TC3
0
R/W
2
TC2
0
R/W
1
TC1
0
R/W
0
TC0
0
R/W
15
TC15
0
R,W
14
TC14
0
R,W
13
TC13
0
R,W
12
TC12
0
R,W
11
TC11
0
R,W
10
TC10
0
R,W
9
TC9
0
R,W
8
TC8
0
R,W
7
TC7
0
R,W
6
TC6
0
R,W
5
TC5
0
R,W
4
TC4
0
R,W
3
TC3
0
R,W
2
TC2
0
R,W
1
TC1
0
R,W
0
TC0
0
R,W
bit
Initial value
Attribute
bit
Initial value
Attribute
(Correct)
29/42
bit
Initial value
Attribute
bit
Initial value
Attribute
Date
2012/
02/29
Page
1376
Item Description
40.4.3.7 The notes of "Serial Timer Compare Register: STMCR" was corrected as shown below.
(Error)
Notes:
· When (0000)H is set to this register, the serial timer register will remain set to "0".
· When "0000"H is set to this register with synchronous transmission disabled (SACSR:TSYNE="0"), the
timer interrupt flag (SACSR:TINT) will be fixed to "1", if the division value of the timer operating clock
(SACSR:TDIV) is set to "0000"b during timer operation.
· If transmission data exists (SSR:TDRE="0") with synchronous transmission enabled
(SACSR:TSYNE="1"), an external trigger enabled (SACSR:TRGE="1"), (0000)H set to this register, and
transmission enabled (SCR:TXE="1"), transmission will be started immediately after an edge of the
external trigger set by the trigger select bits (SACSR:TRG1, 0) is detected.
· This register can be changed only when the serial timer is disabled (SACSR:TMRE="0").
(Correct)
Notes:
· When (0000)H is set to this register, the serial timer register will remain set to "0".
· When "0000"H is set to this register with synchronous transmission disabled (SACSR:TSYNE="0"), the
timer interrupt flag (SACSR:TINT) will be fixed to "1", if the division value of the timer operating clock
(SACSR:TDIV) is set to "0000"b during timer operation.
· This register can be changed only when the serial timer is disabled (SACSR:TMRE="0").
2012/
02/29
1379
40.4.3.8 The notes of bit5 of "Serial Chip Select Control Status Register: SCSCR" was corrected as shown below.
(Error)
Notes:
· This bit can be changed only when transmission and reception are disabled (SCR:TXE=RXE="0").
· Setting this bit is used under one of the following conditions:
· Slave mode (SCR:MS="0")
(Correct)
Notes:
· This bit can be changed only when transmission and reception are disabled (SCR:TXE=RXE="0").
· Setting this bit is used under one of the following conditions:
· Slave mode (SCR:MS="1")
2012/
02/29
1383 40.4.3.10 The all notes of bit15, bit14, bit13, bit12, bit11 to bit8, bit7, bit6, bit5, bit4, bit3 to bit0 of "Serial Chip Select Format
to
Register: SCSFR2-0" was corrected as shown below.
1387
(Error)
Notes
· This bit can be changed only when transmission and reception are disabled (SCR:TXE=RXE="0").
· In the slave mode (SCR:MS="0"), setting this bit has no effect.
(Correct)
Notes:
· This bit can be changed only when transmission and reception are disabled (SCR:TXE=RXE="0").
· In the slave mode (SCR:MS="1"), setting this bit has no effect.
30/42
Date
2012/
02/29
Page
Item Description
1391 40.4.3.11 The description of [bit15 to bit8, bit7 to bit0] of "Transfer Byte Register: TBYTE3-0" was corrected as shown below.
(Error) If one of the following conditions is satisfied, the transfer byte register (TBYTE) is used for synchronous
transmission or external trigger transmission. When transmission operation is started with synchronous transmission
or external trigger transmission, data count set to TBYTE will be transferred.
(Correct) If one of the following conditions is satisfied, the transfer byte register (TBYTE) is used for synchronous
transmission. When transmission operation is started with synchronous transmission, data count set to TBYTE will be
transferred.
2012/
02/29
1392 40.4.3.11 The notes of "Transfer Byte Register: TBYTE3-0" was corrected as shown below.
(Error) If synchronous transmission or external trigger transmission is to be performed when chip select is used during
the master operation (SCR:MS="0"), transfer count varies as follows:
(Correct) If synchronous transmission is to be performed when chip select is used during the master operation
(SCR:MS="0"), transfer count varies as follows:
2012/
02/29
1403
40.4.4.5 The description of "Serial Aid Control Status Register: SACSR" was corrected as shown below.
(Error) The serial aid control status register (SACSR) allows you to control serial test operations, select how to
activate the serial timer, enable/disable timer interrupts, enable/disable synchronous transmission, set the division
value of the operating clock of the serial timer, and enable/disable the serial timer.
(Correct) The serial aid control status register (SACSR) allows you to control serial test operations, enable/disable
timer interrupts, enable/disable synchronous transmission, set the division value of the operating clock of the serial
timer, and enable/disable the serial timer.
31/42
Date
2012/
02/29
Page
1403
and
1404
Item Description
40.4.4.5 The bit name, attribute and function of bit14, bit10, bit9 and the attribute of bit15, bit13, bit11, bit8 of "Serial Aid
Control Status Register: SACSR" were corrected as shown below.
(Error)
15
14
13
12
11
10
9
8
STST
BST
SFD
SFDE
AUTE
TRG1
TRG0
TINT
0
R/W
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
bit
Initial value
Attribute
[bit14] BST: Baud rate setting flag
This bit is used to indicate that automatic baud rate adjustment was made due to Sync Field reception.
When the fifth falling edge of LIN bus is detected in Sync Field, this bit will be updated.
BST
0
1
Baud rate setting flag
No automatic baud rate adjustment
Automatic baud rate adjustment
Notes:
· If automatic baud rate adjustment is disabled (AUTE="0"), this bit will be fixed to "0".
· When software reset is triggered (SCR:UPCL="1"), this bit will be reset to "0".
· This bit takes effect only when the Sync Field detection flag (SACSR:SFD) is set to "1".
· Writing to this bit has no effect.
[bit10, bit9] TRG1-0: Trigger select bits
These bits are used to select how to detect an edge of an external trigger for activating the serial timer.
TRG1
0
0
1
1
TRG0
0
1
0
1
How to detect an edge of an external trigger
Falling edge detected
Rising edge detected
Both edges detected
Setting prohibited
Note:
These bits have no effect when the external trigger enable bit (TRGE) is set to "0".
(Correct)
15
14
13
12
11
STST
Reserved
SFD
SFDE
AUTE
0
R/W
0
R,W
0
R,W
0
0
RX,W0 R(RM1),W
[bit14] Reserved bit
Always set this bit to "0".
[bit10, bit9] Reserved bit
Always set this bit to "0".
32/42
10
9
Reserved
0
RX,W0
8
bit
TINT
0
0
Initial value
RX,W0 R(RM1),W Attribute
Date Page
Item Description
2012/ 1403, 40.4.4.5 The bit name, attribute and function of bit6, bit5 and the attribute of bit4, bit3, bit2, bit1 of "Serial Aid Control Status
02/29 1405,
Register: SACSR" were corrected as shown below.
and
1406
(Error)
7
6
5
4
3
2
1
0
TINTE
TSYNE
TRGE
TDIV3
TDIV2
TDIV1
TDIV0
TMRE
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
bit
Initial value
Attribute
[bit6] TSYNE: Synchronous transmission enable bit
This bit is used to enable or disable synchronous transmission.
When this bit is set to "1", transmission will be activated if the serial timer register (STMR) matches the
serial timer compare register (STMCR).
TSYNE
Description
Synchronous transmission disabled
The serial timer will be used as a timer.
Synchronous transmission enabled
The serial timer will not be used as a timer.
0
1
Notes:
· This bit can be changed only when the serial timer enable bit (TMRE) is set to "0".
· When synchronous transmission is enabled (TSYNE="1") and transmission is disabled (SCR:TXE="0"),
transmission will not be activated, even if the serial timer register (STMR) matches the serial timer
compare register (STMCR).
[bit5] TRGE: External trigger enable bit
This bit is used to select how to activate the serial timer.
TRGE
0
1
Description
When the serial timer enable bit (TMRE) is changed from
"0" to "1", the serial timer will start operation.
When the serial timer enable bit (TMRE) is set to "1", and
an edge of the external trigger set by the trigger select bits
(TRG1, 0) is detected, the serial timer will start operation.
Notes:
· This bit can be changed only when the serial timer enable bit (TMRE) is set to "0".
· When the serial timer enable bit (TMRE) is set to "0", the serial timer will not start operation, even if an
edge of the external trigger set by the trigger select bits (TRG1, 0) is detected.
(Correct)
7
TINTE
0
R/W
6
5
Reserved
0
R/W0
0
R,W0
4
3
2
1
0
TDIV3
TDIV2
TDIV1
TDIV0
TMRE
0
R,W
0
R,W
0
R,W
0
R,W
0
R/W
[bit6, bit5] Reserved bit
Always set this bit to "0".
33/42
bit
Initial value
Attribute
Date
2012/
02/29
Page
1407
Item Description
40.4.4.5 The notes of [bit0] of "Serial Aid Control Status Register: SACSR" was corrected as shown below.
(Error)
Notes:
· When an external trigger is enabled (TRGE="1"), the serial timer will not start operation until an edge of
the external trigger set by the trigger select bits (SAGSR:TRG1, 0) is detected, even if this bit is set to "1".
· To perform synchronous transmission by the serial timer, or perform transmission by an external trigger,
change this bit under one of the following conditions:
· Transmission disabled (SCR:TXE="0")
· Transmission bus idle (SSR:TBI="1")
(Correct)
Notes:
· To perform synchronous transmission by the serial timer, change this bit under one of the following
conditions:
· Transmission disabled (SCR:TXE="0")
· Transmission bus idle (SSR:TBI="1")
2012/
02/29
1409
40.4.4.7 The notes of "Serial Timer Compare Register: STMCR" was corrected as shown below.
(Error)
Notes:
· When (0000)H is set to this register, the serial timer register will remain set to "0".
· When "0000"H is set to this register with synchronous transmission disabled (SACSR:TSYNE="0"), the
timer interrupt flag (SACSR:TINT) will be fixed to "1", if the division value of the timer operating clock
(SACSR:TDIV) is set to "0000"b during timer operation.
· If transmission data exists (SSR:TDRE="0") with synchronous transmission enabled
(SACSR:TSYNE="1"), an external trigger enabled (SACSR:TRGE="1"), (0000)H set to this register, and
transmission enabled (SCR:TXE="1"), transmission will be started immediately after an edge of an
external trigger set by the trigger select bits (SACSR:TRG1, 0) is detected.
· This register can be changed only when the serial timer is disabled (SACSR:TMRE="0").
· If all the following conditions are satisfied, the serial timer register (STMR) might be reset to (0000) H
before baud rate adjustment is made. Therefore, when the automatic baud rate adjustment bit
(SACSR:AUTE) is set to "1", set a larger value to these bits than the value set by the Sync Field upper
limit bit (SFUR).
· The automatic baud rate adjustment bit (SACSR:AUTE) is set to "1"
· These bits have a smaller value than the value set by the Sync Field upper limit bit (SFUR)
(Correct)
Notes:
· When (0000)H is set to this register, the serial timer register will remain set to "0".
· When "0000"H is set to this register with synchronous transmission disabled (SACSR:TSYNE="0"), the
timer interrupt flag (SACSR:TINT) will be fixed to "1", if the division value of the timer operating clock
(SACSR:TDIV) is set to "0000"b during timer operation.
· This register can be changed only when the serial timer is disabled (SACSR:TMRE="0").
· If all the following conditions are satisfied, the serial timer register (STMR) might be reset to (0000) H
before baud rate adjustment is made. Therefore, when the automatic baud rate adjustment bit
(SACSR:AUTE) is set to "1", set a larger value to these bits than the value set by the Sync Field upper
limit bit (SFUR).
· The automatic baud rate adjustment bit (SACSR:AUTE) is set to "1"
· These bits have a smaller value than the value set by the Sync Field upper limit bit (SFUR)
34/42
Date
2012/
02/29
Page
1443
Item Description
40.4.5.5 The description of "Serial Aid Control Status Register: SACSR" was corrected as shown below.
(Error) The serial aid control status register (SACSR) allows you to select how to activate the serial timer,
enable/disable timer interrupts, set the division value of the operating clock of the serial timer, and enable/disable the
serial timer.
(Correct) The serial aid control status register (SACSR) allows you to enable/disable timer interrupts, set the division
value of the operating clock of the serial timer, and enable/disable the serial timer.
2012/
02/29
1443
40.4.5.5 The bit name, attribute and function of bit15 to bit11, bit10, bit9 and the attribute of bit8 of "Serial Aid Control Status
Register: SACSR" were corrected as shown below.
(Error)
15
14
13
12
11
10
9
8
-
-
-
-
-
TRG1
TRG0
TINT
0
R/W
0
RX,WX
0
RX,WX
0
RX,WX
0
RX,WX
0
R/W
0
R/W
0
R/W
bit
Initial value
Attribute
[bit15 to bit11] Undefined
The read value is undefined. Writing has no effect on the operation.
[bit10, bit9] TRG1-0: Trigger select bits
These bits are used to select how to detect an edge of an external trigger for activating the serial timer.
TRG1
0
0
1
1
TRG0
0
1
0
1
How to detect an edge of an external trigger
Falling edge detected
Rising edge detected
Both edges detected
Setting prohibited
Note:
These bits have no effect when the external trigger enable bit (TRGE) is set to "0".
(Correct)
15
14
13
12
11
10
Reserved
0
R0,W0
0
RX,W0
0
R0,W0
0
R0,W0
[bit15 to bit9] Reserved bit
Always set this bit to "0".
35/42
9
8
bit
TINT
0
R0,W0
0
RX,W0
0
0
Initial value
RX,W0 R(RM1),W Attribute
Date
2012/
02/29
Page
1443
and
1444
Item Description
40.4.5.5 The bit name, attribute and function of bit5 and the attribute of bit6, bit4 to bit1 of "Serial Aid Control Status Register:
SACSR" were corrected as shown below.
(Error)
7
6
5
4
3
2
1
0
TINTE
-
TRGE
TDIV3
TDIV2
TDIV1
TDIV0
TMRE
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
bit
Initial value
Attribute
[bit5] TRGE: External trigger enable bit
This bit is used to select how to activate the serial timer.
TRGE
0
1
Description
When the serial timer enable bit (TMRE) is changed from
"0" to "1", the serial timer will start operation.
When the serial timer enable bit (TMRE) is set to "1", and
an edge of the external trigger set by the trigger select bits
(TRG1, 0) is detected, the serial timer will start operation.
Notes:
· This bit can be changed only when the serial timer enable bit (TMRE) is set to "0".
· When the serial timer enable bit (TMRE) is set to "0", the serial timer will not start operation, even if an
edge of the external trigger set by the trigger select bits (TRG1, 0) is detected.
(Correct)
7
6
5
4
3
2
1
0
TINTE
-
Reserved
TDIV3
TDIV2
TDIV1
TDIV0
TMRE
0
R/W
0
R0,WX
0
RX,W0
0
R,W
0
R,W
0
R,W
0
R,W
0
R/W
bit
Initial value
Attribute
[bit5] Reserved bit
Always set this bit to "0".
2012/
02/29
1445
2012/
02/29
1472 40.5.2.10 This section ("Hardware Flow Control") was deleted.
and
1473
1474 40.5.2.11 The description of " How to Start Serial Timer" was corrected as shown below.
2012/
02/29
40.4.5.5 The notes of "[bit0] TMRE: Serial timer enable bit" was deleted.
(Error) There are two ways to start the serial timer: setting "1" to the serial timer enable bit (SACSR:TMRE) or
starting by the external trigger.
(Correct) To start the serial timer: setting "1" to the serial timer enable bit (SACSR:TMRE).
2012/
02/29
1474 40.5.2.11 The description of "· Start by using the serial timer enable bit (SACSR:TMRE)" was corrected as shown below.
(Error) When the external trigger enable bit (SACSR:TRGE) is set to "0" and the serial timer enable bit
(SACSR:TMRE) is set to "1", the serial timer starts and the serial timer register (STMR) starts counting from 0.
(Correct) When the serial timer enable bit (SACSR:TMRE) is set to "1", the serial timer starts and the serial timer
register (STMR) starts counting from 0.
36/42
Date
2012/
02/29
Page
Item Description
1474 40.5.2.11 The title of "Figure 5-13" was corrected as shown below.
(Error) Start by Using Serial Timer Enable Bit (STMCR="10", SACSR:TRGE=TSYNE="0")
(Correct) Start by Using Serial Timer Enable Bit (STMCR="10", SACSR:TSYNE="0")
2012/
02/29
2012/
02/29
2012/
02/29
2012/
02/29
1474 40.5.2.11 The "· Start by External Trigger" of " How to Start Serial Timer" was deleted.
and
1475
1475 40.5.2.11 The description of " Synchronous Transmission Operation" was deleted.
and
1476
1477 40.5.2.11 The "Operation of Serial Timer" of " Transmission Operation by External Trigger" was deleted.
and
1478
1493 40.6.1 The following descriptions were added to "Interrupts of CSIO".
· Comparison value (STMCR) of the serial timer and serial timer value (STMR) are corresponding.
· Chip selection error generation
2012/
02/29
1494
40.6.1.1 Table 6-1 Interrupt Control Bits and Interrupt Factors of CSIO
The flag register and interrupt factor were corrected as shown below.
(Error)
TransCSE
mission
SSR
Serial chip select pin is inactive
SACSR: Writing "0" to the serial chip select
while transmitting in slave
SCEIE
flag bit (SACSR:CSE)
mode (SCR:MS="1")
(Correct)
Serial chip select pin is inactive
while transmitting in slave
mode (SCR:MS="1")
In master mode (SCR:MS=0),
SACSR: Writing "0" to the serial chip select
Transbecause the number of the
CSE SACSR
SCEIE
flag bit (SACSR:CSE)
mission
transmission times is below the
set value of TBYTE, and the
next transmission data is not
written to TDR (SSR:TDRE=1)
2012/
02/29
1501
40.6.1.7 The description of " Master Mode (SCR:MS="0")" was corrected as shown below.
(Error)
· Chip select is used
· Synchronous transmission with the serial timer is used
· Transmission activated by external trigger is used
(Correct)
· Chip select is used
· Synchronous transmission with the serial timer is used
37/42
Date
2012/
02/29
Page
1536
Item Description
40.6.2.5 The description of " How to Start Serial Timer" was corrected as shown below.
(Error) There are two ways to start the serial timer: setting "1" to the serial timer enable bit (SACSR:TMRE) or
starting by the external trigger.
(Correct) To start the serial timer: setting "1" to the serial timer enable bit (SACSR:TMRE).
2012/
02/29
1536
40.6.2.5 The description of "· Start by using the serial timer enable bit (SACSR:TMRE)" was corrected as shown below.
(Error) When the external trigger enable bit (SACSR:TRGE) is set to "0" and the serial timer enable bit
(SACSR:TMRE) is set to "1", the serial timer starts and the serial timer register (STMR) starts counting from 0.
(Correct) When the serial timer enable bit (SACSR:TMRE) is set to "1", the serial timer starts and the serial timer
register (STMR) starts counting from 0.
2012/
02/29
1536
40.6.2.5 The title of "Figure 6-16" was corrected as shown below.
(Error) Start by Using Serial Timer Enable Bit (STMCR="10", SACSR:TRGE=TSYNE="0")
(Correct) Start by Using Serial Timer Enable Bit (STMCR="10", SACSR: TSYNE="0")
2012/
02/29
1536
40.6.2.5 The "· Start by External Trigger" of " How to Start Serial Timer" was deleted.
2012/
02/29
1539
40.6.2.5 The following description was deleted from notes of " Synchronous Transmission Operation".
· If the synchronous transmission is enabled (SACSR:TSYNE="1"), the external trigger is enabled
(SACSR:TRGE="1"), and the serial timer comparison register (STMCR) is set to (0000)H, it will not
operate the synchronous transmission but the transmission by external trigger.
2012/
02/29
1539
to
1541
40.6.2.5 The "Operation of Serial Timer" of " Transmission Operation by External Trigger" was deleted.
38/42
Date
2012/
02/29
Page
1548
Item Description
40.6.2.6 The description of " Operation of Serial Chip Select to Maintain Active (SCSCR:SCAM=1) (Only Valid in Master
Mode (SCR:MS=0))" was corrected as shown below.
(Error)
· If the serial chip select active maintaining bit is "0", the serial chip select pin turns inactive after the hold
delay time has passed.
· If the serial chip select active maintaining bit is "1" and the serial timer synchronous transmission is used,
the serial chip select pin is maintained to be active. Then, when the serial timer value (STMR) and the
serial timer comparison value (STMCR) are matched, transmission operation is restarted. After that, the
serial chip select pin is maintained to be active until the frame transmission is completed as many as the
number of times set with TBYTE.
· If the serial chip select active maintaining bit is "1" and the serial timer external trigger transmission is
used, the serial chip select pin is maintained to be active. After that, if the edge of the external trigger
which is set with the trigger selection bit (SACSR:TRG1, 0) is detected, the transmission operation is
restarted.
(Correct)
· If the serial chip select active maintaining bit is "0", the serial chip select pin turns inactive after the hold
delay time has passed.
· If the serial chip select active maintaining bit is "1" and the serial timer synchronous transmission is used,
the serial chip select pin is maintained to be active. Then, when the serial timer value (STMR) and the
serial timer comparison value (STMCR) are matched, transmission operation is restarted. After that, the
serial chip select pin is maintained to be active until the frame transmission is completed as many as the
number of times set with TBYTE.
2012/
02/29
1582
40.7.3
The description of " How to Start Serial Timer" was corrected as shown below.
(Error) There are three ways to start the serial timer: setting "1" to the serial timer enable bit (SACSR:TMRE), starting
by the external trigger, and starting by the Sync Field.
(Correct) There are two ways to start the serial timer: setting "1" to the serial timer enable bit (SACSR:TMRE) and
starting by the Sync Field.
2012/
02/29
1582
40.7.3
The description of "· Start by using the serial timer enable bit (SACSR:TMRE)" was corrected as shown below.
(Error) When the external trigger enable bit (SACSR:TRGE) is set to "0" and the serial timer enable bit
(SACSR:TMRE) is set to "1", the serial timer starts and the serial timer register (STMR) starts counting from 0.
(Correct) When the serial timer enable bit (SACSR:TMRE) is set to "1", the serial timer starts and the serial timer
register (STMR) starts counting from 0.
2012/
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40.7.3
The title of "Figure 7-16" was corrected as shown below.
(Error) Start by Using Serial Timer Enable Bit (STMCR="10", SACSR:TRGE=TSYNE="0")
(Correct) Start by Using Serial Timer Enable Bit (STMCR="10", SACSR:TSYNE="0")
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40.7.3
The "· Start by External Trigger" of " How to Start Serial Timer" was deleted.
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1583
40.7.3
The following description was deleted from notes of " How to Start Serial Timer ".
When the external trigger enable bit (SAGSR:TRGE) is "1" and the serial timer enable bit (SAGSR:TMRE) is "0",
the serial timer does not operate even if the edge of the external trigger set by the trigger selection bit (SAGSR:TRG1,
0) is detected.
39/42
Date
2012/
02/29
Page
1599
Item Description
40.7.5.1  Slave Operations
The descriptionn of "method of confirming the automatic baud rate adjustment" was corrected as shown below.
The descriptionn of "method of confirming SACSR:BST bit" was deleted.
(Error)
There are two methods that it is confirmed whether the automatic baud rate adjustment was executed in from LIN
Break Field reception to Synch Field reception.
· Method of comparing BGR with STMR
· Method of confirming SACSR:BST bit
(Correct)
The method that it is confirmed whether the automatic baud rate adjustment was executed in from LIN Break Field
reception to Synch Field reception. is as follows.
· Method of comparing BGR with STMR
·
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40.8.2.5 The description of " Activating Serial Timer" was corrected as shown below.
(Error) Activating a serial timer consists of two types: Setting "1" to the serial timer enable bit (SACSR:TMRE);
Activating by external trigger.
(Correct) Activating a serial timer: Setting "1" to the serial timer enable bit (SACSR:TMRE).
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40.8.2.5 The description of "·Activating with serial timer enable bit (SACSR:TMRE)" was corrected as shown below.
(Error) When external trigger enable bit (SACSR : TRGE) is set to "0", setting "1" to serial timer enable bit
(SACSR:TMRE) will activate the serial timer and the serial timer register (STMR) will start counting from "0".
(Correct) When the serial timer enable bit (SACSR:TMRE) is set to "1", the serial timer will activate the serial timer
and the serial timer register (STMR) will start counting from "0".
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40.8.2.5 The title of "Figure 8-5" was corrected as shown below.
(Error) Activating with Serial Timer Enable Bit (STMCR="10", SACSR:TRGE="0")
(Correct) Activating with Serial Timer Enable Bit (STMCR="10")
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and
1642
40.8.2.5 The "·Activating with external trigger" of " Activating Serial Timer" was deleted.
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Date
2012/
02/29
Page
1707
Item Description
41.4.1.4 The address of the "CAN interrupt pending register 3 (INTPND3), CAN interrupt pending register 4 (INTPND4)"
was corrected as shown below.
(Error)
Base-addr +
A0H
CAN interrupt pending
register 4
(INTPND4)
CAN interrupt pending
register 3
(INTPND3)
INTPND3, 4:
Read only
bit[15:8]
bit[7:0]
bit[15:8]
bit[7:0]
IntPnd
[64:57]
IntPnd
[56:49]
IntPnd
[48:41]
IntPnd
[40:33]
Reset: 00H
Reset: 00H
Reset: 00H
Reset: 00H
(Correct)
Base-addr +
A4H
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1707
CAN interrupt pending
register 4
(INTPND4)
CAN interrupt pending
register 3
(INTPND3)
INTPND3, 4:
Read only
bit[15:8]
bit[7:0]
bit[15:8]
bit[7:0]
IntPnd
[64:57]
IntPnd
[56:49]
IntPnd
[48:41]
IntPnd
[40:33]
Reset: 00H
Reset: 00H
Reset: 00H
Reset: 00H
41.4.1.4 The address of the "CAN message valid register 3 (MSGVAL3), CAN message valid register 4 (MSGVAL4)" was
corrected as shown below.
(Error)
CAN message valid
register 4
(MSGVAL4)
Base-addr +
B0H
CAN message valid
register 3
(MSGVAL3)
bit[15:8]
bit[7:0]
bit[15:8]
bit[7:0]
MsgVal
[64:57]
MsgVal
[56:49]
MsgVal
[48:41]
MsgVal
[40:33]
Reset: 00H
Reset: 00H
Reset: 00H
Reset: 00H
MSGVAL3, 4:
Read only
(Correct)
CAN message valid
register 4
(MSGVAL4)
Base-addr +
B4H
CAN message valid
register 3
(MSGVAL3)
bit[15:8]
bit[7:0]
bit[15:8]
bit[7:0]
MsgVal
[64:57]
MsgVal
[56:49]
MsgVal
[48:41]
MsgVal
[40:33]
Reset: 00H
Reset: 00H
Reset: 00H
Reset: 00H
41/42
MSGVAL3, 4:
Read only
Date
2012/
02/29
2012/
02/29
Page
1978
2070
Item
46.3.2
Description
The address of "Figure 3-2 Sector Configuration Diagram" was corrected as shown below.
(Error)
(Correct)
0x33_000
0x33_200
0x33_400
0x33_E00
0x33_FFF
0x33_0000
0x33_2000
0x33_4000
0x33_E000
0x33_FFFF
48.4.1.5 The function of bit7, bit6, bit5, bit4, bit3, bit2 of "Waveform Control Register SIGCR20" was corrected as shown
below.
(Error)
PSEL21
0
0
1
1
PSEL11
0
0
1
1
PSEL01
0
0
1
1
PSEL20
0
1
0
1
Function
PPG0/PPG8
PPG2/PPG10
PPG4/PPG12
Setting prohibited (operation is not guaranteed)
PSEL10
0
1
0
1
Function
PPG0/PPG8
PPG2/PPG10
PPG4/PPG11
Setting prohibited (operation is not guaranteed)
PSEL00
0
1
0
1
Function
PPG0/PPG8
PPG2/PPG10
PPG4/PPG11
Setting prohibited (operation is not guaranteed)
PSEL20
0
1
0
1
Function
PPG0
PPG2
PPG4
Setting prohibited (operation is not guaranteed)
PSEL10
0
1
0
1
Function
PPG0
PPG2
PPG4
Setting prohibited (operation is not guaranteed)
PSEL00
0
1
0
1
Function
PPG0
PPG2
PPG4
Setting prohibited (operation is not guaranteed)
(Correct)
PSEL21
0
0
1
1
PSEL11
0
0
1
1
PSEL01
0
0
1
1
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