The following document contains information on Cypress products. S6BP401A Power Management IC for Automotive ADAS Platform Quad Buck 2.1 MHz DC/DC Converter and Dual LDO with Watchdog Timer Data Sheet (Preliminary) Notice to Readers: This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications. Publication Number S6BP401A_DS405-00024 CONFIDENTIAL Revision 0.1 Issue Date February 19, 2015 v1.2 D a t a S h e e t ( P r e l i m i n a r y ) Notice On Data Sheet Designations Spansion issues data sheets with Advance Information or Preliminary designations to advise readers of product information or intended specifications throughout the product life cycle, including development, qualification, initial production, and full production. In all cases, however, readers are encouraged to verify that they have the latest information before finalizing their design. The following descriptions of Spansion data sheet designations are presented here to highlight their presence and definitions. Advance Information The Advance Information designation indicates that Spansion is developing one or more specific products, but has not committed any design to production. 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This type of document distinguishes these products and their designations wherever necessary, typically on the first page, the ordering information page, and pages with the DC Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first page refers the reader to the notice on this page. Full Production (No Designation on Document) When a product has been in production for a period of time such that no changes or only nominal changes are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include those affecting the number of ordering part numbers available, such as the addition or deletion of a speed option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a description or to correct a typographical error or incorrect specification. Spansion applies the following conditions to documents in this category: “This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur.” Questions regarding these document designations may be directed to your local sales office. 2 CONFIDENTIAL S6BP401A_DS405-00024-0v01-E, February 19, 2015 v1.2 S6BP401A Power Management IC for Automotive ADAS Platform Quad Buck 2.1 MHz DC/DC Converter and Dual LDO with Watchdog Timer Data Sheet (Preliminary) 1. Description S6BP401A is a power management IC, consists of quad buck 2.1 MHz DC/DC converter with built-in switching FETs, dual Low Drop-out regulator (LDOs) and a digital windowed watchdog timer. Having the switching FETs built-in, S6BP401A realizes high power conversion efficiency and high switching frequency up to 2.4 MHz. The internal FETs are capable to handle up to 3A load. As S6BP401A employs the current mode architecture, it has fast load transient response. Built-in output voltage setting resistors and compensation circuits reduce BOM cost and component area. 2. Features Quad Buck DC/DC Converter (DD1 to DD4) 3. – VIN Input Range: 4.5V to 5.5V – Switching Frequency – External clock mode: 1.8 MHz to 2.4 MHz – Internal clock mode: 2.0 MHz to 2.2 MHz – Built-in Switching FETs up to 3A – Built-in Output Voltage Setting Resistors – Built-in Compensation Circuits Dual LDO (LDO1, LDO2) – VIN Input Voltage Range: 2.97V to 5.5V – Built-in Output Voltage Setting resistors Power Good Monitor Output for each DC/DC Converters, LDOs Built-in Windowed Watchdog Timer (WDT) Under Voltage Lockout (UVLO) Thermal Shutdown (TSD) Over Current Protection (OCP) Over Voltage Protection (OVP) Independent Enabling for each DC/DC Converters and LDOs Load-independent Soft-Start Built-in Discharge Resistors Small 6 mm × 6 mm QFN-40 Package Applications Automotive Applications Advanced Driver Assistance Systems (ADAS) Camera Systems such as Security Camera Industrial Applications Publication Number S6BP401A_DS405-00024 Revision 0.1 Issue Date February 19, 2015 This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications. CONFIDENTIAL v1.2 D a t a S h e e t ( P r e l i m i n a r y ) Table of Contents 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 4 CONFIDENTIAL Description ..................................................................................................................................... 3 Features ......................................................................................................................................... 3 Applications .................................................................................................................................... 3 Typical Application.......................................................................................................................... 6 Pin Configuration ............................................................................................................................ 7 Pin Functions .................................................................................................................................. 8 Preset Output Voltage .................................................................................................................... 9 Block Diagram .............................................................................................................................. 11 Absolute Maximum Ratings .......................................................................................................... 13 Recommended Operating Conditions........................................................................................... 14 Electrical Characteristics .............................................................................................................. 15 Operating Mode List ..................................................................................................................... 20 Function........................................................................................................................................ 21 13.1 Turning ON and OFF Sequence ....................................................................................... 21 13.2 Over Current Protection .................................................................................................... 23 13.3 Over Voltage Protection .................................................................................................... 23 13.4 Thermal Shutdown (TSD) .................................................................................................. 24 13.5 Under Voltage Lockout (UVLO) ......................................................................................... 25 13.6 Soft-Start Operation .......................................................................................................... 25 13.7 Discharge Operation ......................................................................................................... 26 13.8 Power Good Monitor and Reset Function ......................................................................... 28 13.9 Watchdog Timer ................................................................................................................ 30 13.10 Internal Linear Regulator Output (VREG).......................................................................... 33 Circuit of General Operation ......................................................................................................... 34 Ordering Information..................................................................................................................... 36 Package Dimensions .................................................................................................................... 37 Major Changes ............................................................................................................................. 38 S6BP401A_DS405-00024-0v01-E, February 19, 2015 v1.2 D a t a S h e e t ( P r e l i m i n a r y ) Figures Figure 4-1 Typical Application..................................................................................................................... 6 Figure 5-1 Pin Configuration ...................................................................................................................... 7 Figure 8-1 Block Diagram .......................................................................................................................... 11 Figure 9-1 Maximum Power Dissipation - Operating Ambient Temperature Characteristics .................... 14 Figure 13-1 Turning ON and OFF Sequence (where EN1 and ENL1 are Connected to VCC) ................ 21 Figure 13-2 Turning ON and OFF Sequence (where EN1 and ENL1 are Respectively Controlled) ......... 22 Figure 13-3 LDO Foldback Over Current Protection Characteristic .......................................................... 23 Figure 13-4 Over Voltage Protection Timing Chart ................................................................................... 24 Figure 13-5 Thermal Shutdown Timing Chart ........................................................................................... 24 Figure 13-6 Soft-Start Operation Timing Chart ......................................................................................... 25 Figure 13-7 Discharge Diagram (DC/DC Converter) ................................................................................ 26 Figure 13-8 Discharge Diagram (LDO)..................................................................................................... 27 Figure 13-9 Power-Good Monitor Output Timing Chart (PG1, PG2, PG3, PG4, PGL2) ........................... 29 Figure 13-10 Power-Good Monitor Output Timing Chart (RST) ............................................................... 29 Figure 13-11 Watchdog Timer State Diagram .......................................................................................... 30 Figure 13-12 Window Watchdog Timing Chart (WDI) ............................................................................... 31 Figure 13-13 Window Watchdog Timing Chart (LD1) ............................................................................... 31 Figure 13-14 De-glitch of Window Watchdog Trigger Pulse ..................................................................... 32 Figure 13-15 VREG OVLO/UVLO Timing Chart ....................................................................................... 33 Tables Table 6-1 Pin Functions .............................................................................................................................. 8 Table 7-1 Preset Output Voltage (Buck DC/DC Converter) ........................................................................ 9 Table 7-2 Preset Output Voltage (LDO) .................................................................................................... 10 Table 9-1 Absolute Maximum Ratings ...................................................................................................... 13 Table 10-1 Recommended Operating Conditions ..................................................................................... 14 Table 11-1 Electrical Characteristics ......................................................................................................... 15 Table 12-1 Operation Mode List ............................................................................................................... 20 Table 13-1 Power Good Monitor and Reset Function Pin List .................................................................. 28 Table 14-1 Parts list .................................................................................................................................. 35 Table 15-1 Ordering information ............................................................................................................... 36 Table 15-2 Preset Code List ..................................................................................................................... 36 February 19, 2015, S6BP401A_DS405-00024-0v01-E CONFIDENTIAL 5 v1.2 D a t a S h e e t 4. ( P r e l i m i n a r y ) Typical Application Figure 4-1 Typical Application 6 CONFIDENTIAL S6BP401A_DS405-00024-0v01-E, February 19, 2015 v1.2 D a t a S h e e t 5. ( P r e l i m i n a r y ) Pin Configuration PG4 1 FB4 2 PVCC4 LDO2 PVCCL2 PVCCL1 LDO1 VCC PG1 VREG PG2 CP1 GND (Corner Pad) PGL2 Figure 5-1 Pin Configuration 40 39 38 37 36 35 34 33 32 31 (Corner Pad) 30 FB1 29 PVCC1 3 28 LX1 LX4 4 27 PGND1 PGND4 5 26 PGND2 25 PGND2 Top View EP (Exposed Pad) FB3 9 22 PVCC2 PG3 10 21 PVCC2 CP2 11 12 13 14 15 16 17 18 19 20 FB2 LX2 EN1 23 EN2 8 EN3 PVCC3 EN4 LX2 ENL1 24 ENL2 7 RST LX3 WDI 6 SYNC PGND3 (Corner Pad) February 19, 2015, S6BP401A_DS405-00024-0v01-E CONFIDENTIAL CP4 CP3 (Corner Pad) 7 v1.2 D a t a S h e e t 6. ( P r e l i m i n a r y ) Pin Functions Table 6-1 Pin Functions Functional Block Pin Number Pin Name I/O 19 30 EN1 FB1 I I Enable input terminal of DD1. Output voltage feedback terminal of DD1. 33 29 PG1 PVCC1 O - Power good output terminal of DD1. Power supply terminal of DD1. 28 27 LX1 PGND1 O - Inductor connect terminal of DD1. Power ground terminal of DD1. 18 20 EN2 FB2 I I Enable input terminal of DD2. Output voltage feedback terminal of DD2. 31 21, 22 PG2 PVCC2 O - Power good output terminal of DD2. Power supply terminal of DD2. 23, 24 25, 26 LX2 PGND2 O - Inductor connect terminal of DD2. Power ground terminal of DD2. 17 9 EN3 FB3 I I Enable input terminal of DD3. Output voltage feedback terminal of DD3. 10 8 PG3 PVCC3 O - Power good output terminal of DD3. Power supply terminal of DD3. 7 6 LX3 PGND3 O - Inductor connect terminal of DD3. Power ground terminal of DD3. 16 2 EN4 FB4 I I Enable input terminal of DD4. Output voltage feedback terminal of DD4. 1 3 PG4 PVCC4 O - Power good output terminal of DD4. Power supply terminal of DD4. 4 5 LX4 PGND4 O - Inductor connect terminal of DD4. Power ground terminal of DD4. 15 36 ENL1 PVCCL1 I - Enable input terminal of LD1. Power supply terminal of LD1. 35 14 LDO1 ENL2 O I Output terminal of LD1. Enable input of LD2. 40 37 PGL2 PVCCL2 O - Power good output terminal of LD2. Power supply terminal of LD2. 38 12 LDO2 WDI O I Output terminal of LD2. Trigger input terminal of WDT. SYNC 13 11 RST SYNC O I Reset input terminal of WDT. External clock input terminal. - 34 VCC - - 32 VREG O - 39 GND - Power supply terminal for analog controller. Internal 1.8V supply voltage capacitor terminal. Do NOT supply or load this terminal externally. Ground terminal for analog controller. - EP CP1, CP2, CP3, CP4 EP - CP - DD1 DD2 DD3 DD4 LD1 LD2 WDT - 8 CONFIDENTIAL Description Exposed pad. Connect to ground plane. Corner pad for reinforcing attachment to a board. Connect to ground plane. S6BP401A_DS405-00024-0v01-E, February 19, 2015 v1.2 D a t a S h e e t 7. ( P r e l i m i n a r y ) Preset Output Voltage Table 7-1 Preset Output Voltage (Buck DC/DC Converter) Preset Output Channel Voltage [V] DD1 DD2 DD3 DD4 Soft-start Time [ms] 1.200 1.200 1.225 1.250 1.225 1.250 1.275 1.300 1.275 1.300 1.325 1.500 1.325 1.500 1.525 1.550 1.525 1.550 1.575 1.000 1.575 1.000 1.025 1.050 1.025 1.050 1.075 1.100 1.075 1.100 1.125 1.150 1.125 1.150 1.175 1.200 1.175 1.200 1.225 1.250 1.225 1.250 1.275 1.200 1.275 1.200 1.225 1.250 1.225 1.250 1.275 1.500 1.275 1.500 1.525 1.550 1.525 1.550 1.575 1.800 1.575 1.800 1.825 1.850 1.825 1.850 1.875 2.500 1.875 2.500 2.525 2.550 2.525 2.550 2.575 3.300 2.575 3.300 3.325 3.350 3.325 3.350 3.375 3.400 3.375 3.400 Maximum Output Under Voltage Over Voltage Current [mA] Threshold [%] Threshold [%] 2000 94.0 106.0 3000 94.0 106.0 2000 95.2 106.0 1000 95.5 106.0 Note: − Soft-start time values are at fOSC = 2.1 MHz February 19, 2015, S6BP401A_DS405-00024-0v01-E CONFIDENTIAL 9 v1.2 D a t a S h e e t − ( P r e l i m i n a r y ) Refer to Chapter 11 for the minimum or maximum values of output voltage, under voltage threshold and over voltage threshold. Table 7-2 Preset Output Voltage (LDO) Preset Output Channel Voltage [V] LD1 LD2 Soft-start Time [ms] 3.300 3.300 3.325 3.350 3.325 3.350 3.375 3.400 3.375 3.400 1.200 1.225 1.200 1.225 1.250 1.275 1.250 1.275 1.800 1.825 1.800 1.825 1.850 1.875 1.850 1.875 2.800 2.825 2.800 2.825 2.850 2.875 2.850 2.875 Maximum Output Under Voltage Over Voltage Current [mA] Threshold [%] Threshold [%] 200 94.0 106.0 500 94.0 106.0 Note: − − 10 CONFIDENTIAL Soft-start time values are at fOSC = 2.1 MHz Refer to Chapter 11 for the minimum or maximum values of output voltage, under voltage threshold and over voltage threshold. S6BP401A_DS405-00024-0v01-E, February 19, 2015 v1.2 D a t a S h e e t 8. ( P r e l i m i n a r y ) Block Diagram Figure 8-1 Block Diagram << DD1 >> FB1 PVCC1 Discharge PWM Comparator Low Priority en1 Voltage Reference PWM AntiLogic Shoot Control Through Error Amplifier Slope Compensation Power Good Monitor pg1 LX1 Current Sense PGND1 Peak Current Comparator ss1 clk << DD2 >> FB2 PVCC2 Discharge en2 Voltage Reference PVCC2 PWM Comparator Low Priority PWM AntiLogic Shoot Control Through Error Amplifier Slope Compensation Power Good Monitor LX2 LX2 Current Sense PGND2 PGND2 pg2 Peak Current Comparator ss2 clk << DD3 >> FB3 PVCC3 Discharge PWM Comparator Low Priority en3 Voltage Reference PWM AntiLogic Shoot Control Through Error Amplifier Slope Compensation Power Good Monitor pg3 LX3 Current Sense PGND3 Peak Current Comparator ss3 clk << DD4 >> FB4 PVCC4 Discharge PWM Comparator Low Priority en4 Voltage Reference Power Good Monitor pg4 ss4 clk February 19, 2015, S6BP401A_DS405-00024-0v01-E CONFIDENTIAL PWM AntiLogic Shoot Control Through Error Amplifier Slope Compensation LX4 Current Sense PGND4 Peak Current Comparator 11 v1.2 D a t a S h e e t ( P r e l i m i n a r y ) << LDO1 >> Low Priority PVCCL1 Voltage Reference LDO1 Power Good Monitor Discharge pgl1 ssl1 enl1 << LDO2 >> Low Priority PVCCL2 Voltage Reference LDO2 Power Good Monitor Discharge pgl2 ssl2 enl2 << Main Control >> << Power Good monitor Output >> PG1 Thermal Shutdown VCC PG2 Under Voltage Lockout PG3 EN1 en1 EN2 en2 PG4 PGL2 EN3 en3 pg1 pg2 pg3 pg4 pgl2 Control Logic EN4 en4 ENL1 enl1 ENL2 enl2 << Watchdog Timer >> Watchdog Timer clk RST pgl1 WDI ss1 ss2 ss3 Soft-Start Control ss4 ssl1 enl2 clk VCC VCC VREG SYNC Linear Regulator Power Good Monitor Oscillator with Synchronization clk GND 12 CONFIDENTIAL S6BP401A_DS405-00024-0v01-E, February 19, 2015 v1.2 D a t a S h e e t 9. ( P r e l i m i n a r y ) Absolute Maximum Ratings Table 9-1 Absolute Maximum Ratings Parameter Symbol Input voltage LX voltage VCC PVCC1, PVCC2, PVCC3, PVCC4 PVCCL1, PVCCL2 -0.3 -0.3 +6.9 +6.9 V V VEN VWDI EN1, EN2, EN3, EN4, EN1L, EN2L WDI -0.3 -0.3 +6.9 +6.9 V V VSYNC VFB SYNC FB1, FB2, FB3, FB4 -0.3 -0.3 +6.9 +6.9 V V VPG VRST PG1, PG2, PG3, PG4, PGL2 RST -0.3 -0.3 +6.9 +6.9 V V VLX LX1, LX2, LX3, LX4 PVCC1 -VCC, PVCC2-VCC, PVCC3-VCC, PVCC4-VCC PGND1-GND, PGND2-GND, PGND3-GND, PGND4-GND -0.3 +6.9 V -0.3 +0.3 V -0.3 +0.3 V -0.3 +6.9 V -0.3 +6.9 V - 6940 mW -40 +150 °C -55 +150 °C VPGND-GND VPVCC-LX VVCC-INPUT Power dissipation PD Junction temperature TJ Storage temperature TSTG PVCC1-LX1, PVCC2-LX2, PVCC3-LX3, PVCC4-LX4 VCC-EN1, VCC-EN2, VCC-EN3, VCC-EN4, VCC-EN1L, VCC-EN2L, VCC-WDI, VCC-SYNC, VCC-FB1, VCC-FB2, VCC-FB3, VCC-FB4 TA ≤ + 25°C, Thermal resistance (θJA): 18°C /W (*1) - Max +6.9 Unit VPVCC VPVCCL VPVCC-VCC Voltage difference Rating Min -0.3 VVCC Power supply voltage Condition V *1: When the IC is mounted on 76.2 mm × 114.3 mm four-layer epoxy board. IC is mounted on a four-layer epoxy board, which terminal bias, and the IC’s thermal pad is connected to the epoxy board. WARNING 1. Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or temperature) in excess of absolute maximum ratings.Do not exceed any of these ratings. February 19, 2015, S6BP401A_DS405-00024-0v01-E CONFIDENTIAL 13 v1.2 D a t a S h e e t ( P r e l i m i n a r y ) Maximum Power dissipation PD [mW] Figure 9-1 Maximum Power Dissipation - Operating Ambient Temperature Characteristics 8000 7000 6000 5000 4000 3000 2000 1000 0 -60 -40 -20 0 20 40 60 80 100 120 140 Ambient Temperature TA [°C] 10. Recommended Operating Conditions Table 10-1 Recommended Operating Conditions Value Parameter Symbol Condition Power supply voltage VVCC VPVCC VCC PVCC1, PVCC2, PVCC3, PVCC4 VPVCCL VEN PVCCL1, PVCCL2 EN1, EN2, EN3, EN4, N1L, EN2L VWDI VSYNC WDI SYNC VFB VPG VRST Input voltage Operating ambient temperature TA Unit Min +4.5 Typ +5.0 Max +5.5 +2.97 VVCC +5.0 - V V 0 - VVCC VVCC V V 0 0 - VVCC VVCC V V FB1, FB2, FB3, FB4 PG1, PG2, PG3, PG4, PGL2 0 0 - VVCC +5.5 V V RST 0 - +5.5 V -40 +25 +125 °C - WARNING: 1. The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated under these conditions. 2. Any use of semiconductor devices will be under their recommended operating condition. 3. Operation under any conditions other than these conditions may adversely affect reliability of device and could result in device failure. 4. No warranty is made with respect to any use, operating conditions or combinations not represented on this data sheet. If you are considering application under any conditions other than listed herein, please contact sales representatives beforehand. 14 CONFIDENTIAL S6BP401A_DS405-00024-0v01-E, February 19, 2015 v1.2 D a t a S h e e t ( P r e l i m i n a r y ) 11. Electrical Characteristics VVCC = VPVCC = 5.0V, VPVCCL = 5.0V, TA = TJ = -40 to +125 °C, unless otherwise noted. Typical values are at TA = +25 °C. Table 11-1 Electrical Characteristics Value Parameter Symbol Condition Unit Min Typ Max - 1.0 - µA 4.10 3.80 4.25 3.95 4.40 4.10 V V - - 0.30 - V Temperature rising - 165 (*1) - °C - - 10 (*1) - °C - 2.0 - VVCC V - 0 - 0.4 V - 50 - µA 50 100 150 kΩ 1.74 1.80 1.86 V 5 - - mA 1.86 1.81 1.67 1.62 1.92 1.87 1.73 1.68 1.98 1.93 1.79 1.74 V V V V 2.0 2.1 2.2 MHz 2.0 0 50 1.8 - 50 100 2.1 fSYNC VVCC 0.4 150 2.4 - V V µA kΩ MHz MHz Supply Current VCC PIN, VEN1 = VEN2 = VEN3 = VEN4 = VENL1 = VENL2 = 0V UVLO: Under Voltage Lockout (VCC) Shutdown current IVCCS Threshold voltage VUVLOR VUVLOF VVCC rising, UVLO release voltage VVCC falling, UVLO stop voltage Hysteresis VUVHYS TSD: Thermal Shutdown Shutdown temperature Hysteresis TTSD TTSDHYS Enable Inputs (EN1, EN2, EN3, EN4, ENL1, ENL2) Input high voltage VIHEN Input low voltage VILEN Input current IIHEN Pull down resistance RPDEN VEN = 5.0V - Internal Linear Regulator Output (VREG) Output voltage VVREG VVCC = 5.0V Maximum output IVREG VVCC = 5.0V current VVREGOVR VVREG rising, Power fail Over voltage lockout threshold VVREGOVF VVREG falling, Power good Under voltage lockout VVREGUVR VVREG rising, Power good threshold VVREGUVF VVREG falling, Power fail Oscillator Switching frequency fOSC Synchronization Input (SYNC) Input high voltage VIHSYNC Input Low voltage VILSYNC Input current IIHSYNC VEN = 5.0V Pull down resistance RPDSYNC Input frequency fSYNC Switching frequency fOSC - February 19, 2015, S6BP401A_DS405-00024-0v01-E CONFIDENTIAL 15 v1.2 D a t a S h e e t ( P r e l i m i n a r y ) Value Parameter Symbol Condition Power Good Monitor (PG1, PG2, PGL2) Over voltage Ratio of power fail threshold to VOUT1, VPGOV threshold VOUT2, VOUTL2 rising Over voltage VPGOVHYS hysteresis Under voltage Ratio of power fail threshold to VOUT1, VPGUV threshold VOUT2, VOUT3 falling Under voltage VPGUVHYS hysteresis Leakage current ILEAKPG VPG = 5.0V Output low voltage VOLPG IPG = 3 mA Propagation time TPPG 5% outside of the threshold, Power fail Power-on reset time TRPG Power good Power Good Monitor (PG3) Over voltage VPGOV Ratio of power fail threshold to VOUT3 rising threshold Over voltage VPGOVHYS hysteresis Under voltage Ratio of power fail threshold to VOUT3 VPGUV threshold falling Under voltage VPGUVHYS hysteresis Leakage current ILEAKPG VPG = 5.0V Output low voltage VOLPG IPG = 3 mA Propagation time TPPG 5% outside of the threshold, Power fail Power-on reset time TRPG Power good Power Good Monitor (PG4) Over voltage VPGOV Ratio of power fail threshold to VOUT4 rising threshold Over voltage VPGOVHYS hysteresis Under voltage Ratio of power fail threshold to VOUT4 VPGUV threshold falling Under voltage VPGUVHYS hysteresis Leakage current ILEAKPG VPG = 5.0V Output low voltage VOLPG IPG = 3 mA Propagation time TPPG 5% outside of the threshold, Power fail Power-on reset time TRPG Power good Reset (RST) Over voltage Ratio of power fail threshold to VOUTL1 VRSOV threshold rising Over voltage VRSOVHYS hysteresis Under voltage Ratio of power fail threshold to VOUTL1 VRSUV threshold falling Under voltage VRSUVHYS hysteresis Leakage current ILEAKRST VRST = 5.0V Output low voltage VOLRST IPG = 3 mA Propagation time TPRST 5% outside of the threshold, Power fail Power-on reset time TRD Power good 16 CONFIDENTIAL Unit Min Typ Max 104.5 106.0 107.5 % - 1.0 - % 92.5 94.0 95.5 % - 1.0 - % 8 0.15 4 (*1) 10 1 0.30 8 (*1) 12 µA V µs ms 104.5 106.0 107.5 % - 1.0 - % 93.7 95.2 96.7 % - 1.0 - % 8 0.15 4 (*1) 10 1 0.30 8 (*1) 12 µA V µs ms 104.5 106.0 107.5 % - 1.0 - % 94.0 95.5 97.0 % - 1.0 - % 8 0.15 4 (*1) 10 1 0.30 8 (*1) 12 µA V µs ms 104.5 106.0 107.5 % - 1.0 - % 92.5 94.0 95.5 % - 1.0 - % 25.6 0.15 4 (*1) 32.0 1 0.30 8 (*1) 38.4 µA V µs ms S6BP401A_DS405-00024-0v01-E, February 19, 2015 v1.2 D a t a S h e e t ( P r e l i m i n a r y ) Value Parameter Symbol Watchdog Timer (WDI) Watchdog sampling TSAM time Ignore window time TIW Open window time TOW Long open window TLOW time Closed window time TCW Window watchdog TWD trigger time Input high voltage VIHWDI Input low voltage VILWDI Input current IIHWDI Pull down resistance RPDWDI DD1: Buck DC/DC Converter Output voltage VOUT1 accuracy DC regulation VREG1 FB1 input resistance RFB1 RONHS1 Switching FET ON resistance RONLS1 Switching FET ILEAK1 leakage current Maximum output IOUT1 current LX1 peak current limit ILIMIT1 Over voltage VOVP1 protection threshold Over voltage VOVPHYS1 protection hysteresis FB1 discharge RDIS1 resistance Soft-start time TCOESS1 coefficient DD2: Buck DC/DC Converter Output voltage VOUT2 accuracy DC regulation VREG2 FB2 input resistance Switching FET ON resistance Switching FET leakage current Maximum output current LX2 peak current limit Over voltage protection threshold Over voltage protection hysteresis FB2 discharge resistance Soft-start time coefficient RFB2 RONHS2 RONLS2 Condition Typ Max - 0.40 0.50 0.60 ms - 25.6 25.6 32.0 32.0 38.4 38.4 ms ms - 102.4 128.0 153.6 ms - 25.6 32.0 38.4 ms - - 48 - ms - 2.0 0 50 50 100 VVCC 0.4 150 V V µA kΩ -1.8 0 +1.8 % -15 (*1) 0 +5 (*1) mV - 190 130 100 - kΩ mΩ mΩ - 1 - µA 2 (*1) - - A 2.5 (*1) - - A 125.0 130.0 135.0 % - - 5.0 - % - - 400 - Ω fOSC = 2.1 MHz, TSS1 = VOUT1 x TCOESS1 - 1.0 - ms/V -1.8 0 +1.8 % -15 (*1) 0 +5 (*1) mV - 190 110 80 - kΩ mΩ mΩ - 1 - µA 3 (*1) - - A 3.5 (*1) - - A 125.0 130.0 135.0 % VWDI = 5.0V VVCC = 5.0V, IOUT1 = 10 mA VVCC = VPVCC1 = 4.5 to 5.5V, IOUT1 = 0 to 2.0A VFB1 = 2.0V ILX1 = 20 mA (PVCC1 to LX1) ILX1 = -20 mA (LX1 to PGND1) IPVCC1 = 5.0V L = 1.5 µH L = 1.5 µH VOUT1 rising, Switching termination threshold VVCC = 5.0V, IOUT2 = 10 mA VVCC = VPVCC2 = 4.5 to 5.5V IOUT2 = 0 to 3.0A VFB2 = 2.0V ILX2 = 20 mA (PVCC2 to LX2) ILX2 = -20 mA (LX2 to PGND2) IPVCC2 = 5.0V IOUT2 L = 1.5 µH ILIMIT2 L = 1.5 µH VOUT2 rising, Switching termination threshold VOVPHYS2 - - 5.0 - % RDIS2 - - 400 - Ω TCOESS2 fOSC = 2.1 MHz, TSS2 = VOUT2 x TCOESS2 - 1.0 - ms/V February 19, 2015, S6BP401A_DS405-00024-0v01-E CONFIDENTIAL - ILEAK2 VOVP2 Unit Min 17 v1.2 D a t a S h e e t Parameter DC regulation VREG3 FB3 input resistance RFB3 RONHS3 Switching FET ON resistance RONLS3 Switching FET ILEAK3 leakage current Maximum output IOUT3 current LX3 peak current limit ILIMIT3 Over voltage VOVP3 protection threshold Over voltage VOVPHYS3 protection hysteresis FB3 discharge RDIS3 resistance Soft-start time TCOESS3 coefficient DD4: Buck DC/DC Converter Output voltage VOUT4 accuracy DC regulation VREG4 FB4 input resistance Switching FET ON resistance Switching FET leakage current Maximum output current LX4 peak current limit Over voltage protection threshold Over voltage protection hysteresis FB4 discharge resistance Soft-start time coefficient RFB4 RONHS4 RONLS4 18 CONFIDENTIAL Condition Symbol DD3: Buck DC/DC Converter Output voltage VOUT3 accuracy ( P r e l i m i n a r y ) Unit Typ Max -1.8 0 +1.8 % -15 (*1) 0 +5 (*1) mV - 190 130 100 - kΩ mΩ mΩ - 1 - µA 2 (*1) - - A 2.5 (*1) - - A 125.0 130.0 135.0 % - - 5.0 - % - - 400 - Ω fOSC = 2.1 MHz, TSS3 = VOUT3 × TCOESS3 - 1.0 - ms/V -1.8 0 +1.8 % -15 (*1) 0 +5 (*1) mV - 190 130 100 - kΩ mΩ mΩ - 1 - µA 1 (*1) - - A 1.5 (*1) - - A 125.0 130.0 135.0 % VVCC = 5.0V, IOUT3 = 10 mA VVCC = VPVCC3 = 4.5 to 5.5V, IOUT3 = 0 to 2.0A VFB3 = 2.0V ILX3 = 20 mA (PVCC3 to LX3) ILX3 = -20 mA (LX3 to PGND3) IPVCC3 = 5.0V L = 1.5 µH L = 1.5 µH VOUT3 rising, Switching termination threshold VVCC = 5.0V, IOUT4 = 10 mA VVCC = VPVCC4 = 4.5 to 5.5V, IOUT4 = 0 to 1.0A VFB4 = 2.0V ILX4 = 20 mA (PVCC4 to LX4) ILX4 = -20 mA (LX4 to PGND4) ILEAK4 IPVCC4 = 5.0V IOUT4 L = 1.5 µH ILIMIT4 L = 1.5 µH VOUT4 rising, Switching termination threshold VOVP4 Value Min VOVPHYS4 - - 5.0 - % RDIS4 - - 400 - Ω TCOESS4 fOSC = 2.1 MHz, TSS4 = VOUT4 × TCOESS4 - 1.0 - ms/V S6BP401A_DS405-00024-0v01-E, February 19, 2015 v1.2 D a t a S h e e t ( P r e l i m i n a r y ) Value Parameter LD1: LDO Regulator Output voltage accuracy DC regulation Output FET leakage current Maximum output current Output current limit LDO1 discharge resistance Soft-start time coefficient LD2: LDO Regulator Output voltage accuracy DC regulation Output FET leakage current Maximum output current Output current limit Symbol VOUTL1 VREGL1 ILEAKL1 IOUTL1 ILIMITL1 Condition VVCC = 5.0V, IOUTL1 = 10 mA VVCC = 4.5 to 5.5V, VPVCCL1 = 2.97 to VVCC IOUTL1 = 0 to IOUTL1 IPVCCL1=5.0V VPVCCL1 - VOUTL1 ≥ 1.6V 0.17V ≤ VPVCCL1 - VOUTL1 < 1.6V VPVCCL1 - VOUTL1 ≥ 1.6V 0.17V ≤ VPVCCL1 - VOUTL1 < 1.6V Typ Max -1.8 0 +1.8 % -15 (*1) 0 +5 (*1) mV - 1 - µA 200 (*1) 100 (*1) 210 (*1) 105 (*1) - - mA mA mA mA RDISL1 - - 400 - Ω TCOESSL1 fOSC = 2.1 MHz, TSSL1 = VOUTL1 × TCOESSL1 - 1.0 - ms/V -1.8 0 +1.8 % -15 (*1) 0 +5 (*1) mV - 1 - µA 500 (*1) 400 (*1) 525 (*1) 420 (*1) - - mA mA mA mA - 400 - Ω - 1.0 - ms/V VOUTL2 VREGL2 ILEAKL2 IOUTL2 ILIMITL2 VVCC = 5.0V, IOUTL2 = 10 mA VVCC = 4.5 to 5.5V, VPVCCL2 = 2.97 to VVCC IOUTL2 = 0 to IOUTL2 IPVCCL2=5.0V VPVCCL2 - VOUTL2 ≥ 1.6V 0.17V ≤ VPVCCL2 - VOUTL2 < 1.6V VPVCCL2 - VOUTL2 ≥ 1.6V 0.17V ≤ VPVCCL2 - VOUTL2 < 1.6V LDO2 discharge RDISL2 resistance Soft-start time TCOESSL2 fOSC = 2.1 MHz, TSSL2 = VOUTL2 × TCOESSL2 coefficient *1: Not production tested, ensured by design. February 19, 2015, S6BP401A_DS405-00024-0v01-E CONFIDENTIAL Unit Min 19 v1.2 D a t a S h e e t ( P r e l i m i n a r y ) 12. Operating Mode List Table 12-1 shows the operation list of S6BP401A. Table 12-1 Operation Mode List Condition Operating Block TJ SYNC ENL1 EN1/ EN2/ EN3/ EN4/ ENL2 < TTSD < TTSD L or H L or H L L L H OFF ON OFF ON OFF OFF OFF OFF OFF OFF OFF ON < TTSD < TTSD L or H L or H H H L H ON ON ON ON ON ON OFF OFF ON ON OFF ON < TTSD < TTSD clock clock L L L H OFF ON OFF ON OFF OFF OFF ON OFF OFF OFF ON < TTSD < TTSD clock clock H H L H ON ON ON ON ON ON ON ON ON ON OFF ON ≥ TTSD ≥ TTSD L or H L or H L L L H OFF ON OFF ON OFF OFF OFF OFF OFF OFF OFF OFF ≥ TTSD ≥ TTSD L or H L or H H H L H ON ON ON ON OFF OFF OFF OFF OFF OFF OFF OFF ≥ TTSD ≥ TTSD clock clock L L L H OFF ON OFF ON OFF OFF OFF OFF OFF OFF OFF OFF ≥ TTSD ≥ TTSD clock clock H H L H ON ON ON ON OFF OFF OFF OFF OFF OFF OFF OFF 20 CONFIDENTIAL Chip Control VREG LDO Watchdog Trigger Monitor Freq. Sync. LD1 DD1/ DD2/ DD3/ DD4/ LD2 S6BP401A_DS405-00024-0v01-E, February 19, 2015 v1.2 D a t a S h e e t ( P r e l i m i n a r y ) 13. Function 13.1 Turning ON and OFF Sequence When all of the enable input terminals (EN1, EN2, EN3, EN4, ENL1 and ENL2) are “Low”, the device is in shutdown state. When any one or more than one of them go “High,” the device is initialized, then the internal linear regulator (VREG) starts generating 1.8V internal supply voltage. After that, each DC/DC converters and LDOs state is transitioned to the state which can be started. In order for the device to start, the VCC terminal voltage must be higher than the under-voltage lockout threshold (VUVLOR). Figure 13-1 depicts the turning-on and off sequence where the enable signals are connected to VCC. Figure 13-2 depicts that where the enable signals are respectively controlled after the IC is powered. Figure 13-1 Turning ON and OFF Sequence (where EN1 and ENL1 are Connected to VCC) VUVLOR VUVLOF VVCC VEN1 VENL1 VVREG VOUT1 VRSUV+VRSUVHYS 10% TYP:40.5ms(*1) VRSUV+VRSUVHYS VOUTL1 10% TYP:0.92ms(*1) VRST Initialization (TYP:1ms) TRD Time *1: Given that the system employs the same external parts with those specified in “Typical Application” February 19, 2015, S6BP401A_DS405-00024-0v01-E CONFIDENTIAL 21 v1.2 D a t a S h e e t ( P r e l i m i n a r y ) Figure 13-2 Turning ON and OFF Sequence (where EN1 and ENL1 are Respectively Controlled) VUVLOR VVCC VEN1 VENL1 VVREG VOUT1 VRSUV+VRSUVHYS 10% TYP:40.5ms(*1) VRSUV+VRSUVHYS VOUTL1 10% TYP:0.92ms(*1) VRST Initialization (TYP:1ms) TRD Initialization (TYP:1ms) Time *1: Given that the system employs the same external parts with those specified in “Typical Application” 22 CONFIDENTIAL S6BP401A_DS405-00024-0v01-E, February 19, 2015 v1.2 D a t a S h e e t ( P r e l i m i n a r y ) 13.2 Over Current Protection The over current protection of the DC/DC converters detects the inductor peak current with on-resistance of Internal high side switching FET. If the DC/DC converter is over current state, the corresponding output voltage is decreased. If the device returns from over current state, the output voltage is target voltage. Each LDOs equips foldback current limiter in order to prevent the IC itself from being damaged or destroyed. The curve of output current and output voltage in over current state is shown in the Figure 13-3. Figure 13-3 LDO Foldback Over Current Protection Characteristic Voltage VOUTL1 VOUTL2 ISL1 ISL2 IOUTL1 IOUTL2 ILIMITL1 ILIMITL2 Current 13.3 Over Voltage Protection The over voltage protection of the DC/DC converters detects the output voltage. If the DC/DC converter is over voltage state, the corresponding channel stops switching and inductor connecting terminal (LX1, LX2, LX3, LX4) is held at high impedance. If the device returns from over voltage state, the channel returns switching automatically. February 19, 2015, S6BP401A_DS405-00024-0v01-E CONFIDENTIAL 23 v1.2 D a t a S h e e t ( P r e l i m i n a r y ) Figure 13-4 Over Voltage Protection Timing Chart VEN1,VEN2, VEN3,VEN4 VOVPHYS1, VOVPHYS2, VOVPHYS3, VOVPHYS4 VOVP1, VOVP2, VOVP3, VOVP4 VPGOV VOUT1,VOUT2, VOUT3,VOUT4 VPGOVHYS TPPG TRPG TRPG VPG1,VPG2, VPG3,VPG4 LX1, LX2, LX3, LX4 Hi-Z Discharge ON Switching Hi-Z Switching OFF Time 13.4 Thermal Shutdown (TSD) If the junction temperature reaches +165°C, all DC/DC converters and LDOs stop outputting voltage. Then the discharge operation is carried out to discharge the output capacitor (The discharge operation continues until the state of the thermal shutdown released.) When the junction temperature drops below +155°C, the soft-starters activate regulators and start generating voltage gradually if the enable is "High." Figure 13-5 Thermal Shutdown Timing Chart TJ 165 deg. 155 deg. VEN1 VOUT1 Soft-Start Soft-Start Time 24 CONFIDENTIAL S6BP401A_DS405-00024-0v01-E, February 19, 2015 v1.2 D a t a S h e e t ( P r e l i m i n a r y ) 13.5 Under Voltage Lockout (UVLO) If the VCC terminal voltage (VVCC) drops below the lower UVLO threshold (VUVLOF), all DC/DC converters (DD1, DD2, DD3, DD4), LDOs (LD1, LD2), windowed watchdog timer (WDT) and the internal linear regulator (VREG) stop working. When the VCC terminal voltage (VVCC) is raised higher than the higher UVLO threshold (VUVLOR), the device returns automatically. 13.6 Soft-Start Operation S6BP401A equips load-independent soft-start function in order to prevent the DC/DC converters and LDOs from having rush current at the start-up. The soft-start timing is shown in the Figure 13-6, and is given by the following equation; 𝑇𝑆𝑆 = 𝑉𝑂𝑈𝑇 × 𝑇𝐶𝑂𝐸𝑆𝑆 , where TSS [ms] : Soft-start time VOUT [V] : Output voltage (VOUT1, VOUT2, VOUT3, VOUT4, VOUTL1, VOUTL2) TCOESS [ms/V] : Soft-start time coefficient (TCOESS1, TCOESS2, TCOESS3, TCOESS4, TCOESSL1, TCOESSL2) Figure 13-6 Soft-Start Operation Timing Chart VEN VOUT(3) VOUT(2) VOUT(1) VOUT TSS=VOUT(1)×TCOESS TSS=VOUT(2)×TCOESS TSS=VOUT(3)×TCOESS Time February 19, 2015, S6BP401A_DS405-00024-0v01-E CONFIDENTIAL 25 v1.2 D a t a S h e e t ( P r e l i m i n a r y ) 13.7 Discharge Operation When an enable signal goes “Low”, the corresponding output capacitor is discharged by the internal discharge resistor and the output voltage is decreased gradually. Note that the discharge time is not consistent: it depends on the output load current. As for a DC/DC converter, the output capacitor is discharged from FB1, FB2, FB3 and FB4 terminal to PGND1, PGND2, PGND3 and PGND4 terminal respectively. As for a LDO, the output capacitor is dis-charged from LDO1, LDO2 terminal to GND terminal. The discharge time required to decrease the output voltage by 90% without any explicit load given by the following equation; 𝑇𝐷𝐼𝑆 = 2.3 × 𝑅𝐷𝐼𝑆 × 𝐶𝑂𝑈𝑇 , where TDIS [ms] : Discharge time RDIS [kΩ] : Discharge resistance (RDIS1, RDIS2, RDIS3, RDIS4, RDISL1, RDISL2) COUT [µF] : Output capacitor Figure 13-7 Discharge Diagram (DC/DC Converter) PVCC1,PVCC2, PVCC3,PVCC4 Power Supply FB1,FB2, FB3,FB4 Error Amp. RDIS1, RDIS2, RDIS3, RDIS4 PWM Control LX1,LX2, LX3,LX4 PGND1,PGND2, PGND3,PGND4 enable 26 CONFIDENTIAL S6BP401A_DS405-00024-0v01-E, February 19, 2015 v1.2 D a t a S h e e t ( P r e l i m i n a r y ) Figure 13-8 Discharge Diagram (LDO) PVCCL1,PVCCL2 Power Supply LDO1,LDO2 RDISL1, RDISL2 enable February 19, 2015, S6BP401A_DS405-00024-0v01-E CONFIDENTIAL 27 v1.2 D a t a S h e e t ( P r e l i m i n a r y ) 13.8 Power Good Monitor and Reset Function Each DC/DC converters and LDOs has power good function to indicate whether the output voltage is in the expected range. The Table 13-1 describes the power good pin names and their functions of each DC/DC converters and LDOs. The Figure 13-9 and Figure 13-10 depict power-good timing chart. Table 13-1 Power Good Monitor and Reset Function Pin List Channel Pin Name Description PG1 Enabling DD1 is followed by rising of the DD1 output voltage (V OUT1). Once VOUT1 reaches within the power good range (VPGUV + VPGUVHYS < VOUT1 < VPGOV – VPGOVHYS), the power good monitor output (PG1 terminal) changes its state from “Low” to “Open” after a power-on-reset time (TRPG). When VOUT1 is out of the power good range (VOUT1 ≤ VPGUV or VOUT1 ≥ VPGOV), PG1 terminal changes its state from “Open” to “Low” after the propagation delay (TPPG). The glitch within TPPG does not affect the power good monitor output. PG2 Enabling DD2 is followed by rising of the DD2 output voltage (V OUT2). Once VOUT2 reaches within the power good range (VPGUV + VPGUVHYS < VOUT2 < VPGOV – VPGOVHYS), the power good monitor output (PG2 terminal) changes its state from “Low” to “Open” after a power-on-reset time (TRPG). When VOUT2 is out of the power good range (VOUT2 ≤ VPGUV or VOUT2 ≥ VPGOV), PG2 terminal changes its state from “Open” to “Low” after the propagation delay (TPPG). The glitch within TPPG does not affect the power good monitor output. DD1 DD2 DD3 PG3 DD4 PG4 LD1 RST LD2 PGL2 28 CONFIDENTIAL Enabling DD3 is followed by rising of the DD3 output voltage (V OUT3). Once VOUT3 reaches within the power good range (VPGUV + VPGUVHYS < VOUT3 < VPGOV – VPGOVHYS), the power good monitor output (PG3 terminal) changes its state from “Low” to “Open” after a power-on-reset time (TRPG). When VOUT3 is out of the power good range (VOUT3 ≤ VPGUV or VOUT3 ≥ VPGOV), PG3 terminal changes its state from “Open” to “Low” after the propagation delay (T PPG). The glitch within TPPG does not affect the power good monitor output. Enabling DD4 is followed by rising of the DD4 output voltage (V OUT4). Once VOUT4 reaches within the power good range (VPGUV + VPGUVHYS < VOUT4 < VPGOV – VPGOVHYS), the power good monitor output (PG4 terminal) changes its state from “Low” to “Open” after a power-on-reset time (TRPG). When VOUT4 is out of the power good range (VOUT4 ≤ VPGUV or VOUT4 ≥ VPGOV), PG4 terminal changes its state from “Open” to “Low” after the propagation delay (T PPG). The glitch within TPPG does not affect the power good monitor output. Enabling LD1 is followed by rising of the LD1 output voltage (V OUTL1). Once VOUTL1 reaches within the power good range (VRSUV + VRSUVHYS < VOUTL1 < VRSOV - VRSOVHYS), the RST terminal changes its state from “Low” to “Open” after a power-on-reset time (TRD). When VOUTL1 is out of the power good range (VOUTL1 ≤ VRSUV or VOUTL1 ≥ VRSOV), RST terminal changes “Open” to “Low” after the propagation delay (TPRST). The glitch within TPRST does not affect the power good monitor output. Enabling LD2 is followed by rising of the LD2 output voltage (V OUTL2). Once VOUTL2 reaches within the power good range (VPGUV + VPGUVHYS < VOUTL2 < VPGOV – VPGOVHYS), the power good monitor output (PGL2 terminal) changes its state from “Low” to “Open” through the power-on-reset time (TRPG). When VOUTL2 is out of the power good range (VOUTL2 ≤ VPGUV or VOUTL2 ≥ VPGOV), PGL2 terminal changes “Open” to “Low” after the propagation delay (T PPG). The glitch within TPPG does not affect the power good monitor output. S6BP401A_DS405-00024-0v01-E, February 19, 2015 v1.2 D a t a S h e e t ( P r e l i m i n a r y ) Figure 13-9 Power-Good Monitor Output Timing Chart (PG1, PG2, PG3, PG4, PGL2) VEN1,VEN2, VEN3,VEN4, VENL2 VOUT1,VOUT2, VOUT3,VOUT4, VOUTL2 VPGOVHYS VPGOV VPGUV VPGUVHYS Not reset VPG1,VPG2, VPG3,VPG4, VPGL2 TRPG < TPPG < TPPG TPPG TRPG TPPG TRPG Time Figure 13-10 Power-Good Monitor Output Timing Chart (RST) VENL1 VRSOVHYS VOUTL1 VRSOV VRSUV VRSUVHYS Not reset VRST TRD < TPRST February 19, 2015, S6BP401A_DS405-00024-0v01-E CONFIDENTIAL < TPRST TPRST TRD TPRST TRD Time 29 v1.2 D a t a S h e e t ( P r e l i m i n a r y ) 13.9 Watchdog Timer S6BP401A employs a digital windowed watchdog timer. The digital windowed watchdog timer starts monitoring trigger signal, when the LD1 output voltage (V OUTL1) reaches the power good level after enabling LD1. Figure 13-11 shows the state diagram of the digital watchdog timer. There are six states in the diagram. In the normal operation, the state is expected to move back and forth between “CW” and “OW”, At first, as described in the section 13.8, enabling LD1 brings “RESET” state, and the “RESET” state is kept for the “Reset Time (TRD)” outputting “Low” from RST terminal. In the second, after TRD in the “RESET” state, the state will transition to “Ignore Window (IW)”, and let RST terminal be “Open”. The “IW” state will be elapsed in the “Ignore Window Time (T IW.)” In the third, after elapsing, the state will transition will transition to “Long Open Window (LOW)” state, and let RST terminal be “Open.” In this state, a trigger signal is expected to be input: if an input trigger arrives, the state will immediately transition to the “Closed Window (CW)” state. Without an input trigger in the “Long Open Window Time (TLOW,)” the state will be elapsed and will transition to “RESET” state. In the “CW” state, a trigger signal is expected NOT to be input: if an input trigger arrives, the state will immediately transition to the “RESET” state. Without an input trigger in the “Closed Window Time (TCW,)” the state will be elapsed and will transition to “Open Window (OW)” state. In the “OW” state, a trigger signal is expected NOT to be input: if an input trigger arrives, the state will immediately transition to the “RESET” state. Without an input trigger in the “Open Window Time (T OW,)” the state will be elapsed and will transition to “Closed Window (CW)” state. In any states above, a power failure of LD1 will cause a transition to “OFF” state, and output “Low” from RST terminal until LD1 goes well. Figure 13-11 Watchdog Timer State Diagram OFF RST=Low LD1 power good LD1 power fail Reset RST=Low TRD timeout No Trigger (TLOW timeout) LD1 power fail IW RST=open T timeout IW Long OW RST=open Trigger LD1 power fail 30 CONFIDENTIAL Trigger No Trigger (TOW timeout) Trigger CW RST=open LD1 power fail No Trigger (TCW timeout) OW RST=open LD1 power fail S6BP401A_DS405-00024-0v01-E, February 19, 2015 v1.2 D a t a S h e e t ( P r e l i m i n a r y ) Figure 13-12 Window Watchdog Timing Chart (WDI) VRSUVHYS VOUTL1 TWD Ignore VWDI State OFF Reset Long OW IW No Trigger No No Trigger Trigger (Wrong) CW CW OW OW Reset VRSUV Wrong Trigger IW Long OW CW Reset IW Long Reset OW IW VRST TRD TIW <TLOW TCW <TOW TCW TOW <TCW Time Figure 13-13 Window Watchdog Timing Chart (LD1) VRSUVHYS VOUTL1 Trigger VWDI State OFF Reset IW Long OW CW OFF Reset IW TPRST VRST <TCW TRD Time February 19, 2015, S6BP401A_DS405-00024-0v01-E CONFIDENTIAL 31 v1.2 D a t a S h e e t ( P r e l i m i n a r y ) Figure 13-14 De-glitch of Window Watchdog Trigger Pulse Window Open Window Closed Window Closed Window TSAM Valid Not Valid H Watchdog Trigger Pulse H H L H L L Valid L H Not Valid H L L H H L Not Valid H H L H Not Valid L H L L L Time TCW TOW TCW : Sampling point 32 CONFIDENTIAL S6BP401A_DS405-00024-0v01-E, February 19, 2015 v1.2 D a t a S h e e t ( P r e l i m i n a r y ) 13.10 Internal Linear Regulator Output (VREG) S6BP401A equips a 1.8V linear regulator as the power source for its internal circuit. A low ESR 1.0µF ceramic capacitor should be connected from VREG pin to GND. VREG is not designed to supply to external load. Unless the VREG terminal voltage is in the range between the over voltage lockout level VVREGOVR and the under voltage lockout level VVREGUVF, S6BP401A considers it abnormal and halts all DC/DC converters, LDOs and windowed watchdog timer. When the VREG terminal voltage returns to the power good voltage range (VVREGUVR ≤ VVREG ≤ VVREGOVF), S6BP401A returns the DC/DC converters, LDOs and window watchdog timer to the normal mode. Soft-start circuits of each regulator gradually generates supply voltage as described in the section 13.6. Figure 13-15 VREG OVLO/UVLO Timing Chart VVREGOVR VVREGOVF VVREG VVREGUVR VVREGUVF VEN1,VEN2, VEN3,VEN4, VENL1,VENL2 VOUT1 Soft-Start Soft-Start Soft-Start VOUT2 Soft-Start Soft-Start Soft-Start Soft-Start Soft-Start Soft-Start Soft-Start Soft-Start Soft-Start Soft-Start Soft-Start Soft-Start Soft-Start Soft-Start Soft-Start Initialization Initialization VOUT3 VOUT4 VOUTL1 VOUTL2 Initialization Time February 19, 2015, S6BP401A_DS405-00024-0v01-E CONFIDENTIAL 33 v1.2 D a t a S h e e t ( P r e l i m i n a r y ) 14. Circuit of General Operation VOUT1 VIN 5V VIN 30 PVCC1 29 VOUT1 C1 GND FB1 28 VOUT1 PGND1 27 VOUT2 FB2 VIN PVCC2a 21 PVCC2b 22 C7 20 C3 L1 C2 LX1 LX2a 23 LX2b 24 VOUT2 VOUT2 C10 C9 C8 L2 PGND2a 25 PGND2b 26 VOUT3 VIN 8 VOUT3 L3 VOUT3 7 C16 LX3 PGND3 6 VOUT4 FB4 PVCC4 VIN 3 C21 2 S6BP401A LX4 PGND4 PVCCL1 LDO1 EN1 19 EN2 18 EN3 17 EN4 16 ENL1 15 ENL2 14 VOUT4 L4 VOUT4 4 C22 M1 C17 PVCC3 C23 FB3 C15 9 5 VIN 36 C27 35 C28 VOUTL1 VOUTL1 EN1 EN2 EN3 PVCCL2 EN4 ENL1 LDO2 VOUT4 or VIN 37 C30 VOUTL2 38 VOUTL2 C31 ENL2 VOUTL1 or VIN C33 PG2 C34 32 VREG PG3 PG4 11 PGL2 SYNC 34 CONFIDENTIAL EP WDI R5 PG3 10 PG4 1 PGL2 40 12 R6 PG2 31 13 PG1 RST WDI 41 GND 39 42 43 44 45 CP1 CP2 CP3 CP4 RST 33 R7 PG1 R8 VCC R9 34 R10 VIN S6BP401A_DS405-00024-0v01-E, February 19, 2015 v1.2 D a t a S h e e t ( P r e l i m i n a r y ) Table 14-1 Parts list Symbol Parts Part number Specifications Vendor C1 Ceramic Capacitor CGA5L1X7R1C106K160AC 10 µF TDK C2 Ceramic Capacitor CGA6P1X7R1C226M250AC 22 µF TDK C3 Ceramic Capacitor CGA6P1X7R1C226M250AC 22 µF TDK C7 Ceramic Capacitor CGA5L1X7R1C106K160AC 10 µF TDK C8 Ceramic Capacitor CGA6P1X7R1C226M250AC 22 µF TDK C9 Ceramic Capacitor CGA6P1X7R1C226M250AC 22 µF TDK C10 Ceramic Capacitor CGA6P1X7R1C226M250AC 22 µF TDK C15 Ceramic Capacitor CGA5L1X7R1C106K160AC 10 µF TDK C16 Ceramic Capacitor CGA6P1X7R1C226M250AC 22 µF TDK C17 Ceramic Capacitor CGA6P1X7R1C226M250AC 22 µF TDK C21 Ceramic Capacitor CGA5L1X7R1C106K160AC 10 µF TDK C22 Ceramic Capacitor CGA6P1X7R1C226M250AC 22 µF TDK C23 Ceramic Capacitor CGA6P1X7R1C226M250AC 22 µF TDK C27 Ceramic Capacitor CGA3E1X7R1C105M080AC 1 µF TDK C28 Ceramic Capacitor CGA3E1X7R1C105M080AC 1 µF TDK C30 Ceramic Capacitor CGA3E1X7R1C105M080AC 1 µF TDK C31 Ceramic Capacitor CGA5L1X7R1C106K160AC 10 µF TDK C33 Ceramic Capacitor CGA3E1X7R1C105M080AC 1 µF TDK C34 Ceramic Capacitor CGA3E1X7R1C105M080AC 1 µF TDK L1 Inductor CLF6045T-1R5N-D 1.5 µH TDK L2 Inductor CLF6045T-1R5N-D 1.5 µH TDK L3 Inductor CLF6045T-1R5N-D 1.5 µH TDK L4 Inductor CLF6045T-1R5N-D 1.5 µH TDK R5 Resistor RG1608P-473-B 47 kΩ SSM R6 Resistor RG1608P-473-B 47 kΩ SSM R7 Resistor RG1608P-473-B 47 kΩ SSM R8 Resistor RG1608P-473-B 47 kΩ SSM R9 Resistor RG1608P-473-B 47 kΩ SSM R10 Resistor RG1608P-473-B 47 kΩ SSM TDK SSM : TDK Corporation : SUSUMU CO., LTD. February 19, 2015, S6BP401A_DS405-00024-0v01-E CONFIDENTIAL 35 v1.2 D a t a S h e e t ( P r e l i m i n a r y ) 15. Ordering Information Table 15-1 Ordering information Part number Package Remarks 40-pin plastic QFN S6BP401A**EN1B000 (VND040) "**" in the table is the meaning of the Preset Code below. Table 15-2 Preset Code List Output Voltage Preset 36 CONFIDENTIAL Code DD1 DD2 DD3 DD4 LD1 LD2 M0 1.250 V 1.125 V 2.550 V 3.350 V 3.325 V 2.800 V M1 1.250 V 1.150 V 2.550 V 3.350 V 3.325 V 2.800 V B0 1.250 V 1.250 V 1.250 V 3.375 V 3.300 V 1.850 V C0 1.250 V 1.250 V 1.250 V 1.850 V 3.300 V 3.375 V J0 1.250 V 1.250 V 1.850 V 3.375 V 3.300 V 2.800 V S6BP401A_DS405-00024-0v01-E, February 19, 2015 v1.2 D a t a S h e e t ( P r e l i m i n a r y ) 16. Package Dimensions February 19, 2015, S6BP401A_DS405-00024-0v01-E CONFIDENTIAL 37 v1.2 D a t a S h e e t ( P r e l i m i n a r y ) 17. Major Changes Page Section Change Results Revision 0.1 - 38 CONFIDENTIAL - Initial release S6BP401A_DS405-00024-0v01-E, February 19, 2015 v1.2 D a t a S h e e t February 19, 2015, S6BP401A_DS405-00024-0v01-E CONFIDENTIAL ( P r e l i m i n a r y ) 39 v1.2 D a t a S h e e t ( P r e l i m i n a r y ) Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. Trademarks and Notice The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind arising out of the use of the information in this document. ® ® ® TM Copyright © 2015 Spansion All rights reserved. Spansion , the Spansion logo, MirrorBit , MirrorBit Eclipse , TM TM TM ORNAND , Easy DesignSim , Traveo and combinations thereof, are trademarks and registered trademarks of Spansion LLC in the United States and other countries. Other names used are for informational purposes only and may be trademarks of their respective owners. 40 CONFIDENTIAL S6BP401A_DS405-00024-0v01-E, February 19, 2015 v1.2