ROHM BD9151MUV

Single-chip Type with Built-in FET Switching Regulator Series
Output 1.5A or Less High Efficiency
Step-down Switching Regulator
with Built-in Power MOSFET
BD9151MUV
No.09027EAT11
●Description
ROHM’s high efficiency dual step-down switching regulator BD9151MUV is a power supply designed to produce a low
voltage including 1.8 volts or 1.2 volts from 2.8 volts to 5.0 volts power supply line. Reset circuits of input power supply
voltage and external Pch MOSFET gate controller are incorporated. Offers high efficiency with our original pulse skip control
technology and synchronous rectifier. Employs a current mode control system to provide faster transient response to
sudden change in load.
●Features
1) Offers fast transient response with current mode PWM control system.
TM
2) Offers highly efficiency for all load range with synchronous rectifier (Pch/Nch FET) and SLLM (Simple Light Load Mode)
3) Incorporates soft-start function.
4) Incorporates Thermal / ULVO protection functions.
5) Incorporates thermal protection and short-current protection circuit with timer latch function. .
6) Incorporates shutdown function Icc=0µA(Typ.)
7) Incorporates reset function
8) Incorporates Pch MOSFET gate controller
9) Employs small surface mount package : VQFN020V4040
●Applications
Power supply for LSI including DSP, Micro computer and ASIC
●Absolute maximum ratings (Ta=25℃)
Parameter
Symbol
AVCC
PVcc
VEN
VSW1
VSW2
Pd1
Pd2
Pd3
Pd4
Topr
Tstg
Tjmax
Vcc Voltage
EN Voltage
SW Voltage
Power Dissipation
Operating Temperature Range
Storage Temperature Range
Maximum Junction Temperature
*1
*2
*3
*4
*5
Unit
V
V
V
V
V
W
W
W
W
℃
℃
℃
Pd, ASO and Tj=150℃ should not be exceeded.
IC only
1-layer. mounted on a 74.2mm×74.2mm×1.6mm glass-epoxy board, occupied area by copper foil : 10.29mm2
4-layer. mounted on a 74.2mm×74.2mm×1.6mm glass-epoxy board, occupied area by copper foil : 10.29mm2 , 2-3 layers 5505 mm2
4-layer. mounted on a 74.2mm×74.2mm×1.6mm glass-epoxy board, occupied area by copper foil : 5505mm2, in each layers
●Operating conditions (Ta=-40～+85℃)
Parameter
Vcc Voltage
EN Voltage
SW Average Output Current
*6
Limit
-0.3～+7*1
-0.3～+7*1
-0.3～+7
-0.3～+7
-0.3～+7
0.34*2
0.70*3
2.21*4
3.56*5
-40～+85
-55～+150
+150
Symbol
AVCC、PVCC
VEN
ISW1
ISW2
Min.
2.8
0
-
Typ.
3.3
-
Max.
5.5
5.5
0.4*6
0.8*6
Unit
V
V
A
A
Pd and ASO should not be exceeded.
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1/16
2009.08 - Rev.A
Technical Note
BD9151MUV
●Electrical Characteristics
◎(Unless otherwise noted, Ta=25℃, AVCC=PVCC=3.3V, EN=AVCC)
Limit
Parameter
Symbol
MIN.
TYP.
Standby Current
ISTB
0
Bias Current
ICC
400
EN Low Voltage
VENL
GND
EN High Voltage
VENH
2
Vcc
EN Input Current
IEN
1
Oscillation Frequency
FOSC
0.8
1.0
RONP1
0.27
Pch FET ON Resistance
RONP2
0.18
0.27
RONN1
Nch FET ON Resistance
RONN2
0.18
ITH Sink Current 1
ITHSI1
10
20
ITH Source Current 1
ITHSO1
10
20
ITH Sink Current 2
ITHSI2
10
20
ITH Source Current 2
ITHSO2
10
20
FB Reference Voltage 1
FB1
1.773
1.800
FB Reference Voltage 2
FB2
1.182
1.200
UVLO Threshold Voltage
VUVLOL
2.4
2.5
UVLO Release Voltage
VUVLOH
2.45
2.6
Reset Threshold Voltage
PG1
2.74
2.87
Reset Release Voltage
PG2
2.84
2.97
Reset ON resistance
RONPG
140
Reset Delay
TPG
8
16
MONI Discharge Resistance
RMONI
110
PGATEB Sink Current
IPGATEB
1.5
4
Soft start time
TSS
0.25
0.5
Timer latch time
TLATCH
0.5
1.0
0.9
VSCP1
Output Short circuit
Threshold Voltage
VSCP2
0.6
MAX
10
800
0.8
10
1.2
0.46
0.30
0.46
0.30
1.827
1.218
2.6
2.8
3.00
3.10
240
32
190
6.5
1.0
2.0
1.26
0.84
Unit
µA
µA
V
V
µA
MHz
Ω
Ω
Ω
Ω
µA
µA
µA
µA
V
V
V
V
V
V
Ω
ms
Ω
uA
ms
ms
V
V
Conditions
EN=0V
In standby mode
In active mode
VEN=2V
AVCC = PVCC =3.3V
AVCC = PVCC =3.3V
AVCC = PVCC =3.3V
AVCC = PVCC =3.3V
VFB1=2.0V
VFB 1=1.6V
VFB 2=1.4V
VFB 2=1.0V
±1.5%
±1.5%
AVCC =3.3→0V
AVCC =0→3.3V
AVCC =3.3V→0V
AVCC =0V→3.3V
AVCC =3.3V
In SCP/TSD operation
FB1=1.8→0V
FB2=1.2→0V
●Top View
4.0±0.1
4.0±0.1
D9151
1.0Max.
Lot No.
0.08 S
C0.2 2.1±0.1
5
6
20
16
1.0
10
15
0.5
2.1±0.1
0.4±0.1
1
0.02 +0.03
-0.02
(0.22)
S
11
0.25 +0.05
-0.04
VQFN020V4040
(Unit :mm)
Fig.1 BD9151MUV TOP View
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2/16
2009.08 - Rev.A
Technical Note
BD9151MUV
●Block Diagram
VCC
VOUT3
PGATE
PGATEB
AVCC
MONI
VCC
UVLO/
Delay
AGND
PGOOD
Comp
RESET
VCC
FB1
VOUT1
PVCC1
Current
Comp
Current
R
Gm Amp
Q
VCC
Slope1
EN
SW1
Driver
Logic
ITH1
PGND1
SCP1
Delay
CLK1
VREF
OSC
SCP/
TSD
UVLO
CLK2
VCC
Delay
PVCC2
SCP2
VOUT2
VOUT1
+
Soft
Start
AGND
Sense/
Protect
S
Current
Current
Comp
FB2
R
Gm Amp
Q
S
Soft
Start/
Delay
VOUT2
SW2
+
Slope2
AGND
Sense/
Protect
Driver
CLK2
Logic
PGND2
ITH2
AGND
Fig.2 BD9151MUV Block Diagram
●Pin No. & function table
Pin
Pin
PIN Function
No.
name
1
PGND2 Ch2 Low side source pin
2
PGND2 Ch2 Low side source pin
Pin
No.
11
12
Pin
name
AGND
AVCC
PGATEB
3
PVCC2 Ch2 High side FET source pin
13
4
PVCC1 Ch1 High side FET source pin
14
5
PGND1 Ch1 Low side source pin
15
PIN Function
Ground
Power supply input pin
External Pch MOS Gate Drive pin
(Low Active)
PGATEB reverse logic output signal
PGATE
(High Active)
MONI 3.3V Output monitor pin
6
SW1
Ch1 Pch/Nch FET drain output pin
16
ITH2
Ch2 GmAmp output pin
/ Connected phase compensation capacitor
7
8
SW1
FB1
Ch1 Pch/Nch FET drain output pin
Ch1 output voltage detect pin
17
18
FB2
EN
Ch2 output voltage detect pin
Enable pin (High Active)
9
ITH1
Ch1 GmAmp output pin
/Connected phase compensation capacitor
19
SW2
Ch2 Pch/Nch FET drain output pin
20
SW2
Ch2 Pch/Nch FET drain output pin
10
RESET RESET Output pin
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3/16
2009.08 - Rev.A
Technical Note
BD9151MUV
●Characteristics data【BD9151MUV】
2.0
【VOUT1=1.8V】
1.5
1.0
【VOUT1=1.8V】
OUTPUT VOLTAGE:VOUT[V]
OUTPUT VOLTAGE:VOUT[V]
Ta=25℃
Io=0A
【VOUT2=1.2V】
0.5
1.5
【VOUT2=1.2V】
1.0
VCC=3.3V
Ta=25℃
Io=0A
0.5
0.0
1
2
3
4
INPUT VOLTAGE:VCC[V]
5
0
1
2
3
4
EN VOLTAGE:VEN[V]
Fig.3 VCC – VOUT1,VOUT2
1.80
VCC=3.3V
VCC=3.3V
Io=0AIo=0A
90 Vcc=3.3V
【VOUT1=1.8V】
80
【VOUT2=1.2V】
【VOUT2=1.2V
設定】
1.23
1.20
1.18
VCC=3.3V
Io=0A
-40
80
-20
0
20
40
60
TEMPERATURE:Ta[℃]
50
Vcc=5V
【VOUT2=1.2V】
Ta=25℃
10
1
Ta=25℃
*VOUT2=1mA loaded
0
1
10
100
OUTPUT CURRENT:IOUT[mA]
1000
Fig.8 VOUT1 Efficiency
1.2
1.0
VCC=3.3V
10
100
OUTPUT CURRENT:IOUT[mA]
1.1
1
0.9
Ta=25℃
0.8
0.8
1000
-40
Fig.9 VOUT2 Efficiency
-20
0
20
40
TEMPERATURE:Ta[℃]
60
2.8
80
1.6
200
NMOS
125
100
75
1.4
1.2
1.0
0.8
0.6
50
0.4
25
0.2
0
-40
-20
600
0
20
40
60
80
TEMPERATURE:Ta[℃]
CIRCUIT CURRENT:I CC [μA]
PMOS
150
5.3
1.8
225
175
3.8
4.3
4.8
INPUT VOLTAGE:VCC[V]
Fig.11 VCC-Fosc
2.0
VCC=3.3V
250
3.3
Fig.10 Ta- Fosc
EN VOLTAGE:VEN[V]
ON RESISTANCE:RON[mΩ]
30
*VOUT1=1mA loaded
0
275
Vcc=5V
【VOUT1=1.8V】
40
10
FREQUENCY:FOSC[MHz]
FREQUENCY:FOSC[MHz]
EFFICIENCY:η[%]
60
20
50
20
1.2
70
30
60
80
80
40
70
Fig. 7 Ta-VOUT1
Vcc=3.3V
【VOUT2=1.2V】
90
4
100
Fig. 6 Ta-VOUT1
100
1
2
3
OUTPUT CURRENT:IOUT[A]
Fig.5 IOUT - VOUT
1.15
1.75
0
20
40
60
TEMPERATURE:Ta[℃]
VCC=3.3V
Ta=25℃
0
EFFICIENCY:η[%]
1.83
OUTPUT VOLTAGE:VOUT[V]
OUTPUT VOLTAGE:VOUT[V]
【VOUT1=1.8V】
-20
0.5
5
1.25
-40
【VOUT2=1.2V】
1.0
Fig.4 VEN - VOUT
1.85
1.78
【VOUT1=1.8V】
1.5
0.0
0.0
0
300
OUTPUT VOLTAGE:VOUT[V]
2.0
2.0
100
Fig.12 Ta – RONN, RONP
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VCC=3.3V
0.0
500
400
300
200
VCC=3.3V
100
0
-40
-20
0
20
40
60
TEMPERATURE:Ta[℃]
Fig.13 Ta－EN1,EN2
4/16
80
-4 0
-2 0
0
20
40
60
80
T EM PER AT U R E:T a[℃ ]
Fig.14 Ta－Icc
2009.08 - Rev.A
Technical Note
BD9151MUV
VCC=3.3V,Ta=25℃
VOUT1
VCC=3.3V,Ta=25℃
VOUT3
VOUT1
VCC=3.3V,Ta=25℃
VOUT1
VOUT3
VOUT2
VOUT2
Fig.15 Soft start waveform
(Io1=0mA,Io2=0mA,Io3=0mA)
RESET
PGATE
VOUT2
Fig.16 Soft start waveform
(Io1=400mA,Io2=800mA,Io3=600mA)
SW1
Fig.17 Soft start waveform
(Io1=0mA,Io2=0mA,PGATE)
SW1
VOUT1
VOUT2
VCC=3.3V,Ta=25℃,VOUT1=1.8V
VOUT1
VOUT1
Fig.18 Soft start waveform
(Io1=0mA,Io2=0mA,RESET)
VCC=3.3V,Ta=25℃,VOUT1=1.8V
Fig.19 SW1 waveform
(Io=0mA)
Fig.20 SW1 waveform
(Io=400mA)
VCC=3.3V,Ta=25℃,VOUT=1.8V
SW2
SW2
VCC=3.3V,Ta=25℃,VOUT2=1.2V
VOUT2
VOUT1
VCC=3.3V,Ta=25℃,VOUT2=1.2V
IOUT1
VOUT2
Fig.21 SW2 waveform
(Io=0mA)
Fig.22 SW2 waveform
(Io=800mA)
VCC=5V,Ta=25℃,VOUT=1.8V
VCC=5V,Ta=25℃,VOUT2=1.2V
VCC=5V,Ta=25℃,VOUT2=1.2V
VOUT2
VOUT1
Fig.23 VOUT1 transient response
(Io=200mA→400mA / 10usec)
VOUT2
IOUT2
IOUT2
IOUT1
Fig.24 VOUT1 transient response
(Io=400mA→200mA/ 10usec)
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Fig.25 VOUT2 transient response
(Io=400mA→800mA/ 10usec)
5/16
Fig.26 VOUT2 transient response
(Io=800mA→400mA/ 10usec)
2009.08 - Rev.A
Technical Note
BD9151MUV
●Operation
BD9151MUV is a synchronous rectifying step-down switching regulator that achieves faster transient response by employing
current mode PWM control system. It utilizes switching operation in PWM (Pulse Width Modulation) mode for heavier load,
TM
while it utilizes SLLM (Simple Light Load Mode) operation for lighter load to improve efficiency.
○Synchronous rectifier
It does not require the power to be dissipated by a rectifier externally connected to a conventional DC/DC converter IC, and
its P.N junction shoot-through protection circuit limits the shoot-through current during operation, by which the power
dissipation of the set is reduced.
○Current mode PWM control
Synthesizes a PWM control signal with a inductor current feedback loop added to the voltage feedback.
・PWM (Pulse Width Modulation) control
The oscillation frequency for PWM is 1 MHz. SET signal form OSC turns ON a high side MOS FET (while a low side
MOS FET is turned OFF), and an inductor current IL increases. The current comparator (Current Comp) receives two
signals, a current feedback control signal (SENSE: Voltage converted from IL) and a voltage feedback control signal (FB),
and issues a RESET signal if both input signals are identical to each other, and turns OFF the high side MOS FET (while a
low side MOS FET is turned ON) for the rest of the fixed period. The PWM control repeat this operation.
TM
・SLLM (Simple Light Load Mode) control
When the control mode is shifted from PWM for heavier load to the one for lighter load or vise versa, the switching pulse is
designed to turn OFF with the device held operated in normal PWM control loop, which allows linear operation without
voltage drop or deterioration in transient response during the mode switching from light load to heavy load or vise versa.
Although the PWM control loop continues to operate with a SET signal from OSC and a RESET signal from Current Comp,
it is so designed that the RESET signal is held issued if shifted to the light load mode, with which the switching is tuned
OFF and the switching pulses are thinned out under control. Activating the switching intermittently reduces the switching
dissipation and improves the efficiency.
SENSE
Current
Comp
RESET
VOUT
Level
Shift
R Q
FB
SET
Driver
Logic
S
Gm Amp.
ITH
IL
VOUT
SW
Load
OSC
Fig.27 Diagram of current mode PWM control
PVCC
Current
Comp
SENSE
PVCC
SENSE
Current
Comp
FB
FB
SET
GND
SET
GND
RESET
GND
RESET
GND
SW
GND
SW
IL
GND
IL(AVE)
IL
0A
VOUT
VOUT(AVE)
VOUT
VOUT(AVE)
Not switching
Fig.29 SLLM
Fig.28 PWM switching timing chart
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TM
switching timing chart
2009.08 - Rev.A
Technical Note
BD9151MUV
●Description of operations
・Soft start function
EN terminal shifted to “High” activates a soft-starter to gradually establish the output voltage with the current limited during
startup, by which it is possible to prevent an overshoot of output voltage and an inrush current.
・Shutdown function
With EN terminal shifted to “Low”, the device turns to Standby Mode, and all the function blocks including reference
voltage circuit, internal oscillator and drivers are turned to OFF. Circuit current during standby is 0µF (Typ.).
・UVLO function
Detects whether the input voltage sufficient to secure the output voltage of BU9151MUV is supplied. And the hysteresis width of
100mV (Typ.) is provided to prevent output chattering. Each the outputs have UVLO. It is possible to set output sequence easy.
・Reset function
When AVCC input voltage is over .2.97V (typ), after 16msec (typ.) delay, outputs RESET. The hysteresis is 100mV (Typ).
・Pch MOSFET gate controller function
PGATEB pin has function to make FET active with steady current. With connecting Pch MOSFET gate, soft start turned to be ON.
・Discharge function
MONI pin is open drain pin of Nch MOS. After 4msec (typ) delay from the time UVLO release, it turns to be OFF.
By Low, UVLO detection of EN pin, Nch MOS becomes active and discharge the connection.
・External synchronous signal output function
PGATE pin outputs High active after 4msec (Typ.) delay from the UVLO release.
・Start up sequence function
BU9151MUV outputs output voltage 2ch (1.2V) after the UVLO release, and after 2msec(typ.) from the UVLO release,
it outputs 1ch(1.8V), and the last, after 4msec from the UVLO release, PGATEB becomes active, and external
Pch MOSFET will be ON, and outputs 3ch(VCC equivalent). During the OFF time, 3ch output is discharged by MONI pin,
then 1ch output and 2ch output are naturally discharged.
PG2 (2.97V)
PG1 (2.87V)
V UVLOH (2.6V)
V UVLOL(2.5V)
VCC
EN
VOUT1(1.8V)
TSS
TSS(0.5m s)
TSS
VOUT2(1.2V)
TSS
TSS(0.5ms)
delay1 (2m s)
PGATE
TSS
delay1 (2ms)
delay2 (4ms)
delay1 (2ms)
delay2 (4m s)
delay2 (4ms)
PGATEB
VOUT3(3.3V)
TSS(1m s)＊
TSS(1m s)＊
discharge ON
discharge ON
RESET
TPG (16ms)
TPG (16ms)
*Starting time of VOUT3
TSS(1m s)＊
discharge ON
TPG (16m s)
TSS=1ms (when BD9151MUV is used) It depends on gate capacity when using Pch MOSFET
Fig.30 Soft start, Shut down, UVLO timing chart
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7/16
2009.08 - Rev.A
Technical Note
BD9151MUV
・Short-current protection circuit with time latch function
Turns OFF the output to protect the IC from breakdown when the incorporated current limiter is activated continuously for
the fixed time(TLATCH) or more. The output thus held tuned OFF may be recovered by restarting EN or by re-unlocking
UVLO.
EN
SCP
VOUT1
Output voltage OFF latch
Threshold voltage
VOUT2
IL Limit
IL1
IL2
Standby mode
t2=TLATCH
t1<TLATCH
Active mode
Standby mode
Timer latch
EN
Active mode
EN
Fig.31 Timer latch short-current protection timing chart
●Switching regulator efficiency
Efficiency ŋ may be expressed by the equation shown below:
η=
VOUT×IOUT
Vin×Iin
×100[%]=
POUT
Pin
×100[%]=
POUT
POUT+PDα
×100[%]
Efficiency may be improved by reducing the switching regulator power dissipation factors PDα as follows:
Dissipation factors:
2
1) ON resistance dissipation of inductor and FET：PD(I R)
2) Gate charge/discharge dissipation：PD(Gate)
3) Switching dissipation：PD(SW)
4) ESR dissipation of capacitor：PD(ESR)
5) Operating current dissipation of IC：PD(IC)
2
2
1)PD(I R)=IOUT ×(RCOIL+RON) (RCOIL[Ω]：DC resistance of inductor, RON[Ω]：ON resistance of FET, IOUT[A]：Output
current.)
2)PD(Gate)=Cgs×f×V (Cgs[F]：Gate capacitance of FET, f[H]：Switching frequency, V[V]：Gate driving voltage of FET)
3)PD(SW)=
2
Vin ×CRSS×IOUT×f
IDRIVE
(CRSS[F]：Reverse transfer capacitance of FET, IDRIVE[A]：Peak current of gate.)
2
4)PD(ESR)=IRMS ×ESR (IRMS[A]：Ripple current of capacitor, ESR[Ω]：Equivalent series resistance.)
5)PD(IC)=Vin×ICC (ICC[A]：Circuit current.)
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2009.08 - Rev.A
Technical Note
BD9151MUV
●Consideration on permissible dissipation and heat generation
As BU9151MUV functions with high efficiency without significant heat generation in most applications, no special consideration
is needed on permissible dissipation or heat generation. In case of extreme conditions, however, including lower input voltage,
higher output voltage, heavier load, and/or higher temperature, the permissible dissipation and/or heat generation must be
carefully considered.
For dissipation, only conduction losses due to DC resistance of inductor and ON resistance of FET are considered. Because
the conduction losses are considered to play the leading role among other dissipation mentioned above including gate
charge/discharge dissipation and switching dissipation.
P=IOUT2×RON
RON=D×RONH+(1-D)RONL
22
4 層基板
(表層放熱銅箔
①①4 layers
(copper
foil area : 5505mm
5505mm ))
(各層に銅箔積層
(copper
foil in each) layers)
θj-a=35.1
℃/W
θj-a=35.1
℃/W
2
②②4 layers
(copper
foil area : 10.29mm
10.29mm2))
4 層基板
(表層放熱銅箔
2
2
(copper
foil in 2-3 layers:
5505mm
)
5505mm
)
(2,3 層に銅箔積層
θj-a=103.3
℃/W
θj-a=103.3
℃/W
22
③③1 layer
(copper
foil area : 10.29mm
1 層基板
(表層放熱銅箔
10.29mm))
θj-a=178.6
℃/W
θj-a=178.6
℃/W
④④ICIConly
単体時
θj-a=367.6
℃/W
θj-a=367.6
℃/W
4.0
①3.56W
Power Dissipation :Pd [W]
3.0
D：ON Duty(=VOUT/VCC)
RONH：ON resistance of High side MOS FET
RONL：ON resistance of Low side MOS FET
IOUT：Output current
②2.21W
2.0
1.0
③0.70W
④0.34W
0
0
25
50
75
100 105
125
150
Ambient Temperature :Ta [℃]
Fig.32 Heat radiation characteristics (VQFN020V4040)
If VCC=3.3V, VOUT1=1.8V, VOUT2=1.2V, RONH1=0.27Ω, RONL1=0.18Ω, RONH2=0.27Ω, RONL2=0.18Ω
IOUT1=0.4A, IOUT2=0.8A, for example,
D1=VOUT1/VCC=1.8/3.3=0.55
D2=VOUT2/VCC=1.2/3.3=0.36
RON1=0.55×0.27+(1-0.55)×0.18
=0.1485+0.081
=0.2295[Ω]
RON2=0.36×0.27+(1-0.36)×0.18
=0.0972+0.1152
=0.2124[Ω]
P=0.42×0.2295+0.82×0.2124=0.173[W]
As RONH is greater than RONL in BU9151MUV, the dissipation increases as the ON duty becomes greater.
With the consideration on the dissipation as above, thermal design must be carried out with sufficient margin allowed.
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9/16
2009.08 - Rev.A
Technical Note
BD9151MUV
●Selection of components externally connected
1. Selection of inductor (L)
IL
The inductance significantly depends on output ripple current.
As seen in the equation (1), the ripple current decreases as the i
nductor and/or switching frequency increases.
ΔIL
VCC
ΔIL=
IL
(VCC-VOUT)×VOUT
L×VCC×f
[A]・・・(1)
Appropriate ripple current at output should be 20% more or less of
the maximum output current.
VOUT
L
ΔIL=0.3×IOUTmax. [A]・・・(2)
Co
L=
(VCC-VOUT)×VOUT
ΔIL×VCC×f
[H]・・・(3)
(ΔIL: Output ripple current, and f: Switching frequency)
Fig.33 Output ripple current
※Current exceeding the current rating of the inductor results in magnetic saturation of the inductor, which decreases efficiency.
The inductor must be selected allowing sufficient margin with which the peak current may not exceed its current rating.
If VCC=3.3V, VOUT=1.8V, f=1.0MHz, ΔIL=0.3×0.8A=0.24A, for example,(BD9151MUV)
L=
(3.3-1.8)×1.8
0.24×3.3×1.0M
=2.02μ → 2.2[μH]
※Select the inductor of low resistance component (such as DCR and ACR) to minimize dissipation in the inductor for
better efficiency.
2. Selection of output capacitor (CO)
Output capacitor should be selected with the consideration on the stability region
and the equivalent series resistance required to smooth ripple voltage.
VCC
Output ripple voltage is determined by the equation (4)：
VOUT
L
ESR
ΔVOUT=ΔIL×ESR [V]・・・(4)
(ΔIL: Output ripple current, ESR: Equivalent series resistance of output capacitor)
Co
Fig.34 Output capacitor
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※Rating of the capacitor should be determined allowing sufficient margin against
output voltage. A 22μF to 100μF ceramic capacitor is recommended.
Less ESR allows reduction in output ripple voltage.
10/16
2009.08 - Rev.A
Technical Note
BD9151MUV
3. Selection of input capacitor (Cin)
VCC
Input capacitor to select must be a low ESR capacitor of the capacitance
sufficient to cope with high ripple current to prevent high transient voltage.
ripple current IRMS is given by the equation (5):
Cin
VOUT
L
IRMS=IOUT×
Co
√VOUT(VCC-VOUT)
VCC
The
[A]・・・(5)
< Worst case > IRMS(max.)
When Vcc=2×VOUT, IRMS=
IOUT
2
If VCC=5.0V, VOUT=1.8V, and IOUTmax.=0.4A, (BD9151MUV)
Fig.35 Input capacitor
IRMS=2×
√1.8(5.0-1.8)
5.0
=0.48[ARMS]
A low ESR 22µF/10V ceramic capacitor is recommended to reduce ESR dissipation of input capacitor for better efficiency.
4. Determination of RITH, CITH that works as a phase compensator
As the Current Mode Control is designed to limit a inductor current, a pole (phase lag) appears in the low frequency area
due to a CR filter consisting of a output capacitor and a load resistance, while a zero (phase lead) appears in the high
frequency area due to the output capacitor and its ESR. So, adding a zero to the power amplifier output with C easily
compensates the phases and R as described below to cancel a pole at the power amplifier.
fp(Min.)
A
0
fz(ESR)
IOUTMin.
Phase
[deg]
1
2π×RO×CO
1
fz(ESR)=
2π×ESR×CO
fp=
fp(Max.)
Gain
[dB]
IOUTMax.
Pole at power amplifier
When the output current decreases, the load resistance Ro
increases and the pole frequency lowers.
0
-90
fp(Min.)=
1
[Hz]←with lighter load
2π×ROMax.×CO
fp(Max.)=
1
2π×ROMin.×CO
Fig.36 Open loop gain characteristics
A
[Hz] ←with heavier load
fz(Amp.)
Gain
[dB]
Zero at power amplifier
Increasing capacitance of the output capacitor lowers the pole
frequency while the zero frequency does not change.
(This is because when the capacitance is doubled, the capacitor
ESR reduces to half.)
0
0
Phase
[deg]
-90
fz(Amp.)=
1
2π×RITH×CITH
Fig.37 Error amp phase compensation characteristics
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11/16
2009.08 - Rev.A
Technical Note
BD9151MUV
RITH1
R1
CITH1
VOUT1
L1
COUT1
RESET
ITH1
FB1
SW1
SW1
AGND
PGND1
AVCC
PVCC1
PGATEB
PVCC2
U1
CIN1
CIN2
PGATE
PGND2
COUT2
MONI
PGND2
VOUT2
COUT3
ITH2
FB2
EN
SW2
SW2
RITH2
L2
CITH2
VOUT3
Fig.38 External parts sketch
Stable feedback loop may be achieved by canceling the pole fp (Min.) produced by the output capacitor and the load
resistance with CR zero correction by the error amplifier.
fz(Amp.)= fp(Min.)
1
2π×RITH×CITH
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=
1
2π×ROMax.×CO
12/16
2009.08 - Rev.A
Technical Note
BD9151MUV
●BD9151MUV
Caution of Board layout
RITH1
R1
CITH1
L1
RESET ITH1
FB1
AGND
PGND1
AVCC
PVCC1
PGATEB
PVCC2
PGATE
PGND2
MONI
PGND2
ITH2
FB2
COUT1
SW1 SW1
U1
COUT3
VOUT1
EN
SW2
RITH2
CIN1
CIN2
COUT2
VOUT2
SW2
L2
CITH2
VOUT3
Fig.39 Example of board layout
①Lay out the input ceramic capacitor CIN closer to the pins PVCC and PGND, and the output capacitor Co closer to
the pin PGND.
②Lay out CITH and RITH between the pins ITH and GND as neat as possible with least necessary wiring.
※VQFN020V4040 (BD9151MUV) has thermal PAD on the reverse of the package.
The package thermal performance may be enhanced by bonding the PAD to GND plane which take a large area of PCB.
●Recommended parts list, using the application above
Symbol
Parts name
Value
L1,2
Inductor
2.2µH
CIN1,CIN2
Ceramic capacitor
22µF
Cout1,Cout2
Ceramic capacitor
CITH1
Ceramic capacitor
RITH1
Resistor
CITH2
RITH2
Company
TDK
TAIYO YUDEN
Parts number
LTF5022-2R2N3R2
NR3012T2R2M
Murata
GRM32EB11A226KE20
22µF
Murata
GRM31CB30J226KE18
330pF
Murata
GRM18 Series
22kΩ
Rohm
MCR03 Series
Ceramic capacitor
220pF
Murata
GRM18 Series
Resistor
15kΩ
Rohm
MCR03 Series
U1
Pch FET
-
Rohm
RT1A040ZP
Cout3
Ceramic capacitor
22µF
Murata
GRM31CB30J226KE18
R1
Resistor
10kΩ
Rohm
MCR03 Series
※The parts list presented above is an example of recommended parts. Although the parts are sound, actual circuit
characteristics should be checked on your application carefully before use. Be sure to allow sufficient margins to
accommodate variations between external devices and BU9151MUV when employing the depicted circuit with other
circuit constants modified. Both static and transient characteristics should be considered in establishing these margins.
When switching noise is substantial and may impact the system, a low pass filter should be inserted between the VCC and
PVCC pins, and a schottky barrier diode or snubber established between the SW and PGND pins.
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13/16
2009.08 - Rev.A
Technical Note
BD9151MUV
●I/O Equivalent circuits
・EN pin
・SW1,SW2
PVCC
PVCC
PVCC
EN
SW1,SW2
・FB1,FB2 pin
・ITH1,ITH2 pin
AVCC
FB1,FB2
ITH1,ITH2
・PGATEB pin
・RESET,MONI pin
AVCC
AVCC
RESET,MONI
PGATEB
・PGATE pin
AVCC
PGATE
Fig.40 I/O Equivalent circuits
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14/16
2009.08 - Rev.A
Technical Note
BD9151MUV
●Notes for use
1. Absolute Maximum Ratings
While utmost care is taken to quality control of this product, any application that may exceed some of the absolute
maximum ratings including the voltage applied and the operating temperature range may result in breakage. If broken,
short-mode or open-mode may not be identified. So if it is expected to encounter with special mode that may exceed the
absolute maximum ratings, it is requested to take necessary safety measures physically including insertion of fuses.
2. Electrical potential at GND
GND must be designed to have the lowest electrical potential In any operating conditions.
3. Short-circuiting between terminals, and mis-mounting
When mounting to pc board, care must be taken to avoid mistake in its orientation and alignment. Failure to do so may
result in IC breakdown. Short-circuiting due to foreign matters entered between output terminals, or between output and
power supply or GND may also cause breakdown.
4. Thermal shutdown protection circuit
Thermal shutdown protection circuit is the circuit designed to isolate the IC from thermal runaway, and not intended to
protect and guarantee the IC. So, the IC the thermal shutdown protection circuit of which is once activated should not be
used thereafter for any operation originally intended.
5. Inspection with the IC set to a pc board
If a capacitor must be connected to the pin of lower impedance during inspection with the IC set to a pc board, the
capacitor must be discharged after each process to avoid stress to the IC. For electrostatic protection, provide proper
grounding to assembling processes with special care taken in handling and storage. When connecting to jigs in the
inspection process, be sure to turn OFF the power supply before it is connected and removed.
6. Input to IC terminals
+
This is a monolithic IC with P isolation between P-substrate and each element as illustrated below. This P-layer and the
N-layer of each element form a P-N junction, and various parasitic element are formed.
If a resistor is joined to a transistor terminal as shown in Fig 41.
○P-N junction works as a parasitic diode if the following relationship is satisfied; GND>Terminal A (at resistor side),
or GND>Terminal B (at transistor side); and
○if GND>Terminal B (at NPN transistor side),
a parasitic NPN transistor is activated by N-layer of other element adjacent to the above-mentioned parasitic diode.
The structure of the IC inevitably forms parasitic elements, the activation of which may cause interference among circuits,
and/or malfunctions contributing to breakdown. It is therefore requested to take care not to use the device in such
manner that the voltage lower than GND (at P-substrate) may be applied to the input terminal, which may result in
activation of parasitic elements.
Resistor
Transistor (NPN)
ESR
Pin A
C
Pin B
B
E
Pin A
N
P
+
N
P
P
+
N
Parasitic
element
N
P+
P substrate
Parasitic element
GND
B
N
P
P
C
+
N
E
Parasitic
element
P substrate
Parasitic element
GND
GND
GND
Other adjacent elements
Fig.41 Simplified structure of monorisic IC
7. Ground wiring pattern
If small-signal GND and large-current GND are provided, It will be recommended to separate the large-current GND
pattern from the small-signal GND pattern and establish a single ground at the reference point of the set PCB so that
resistance to the wiring pattern and voltage fluctuations due to a large current will cause no fluctuations in voltages of the
small-signal GND. Pay attention not to cause fluctuations in the GND wiring pattern of external parts as well.
8 . Selection of inductor
It is recommended to use an inductor with a series resistance element (DCR) 0.1Ω or less. Especially, in case output
voltage is set 1.6V or more, note that use of a high DCR inductor will cause an inductor loss, resulting in decreased output
voltage. Should this condition continue for a specified period (soft start time + timer latch time), output short circuit
protection will be activated and output will be latched OFF. When using an inductor over 0.1Ω, be careful to ensure
adequate margins for variation between external devices and BU9151MUV, including transient as well as static
characteristics. Furthermore, in any case, it is recommended to start up the output with EN after supply voltage is within
operation range.
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15/16
2009.08 - Rev.A
Technical Note
BD9151MUV
●Ordering part number
B
D
9
Part No.
1
5
1
M
Part No.
U
V
-
E
2
Packaging and forming specification
Package
MUV: VQFN20V4040
E2: Embossed tape and reel
(VQFN20V4040)
VQFN020V4040
<Tape and Reel information>
4.0±0.1
4.0±0.1
2.1±0.1
1.0
0.4±0.1
1
6
16
0.5
Direction
of feed
E2
The direction is the 1pin of product is at the upper left when you hold
( reel on the left hand and you pull out the tape on the right hand
)
5
20
10
15
2500pcs
(0.22)
S
C0.2
Embossed carrier tape
Quantity
11
2.1±0.1
0.08
S
+0.03
0.02 –0.02
1.0MAX
1PIN MARK
Tape
+0.05
0.25 –0.04
1pin
(Unit : mm)
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Reel
16/16
Direction of feed
∗ Order quantity needs to be multiple of the minimum quantity.
2009.08 - Rev.A
Notice
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the
consent of ROHM Co.,Ltd.
The content specified herein is subject to change for improvement without notice.
The content specified herein is for the purpose of introducing ROHM's products (hereinafter
"Products"). If you wish to use any such Product, please be sure to refer to the specifications,
which can be obtained from ROHM upon request.
Examples of application circuits, circuit constants and any other information contained herein
illustrate the standard usage and operations of the Products. The peripheral conditions must
be taken into account when designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specified in this document.
However, should you incur any damage arising from any inaccuracy or misprint of such
information, ROHM shall bear no responsibility for such damage.
The technical information specified herein is intended only to show the typical functions of and
examples of application circuits for the Products. ROHM does not grant you, explicitly or
implicitly, any license to use or exercise intellectual property or other rights held by ROHM and
other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the
use of such technical information.
The Products specified in this document are intended to be used with general-use electronic
equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices).
The Products specified in this document are not designed to be radiation tolerant.
While ROHM always makes efforts to enhance the quality and reliability of its Products, a
Product may fail or malfunction for a variety of reasons.
Please be sure to implement in your equipment using the Products safety measures to guard
against the possibility of physical injury, fire or any other damage caused in the event of the
failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM
shall bear no responsibility whatsoever for your use of any Product outside of the prescribed
scope or not in accordance with the instruction manual.
The Products are not designed or manufactured to be used with any equipment, device or
system which requires an extremely high level of reliability the failure or malfunction of which
may result in a direct threat to human life or create a risk of human injury (such as a medical
instrument, transportation equipment, aerospace machinery, nuclear-reactor controller,
fuel-controller or other safety device). ROHM shall bear no responsibility in any way for use of
any of the Products for the above special purposes. If a Product is intended to be used for any
such special purpose, please contact a ROHM sales representative before purchasing.
If you intend to export or ship overseas any Product or technology specified herein that may
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R0039A