ACE24C128B/256B/512B Two-wire Serial EEPROM Description The ACE24C128B/256B/512B provides 131,072/262,144/524,288 bits of serial electrically erasable and programmable read-only memory (EEPROM), organized as 16,384/32,768/65,536 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The ACE24C128B/256B/512B is available in space-saving 8-lead PDIP, 8-lead SOP, and 8-lead TSSOP packages and is accessed via a two-wire serial interface. In addition, the ACE24C128B/256B/512B is available in 1.7V (1.7V to 5.5V) version. Features Wide Voltage Operation - VCC = 1.7V to 5.5V Operating Ambient Temperature: -40℃ to +85℃ Internally Organized: - ACE24C128B, 16,384 * 8 (128K bits) - ACE24C256B, 32,768 * 8 (256K bits) - ACE24C512B, 65,536 * 8 (512K bits) Two-wire Serial Interface Schmitt Trigger, Filtered Inputs for Noise Suppression Bidirectional Data Transfer Protocol 1 MHz (5V), 400 KHz (1.7V, 2.5V, 2.7V) Compatibility Write Protect Pin for Hardware Data Protection 64-byte Page (128K, 256K), 128-byte (512K) Write Modes Partial Page Writes Allowed Self-timed Write Cycle (5 ms max) High-reliability - Endurance: 1 Million Write Cycles - Data Retention: 100 Years Absolute Maximum Ratings DC Supply Voltage -0.3 to 6.5V Input / Output Voltage GND-0.3V to VCC+0.3V Operating Ambient Temperature -40℃ to 85℃ Storage Temperature -65℃ to 150℃ *Notice: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification are not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. VER 1.4 1 ACE24C128B/256B/512B Two-wire Serial EEPROM Packaging Type DIP-8 SOP-8 TSSOP-8 Pin Configurations Pin Name Type Functions A0-A2 I Address Inputs SDA I/O & Open-drain Serial Data SCL I Serial Clock Input WP I Write Protect GND P Ground VCC P Power Supply Ordering information ACE24C128B/256B/512B XX + X H Halogen-free U : Tube T : Tape and Reel Pb - free DP : DIP-8 FM : SOP-8 TM : TSSOP-8 VER 1.4 2 ACE24C128B/256B/512B Two-wire Serial EEPROM Block Diagram VER 1.4 3 ACE24C128B/256B/512B Two-wire Serial EEPROM Pin Descriptions Device/Page Addresses (A2, A1 and A0): The A2, A1 and A0 pins are device address inputs that are hard wire for the ACE24C128B/256B/512B. Eight 128K/256K/512K devices may be addressed on a single bus system (device addressing is discussed in detail under the Device Addressing section). Serial Data (SDA): The SDA pin is bi-directional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open- collector devices. Serial Clock (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device. Write Protect (WP): The ACE24C128B/256B/512B has a Write Protect pin that provides hardware data protection. The Write Protect pin allows normal read/write operations when connected to ground (GND). When the Write Proection pin is connected to Vcc, the write protection feature is enabled and operates as shown in the following Table 2. Write Protect Description WP Pin Status At VCC At GND Part of the Array Protected ACE24C128B ACE24C256B ACE24C512B Full (128K) Array Full (256K) Array Full (512K) Array Normal Read / Write Operations Table 2 Memory Organization ACE24C128B, 128K SERIAL EEPROM: Internally organized with 256 pages of 64 bytes each, the 128K requires an 14-bit data word address for random word addressing. ACE24C256B, 256K SERIAL EEPROM: Internally organized with 512 pages of 64 bytes each, the 256K requires an 15-bit data word address for random word addressing. ACE24C512B, 512K SERIAL EEPROM: Internally organized with 512 pages of 128 bytes each, the 512K requires an 16-bit data word address for random word addressing. VER 1.4 4 ACE24C128B/256B/512B Two-wire Serial EEPROM Device Operation Clock and Data Transitions: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (see to Figure 1 on page 4). Data changes during SCL high periods will indicate a start or stop condition as defined below. Start Condition: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (see to Figure 2 on page 4). Stop Condition: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode (see Figure 2 on page 4). Acknowledge: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a "0" to acknowledge that it has received each word. This happens during the ninth clock cycle. Standby Mode: The ACE24C128B/256B/512B features a low-power standby mode which is enabled: (a) upon power-up and (b) after the receipt of the STOP bit and the completion of any internal operations Memory Reset: After an interruption in protocol, power loss or system reset, any two-wire part can be reset by following these steps: 1. Clock up to 9 cycles. 2. Look for SDA high in each cycle while SCL is high. 3. Create a start condition. Figure 1: Data Validity VER 1.4 5 ACE24C128B/256B/512B Two-wire Serial EEPROM Figure 2: Start and Stop Definition Figure 3: Output Acknowledge Device Addressing The 128K/256K/512K EEPROM devices all require an 8-bit device address word following a start condition to enable the chip for a read or write operation (see to Figure 4 on page 7). The device address word consists of a mandatory "1", "0" sequence for the first four most significant bits as shown. This is common to all the Serial EEPROM devices. The 128K/256K/512K EEPROM uses A2, A1 and A0 device address bits to allow as much as eight devices on the same bus. These 3 bits must be compared to their corresonding hardwired input pins. The A2, A1 and A0 pins use an internal proprietary circuit that biases them to a logic low condition if the pins are allowed to float. VER 1.4 6 ACE24C128B/256B/512B Two-wire Serial EEPROM The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low. Upon a compare of the device address, the EEPROM will output a "0". If a compare is not made, the chip will return to a standby state. DATA SECURITY: The ACE24C128B/256B/512B has a hardware data protection scheme that allows the user to write protect the entire memory when the WP pin is at VCC. Write Operations Byte Write: A write operation requires an 8-bit data word address following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a "0" and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a "0" and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. At this time the EEPROM enters an internally timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete (see Figure 5 on page 7). Page Write: The 128K/256K EEPROM is capable of an 64-byte page writes, and 512K device is capable of an 128byte page writes. A page write is initiated the same as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to 63 (128K/256K) or 127 (512K) more data words. The EEPROM will respond with a “0” after each data word received. The microcontroller must terminate the page write aequence with a stop condition (see Figure 6 on page 7). The data word address lower six (128K/256K) or seven (512K) bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than 64 (128K/256K) or 128 (512K) data words are transmitted to the EEPROM, the data word address will “roll over” and previous data will be overwritten. Acknowledge Polling: Once the internally timed write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM respond with a "0", allowing the read or write sequence to continue. Read Operations Read operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to "1". There are three read operations: current address read, random address read and sequential read. VER 1.4 7 ACE24C128B/256B/512B Two-wire Serial EEPROM Current Address Read: The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address "roll over" during read is from the last byte of the last memory page to the first byte of the first page. The address "roll over" during write is from the last byte of the current page to the first byte of the same page. Once the device address with the read/write select bit set to "1" is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an input "0" but does generate a following stop condition (see Figure 7 on page 8). Read Operations Random Read: A random read requires a "dummy" byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another start condition. The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a "0" but does generate a following stop condition (see Figure 8 on page 8). Sequential Read: Sequential reads are initiated by either a current address read or a random address read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will "roll over" and the sequential read will continue. The sequential read operation is terminated when the microcontroller does not respond with a "0" but does generate a following stop condition (see Figure 9 on page 8). Figure 4: Device Address VER 1.4 8 ACE24C128B/256B/512B Two-wire Serial EEPROM Figure 5: Byte Write Figure 6: Page Write Figure 7: Current Address Read VER 1.4 9 ACE24C128B/256B/512B Two-wire Serial EEPROM Figure 8: Random Read Figure 9: Sequential Read VER 1.4 10 ACE24C128B/256B/512B Two-wire Serial EEPROM DC Characteristics Applicable over recommended operating range from: TA=-40℃ to +85℃, VCC=+1.7V to +5.5V, (unless otherwise noted). Symbol Parameter VCC1 Supply Voltage VCC2 Test Condition Min Typ Max Units 1.7 5.5 V Supply Voltage 2.5 5.5 V VCC3 Supply Voltage 2.7 5.5 V VCC4 Supply Voltage 4.5 5.5 V ICC1 Supply Current VCC = 5.0V READ at 400 kHz 0.4 1.0 mA ICC2 Supply Current VCC = 5.0V WRITE at 400 kHz 2.0 3.0 mA ISB1 Standby Current VCC = 1.7V VIN = VCC or Vss 0.6 1.0 uA ISB2 Standby Current VCC = 2.5V VIN = VCC or Vss 1.0 2.0 uA ISB3 Standby Current VCC = 2.7V VIN = VCC or Vss 1.0 2.0 Ua ISB4 Standby Current VCC = 5.0V VIN = VCC or Vss 2.0 5.0 uA ILI Input Leakage Current VIN = VCC or Vss 0.1 3.0 uA ILO Output Leakage Current VOUT = VCC or Vss 0.05 3.0 uA VIL1 Input Low Level VCC = 1.8V to 5.5V -0.3 VCC*0.3 V VIH1 Input High Level VCC = 1.8V to 5.5V VCC*0.7 VCC+0.3 V VIL2 Input Low Level VCC = 1.7V -0.3 VCC*0.2 V VIH2 Input High Level VCC = 1.7V VCC*0.7 VCC+0.3 V VOL3 Output Low Level VCC =5.0V IOL = 3.0 mA 0.4 V VOL2 Output Low Level VCC =3.0V IOL = 2.1 mA 0.4 V VOL1 Output Low Level VCC =1.7V IOL = 0.15 mA 0.2 V Max Units VI/O=0V 8 pF VIN=0V 6 pF Pin Capacitance Applicable over recommended operating range from: TA=25℃, f=1.0MHz, Vcc=1.7V Symbol CI/O CIN Parameter Input / Output Capacitance (SDA) Input Capacitance (A0, A1, A1, SCL) Test Condition Min Typ VER 1.4 11 ACE24C128B/256B/512B Two-wire Serial EEPROM AC Characteristics Applicable over recommended operating range from: TA =-40℃ to +85℃, VCC=+1.7V to +5.5V, CL =1TTL Gate and 100pF (unless otherwise noted). 1.7V≦VCC≦2.5V 2.5V≦VCC≦5.5V Min Min Symbol Parameter fSCL Clock Frequency, SCL TLOW Clock Pulse Width Low 1.2 0.6 µs THIGH Clock Pulse Width High 0.6 0.4 µs TI Noise Suppression Time TAA Clock Low to Data Out Valid TBUF Time the bus must be free before a new transmission can Start Typ Max Typ 400 0.9 Units 1000 50 0.1 Max 0.05 kHz 50 ns 0.9 µs 1.2 0.5 µs THD.STA Start Hold Time 0.6 0.25 µs TSU.STA Start Setup Time 0.6 0.25 µs THD.DAT Data In Hold Time 0 0 µs TSU.DAT Data In Setup Time 100 100 ns TR 1 Inputs Rise Time TF Inputs Fall Time 1 0.3 0.3 µs 300 300 ns TSU.STO Stop Setup Time 0.6 0.25 µs TDH Data Out Hold Time 50 50 ns TWR Write Cycle Time Endurance 5.0V, 25℃, Page Mode 3.3 5 1M 3.3 5 ms Write Cycles Notes:1. This parameter is characterized and not 100% tested. 2.AC measurement conditions: RL (connects to Vcc): 1.3kΩ(2.5V,5V),10kΩ(1.7V) Input pulse voltages: 0.3 Vcc to 0.7 Vcc Input rise and fall times: ≦50 ns Input and output timing reference voltages: 0.5Vcc The value of RL should be concerned according to the actual loading on the user’s system. VER 1.4 12 ACE24C128B/256B/512B Two-wire Serial EEPROM Bus Timing Figure 10: SCL: Serial Clock, SDA: Serial Data I/O Write Cycle Timing Figure 11: SCL: Serial Clock, SDA: Serial Data I/O Note: The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal velar/write cycle. VER 1.4 13 ACE24C128B/256B/512B Two-wire Serial EEPROM Packaging information DIP-8 VER 1.4 14 ACE24C128B/256B/512B Two-wire Serial EEPROM Packaging information SOP-8 VER 1.4 15 ACE24C128B/256B/512B Two-wire Serial EEPROM Packaging information TSSOP-8 VER 1.4 16 ACE24C128B/256B/512B Two-wire Serial EEPROM Notes ACE does not assume any responsibility for use as critical components in life support devices or systems without the express written approval of the president and general counsel of ACE Electronics Co., LTD. As sued herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and shoes failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. ACE Technology Co., LTD. http://www.ace-ele.com/ VER 1.4 17