CDB4340/41 Evaluation Board for CS4340 and CS4341 Features Description l Demonstrates The CDB4340/41 evaluation board is an excellent means for quickly evaluating the CS4340/41 family of 24-bit, stereo D/A converters. Evaluation requires an analog signal analyzer, a digital signal source, a PC for controlling the CS4341 and a power supply. Analog outputs are provided via RCA phono jacks for both channels. recommended layout and grounding arrangements l CS8414 Receives AES/EBU, S/PDIF, & EIAJ-340 Compatible Digital Audio l Digital and Analog Patch Areas l Requires only a digital signal source and power supplies for a complete Digital-toAnalog-Converter system The CS8414 digital audio receiver I.C. provides the system timing necessary to operate the Digital-to-Analog converters and will accept AES/EBU, S/PDIF, and EIAJ340 compatible audio data. The evaluation board may also be configured to accept external timing signals for operation in a user application during system development. ORDERING INFORMATION CDB4340, CDB4341 I/O for Clocks and Data CS8414 Digital Audio Interface Preliminary Product Information P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com Control Port CS4340/41 Evaluation Board Mute Circuit Analog Filter This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. Copyright Cirrus Logic, Inc. 1999 (All Rights Reserved) NOV ‘99 DS297DB3 1 CDB4340/41 TABLE OF CONTENTS 1. 2. 3. 4. 5. 6. 7. 8. 9. CDB4340/41 SYSTEM OVERVIEW ............................................................... 3 CS4340/41 DIGITAL TO ANALOG CONVERTER ......................................... 3 CS8414 DIGITAL AUDIO RECEIVER ............................................................ 3 CS8414 DATA FORMAT ................................................................................ 3 ANALOG OUTPUT FILTER ........................................................................... 4 INPUT/OUTPUT FOR CLOCKS AND DATA ................................................. 4 POWER SUPPLY CIRCUITRY ....................................................................... 4 GROUNDING AND POWER SUPPLY DECOUPLING .................................. 4 CDB4341 CONTROL PORT SOFTWARE ..................................................... 4 LIST OF FIGURES Figure 1. System Block Diagram and Signal Flow .............................................. 8 Figure 2. CS4340/41 ........................................................................................... 9 Figure 3. Analog Output Passive Filter .............................................................. 10 Figure 4. External Mute Circuit .......................................................................... 11 Figure 5. CS8414 Digital Audio Receiver Connections ..................................... 12 Figure 6. Digital Audio Inputs ............................................................................ 13 Figure 7. MCLK Divider and Voltage Level Converter ...................................... 14 Figure 8. Control Port Interface ......................................................................... 15 Figure 9. Reset Circuitry .................................................................................... 16 Figure 10. Power Supply ................................................................................... 17 Figure 11. I/O for Clocks and Data .................................................................... 18 Figure 12. Silkscreen Top ................................................................................. 19 Figure 13. Top Side ........................................................................................... 20 Figure 14. Bottom Side ...................................................................................... 21 LIST OF TABLES Table 1. CS8414 Supported Formats.................................................................... 3 Table 2. System Connections ............................................................................... 5 Table 3. CDB4340 Jumper Selectable Options..................................................... 5 Table 4. CDB4341 (I2C Mode) Jumper Selectable Options.................................. 6 Table 5. CDB4341 (SPI Mode) Jumper Selectable Options ................................. 7 Contacting Cirrus Logic Support For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: http://www.cirrus.com/corporate/contacts/ I 2 C is a registered trademark of Philips Semiconductors. Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com. 2 DS297DB3 CDB4340/41 1. CDB4340/41 SYSTEM OVERVIEW The CDB4340/41 evaluation board is an excellent means of quickly evaluating the CS4340/41. The CS8414 digital audio interface receiver provides an easy interface to digital audio signal sources including the majority of digital audio test equipment. The evaluation board also allows the user to supply clocks and data through a 10-pin header for system development. The CDB4340/41 schematic has been partitioned into 10 schematics shown in Figures 2 through 11. Each partitioned schematic is represented in the system diagram shown in Figure 1. Notice that the the system diagram also includes the interconnections between the partitioned schematics. 2. CS4340/41 DIGITAL TO ANALOG CONVERTER A description of the CS4340 is included in the CS4340 data sheet. A description of the CS4341 is included in the CS4341 data sheet. 3. CS8414 DIGITAL AUDIO RECEIVER The system receives and decodes the standard S/PDIF data format using a CS8414 Digital Audio Receiver, Figure 4. The outputs of the CS8414 include a serial bit clock, serial data, left-right clock (FSYNC), de-emphasis control and a 256 Fs master clock. The operation of the CS8414 and a discussion of the digital audio interface are included in the CS8414 Datasheet. During normal operation, the CS8414 operates in the Channel Status mode where the LED’s display channel status information for the channel selected by the CSLR/FCK jumper. This allows the CS8414 to decode the de-emphasis bit from the digital audio interface for control of the CS4340 de-emphasis filter. When the Error Information Switch is activated, the CS8414 operates in the Error and Frequency in- DS297DB3 formation mode. The information displayed by the LED’s can be decoded by consulting the CS8414 data sheet. It is likely that the de-emphasis control for the CS4340 will be erroneous and produce an incorrect audio output if the Error Information Switch is activated and the CS4340 is in the internal serial clock mode. Encoded sample frequency information can be displayed provided a proper clock is being applied to the FCK pin of the CS8414. When an LED is lit, this indicates a "1" on the corresponding pin located on the CS8414. When an LED is off, this indicates a "0" on the corresponding pin. Neither the L or R option of CSLR/FCK should be selected if the FCK pin is being driven by a clock signal. The evaluation board has been designed such that the input can be either optical or coax (see Figure 6). However, both inputs cannot be driven simultaneously. 4. CS8414 DATA FORMAT The CS8414 data format can be set with jumpers M0, M1, M2, and M3, as described the CS8414 datasheet. The format selected must be compatible with the data format of the CS4340 or CS4341, shown in the CS4340 and CS4341 datasheets. Please note that the CS8414 does not support all the possible modes of the CS4340 or CS4341, see Table 1 for details. The default settings for M0-M3 on the evaluation board are given in Tables 3-5. CS4341 CS4340 CS8414 External Internal Format Format Format SCLK SCLK 0 2 Yes Yes 1 0 2 Yes No 2 1 0 No Yes 3 2 Unsupported 4 Unsupported 5 3 5 Yes No 6 6 Yes Yes 7 0 2 Yes No Table 1. CS8414 Supported Formats 3 CDB4340/41 5. ANALOG OUTPUT FILTER The evaluation board includes a pair of single pole passive filters. The passive filters, Fig. 3, have a corner frequency of approximately 95 kHz with JP3 and JP6 installed and 190 kHz without JP3 and JP6. 6. INPUT/OUTPUT FOR CLOCKS AND DATA The evaluation board has been designed to allow the interface to external systems via the 10-pin header, J9. This header allows the evaluation board to accept externally generated clocks and data. The schematic for the clock/data I/O is shown in Figure 11. The 74HC243 transceiver functions as an I/O buffer where jumpers HDR1-HDR6 determine if the transceiver operates as a transmitter or receiver. A transmit function is implemented with the HDR1-HDR6 jumpers in the 8414 position. LRCK, SDATA, and SCLK from the CS8414 will be outputs on J9. The transceiver operates as a receiver with jumpers HDR1-HDR6 in the EXTERNAL position. MCLK, LRCK, SDATA and SCLK on J9 become inputs. 7. POWER SUPPLY CIRCUITRY Power is supplied to the evaluation board by three binding posts (GND, +5V, +3V/+5V) (see Figure 10). The +5V input supplies power to the +5 Volt digital circuitry (VA+5, VD+5, VDPC+5), while the +3V/+5V input supplies power to the Voltage Level Converter and the CS4340/41 for evaluation in either +3 or +5 Volt mode. Note, the 4 supply voltages, VCCA and VCCB, to the Voltage Level Converter (LVXC4245) must remain within 2.25 Volts of each other in order to maintain proper operation. 8. GROUNDING AND POWER SUPPLY DECOUPLING The CS4340/41 requires careful attention to power supply and grounding arrangements to optimize performance. Figure 10 details the power distribution used on this board. The CDB4340/41 ground plane is split to control the digital return currents in order to minimize digital interference. The decoupling capacitors are located as close to the CS4340/41 as possible. Extensive use of ground plane fill on both the analog and digital sections of the evaluation board yields large reductions in radiated noise. 9. CDB4341 CONTROL PORT SOFTWARE The CDB4341 is shipped with Windows based software for interfacing with the CS4341 control port via the DB25 connector, P1. The software can be used to communicate with the CS4341 in either SPI or I2C mode; however, in SPI mode the CS4341 registers are write-only. Run SETUP.EXE from the distribution diskette to install the software. Further documentation for the software is available on the distribution diskette. The documentation is available in the plain text format file, README.TXT. DS297DB3 CDB4340/41 CONNECTOR INPUT/OUTPUT SIGNAL PRESENT +5 V input + 5 Volt power +3V/+5V input + 3 Volt or + 5 Volt power for the CS4340/41 and the Voltage Level Converter GND input ground connection from power supply Digital input input digital audio interface input via coax Optical input input digital audio interface input via optical J9 input/output I/O for master, serial, left/right clocks and serial data Parallel Port input/output parallel connection to PC for SPI/I2C control port signals Control I/O input/output I/O for SPI/I2C control port signals AOUTA output channel A analog output with single-pole passive filter AOUTB output channel B analog output with single-pole passive filter Table 2. System Connections JUMPER CSLR/FCK PURPOSE FUNCTION SELECTED HI *LO See CS8414 Datasheet for details CS8414 mode selection *Low *High *Low *Low See CS8414 Datasheet for details Selects SCLK Mode INT *EXT Internal SCLK Mode External SCLK Mode Selects source of de-emphasis control *8414 DEM CS8414 de-emphasis De-emphasis input static low HDR1-6 Selects source of clocks and audio data *8414 EXT Selects CS8414 as source Digital I/O header becomes an source HDR 7 Enables the external mute for AOUTA *ON OFF Mute Enabled Mute Disabled HDR 8 Enables the external mute for AOUTB *ON OFF Mute Enabled Mute Disabled MCLK Selects High-Rate or Base-Rate Modes *x1 ÷2 Selects Base-Rate Mode Selects High-Rate Mode HDR15 DIF1 HI *LOW See CS4340 Datasheet for details HDR16 DIF0 HI *LOW See CS4340 Datasheet for details HDR17 DEM0 HI *LOW See CS4340 Datasheet for details M0 M1 M2 M3 SCLK DEM_8414 ENCTRL Selects channel for CS8414 channel status information POSITION Enables/Disables parallel port Enable *Disable Invalid for CS4340 Disables parallel port Table 3. CDB4340 Jumper Selectable Options *Default setting from factory DS297DB3 5 CDB4340/41 JUMPER CSLR/FCK PURPOSE FUNCTION SELECTED HI *LO See CS8414 Datasheet for details CS8414 mode selection *Low *High *Low *Low See CS8414 Datasheet for details Selects SCLK Mode INT *EXT Internal SCLK Mode External SCLK Mode Selects source of de-emphasis control *8414 DEM “Don’t Care” for CS4341 HDR1-6 Selects source of clocks and audio data *8414 EXT Selects CS8414 as source Digital I/O header becomes an source HDR 7 Enables the external mute for AOUTA *ON OFF Mute Enabled Mute Disabled HDR 8 Enables the external mute for AOUTB *ON OFF Mute Enabled Mute Disabled MCLK Selects High-Rate or Base-Rate Modes *x1 ÷2 Selects Base-Rate Mode Selects High-Rate Mode HDR15 SCL Pull-Up *HI LOW SCL pulled high Invalid for I2C mode HDR16 SDA Pull-Up *HI LOW SDA pulled high Invalid for I2C mode HDR17 AD0 HI *LOW “Don’t Care” for Control Port Mode M0 M1 M2 M3 SCLK DEM_8414 ENCTRL Selects channel for CS8414 channel status information POSITION Enables/Disables parallel port *Enable Disable Enables parallel port Disables parallel port (must use HDR14) Table 4. CDB4341 (I2C Mode) Jumper Selectable Options *Default setting from factory Notes: 6 The CDB4341 evaluation board is shipped from the factory configured for I2C mode. DS297DB3 CDB4340/41 JUMPER CSLR/FCK PURPOSE FUNCTION SELECTED HI *LO See CS8414 Datasheet for details CS8414 mode selection *Low *High *Low *Low See CS8414 Datasheet for details Selects SCLK Mode INT *EXT Internal SCLK Mode External SCLK Mode Selects source of de-emphasis control *8414 DEM “Don’t Care” for CS4341 HDR1-6 Selects source of clocks and audio data *8414 EXT Selects CS8414 as source Digital I/O header becomes an source HDR 7 Enables the external mute for AOUTA *ON OFF Mute Enabled Mute Disabled HDR 8 Enables the external mute for AOUTB *ON OFF Mute Enabled Mute Disabled MCLK Selects High-Rate or Base-Rate Modes *x1 ÷2 Selects Base-Rate Mode Selects High-Rate Mode HDR15 CCLK Pull-up or Pull-down *HI LOW “Don’t Care” for SPI mode HDR16 CDIN Pull-up or Pull-down *HI LOW “Don’t Care” for SPI mode HDR17 CS Pull-up HI *LOW “Don’t Care” for Control Port Mode M0 M1 M2 M3 SCLK DEM_8414 ENCTRL Selects channel for CS8414 channel status information POSITION Enables/Disables parallel port *Enable Disable Enables parallel port Disables parallel port (must use HDR14) Table 5. CDB4341 (SPI Mode) Jumper Selectable Options *Default setting from factory Notes: DS297DB3 When in SPI mode, it is not possible to read the control registers of the CS4341. The CDB4341 evaluation board is shipped from the factory configured for I2C mode. 7 CDB4340/41 I/O for Clocks and Data Fig 11 Digital Audio Input Fig 6 Control Port Interface Fig 8 RXN RXP CS8414 Digital Audio Receiver Connections Fig 5 MCLK LRCK SCLK SDATA Voltage MCLK LRCK Level Converter SCLK SDATA Fig 7 CS4340/41 Fig 2 Reset Circuit Fig 9 Passive Analog Filter Fig 3 External Mute Circuit Fig 4 Figure 1. System Block Diagram and Signal Flow 8 DS297DB3 MUTEC DS297DB3 C44 3.3UF TP5 MUTEC ALP FERRITE_BEAD L1 VA+3/+5 1 C17 .1UF X7R RST SDATA-A DEM1/SCLK-A LRCK-A MCLK-A DIF1/SCL/CCLK-A DIF0/SDA/CDIN R10 499 R13 499 R14 499 R41 49.9 R40 200 R39 200 2 U7 3 4 5 6 7 C23 10UF 1 2 3 4 5 6 7 8 /RST MUTEC SDATA AOUTA SCLK VA CS4341 LRCK AGND MCLK AOUTB SCL/CCLK REF_GND SDA/CDIN VCOM AD0//CS FILT+ 16 15 14 13 12 11 10 9 AGND 3.3UF TP4 ARP C43 CS4341_KS 8 DEM0/AD0/CS-A 1UF C34 1UF C35 C20 .1UF C21 .1UF AGND X7R X7R 9 CDB4340/41 Figure 2. CS4340/41 10 HDR1X2 HDR7 1 2 MUTEA R18 ALP R28 10K J4 CON_RCA_RA 560 C18 1500PF COG 1 C6 1500PF COG 2 3 4 NC AOUTLP A JP3 AGND AGND AGND HDR1X2 HDR8 1 2 MUTEB R17 ARP R29 10K J3 CON_RCA_RA 560 C22 1500PF COG 1 C5 1500PF COG 2 3 4 NC AOUTRP B JP6 AGND DS297DB3 AGND Figure 3. Analog Output Passive Filter CDB4340/41 AGND DS297DB3 VA+3/+5 2 MMUN2111LT1 Q3 1 MUTEA Q1 2SC2878 3 MUTEB 2 2 3 R25 MUTEC 2K Q4 MMUN2211LT1 1 Q2 2SC2878 3 3 1 1 2 AGND R31 AGND 2K AGND 11 CDB4340/41 Figure 4. External Mute Circuit 1 2 3 12 HDR1X3 HDR5 HDR1X3 HDR3 GND C1 10UF 1 2 3 VA+5 1 2 3 MCLK HDR1X3 HDR4 VA GND 1 2 3 SCLK HDR1X3 HDR2 C26 C16 .1UF VD+5 RN3 560 VD+5 C31 14 VCC D1 LED_RECT 2 .1UF X7R 1UF 1 SN74HC04N D3 4 3 6 5 RXP RXN LED_RECT CSLR/FCK D5 LED_RECT VD1 SDATA GND U8 HDR1X3 HDR1 10 1 2 3 LRCK R11 VD1 C27 U2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 C VERF CD/F1 CE/F2 CC/F0 SDATA CB/E2 ERF CA/E1 M1 /C0/E0 M0 VD+ VA+ DGND AGND RXP FILT RXN MCK FSYNC M2 SCK M3 CS12/FCK SEL U CBL 28 27 26 25 24 23 22 21 20 19 18 17 16 15 CS8414_M0 .1UF X7R CS8414_M1 1UF C32 CS8414_M2 VA R9 470 C33 CS8414 .068UF X7R 8 9 CSLR/FCK 10 11 SW_B3W_1100 S4 D4 LED_RECT R7 47.5K ERROR & FREQ D2 12 LED_RECT 13 GND GND HDR1X3 M2 1 2 M2 3 HDR1X3 CSLR/FCK 1 2 CSLR/FCK 3 R6 47.5K 8414_DEM HDR1X3 8414_DEM 1 DEM 2 3 8414 DEM1/SCLK SCLK HDR1X3 EXT_INT_SCLK 1 INT 2 3 EXT TP10 VD1 7 HDR1X3 M1 1 2 M1 3 HDR1X3 M3 1 2 8414_M 3 GND 8414_DEM D6 LED_RECT HDR1X3 M0 1 2 M0 3 INT/EXT SCLK GND CDB4340/41 DS297DB3 Figure 5. CS8414 Digital Audio Receiver Connections DS297DB3 DIGITAL INPUT OPTICAL INPUT OPT1 J5 CON_RCA_RA NC 3 4 6 C11 1 2 C10 1 RXN R30 .01UF 75 RXP .01UF 2 3 C9 .01UF L4 4 47UH 5 GND VD+5 TORX173 GND 13 CDB4340/41 Figure 6. Digital Audio Inputs 14 VA+3/+5 MCLK VD+5 VD+5 VD+5 4 3 2 1 10 11 12 13 GND /SET1 CLOCK1 DATA1 /RST1 /SET2 CLOCK2 DATA2 /RST2 Q1 /Q1 Q2 /Q2 GND VD+5 J20 HDR1X3 MCLK 1 2 3 VD+5 VCC 14 5 HRM 6 BRM MCLK-B 9 SDATA DEM1/SCLK LRCK DIF1/SCL/CCLK 8 DEM0/AD0/CS 19 1 /G DIR 2 3 4 5 6 7 8 9 A1 A2 A3 A4 A5 A6 A7 A8 VCC 20 B1 B2 B3 B4 B5 B6 B7 B8 18 17 16 15 14 13 12 11 GND 10 C14 .1UF AGND U5 U1 SDATA-A DEM1/SCLK-A LRCK-A MCLK-A DIF1/SCL/CCLK-A DEM0/AD0/CS-A 7 MC74HC74AN GND SN74VHC245DW VD+5 GND C15 .1UF GND CDB4340/41 DS297DB3 Figure 7. MCLK Divider and Voltage Level Converter GND DS297DB3 C7 VDPC+5 .1UF VCC PC0 VDPC+5 14 U6 2 U6 3 12 LATCH 11 SN74HCT125N GND SN74HCT125N 7 1 13 1K 1K 1K 1K 1K 1K GND 4 GND SN74HCT125N R2 R3 R5 R4 R8 R12 6 5 U6 LATCH ENCTRL DB25M_RA P1 1 14 2 15 3 16 4 17 5 18 6 19 7 20 8 21 9 22 10 23 11 24 12 25 13 U3 DIF1/SCL/CCLK VCC GND 20 10 10 SN74HCT125N 9 DIF0/SDA/CDIN 8 U6 DEM0/AD0/CS VDPC+5 SN74HC574N VDPC+5 2K 19 18 17 16 15 14 13 12 VA+3/+5 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 2K 1D 2D 3D 4D 5D 6D 7D 8D 2K 2 3 4 5 6 7 8 9 .1UF /OC CLK C4 GND 1 11 VDPC+5 R22 R23 R21 R19 DIF1/SCL/CCLK DIF0/SDA/CDIN DEM0/AD0/CS GND GND Figure 8. Control Port Interface HDR1X3 HDR17 1 2 3 HDR1X3 HDR18 1 2 3 ENCTRL 2K R20 HDR1X3 HDR16 1 2 3 GND 15 CDB4340/41 HDR4X2 HDR14 1 2 3 4 5 6 7 8 2K GND HDR1X3 HDR15 1 2 3 2K R16 GND 16 VA+3/+5 D7 BAT85 R1 200K C29 100 RST AGND S1 SW_B3W_1100 R27 3.3UF AGND CDB4340/41 DS297DB3 Figure 9. Reset Circuitry DS297DB3 +5V GND CON_BANANA +3V/+5V CON_BANANA J6 CON_BANANA J7 J1 Z1 P6KE6V8P Z2 C12 47UF C2 47UF C25 VA+5 .1UF VA+3/+5 AGND C13 47UF L2 FB .1UF C3 .1UF L3 FB C8 P6KE6V8P GND VD+5 Figure 10. Power Supply 17 CDB4340/41 GND 10UF C19 VDPC+5 18 GND 7 MCLK SCLK LRCK SDATA 8 9 10 11 VD+5 14 U4 74HC243 GND A4 A3 A2 A1 B4 B3 B2 B1 VCC GBA /GAB 9 7 5 3 1 6 5 4 3 10 8 6 4 2 MCLK SCLK LRCK SDATA J9 HDR5X2 13 1 GND DIGITAL I/O C24 .1UF 8414 EXTERNAL CLK SOURCE GND GND VD+5 CDB4340/41 DS297DB3 Figure 11. I/O for Clocks and Data 1 2 3 HDR1X3 HDR6 CDB4340/41 Figure 12. Silkscreen Top DS297DB3 19 CDB4340/41 Figure 13. Top Side 20 DS297DB3 CDB4340/41 Figure 14. Bottom Side DS297DB3 21