EP7312 - High-performance System-on-chip w

EP7312 Data Sheet
FEATURES
High-performance,
Low-power, System-on-chip
with SDRAM & Enhanced
Digital Audio Interface
ARM®720T Processor
— ARM7TDMI CPU Operating at Speeds of 74 and
90 MHz
— 8 kBytes of Four-way Set-associative Cache
— MMU with 64-entry TLB
— Thumb™ Code Support Enabled
Ultra low power
— 90 mW at 74 MHz Typical
— 108 mW at 90 MHz Typical
— <.03 mW in the Standby State
Advanced Audio Decoder/decompression Capability
— Supports bit streams with adaptive bit rates.
— Allows for support of multiple audio decompression
algorithms (MP3, WMA, AAC, Audible, etc.).
OVERVIEW
The Cirrus Logic™ EP7312 is designed for ultra-low-power
portable and line-powered applications such as portable
consumer entertainment devices, home and car audio juke box
systems, and general purpose industrial control applications, or
any device that features the added capability of digital audio
compression & decompression. The core-logic functionality of
the device is built around an ARM720T processor with
8 kBytes of four-way set-associative unified cache and a write
buffer. Incorporated into the ARM720T is an enhanced
memory management unit (MMU) which allows for support of
sophisticated operating systems like Microsoft® Windows®
CE and Linux®.
(cont.)
(cont.)
BLOCK DIAGRAM
Serial
Interface
EPB Bus
Power
Managem ent
(2) UARTs
w/ IrDA
Clocks &
Tim ers
ARM720T
ICE-JTAG
Interrupts,
PW M & GPIO
ARM 7TDM I CPU Core
8 KB
Cache
Boot
ROM
W rite
Buffer
Bus
Bridge
MMU
Keypad&
Touch
Screen I/F
Internal Data Bus
M em ory Controller
M averickKey TM
SRAM I/F
SDRAM I/F
On-chip SRAM
48 KB
USER INTERFACE
SERIAL PORTS
Digital
Audio
Interface
LCD
Controller
MEMORY and STORAGE
Copyright Cirrus Logic, Inc. 2011
http://www.cirrus.com
(All Rights Reserved)
MAR ‘11
DS508F2
EP7312
High-Performance, Low-Power System on Chip
FEATURES (cont)
48 KBytes of On-chip SRAM
MaverickKey™ IDs
— 32-bit unique ID can be used for DRM-compliant 128bit random ID.
Available in 74 and 90 MHz clock speeds.
LCD controller
— Interfaces directly to a single-scan panel monochrome
STN LCD.
— Interfaces to a single-scan panel color STN LCD with
minimal external glue logic.
Full JTAG Boundary Scan and Embedded ICE Support
Integrated Peripheral Interfaces
— 32-bit SDRAM Interface, Up to 2 External Banks
— 8/32/16-bit SRAM/FLASH/ROM Interface
— Digital Audio Interface provides glueless interface to
low-power DACs, ADCs, and CODECs.
— Two Synchronous Serial Interfaces (SSI1, SSI2)
— CODEC Sound Interface
— 88 Keypad Scanner
— 27 General-purpose Input/Output Pins
— Dedicated LED Flasher Pin from the RTC
Internal Peripherals
— Two 16550-compatible UARTs
— IrDA Interface
— Two PWM Interfaces
— Real-time Clock
— Two General-purpose 16-bit Timers
— Interrupt Controller
— Boot ROM
Package
— 208-Pin LQFP
— 256-Ball PBGA
The fully static EP7312 is optimized for low power
dissipation and is fabricated using a 0.25 micron CMOS
process.
OVERVIEW (cont.)
The EP7312 is designed for ultra-low-power operation. Its core
operates at only 2.5 V, while its I/O has an operation range of
2.5 V–3.3 V. The device has three basic power states:
operating, idle and standby.
MaverickKey unique hardware programmed IDs are a solution
to the growing concern over secure web content and
commerce. With Internet security playing an important role in
the delivery of digital media such as books or music,
traditional software methods are quickly becoming unreliable.
The MaverickKey unique IDs provide OEMs with a method of
utilizing specific hardware IDs such as those assigned for
SDMI (Secure Digital Music Initiative) or any other
authentication mechanism.
2
The EP7312 integrates an interface to enable a direct
connection to many low cost, low power, high quality audio
converters. In particular, high quality ADCs, DACs, or
CODECs such as the Cirrus Logic CS53L32A, CS43L42, and
CS42L50 are easily added to an EP73xx design via the DAI.
Some of these devices feature digital bass and treble boost,
digital volume control and compressor-limiter functions.
Simply by adding desired memory and peripherals to the
highly integrated EP7312 completes a low-power system
solution. All necessary interface logic is integrated on-chip.
Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
DS508F2
EP7312
High-Performance, Low-Power System on Chip
Table of Contents
FEATURES ...........................................................................................................................................1
OVERVIEW ...........................................................................................................................................1
FEATURES (cont) .......................................................................................................................................................2
OVERVIEW (cont.) ......................................................................................................................................................2
Description of the EP7312’s Components, Functionality, and Interfaces ....................................6
Processor Core - ARM720T ..................................................................................................................................6
Power Management ..............................................................................................................................................6
MaverickKey™ Unique ID .....................................................................................................................................6
Memory Interfaces .................................................................................................................................................6
Digital Audio Capability .........................................................................................................................................7
Universal Asynchronous Receiver/Transmitters (UARTs) .....................................................................................7
Digital Audio Interface (DAI) ..................................................................................................................................7
CODEC Interface ..................................................................................................................................................8
SSI2 Interface ........................................................................................................................................................8
Synchronous Serial Interface ................................................................................................................................8
LCD Controller .......................................................................................................................................................8
64-Key Keypad Interface .......................................................................................................................................8
Interrupt Controller ................................................................................................................................................9
Real-Time Clock ....................................................................................................................................................9
PLL and Clocking ..................................................................................................................................................9
DC-to-DC Converter Interface (PWM) .................................................................................................................10
Timers .................................................................................................................................................................10
General Purpose Input/Output (GPIO) ................................................................................................................10
Hardware Debug Interface ..................................................................................................................................10
LED Flasher ........................................................................................................................................................10
Internal Boot ROM ...............................................................................................................................................10
Packaging ............................................................................................................................................................10
Pin Multiplexing ................................................................................................................................................... 11
System Design ....................................................................................................................................................12
ELECTRICAL SPECIFICATIONS ......................................................................................................13
Absolute Maximum Ratings .................................................................................................................................13
Recommended Operating Conditions .................................................................................................................13
DC Characteristics ..............................................................................................................................................13
Timings ...............................................................................................................................................15
Timing Diagram Conventions ....................................................................................................................15
Timing Conditions ......................................................................................................................................15
SDRAM Interface ................................................................................................................................................16
SDRAM Load Mode Register Cycle ..........................................................................................................17
SDRAM Burst Read Cycle .........................................................................................................................18
SDRAM Burst Write Cycle .........................................................................................................................19
SDRAM Refresh Cycle ..............................................................................................................................20
Static Memory ......................................................................................................................................................21
Static Memory Single Read Cycle .............................................................................................................22
Static Memory Single Write Cycle ..............................................................................................................23
Static Memory Burst Read Cycle ...............................................................................................................24
Static Memory Burst Write Cycle ...............................................................................................................25
SSI1 Interface ......................................................................................................................................................26
DS508F2
Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
3
EP7312
High-Performance, Low-Power System on Chip
SSI2 Interface ..................................................................................................................................................... 27
LCD Interface ...................................................................................................................................................... 28
JTAG Interface .................................................................................................................................................... 29
Packages ........................................................................................................................................... 30
208-Pin LQFP Package Characteristics ............................................................................................................. 30
208-Pin LQFP Pin Diagram ................................................................................................................................ 31
208-Pin LQFP Numeric Pin Listing ..................................................................................................................... 32
256-Ball PBGA Package Characteristics ............................................................................................................ 38
256-Ball PBGA Pinout (Top View) ....................................................................................................................... 39
256-Ball PBGA Ball Listing ................................................................................................................................. 40
JTAG Boundary Scan Signal Ordering ............................................................................................................... 45
CONVENTIONS ................................................................................................................................. 50
Acronyms and Abbreviations .............................................................................................................................. 50
Units of Measurement ......................................................................................................................................... 50
General Conventions .......................................................................................................................................... 51
Pin Description Conventions ............................................................................................................................... 51
Ordering Information ....................................................................................................................... 52
Environmental, Manufacturing, & Handling Information ............................................................. 52
Revision History .............................................................................................................................. 53
4
Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
DS508F2
EP7312
High-Performance, Low-Power System on Chip
List of Figures
Figure 1. A Fully-Configured EP7312-Based System ...................................................................................................12
Figure 2. Legend for Timing Diagrams .........................................................................................................................15
Figure 3. SDRAM Load Mode Register Cycle Timing Measurement ............................................................................17
Figure 4. SDRAM Burst Read Cycle Timing Measurement ..........................................................................................18
Figure 5. SDRAM Burst Write Cycle Timing Measurement ..........................................................................................19
Figure 6. SDRAM Refresh Cycle Timing Measurement ................................................................................................20
Figure 7. Static Memory Single Read Cycle Timing Measurement ...............................................................................22
Figure 8. Static Memory Single Write Cycle Timing Measurement ...............................................................................23
Figure 9. Static Memory Burst Read Cycle Timing Measurement ................................................................................24
Figure 10. Static Memory Burst Write Cycle Timing Measurement ..............................................................................25
Figure 11. SSI1 Interface Timing Measurement ...........................................................................................................26
Figure 12. SSI2 Interface Timing Measurement ...........................................................................................................27
Figure 13. LCD Controller Timing Measurement ..........................................................................................................28
Figure 14. JTAG Timing Measurement .........................................................................................................................29
Figure 15. 208-Pin LQFP Package Outline Drawing ....................................................................................................30
Figure 16. 208-Pin LQFP (Low Profile Quad Flat Pack) Pin Diagram ..........................................................................31
Figure 17. 256-Ball PBGA Package ..............................................................................................................................38
List of Tables
Table 1. Power Management Pin Assignments ..............................................................................................................6
Table 2. Static Memory Interface Pin Assignments ........................................................................................................6
Table 3. SDRAM Interface Pin Assignments ..................................................................................................................7
Table 4. Universal Asynchronous Receiver/Transmitters Pin Assignments ...................................................................7
Table 5. DAI Interface Pin Assignments .........................................................................................................................7
Table 6. CODEC Interface Pin Assignments ..................................................................................................................8
Table 7. SSI2 Interface Pin Assignments .......................................................................................................................8
Table 8. Serial Interface Pin Assignments ......................................................................................................................8
Table 9. LCD Interface Pin Assignments ........................................................................................................................8
Table 10. Keypad Interface Pin Assignments .................................................................................................................9
Table 11. Interrupt Controller Pin Assignments ..............................................................................................................9
Table 12. Real-Time Clock Pin Assignments ..................................................................................................................9
Table 13. PLL and Clocking Pin Assignments ................................................................................................................9
Table 14. DC-to-DC Converter Interface Pin Assignments ...........................................................................................10
Table 15. General Purpose Input/Output Pin Assignments ..........................................................................................10
Table 16. Hardware Debug Interface Pin Assignments ................................................................................................10
Table 17. LED Flasher Pin Assignments ......................................................................................................................10
Table 18. DAI/SSI2/CODEC Pin Multiplexing ...............................................................................................................11
Table 19. Pin Multiplexing .............................................................................................................................................11
Table 20. 208-Pin LQFP Numeric Pin Listing ...............................................................................................................32
Table 21. 256-Ball PBGA Ball Listing ...........................................................................................................................40
Table 22. JTAG Boundary Scan Signal Ordering .........................................................................................................45
Table 23. Acronyms and Abbreviations ........................................................................................................................50
Table 24. Unit of Measurement .....................................................................................................................................50
Table 25. Pin Description Conventions .........................................................................................................................51
DS508F2
Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
5
EP7312
High-Performance, Low-Power System on Chip
Description of the EP7312’s Components, Functionality, and Interfaces
The following sections describe the EP7312 in more detail.
Processor Core - ARM720T
The EP7312 incorporates an ARM 32-bit RISC micro
controller that controls a wide range of on-chip peripherals.
The processor utilizes a three-stage pipeline consisting of
fetch, decode and execute stages. Key features include:
•
•
•
•
ARM (32-bit) and Thumb (16-bit compressed) instruction
sets
Enhanced MMU for Microsoft Windows CE and other
operating systems
8 KB of 4-way set-associative cache.
Translation Look Aside Buffers with 64 Translated Entries
Power Management
The EP7312 is designed for ultra-low-power operation. Its core
operates at only 2.5 V, while its I/O has an operation range of
2.5 V–3.3 V. The device has three basic power states:
• Operating — This state is the full performance state.
All the clocks and peripheral logic are enabled.
• Idle — This state is the same as the Operating State,
except the CPU clock is halted while waiting for an
event such as a key press.
• Standby — This state is equivalent to the computer
being switched off (no display), and the main
oscillator shut down. An event such as a key press
can wake-up the processor.
Table 1 shows the power management pin assignments.
Table 1. Power Management Pin Assignments
Pin Mnemonic
I/O
Pin Description
BATOK
I
Battery ok input
nEXTPWR
I
External power supply sense
input
nPWRFL
I
Power fail sense input
nBATCHG
I
Battery changed sense input
Both a specific 32-bit ID as well as a 128-bit random ID is
programmed into the EP7312 through the use of laser probing
technology. These IDs can then be used to match secure
copyrighted content with the ID of the target device the
EP7312 is powering, and then deliver the copyrighted
information over a secure connection. In addition, secure
transactions can benefit by also matching device IDs to server
IDs. MaverickKey IDs provide a level of hardware security
required for today’s Internet appliances.
Memory Interfaces
There are two main external memory interfaces. The first one
is the ROM/SRAM/FLASH-style interface that has
programmable wait-state timings and includes burst-mode
capability, with six chip selects decoding six 256 MB sections
of addressable space. For maximum flexibility, each bank can
be specified to be 8-, 16-, or 32-bits wide. This allows the use
of 8-bit-wide boot ROM options to minimize overall system
cost. The on-chip boot ROM can be used in product
manufacturing to serially download system code into system
FLASH memory. To further minimize system memory
requirements and cost, the ARM Thumb instruction set is
supported, providing for the use of high-speed 32-bit
operations in 16-bit op-codes and yielding industry-leading
code density. shows the Static Memory Interface pin
assignments.
Table 2. Static Memory Interface Pin Assignments
Pin Mnemonic
O
Chip select out
A[27:0]
O
Address output
D[31:0]
I/O
Data I/O
nMOE/nSDCAS
(Note)
O
ROM expansion OP enable
nMWE/nSDWE
(Note)
O
ROM expansion write enable
HALFWORD
O
Halfword access select
output
WORD
O
Word access select output
O
Transfer direction
Note:
MaverickKey unique hardware programmed IDs are a solution
to the growing concern over secure web content and
commerce. With Internet security playing an important role in
the delivery of digital media such as books or music,
traditional software methods are quickly becoming unreliable.
The MaverickKey unique IDs provide OEMs with a method of
utilizing specific hardware IDs such as those assigned for
SDMI (Secure Digital Music Initiative) or any other
authentication mechanism.
6
Pin Description
nCS[5:0]
WRITE/nSDRAS
MaverickKey™ Unique ID
I/O
(Note)
Pins are multiplexed. See Table 19 on page 11 for
more information.
Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
DS508F2
EP7312
High-Performance, Low-Power System on Chip
The second is the programmable 16- or 32-bit-wide SDRAM
interface that allows direct connection of up to two banks of
SDRAM, totaling 512 Mb. To assure the lowest possible power
consumption, the EP7312 supports self-refresh SDRAMs,
which are placed in a low-power state by the device when it
enters the low-power Standby State. Table 3 shows the
SDRAM Interface pin assignments.
Table 3. SDRAM Interface Pin Assignments
Pin Mnemonic
I/O
Pin Description
communication interface directly. Table 4 shows the UART pin
assignments.
Table 4. Universal Asynchronous Receiver/Transmitters Pin
Assignments
Pin Mnemonic
I/O
Pin Description
TXD[1]
O
UART 1 transmit
RXD[1]
I
UART 1 receive
CTS
I
UART 1 clear to send
SDCLK
O
SDRAM clock output
DCD
I
UART 1 data carrier detect
SDCKE
O
SDRAM clock enable output
DSR
I
UART 1 data set ready
nSDCS[1:0]
O
SDRAM chip select out
TXD[2]
O
UART 2 transmit
WRITE/nSDRAS
(Note 2)
O
SDRAM RAS signal output
RXD[2]
I
UART 2 receive
nMOE/nSDCAS
(Note 2)
O
SDRAM CAS control signal
LEDDRV
O
Infrared LED drive output
nMWE/nSDWE
(Note 2)
O
SDRAM write enable control
signal
PHDIN
I
Photo diode input
A[27:15]/DRA[0:12]
(Note 1)
O
SDRAM address
O
SDRAM internal bank select
I/O
SDRAM byte lane mask
SDQM[3:2]
O
SDRAM byte lane mask
D[31:0]
I/O
Data I/O
A[14:13]/DRA[12:14]
PD[7:6]/SDQM[1:0]
Note:
(Note 2)
Digital Audio Interface (DAI)
1. Pins A[27:13] map to DRA[0:14] respectively.
(i.e. A[27}/DRA[0}, A[26}/DRA[1], etc.) This is to
balance the load for large memory systems.
2. Pins are multiplexed. See Table 19 on page 11 for
more information.
The EP7312 integrates an interface to enable a direct
connection to many low cost, low power, high quality audio
converters. In particular, the DAI can directly interface with
the Crystal‚ CS43L41/42/43 low-power audio DACs and the
Crystal‚ CS53L32 low-power ADC. Some of these devices
feature digital bass and treble boost, digital volume control and
compressor-limiter functions. Table 5 shows the DAI Interface
pin assignments.
Table 5. DAI Interface Pin Assignments
Pin Mnemonic
Digital Audio Capability
The EP7312 uses its powerful 32-bit RISC processing engine
to implement audio decompression algorithms in software. The
nature of the on-board RISC processor, and the availability of
efficient C-compilers and other software development tools,
ensures that a wide range of audio decompression algorithms
can easily be ported to and run on the EP7312
Universal Asynchronous
Receiver/Transmitters (UARTs)
Pin Description
SCLK
O
Serial bit clock
SDOUT
O
Serial data out
SDIN
I
Serial data in
LRCK
O
Sample clock
MCLKIN
I
Master clock input
MCLKOUT
O
Master clock output
Note:
The EP7312 includes two 16550-type UARTs for RS-232
serial communications, both of which have two 16-byte FIFOs
for receiving and transmitting data. The UARTs support bit
rates up to 115.2 kbps. An IrDA SIR protocol encoder/decoder
can be optionally switched into the RX/TX signals to/from
UART 1 to enable these signals to drive an infrared
DS508F2
I/O
See Table 18 on page 11 for information on pin
multiplexes.
Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
7
EP7312
High-Performance, Low-Power System on Chip
CODEC Interface
Synchronous Serial Interface
The EP7312 includes an interface to telephony-type CODECs
for easy integration into voice-over-IP and other voice
communications systems. The CODEC interface is
multiplexed to the same pins as the DAI and SSI2. Table 6
shows the CODEC Interface Pin Assignments.
The EP7312 Synchronous Serial Interface has these features:
Table 6. CODEC Interface Pin Assignments
Pin Mnemonic
I/O
O
Serial bit clock
PCMOUT
O
Serial data out
PCMIN
I
Serial data in
PCMSYNC
O
Frame sync
Table 8. Serial Interface Pin Assignments
Pin Mnemonic
See Table 18 on page 11 for information on pin
multiplexes.
SSI2 Interface
An additional SPI/Microwire1-compatible interface is
available for both master and slave mode communications. The
SSI2 unit shares the same pins as the DAI and CODEC
interfaces through a multiplexer. The SSI2 Interface has these
features:
•
•
•
•
Synchronous clock speeds of up to 512 kHz
Separate 16 entry TX and RX half-word wide FIFOs
Half empty/full interrupts for FIFOs
Separate RX and TX frame sync signals for asymmetric
traffic
Table 7 shows the SSI2 Interface pin assignments.
Table 7. SSI2 Interface Pin Assignments
Pin Mnemonic
I/O
Pin Description
SSICLK
I/O
Serial bit clock
SSITXDA
O
Serial data out
SSIRXDA
I
Serial data in
SSITXFR
I/O
Transmit frame sync
SSIRXFR
I/O
Receive frame sync
Note:
ADC (SSI) Interface: Master mode only; SPI and
Microwire1-compatible (128 kbps operation)
• Selectable serial clock polarity
Table 8 shows the Synchronous Serial Interface pin
assignments.
Pin Description
PCMCLK
Note:
•
See Table 18 on page 11 for information on pin
multiplexes.
I/O
Pin Description
ADCLK
O
SSI1 ADC serial clock
ADCIN
I
SSI1 ADC serial input
ADCOUT
O
SSI1 ADC serial output
nADCCS
O
SSI1 ADC chip select
SMPCLK
O
SSI1 ADC sample clock
LCD Controller
A DMA address generator is provided that fetches video
display data for the LCD controller from memory. The display
frame buffer start address is programmable, allowing the LCD
frame buffer to be in SDRAM, internal SRAM or external
SRAM. The LCD controller has these features:
•
Interfaces directly to a single-scan panel monochrome STN
LCD
• Interfaces to a single-scan panel color STN LCD with
minimal external glue logic
• Panel width size is programmable from 32 to 1024 pixels in
16-pixel increments
• Video frame buffer size programmable up to
128 KB
• Bits per pixel of 1, 2, or 4 bits
Table 9 shows the LCD Interface pin assignments.
Table 9. LCD Interface Pin Assignments
Pin Mnemonic
I/O
Pin Description
CL1
O
LCD line clock
CL2
O
LCD pixel clock out
DD[3:0]
O
LCD serial display data bus
FRM
O
LCD frame synchronization pulse
M
O
LCD AC bias drive
64-Key Keypad Interface
Matrix keyboards and keypads can be easily read by the
EP7312. A dedicated 8-bit column driver output generates
8
Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
DS508F2
EP7312
High-Performance, Low-Power System on Chip
strobes for each keyboard column signal. The pins of Port A,
when configured as inputs, can be selectively OR'ed together
to provide a keyboard interrupt that is capable of waking the
system from a STANDBY or IDLE state. The Keypad
Interface has these features:
•
•
•
•
•
Column outputs can be individually set high with the
remaining bits left at high-impedance
Column outputs can be driven all-low, all-high, or all-highimpedance
Keyboard interrupt driven by OR'ing together all Port A
bits
Keyboard interrupt can be used to wake up the system
88 keyboard matrix usable with no external logic, extra
keys can be added with minimal glue logic
Real-Time Clock
The EP7312 contains a 32-bit Real Time Clock (RTC) that can
be written to and read from in the same manner as the timer
counters. It also contains a 32-bit output match register which
can be programmed to generate an interrupt.
• Driven by an external 32.768 kHz crystal oscillator
Table 12 shows the Real-Time Clock pin assignments.
Table 12. Real-Time Clock Pin Assignments
Pin Mnemonic
Table 10 shows the Keypad Interface Pin Assignments.
Table 10. Keypad Interface Pin Assignments
Pin Mnemonic
I/O
COL[7:0]
Pin Description
RTCIN
Real-Time Clock Oscillator Input
RTCOUT
Real-Time Clock Oscillator Output
VDDRTC
Real-Time Clock Oscillator Power
VSSRTC
Real-Time Clock Oscillator Ground
Pin Description
Keyboard scanner column
drive
O
Interrupt Controller
PLL and Clocking
The EP7312 processor and peripheral clocks have these
features:
•
When unexpected events arise during the execution of a
program (i.e., interrupt or memory fault) an exception is
usually generated. When these exceptions occur at the same
time, a fixed priority system determines the order in which
they are handled. The EP7312 interrupt controller has two
interrupt types: interrupt request (IRQ) and fast interrupt
request (FIQ). The interrupt controller has the ability to control
interrupts from 22 different FIQ and IRQ sources. The
Interrupt controller has these features:
•
Supports 22 interrupts from a variety of sources (such as
UARTs, SSI1, and key matrix.)
• Routes interrupt sources to the ARM720T’s IRQ or FIQ
(Fast IRQ) inputs
• Five dedicated off-chip interrupt lines operate as level
sensitive interrupts
Table 11 shows the interrupt controller pin assignments.
Processor and peripheral clocks operate from a single
3.6864 MHz crystal or external 13 MHz clock
• Programmable clock speeds allow the peripheral bus to run
at 18 MHz when the processor is set to 18 MHz and at
36 MHz when the processor is set to 36, 49 or 74 MHz, and
at 45 MHz when the processor is set to 90 MHz.
Table 13 shows the PLL and clocking pin assignments.
Table 13. PLL and Clocking Pin Assignments
Pin Mnemonic
Pin Description
MOSCIN
Main Oscillator Input
MOSCOUT
Main Oscillator Output
VDDOSC
Main Oscillator Power
VSSOSC
Main Oscillator Ground
.
Table 11. Interrupt Controller Pin Assignments
Pin Mnemonic
I/O
Pin Description
nEINT[2:1]
I
External interrupt
EINT[3]
I
External interrupt
nEXTFIQ
I
External Fast Interrupt input
I
Media change interrupt input
nMEDCHG/nBROM
Note:
DS508F2
(Note)
Pins are multiplexed. See Table 19 on page 11 for
more information.
Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
9
EP7312
High-Performance, Low-Power System on Chip
DC-to-DC Converter Interface (PWM)
Table 16. Hardware Debug Interface Pin Assignments
•
Provides two 96 kHz clock outputs with programmable
duty ratio (from 1-in-16 to 15-in-16) that can be used to
drive a positive or negative DC to DC converter
Table 14 shows the DC-to-DC Converter Interface pin
assignments.
Pin Mnemonic
I/O
Pin Description
TCLK
I
JTAG clock
TDI
I
JTAG data input
TDO
O
JTAG data output
nTRST
I
JTAG async reset input
TMS
I
JTAG mode select
Table 14. DC-to-DC Converter Interface Pin Assignments
Pin Mnemonic
DRIVE[1:0]
I/O
I/O
FB[1:0]
I
Pin Description
PWM drive output
LED Flasher
PWM feedback input
A dedicated LED flasher module can be used to generate a low
frequency signal on Port D pin 0 for the purpose of blinking an
LED without CPU intervention. The LED flasher feature is
ideal as a visual annunciator in battery powered applications,
such as a voice mail indicator on a portable phone or an
appointment reminder on a PDA. Table 17 shows the LED
Flasher pin assignments.
Timers
•
•
Internal (RTC) timer
Two internal 16-bit programmable hardware count-down
timers
General Purpose Input/Output (GPIO)
•
•
•
•
• Three 8-bit and one 3-bit GPIO ports
• Supports scanning keyboard matrix
Table 15 shows the GPIO pin assignments.
Software adjustable flash period and duty cycle
Operates from 32 kHz RTC clock
Will continue to flash in IDLE and STANDBY states
4 mA drive current
Table 17. LED Flasher Pin Assignments
Table 15. General Purpose Input/Output Pin Assignments
Pin Mnemonic
I/O
Pin Description
PA[7:0]
I/O
GPIO port A
PB[7:0]
I/O
GPIO port B
I/O
GPIO port D
I/O
GPIO port D
(Note)
I/O
GPIO port D
PE[1:0]/BOOTSEL[1:0] (Note)
I/O
GPIO port E
PE[2]/CLKSEL
I/O
GPIO port E
Pin Mnemonic
PD[0]/LEDFLSH
Note:
PD[0]/LEDFLSH
(Note)
PD[5:1]
PD[7:6]/SDQM[1:0]
(Note)
(Note)
I/O
O
Pin Description
LED flasher driver
Pins are multiplexed. See Table 19 on page 11 for
more information.
Internal Boot ROM
The internal 128-byte Boot ROM facilitates download of saved
code to the on-board SRAM/FLASH.
Packaging
Note:
Pins are multiplexed. See Table 19 on page 11 for
more information.
The EP7312 is available in a 208-pin LQFP package, 256-ball
PBGA package, or a 204-ball TFBGA package.
Hardware Debug Interface
• Full JTAG boundary scan and Embedded ICE support
Table 16 shows the Hardware Debug Interface pin
assignments.
10
Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
DS508F2
EP7312
High-Performance, Low-Power System on Chip
Pin Multiplexing
Table 18 shows the pin multiplexing of the DAI, SSI2 and the
CODEC. The selection between SSI2 and the CODEC is
controlled by the state of the SERSEL bit in SYSCON2. The
choice between the SSI2, CODEC, and the DAI is controlled
by the DAISEL bit in SYSCON3 (see the EP7312 User’s
Manual for more information).
Table 18. DAI/SSI2/CODEC Pin Multiplexing
Pin
Mnemonic
I/O
DAI
SSI2
CODEC
SSICLK
I/O
SCLK
SSICLK
PCMCLK
SSITXDA
O
SDOUT
SSITXDA
PCMOUT
SSIRXDA
I
SDIN
SSIRXDA
PCMIN
SSITXFR
I/O
LRCK
SSITXFR
PCMSYNC
SSIRXFR
I
MCLKIN
SSIRXFR
p/u
BUZ
O
MCLKOUT
DS508F2
Table 19 shows the pins that have been multiplexed in the
EP7312.
Table 19. Pin Multiplexing
Signal
Block
Signal
Block
nMOE
Static Memory
nSDCAS
SDRAM
nMWE
Static Memory
nSDWE
SDRAM
WRITE
Static Memory
nSDRAS
SDRAM
A[27:15]
Static Memory
DRA[0:12]
SDRAM
A[14:13]
Static Memory
DRA[13:14]
SDRAM
PD[7:6]
GPIO
SDQM[1:0]
SDRAM
RUN
System
Configuration
CLKEN
System
Configuration
nMEDCHG
Interrupt
Controller
nBROM
Boot ROM
select
PD[0]
GPIO
LEDFLSH
LED Flasher
PE[1:0]
GPIO
BOOTSEL[1:0]
System
Configuration
PE[2]
GPIO
CLKSEL
System
Configuration
Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
11
EP7312
High-Performance, Low-Power System on Chip
System Design
As shown in system block diagram, simply adding desired
memory and peripherals to the highly integrated EP7312
CRYSTAL
MOSCIN
CRYSTAL
RTCIN
completes a low-power system solution. All necessary
interface logic is integrated on-chip.
DD[0-3]
CL1
CL2
FRM
M
LCD
COL[0-7]
KEYBOARD
D[0-31]
PA[0-7]
A[0-27]
PB[0-7]
nMOE
WRITE
PD[0-7]
SDRAS/
SDCAS
16
SDRAM
16
SDRAM
16
SDRAM
6
SDRAM
SDCS[0]
SDQM[0-3]
EP7312
PE[0-2]
nPOR
nPWRFL
BATOK
nEXTPWR
nBATCHG
RUN
WAKEUP
SDQM[0-3]
nCS[0]
nCS[1]
BATTERY
DRIVE[0-1]
DC-TO-DC
CONVERTERS
16
FLASH
16
FLASH
SSICLK
SSITXFR
SSITXDA
SSIRXDA
SSIRXFR
16
FLASH
6
FLASH
LEDDRV
PHDIN
IR LED AND
PHOTODIODE
RXD[[1/2]
TXD[1/2]
DSR
CTS
DCD
2RS-232
TRANSCEIVERS
ADCCLK
nADCCS
ADCOUT
ADCIN
SMPCLK
ADC
CS[n]
WORD
EXTERNAL MEMORYMAPPED EXPANSION
BUFFERS
nCS[2]
nCS[3]
BUFFERS
AND
LATCHES
DC
INPUT
SDCS[1]
FB[0-1]
ADDITIONAL I/O
POWER
SUPPLY UNIT
AND
COMPARATORS
LEDFLSH
CODEC/SSI2/
DAI
DIGITIZER
Figure 1. A Fully-Configured EP7312-Based System
Note:
12
A system can only use one of the following peripheral interfaces at any given time: SSI2,CODEC or DAI.
Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
DS508F2
EP7312
High-Performance, Low-Power System on Chip
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
DC Core, PLL, and RTC Supply Voltage
2.9 V
DC I/O Supply Voltage (Pad Ring)
3.6 V
DC Pad Input Current
10 mA/pin; 100 mA cumulative
Storage Temperature, No Power
–40C to +125C
Recommended Operating Conditions
DC core, PLL, and RTC Supply Voltage
2.5 V  0.2 V
DC I/O Supply Voltage (Pad Ring)
2.3 V - 3.5 V
DC Input / Output Voltage
O–I/O supply voltage
Operating Temperature
Extended -20C to +70C; Commercial 0C to +70C;
Industrial -40C to +85C
DC Characteristics
All characteristics are specified at VDDCORE = 2.5 V, VDDIO = 3.3 V and VSS = 0 V over an operating temperature of 0°C to +70°C
for all frequencies of operation. The current consumption figures have test conditions specified per parameter.”
Symbol
Parameter
Min
Typ
Max
Unit
Conditions
VIH
CMOS input high voltage
0.65 VDDIO
-
VDDIO + 0.3
V
VDDIO = 2.5 V
VIL
CMOS input low voltage
VSS  0.3
-
0.25 VDDIO
V
VDDIO = 2.5 V
VT+
Schmitt trigger positive going
threshold
-
-
2.1
V
VT-
Schmitt trigger negative going
threshold
0.8
-
-
V
Vhst
Schmitt trigger hysteresis
0.1
-
0.4
V
VIL to VIH
VDD – 0.2
2.5
2.5
-
-
V
V
V
IOH = 0.1 mA
IOH = 4 mA
IOH = 12 mA
Output drive 2a
-
-
0.3
0.5
0.5
V
V
V
IOL = –0.1 mA
IOL = –4 mA
IOL = –12 mA
Input leakage current
-
-
1.0
µA
VIN = VDD or GND
currentb c
25
-
100
µA
VOUT = VDD or GND
CIN
Input capacitance
8
-
10.0
pF
COUT
Output capacitance
8
-
10.0
pF
CMOS output high voltagea
VOH
Output drive 1a
Output drive 2a
CMOS output low voltagea
VOL
IIN
IOZ
DS508F2
Output drive 1a
Bidirectional 3-state leakage
Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
13
EP7312
High-Performance, Low-Power System on Chip
Symbol
CI/O
Parameter
Transceiver capacitance
IDDSTANDBY
@ 25 C
IDDSTANDBY
@ 70 C
IDDSTANDBY
@ 85 C
Standby current consumption1
Core, Osc, RTC @2.5 V
I/O @ 3.3 V
Standby current consumption1
Core, Osc, RTC @2.5 V
I/O @ 3.3 V
Typ
Max
Unit
8
-
10.0
pF
-
77
41
-
-
-
570
111
Core, Osc, RTC @2.5 V
I/O @ 3.3 V
Idle current consumption1
Core, Osc, RTC @2.5 V
I/O @ 3.3 V
IDDIDLE
at 90 MHz
Idle current consumption1
Core, Osc, RTC @2.5 V
I/O @ 3.3 V
VDDSTANDBY Standby supply voltage
-
-
-
1693
163
6
10
-
Conditions
µA
Only nPOR, nPWRFAIL,
nURESET, PE0, PE1, and RTS
are driven, while all other float,
VIH = VDD ± 0.1 V,
VIL = GND ± 0.1 V
µA
Only nPOR, nPWRFAIL,
nURESET, PE0, PE1, and RTS
are driven, while all other float,
VIH = VDD ± 0.1 V,
VIL = GND ± 0.1 V
µA
Only nPOR, nPWRFAIL,
nURESET, PE0, PE1, and RTS
are driven, while all other float,
VIH = VDD ± 0.1 V,
VIL = GND ± 0.1 V
mA
Both oscillators running, CPU
static, Cache enabled, LCD
disabled, VIH = VDD ± 0.1 V, VIL
= GND ± 0.1 V
Standby current consumption1
IDDidle
at 74 MHz
-
7
11
-
mA
Both oscillators running, CPU
static, Cache enabled, LCD
disabled, VIH = VDD ± 0.1 V, VIL
= GND ± 0.1 V
2.0
-
-
V
Minimum standby voltage for
state retention, internal SRAM
cache, and RTC operation only
a.
Refer to the strength column in the pin assignment tables for all package types.
b.
Assumes buffer has no pull-up or pull-down resistors.
c.
The leakage value given assumes that the pin is configured as an input pin but is not currently being driven.
Note:
14
Min
1) Total power consumption = IDDCORE x 2.5 V + IDDIO x 3.3 V
2) A typical design will provide 3.3 V to the I/O supply (i.e., VDDIO), and 2.5 V to the remaining logic. This is to allow the I/O to be
compatible with 3.3 V powered external logic (i.e., 3.3 V SDRAMs).
2) Pull-up current = 50 µA typical at VDD = 3.3 V.
Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
DS508F2
EP7312
High-Performance, Low-Power System on Chip
Timings
Timing Diagram Conventions
This data sheet contains timing diagrams. The following key explains the components used in these diagrams. Any variations are
clearly labelled when they occur. Therefore, no additional meaning should be attached unless specifically stated.
C lo c k
H ig h t o L o w
H ig h / L o w
to H ig h
B u s C h a n g e
B u s V a lid
U n d e f in e d / I n v a lid
V a lid B u s t o T r is t a t e
B u s / S ig n a l O m is s io n
Figure 2. Legend for Timing Diagrams
Timing Conditions
Unless specified otherwise, the following conditions are true for all timing measurements. All characteristics are specified at
VDDIO = 3.1 - 3.5 V and VSS = 0 V over an operating temperature of -40C to +85C. Pin loadings is 50 pF. The timing values are
referenced to 1/2 VDD.
DS508F2
Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
15
EP7312
High-Performance, Low-Power System on Chip
SDRAM Interface
Figure 3 through Figure 6 define the timings associated with all phases of the SDRAM. The following table contains the values for
the timings of each of the SDRAM modes.
Parameter
Symbol
Min
Typ
Max
Unit
SDCLK falling edge to SDCS assert delay time
tCSa
0
2
4
ns
SDCLK falling edge to SDCS deassert delay time
tCSd
3
2
10
ns
SDCLK falling edge to SDRAS assert delay time
tRAa
1
3
7
ns
SDCLK falling edge to SDRAS deassert delay time
tRAd
3
1
10
ns
SDCLK falling edge to SDRAS invalid delay time
tRAnv
2
4
7
ns
SDCLK falling edge to SDCAS assert delay time
tCAa
2
2
5
ns
SDCLK falling edge to SDCAS deassert delay time
tCAd
5
0
3
ns
SDCLK falling edge to ADDR transition time
tADv
3
1
5
ns
SDCLK falling edge to ADDR invalid delay time
tADx
2
2
5
ns
SDCLK falling edge to SDMWE assert delay time
tMWa
3
1
5
ns
SDCLK falling edge to SDMWE deassert delay time
tMWd
4
0
4
ns
DATA transition to SDCLK falling edge time
tDAs
2
-
-
ns
SDCLK falling edge to DATA transition hold time
tDAh
1
-
-
ns
SDCLK falling edge to DATA transition delay time
tDAd
0
-
15
ns
16
Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
DS508F2
EP7312
High-Performance, Low-Power System on Chip
SDRAM Load Mode Register Cycle
SDCLK
tCSa
tCSd
tRAa
tRAd
tCAa
tCAd
SDCS
SDRAS
SDCAS
tADv
tADx
ADDR
DATA
SDQM
SDMWE
tMWa
tMWd
Figure 3. SDRAM Load Mode Register Cycle Timing Measurement
Note:
DS508F2
1. Timings are shown with CAS latency = 2
2. The SDCLK signal may be phase shifted relative to the rest of the SDRAM control and data signals due to uneven loading.
Designers should take care to ensure that delays between SDRAM control and data signals are approximately equal
Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
17
EP7312
High-Performance, Low-Power System on Chip
SDRAM Burst Read Cycle
SDCLK
tCSa
SDCS
tCSa
tCSd
tCSd
tRAa
SDRAS
tRAnv
tRAd
tCAa
tCAd
SDCAS
tADv
ADDR
tADv
ADRAS
ADCAS
tDAs
DATA
tDAs
D1
tDAh
tDAs
D2
tDAh
tDAs
D3
tDAh
D4
tDAh
SDQM
[0:3]
SDMWE
Figure 4. SDRAM Burst Read Cycle Timing Measurement
Note:
18
1. Timings are shown with CAS latency = 2
2. The SDCLK signal may be phase shifted relative to the rest of the SDRAM control and data signals due to uneven loading.
Designers should take care to ensure that delays between SDRAM control and data signals are approximately equal.
Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
DS508F2
EP7312
High-Performance, Low-Power System on Chip
SDRAM Burst Write Cycle
SDCLK
tCSa
tCSa
tCSd
SDCS
tCSd
tRAa
tRAd
SDRAS
tCAa
tCAd
SDCAS
tADv
tADv
ADCAS
ADRAS
ADDR
tDAd
tDAd
D1
DATA
SDQM
tDAd
tDAd
D2
D3
D4
0
tMWa
tMWd
SDMWE
Figure 5. SDRAM Burst Write Cycle Timing Measurement
Note:
DS508F2
1. Timings are shown with CAS latency = 2
2. The SDCLK signal may be phase shifted relative to the rest of the SDRAM control and data signals due to uneven loading.
Designers should take care to ensure that delays between SDRAM control and data signals are approximately equal
Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
19
EP7312
High-Performance, Low-Power System on Chip
SDRAM Refresh Cycle
SDCLK
tCSa
tCSd
tRAa
tRAd
SDCS
SDRAS
tCAd
SDCAS
tCAa
SDATA
ADDR
SDQM
[3:0]
SDMWE
Figure 6. SDRAM Refresh Cycle Timing Measurement
Note:
20
1. Timings are shown with CAS latency = 2
2. The SDCLK signal may be phase shifted relative to the rest of the SDRAM control and data signals due to uneven loading.
Designers should take care to ensure that delays between SDRAM control and data signals are approximately equal
Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
DS508F2
EP7312
High-Performance, Low-Power System on Chip
Static Memory
Figure 7 through Figure 10 define the timings associated with all phases of the Static Memory. The following table contains the
values for the timings of each of the Static Memory modes.
Parameter
Symbol
Min
Typ
Max
Unit
EXPCLK rising edge to nCS assert delay time
tCSd
2
8
20
ns
EXPCLK falling edge to nCS deassert hold time
tCSh
2
7
20
ns
EXPCLK rising edge to A assert delay time
tAd
4
9
16
ns
EXPCLK falling edge to A deassert hold time
tAh
3
10
19
ns
EXPCLK rising edge to nMWE assert delay time
tMWd
3
6
10
ns
EXPCLK rising edge to nMWE deassert hold time
tMWh
3
6
10
ns
EXPCLK falling edge to nMOE assert delay time
tMOEd
3
7
10
ns
EXPCLK falling edge to nMOE deassert hold time
tMOEh
2
7
10
ns
EXPCLK falling edge to HALFWORD deassert delay time
tHWd
2
8
20
ns
EXPCLK falling edge to WORD assert delay time
tWDd
2
8
16
ns
EXPCLK rising edge to data valid delay time
tDv
8
13
21
ns
EXPCLK falling edge to data invalid delay time
tDnv
6
15
30
ns
Data setup to EXPCLK falling edge time
tDs
-
-
1
ns
EXPCLK falling edge to data hold time
tDh
-
-
3
ns
EXPCLK rising edge to WRITE assert delay time
tWRd
5
11
23
ns
EXPREADY setup to EXPCLK falling edge time
tEXs
-
-
0
ns
EXPCLK falling edge to EXPREADY hold time
tEXh
-
-
0
ns
DS508F2
Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
21
EP7312
High-Performance, Low-Power System on Chip
Static Memory Single Read Cycle
EXPCLK
tCSd
tCSh
nCS
tAd
A
nMWE
tMOEd
tMOEh
nMOE
tHWd
HALFWORD
tWDd
WORD
tDs
tDh
D
tEXs
tEXh
EXPRDY
tWRd
WRITE
Figure 7. Static Memory Single Read Cycle Timing Measurement
Note:
22
1. The cycle time can be extended by integer multiples of the clock period (22 ns at 45 MHz, 27 ns at 36 MHz, 54 ns at
18.432 MHz, and 77 ns at 13 MHz), by either driving EXPRDY low and/or by programming a number of wait states. EXPRDY is
sampled on the falling edge of EXPCLK before the data transfer. If low at this point, the transfer is delayed by one clock period
where EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity.
2. Address, Halfword, Word, and Write hold state until next cycle.
Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
DS508F2
EP7312
High-Performance, Low-Power System on Chip
Static Memory Single Write Cycle
EXPCLK
tCSd
tCSh
nCS
tAd
A
tMWd
tMWh
nMWE
nMOE
tHWd
HALFWORD
tWDd
WORD
tDv
D
tEXs
tEXh
EXPRDY
WRITE
Figure 8. Static Memory Single Write Cycle Timing Measurement
Note:
DS508F2
1. The cycle time can be extended by integer multiples of the clock period (22 ns at 45 MHz, 27 ns at 36 MHz, 54 ns at
18.432 MHz, and 77 ns at 13 MHz), by either driving EXPRDY low and/or by programming a number of wait states. EXPRDY is
sampled on the falling edge of EXPCLK before the data transfer. If low at this point, the transfer is delayed by one clock period
where EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity.
2. Zero wait states for sequential writes is not permitted for memory devices which use nMWE pin, as this cannot be driven with
valid timing under zero wait state conditions.
3. Address, Data, Halfword, Word, and Write hold state until next cycle.
Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
23
EP7312
High-Performance, Low-Power System on Chip
Static Memory Burst Read Cycle
EXPCLK
tCSd
tCSh
nCS
tAd
tAh
tAh
tAh
A
nMWE
tMOEd
tMOEh
nMOE
tHWd
HALF
WORD
tWDd
WORD
tDs tDh
tDs tDh
tDs
tDh
tDs
tDh
D
tEXs
tEXh
EXPRDY
tWRd
WRITE
Figure 9. Static Memory Burst Read Cycle Timing Measurement
Note: 1. Four cycles are shown in the above diagram (minimum wait states, 1-0-0-0). This is the maximum number of consecutive
cycles that can be driven. The number of consecutive cycles can be programmed from 2 to 4, inclusively.
2. The cycle time can be extended by integer multiples of the clock period (22 ns at 45 MHz, 27 ns at 36 MHz, 54 ns at
18.432 MHz, and 77 ns at 13 MHz), by either driving EXPRDY low and/or by programming a number of wait states. EXPRDY is
sampled on the falling edge of EXPCLK before the data transfer. If low at this point, the transfer is delayed by one clock period
where EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity.
3. Consecutive reads with sequential access enabled are identical except that the sequential access wait state field is used to
determine the number of wait states, and no idle cycles are inserted between successive non-sequential ROM/expansion
cycles. This improves performance so the SQAEN bit should always be set where possible.
4. Address, Halfword, Word, and Write hold state until next cycle.
24
Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
DS508F2
EP7312
High-Performance, Low-Power System on Chip
Static Memory Burst Write Cycle
EXPCLK
tCSd
tCSh
nCS
tAh
tAd
tAh
tAh
A
tMWd
tMWd
tMWd
tMWh
nMWE
tMWd
tMWh
tMWh
tMWh
nMOE
tHWd
HALF
WORD
WORD
tWDd
tDv
tDnv
tDv
tDnv
tDv
tDnv
tDv
D
tEXs
tEXh
EXPRDY
WRITE
Figure 10. Static Memory Burst Write Cycle Timing Measurement
Note:
DS508F2
1. Four cycles are shown in the above diagram (minimum wait states, 1-1-1-1). This is the maximum number of consecutive
cycles that can be driven. The number of consecutive cycles can be programmed from 2 to 4, inclusively.
2. The cycle time can be extended by integer multiples of the clock period (22 ns at 45 MHz, 27 ns at 36 MHz, 54 ns at
18.432 MHz, and 77 ns at 13 MHz), by either driving EXPRDY low and/or by programming a number of wait states. EXPRDY is
sampled on the falling edge of EXPCLK before the data transfer. If low at this point, the transfer is delayed by one clock period
where EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity.
3. Zero wait states for sequential writes is not permitted for memory devices which use nMWE pin, as this cannot be driven with
valid timing under zero wait state conditions.
4. Address, Data, Halfword, Word, and Write hold state until next cycle.
Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
25
EP7312
High-Performance, Low-Power System on Chip
SSI1 Interface
Parameter
Symbol
Min
Max
Unit
ADCCLK falling edge to nADCCSS deassert delay time
tCd
9
10
ms
ADCIN data setup to ADCCLK rising edge time
tINs
-
15
ns
ADCIN data hold from ADCCLK rising edge time
tINh
-
14
ns
ADCCLK falling edge to data valid delay time
tOvd
7
13
ns
ADCCLK falling edge to data invalid delay time
tOd
2
3
ns
ADC
CLK
tCd
nADC
CSS
tINs
tINh
ADCIN
tOvd
tOd
ADC
OUT
Figure 11. SSI1 Interface Timing Measurement
26
Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
DS508F2
EP7312
High-Performance, Low-Power System on Chip
SSI2 Interface
Parameter
Symbol
Min
Max
Unit
SSICLK period (slave mode)
tclk_per
185
2050
ns
SSICLK high time
tclk_high
925
1025
ns
SSICLK low time
tclk_low
925
1025
ns
SSICLK rise/fall time
tclkrf
3
18
ns
SSICLK rising edge to RX and/or TX frame sync high time
tFRd
-
3
ns
SSICLK rising edge to RX and/or TX frame sync low time
tFRa
-
8
ns
tFR_per
960
990
ns
SSIRXDA setup to SSICLK falling edge time
tRXs
3
7
ns
SSIRXDA hold from SSICLK falling edge time
tRXh
3
7
ns
SSICLK rising edge to SSITXDA data valid delay time
tTXd
-
2
ns
SSITXDA valid time
tTXv
960
990
ns
SSIRXFR and/or SSITXFR period
tclk_per
tclk_high
tclk_low
SSI
CLK
tclkrf
tFRd
tFRa
tFR_per
SSIRXFR/
SSITXFR
tRXh
tRXs
SSI
RXDA
D7
D2
D1
D0
D7
D2
D1
D0
tTXd
SSI
TXDA
tTXv
Figure 12. SSI2 Interface Timing Measurement
DS508F2
Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
27
EP7312
High-Performance, Low-Power System on Chip
LCD Interface
Parameter
Symbol
Min
Max
Unit
CL[2] falling to CL[1] rising delay time
tCL1d
 10
25
ns
CL[1] falling to CL[2] rising delay time
tCL2d
80
3,475
ns
CL[1] falling to FRM transition time
tFRMd
300
10,425
ns
CL[1] falling to M transition time
tMd
 10
20
ns
CL[2] rising to DD (display data) transition time
tDDd
 10
20
ns
CL[2]
tCL2d
tCL1d
CL[1]
tFRMd
FRM
tMd
M
tDDd
DD [3:0]
Figure 13. LCD Controller Timing Measurement
28
Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
DS508F2
EP7312
High-Performance, Low-Power System on Chip
JTAG Interface
Parameter
Symbol
Min
Max
Units
TCK clock period
tclk_per
2
-
ns
TCK clock high time
tclk_high
1
-
ns
TCK clock low time
tclk_low
1
-
ns
JTAG port setup time
tJPs
-
0
ns
JTAG port hold time
tJPh
-
3
ns
JTAG port clock to output
tJPco
-
10
ns
JTAG port high impedance to valid output
tJPzx
-
12
ns
JTAG port valid output to high impedance
tJPxz
-
19
ns
tclk_per
tclk_high
tclk_low
TCK
tJPs
tJPh
TMS
TDI
tJPzx
tJPco
tJPxz
TDO
Figure 14. JTAG Timing Measurement
DS508F2
Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
29
EP7312
High-Performance, Low-Power System on Chip
Packages
208-Pin LQFP Package Characteristics
29.60 (1.165)
30.40 (1.197)
27.80 (1.094)
28.20 (1.110)
0.17 (0.007)
0.27 (0.011)
27.80 (1.094)
28.20 (1.110)
EP7312
29.60 (1.165)
30.40 (1.197)
208-Pin LQFP
0.50
(0.0197)
BSC
Pin 1 Indicator
Pin 208
Pin 1
1.35 (0.053)
1.45 (0.057)
0.45 (0.018)
0.75 (0.030)
1.00 (0.039) BSC
0 MIN
7 MAX
0.09 (0.004)
0.20 (0.008)
0.05 (0.002)
0.15 (0.006)
1.40 (0.055)
1.60 (0.063)
Figure 15. 208-Pin LQFP Package Outline Drawing
Note:
30
1) Dimensions are in millimeters (inches), and controlling dimension is millimeter.
2) Drawing above does not reflect exact package pin count.
3) Before beginning any new design with this device, please contact Cirrus Logic for the latest package information.
4) For pin locations, please see Figure 16. For pin descriptions see the EP7312 User’s Manual.
Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
DS508F2
EP7312
High-Performance, Low-Power System on Chip
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
nURESET
nMEDCHG/nBROM
nPOR
BATOK
nEXTPWR
nBATCHG
D[7]
VSSIO
A[7]
D[8]
A[8]
D[9]
A[9]
D[10]
A[10]
D[11]
VSSIO
VDDIO
A[11]
D[12]
A[12]
D[13]
A[13]\DRA[14]
D[14]
A[14]/DRA[13]
D[15]
A[15]/DRA[12]
D[16]
A[16]/DRA[11]
D[17]
A[17]/DRA[10]
nTRST
VSSIO
VDDIO
D[18]
A[18/DRA[9]
D[19]
A[19]/DRA[8]
D[20]
A[20]/DRA[7]
VSSIO
D[21]
A[21]/DRA[6]
D[22]
A[22]/DRA[5]
D[23]
A[23]/DRA[4]
D[24]
VSSIO
VDDIO
A[24]/DRA[3]
HALFWORD
208-Pin LQFP Pin Diagram
EP7312
208-Pin LQFP
(Top View)
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
D[25]
A[25]/DRA[2]
D[26]
A[26]/DRA[1]
D[27]
A[27]/DRA[0]
VSSIO
D[28]
D[29]
D[30]
D[31]
BUZ
COL[0]
COL[1]
TCLK
VDDIO
COL[2]
COL[3]
COL[4]
COL[5]
COL[6]
COL[7]
FB[0]
VSSIO
FB[1]
SMPCLK
ADCOUT
ADCCLK
DRIVE[0]
DRIVE[1]
VDDIO
VSSIO
VDDCORE
VSSCORE
nADCCS
ADCIN
SSIRXFR
SSIRXDA
SSITXDA
SSITXFR
VSSIO
SSICLK
PD[0]/LEDFLSH
PD[1]
PD[2]
PD[3]
TMS
VDDIO
PD[4]
PD[5]
PD[6]/SDQM[0]
PD[7]/SDQM[1]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
nCS[5]
VDDIO
VSSIO
EXPCLK
WORD
WRITE/nSDRAS
RUN/CLKEN
EXPRDY
TXD[2]
RXD[2]
TDI
VSSIO
PB[7]
PB[6]
PB[5]
PB[4]
PB[3]
PB[2]
PB[1]
PB[0]
VDDIO
TDO
PA[7]
PA[6]
PA[5]
PA[4]
PA[3]
PA[2]
PA[1]
PA[0]
LEDDRV
TXD[1]
VSSIO
PHDIN
CTS
RXD[1]
DCD
DSR
nTEST[1]
nTEST[0]
EINT[3]
nEINT[2]
nEINT[1]
nEXTFIQ
PE[2]/CLKSEL
PE[1]BOOTSEL[1]
PE[0]BOOTSEL[0]
VSSRTC
RTCOUT
RTCIN
VDDRTC
N/C
VDDOSC
MOSCIN
MOSCOUT
VSSOSC
WAKEUP
nPWRFL
A[6]
D[6]
A[5]
D[5]
VDDIO
VSSIO
A[4]
D[4]
A[3]
D[3]
A[2]
VSSIO
D[2]
A[1]
D[1]
A[0]
D[0]
VSSCORE
VDDCORE
VSSIO
VDDIO
CL[2]
CL[1]
FRM
M
DD[3]
DD[2]
VSSIO
DD[1]
DD[0]
nSDCS[1]
nSDCS[0]
SDQM[3]
SDQM[2]
VDDIO
VSSIO
SDCKE
SDCLK
nMWE/nSDWE
nMOE/nSDCAS
VSSIO
nCS[0]
nCS[1]
nCS[2]
nCS[3]
nCS[4]
Figure 16. 208-Pin LQFP (Low Profile Quad Flat Pack) Pin Diagram
Note:
DS508F2
1. N/C should not be grounded but left as no connects.
Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
31
EP7312
High-Performance, Low-Power System on Chip
208-Pin LQFP Numeric Pin Listing
Table 20. 208-Pin LQFP Numeric Pin Listing
32
Pin
No.
Signal
Reset
State
Type
Description
1
nCS[5]
Low
O
Chip select 5
2
3
VDDIO
Pad Pwr
Digital I/O power, 3.3 V
VSSIO
Pad Gnd
4
EXPCLK
1
I/O ground
I
Expansion clock input
5
WORD
1
Low
O
Word access select output
6
WRITE/nSDRAS
1
Low
O
Transfer direction / SDRAM
RAS signal output
7
RUN/CLKEN
1
Low
O
Run output / clock enable
output
8
EXPRDY
1
I
Expansion port ready input
9
TXD[2]
1
High
O
UART 2 transmit data output
10
RXD[2]
11
TDI
12
VSSIO
†
Strength
1
with p/u*
13
PB[7]
1
Input
14
PB[6]
1
Input
15
PB[5]
1
Input
16
PB[4]
1
Input
17
PB[3]
1
Input
18
PB[2]
1
Input
19
PB[1]
1
Input
20
PB[0]
1
Input
21
VDDIO
I
UART 2 receive data input
I
JTAG data input
Pad Gnd
I/O ground
‡
I/O
GPIO port B
‡
I/O
GPIO port B
‡
I/O
GPIO port B
‡
I/O
GPIO port B
‡
I/O
GPIO port B
‡
I/O
GPIO port B
‡
I/O
GPIO port B
‡
I/O
GPIO port B
Pad Pwr
Digital I/O power, 3.3 V
‡
O
JTAG data out
‡
I/O
GPIO port A
‡
I/O
GPIO port A
‡
I/O
GPIO port A
‡
I/O
GPIO port A
‡
I/O
GPIO port A
‡
I/O
GPIO port A
‡
I/O
GPIO port A
‡
I/O
GPIO port A
22
TDO
1
Input
23
PA[7]
1
Input
24
PA[6]
1
Input
25
PA[5]
1
Input
26
PA[4]
1
Input
27
PA[3]
1
Input
28
PA[2]
1
Input
29
PA[1]
1
Input
30
PA[0]
1
Input
31
LEDDRV
1
Low
O
IR LED drive
32
TXD[1]
1
High
O
UART 1 transmit data out
33
VSSIO
1
High
Pad Gnd
I/O ground
34
PHDIN
I
Photodiode input
35
CTS
I
UART 1 clear to send input
36
RXD[1]
I
UART 1 receive data input
37
DCD
I
UART 1 data carrier detect
Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
DS508F2
EP7312
High-Performance, Low-Power System on Chip
Table 20. 208-Pin LQFP Numeric Pin Listing (Continued)
Pin
No.
DS508F2
Signal
†
Strength
Reset
State
Type
Description
38
DSR
I
UART 1 data set ready input
39
nTEST[1]
With p/u*
I
Test mode select input
40
nTEST[0]
With p/u*
I
Test mode select input
41
EINT[3]
I
External interrupt
42
nEINT[2]
I
External interrupt input
43
nEINT[1]
I
External interrupt input
44
nEXTFIQ
I
External fast interrupt input
45
PE[2]/CLKSEL
1
Input
‡
I/O
GPIO port E / clock input
mode select
46
PE[1]/BOOTSEL[1]
1
Input
‡
I/O
GPIO port E / boot mode
select
47
PE[0]/BOOTSEL[0]
1
Input
‡
I/O
GPIO port E / Boot mode
select
48
VSSRTC
RTC Gnd
Real time clock ground
49
RTCOUT
O
Real time clock oscillator
output
50
RTCIN
I
Real time clock oscillator
input
51
VDDRTC
RTC power
Real time clock power, 2.5 V
52
N/C
53
PD[7]/SDQM[1]
1
Low
I/O
GPIO port D / SDRAM byte
lane mask
54
PD[6]/SDQM[0]
1
Low
I/O
GPIO port D / SDRAM byte
lane mask
55
PD[5]
1
Low
I/O
GPIO port D
56
PD[4]
1
Low
57
VDDIO
I/O
GPIO port D
Pad Pwr
Digital I/O power, 3.3 V
58
TMS
with p/u*
I
JTAG mode select
59
PD[3]
1
Low
I/O
GPIO port D
60
PD[2]
1
Low
I/O
GPIO port D
61
PD[1]
1
Low
I/O
GPIO port D
I/O
GPIO port D / LED blinker
output
I/O
DAI/CODEC/SSI2 serial clock
62
PD[0]/LEDFLSH
1
Low
63
SSICLK
1
Input
‡
64
VSSIO
Pad Gnd
I/O ground
65
SSITXFR
1
Low
I/O
DAI/CODEC/SSI2 serial clock
66
SSITXDA
1
Low
O
DAI/CODEC/SSI2 serial data
output
67
SSIRXDA
I
DAI/CODEC/SSI2 serial data
input
68
SSIRXFR
I/O
DAI/CODEC/SSI2 frame sync
69
ADCIN
70
nADCCS
71
Input
‡
I
SSI1 ADC serial input
O
SSI1 ADC chip select
VSSCORE
Core ground
Core ground
72
VDDCORE
Core Pwr
Core power, 2.5 V
73
VSSIO
Pad Gnd
I/O ground
74
VDDIO
Pad Pwr
Digital I/O power, 3.3 V
75
DRIVE[1]
2
High /
Low
I/O
PWM drive output
76
DRIVE[0]
2
High /
Low
I/O
PWM drive output
77
ADCCLK
1
Low
O
SSI1 ADC serial clock
78
ADCOUT
1
Low
O
SSI1 ADC serial data output
1
High
Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
33
EP7312
High-Performance, Low-Power System on Chip
Table 20. 208-Pin LQFP Numeric Pin Listing (Continued)
Pin
No.
Signal
79
SMPCLK
80
FB[1]
81
82
Type
Description
Low
O
SSI1 ADC sample clock
I
PWM feedback input
VSSIO
Pad Gnd
I/O ground
FB[0]
I
PWM feedback input
1
83
COL[7]
1
High
O
Keyboard scanner column
drive
84
COL[6]
1
High
O
Keyboard scanner column
drive
85
COL[5]
1
High
O
Keyboard scanner column
drive
86
COL[4]
1
High
O
Keyboard scanner column
drive
87
COL[3]
1
High
O
Keyboard scanner column
drive
88
COL[2]
1
High
O
Keyboard scanner column
drive
89
VDDIO
Pad Pwr
Digital I/O power, 3.3 V
90
TCLK
I
JTAG clock
91
COL[1]
1
High
O
Keyboard scanner column
drive
92
COL[0]
1
High
O
Keyboard scanner column
drive
93
BUZ
1
Low
O
Buzzer drive output
94
D[31]
1
Low
I/O
Data I/O
95
D[30]
1
Low
I/O
Data I/O
96
D[29]
1
Low
I/O
Data I/O
97
D[28]
1
Low
I/O
Data I/O
98
VSSIO
Pad Gnd
I/O ground
System byte address /
SDRAM address
99
A[27]/DRA[0]
2
Low
O
100
D[27]
1
Low
I/O
Data I/O
System byte address /
SDRAM address
101
A[26]/DRA[1]
2
Low
O
102
D[26]
1
Low
I/O
Data I/O
103
A[25]/DRA[2]
2
Low
O
System byte address /
SDRAM address
104
D[25]
1
Low
I/O
Data I/O
105
HALFWORD
1
Low
O
Halfword access select output
106
A[24]/DRA[3]
1
Low
O
System byte address /
SDRAM address
107
VDDIO
—
Pad Pwr
Digital I/O power, 3.3 V
108
VSSIO
—
Pad Gnd
I/O ground
109
D[24]
1
Low
I/O
Data I/O
110
A[23]/DRA[4]
1
Low
O
System byte address /
SDRAM address
111
D[23]
1
Low
I/O
Data I/O
System byte address /
SDRAM address
112
A[22]/DRA[5]
1
Low
O
113
D[22]
1
Low
I/O
Data I/O
O
System byte address /
SDRAM address
114
34
Reset
State
†
Strength
A[21]/DRA[6]
1
Low
115
D[21]
1
Low
116
VSSIO
117
A[20]/DRA[7]
1
Low
I/O
Data I/O
Pad Gnd
I/O ground
O
System byte address /
SDRAM address
Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
DS508F2
EP7312
High-Performance, Low-Power System on Chip
Table 20. 208-Pin LQFP Numeric Pin Listing (Continued)
DS508F2
Pin
No.
Signal
118
D[20]
†
Strength
1
Reset
State
Type
Low
I/O
Data I/O
System byte address /
SDRAM address
Description
119
A[19]/DRA[8]
1
Low
O
120
D[19]
1
Low
I/O
Data I/O
121
A[18]/DRA[9]
1
Low
O
System byte address /
SDRAM address
122
D[18]
1
Low
I/O
Data I/O
123
VDDIO
Pad Pwr
Digital I/O power, 3.3 V
124
VSSIO
Pad Gnd
I/O ground
125
nTRST
I
JTAG async reset input
126
A[17]/DRA[10]
1
Low
O
System byte address /
SDRAM address
127
D[17]
1
Low
I/O
Data I/O
128
A[16]/DRA[11]
1
Low
O
System byte address /
SDRAM address
129
D[16]
1
Low
I/O
Data I/O
System byte address /
SDRAM address
130
A[15]/DRA[12]
1
Low
O
131
D[15]
1
Low
I/O
Data I/O
System byte address /
SDRAM address
132
A[14]/DRA[13]
1
Low
O
133
D[14]
1
Low
I/O
Data I/O
134
A[13]/DRA[14]
1
Low
O
System byte address /
SDRAM address
135
D[13]
1
Low
I/O
Data I/O
System byte address
136
A[12]
1
Low
O
137
D[12]
1
Low
I/O
Data I/O
138
A[11]
1
Low
O
System byte address
139
VDDIO
Pad Pwr
Digital I/O power, 3.3 V
140
VSSIO
Pad Gnd
I/O ground
141
D[11]
1
Low
I/O
Data I/O
142
A[10]
1
Low
O
System byte address
143
D[10]
1
Low
I/O
Data I/O
System byte address
144
A[9]
1
Low
O
145
D[9]
1
Low
I/O
Data I/O
146
A[8]
1
Low
O
System byte address
147
D[8]
1
Low
I/O
Data I/O
148
A[7]
1
Low
O
System byte address
149
VSSIO
Pad Gnd
I/O ground
150
D[7]
151
1
Low
I/O
Data I/O
nBATCHG
I
Battery changed sense input
152
nEXTPWR
I
External power supply sense
input
153
BATOK
154
nPOR
155
nMEDCHG/nBROM
156
nURESET
157
VDDOSC
Schmitt
Schmitt
I
Battery OK input
I
Power-on reset input
I
Media change interrupt input /
internal ROM boot enable
I
User reset input
Oscillator Power
Oscillator power in, 2.5 V
158
MOSCIN
I
Main oscillator input
159
MOSCOUT
O
Main oscillator output
160
VSSOSC
Oscillator Ground
Oscillator Ground
Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
35
EP7312
High-Performance, Low-Power System on Chip
Table 20. 208-Pin LQFP Numeric Pin Listing (Continued)
Pin
No.
Signal
161
WAKEUP
162
nPWRFL
163
A[6]
1
Low
164
D[6]
1
Low
I/O
Data I/O
165
A[5]
1
Low
Out
System byte address
166
D[5]
1
Low
167
VDDIO
168
VSSIO
Pad Gnd
I/O ground
169
A[4]
1
Low
O
System byte address
170
D[4]
1
Low
I/O
Data I/O
171
A[3]
2
Low
O
System byte address
172
D[3]
1
Low
I/O
Data I/O
173
A[2]
2
Low
O
System byte address
174
VSSIO
Pad Gnd
I/O ground
175
D[2]
1
Low
I/O
Data I/O
System byte address
Reset
State
Type
Schmitt
Description
I
System wake up input
I
Power fail sense input
O
System byte address
I/O
Data I/O
Pad Pwr
Digital I/O power, 3.3 V
176
A[1]
2
Low
O
177
D[1]
1
Low
I/O
Data I/O
178
A[0]
2
Low
O
System byte address
179
D[0]
1
Low
I/O
Data I/O
180
VSSCORE
Core ground
Core ground
181
VDDCORE
Core Pwr
Core power, 2.5 V
182
VSSIO
Pad ground
I/O ground
183
VDDIO
Pad Power
Digital I/O power, 3.3 V
184
CL[2]
1
Low
O
LCD pixel clock out
185
CL[1]
1
Low
O
LCD line clock
O
LCD frame synchronization
pulse
186
36
†
Strength
FRM
1
Low
187
M
1
Low
O
LCD AC bias drive
188
DD[3]
1
Low
I/O
LCD serial display data
189
DD[2]
1
Low
I/O
LCD serial display data
190
VSSIO
191
DD[1]
1
192
DD[0]
193
194
Pad Gnd
I/O ground
Low
I/O
LCD serial display data
1
Low
I/O
LCD serial display data
nSDCS[1]
1
High
O
SDRAM chip select 1
nSDCS[0]
1
High
O
SDRAM chip select 0
195
SDQM[3]
2
Low
I/O
SDRAM byte lane mask
196
SDQM[2]
2
Low
I/O
SDRAM byte lane mask
197
VDDIO
Pad Pwr
Digital I/O power, 3.3 V
198
VSSIO
Pad Gnd
I/O ground
199
SDCKE
2
Low
I/O
SDRAM clock enable output
200
SDCLK
2
Low
I/O
SDRAM clock out
201
nMWE/nSDWE
1
High
O
ROM, expansion write
enable/ SDRAM write enable
control signal
202
nMOE/nSDCAS
1
High
O
ROM, expansion OP
enable/SDRAM CAS control
signal
203
VSSIO
Pad Gnd
I/O ground
204
nCS[0]
1
High
O
Chip select 0
205
nCS[1]
1
High
O
Chip select 1
Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
DS508F2
EP7312
High-Performance, Low-Power System on Chip
Table 20. 208-Pin LQFP Numeric Pin Listing (Continued)
Pin
No.
Signal
206
nCS[2]
207
nCS[3]
208
nCS[4]
Reset
State
Type
Description
1
High
O
Chip select 2
1
High
O
Chip select 3
1
High
O
Chip select 4
†
Strength
*
“With p/u” means with internal pull-up of 100 KOhms on the pin.
†
Strength 1 = 4 ma
Strength 2 = 12 ma
‡
Input. Port A,B,D,E GPIOs default to input at nPOR and URESET conditions.
DS508F2
Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
37
EP7312
High-Performance, Low-Power System on Chip
256-Ball PBGA Package Characteristics
0.85 (0.034)
±0.05 (.002)
17.00 (0.669)
±0.20 (.008)
Pin 1 Corner
D1
0.40 (0.016)
±0.05 (.002)
15.00 (0.590)
±0.20 (.008)
30° TYP
Pin 1 Indicator
17.00 (0.669)
±0.20 (.008)
E1
15.00 (0.590)
±0.20 (.008)
2 Layer
0.36 (0.014)
±0.09 (0.004)
TOP VIEW
SIDE VIEW
D
17.00 (0.669)
Pin 1 Corner
1.00 (0.040)
1.00 (0.040)
REF
E
16 15 14 13 12 11 10 9 8 7
6 5
1.00 (0.040)
REF
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
1.00 (0.040)
0.50
R
3 Places
4 3 2
17.00 (0.669)
BOTTOM VIEW
JEDEC #: MO-151
Ball Diameter: 0.50 mm ± 0.10 mm
17 ¥ 17 ¥ 1.61 mm body
Figure 17. 256-Ball PBGA Package
Note:
38
1) For pin locations see Table 21.
2) Dimensions are in millimeters (inches), and controlling dimension is millimeter
3) Before beginning any new EP7312 design, contact Cirrus Logic for the latest package information.
Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
DS508F2
EP7312
High-Performance, Low-Power System on Chip
256-Ball PBGA Pinout (Top View)
1
2
3
4
5
6
7
8
9
10
11
12
13
A
VDDIO
nCS[4]
nCS[1]
SDCLK
SDQM[3]
DD[1]
M
VDDIO
D[0]
D[2]
A[3]
VDDIO
A[6]
B
nCS[5]
VDDIO
nCS[3]
nMOE/
nSDCAS
VDDIO
nSDCS[1]
DD[2]
CL[1]
VDDCORE
D[1]
A[2]
A[4]
A[5]
WAKEUP
VDDIO
nURESET B
C
VDDIO
EXPCLK
VSSIO
VDDIO
VSSIO
VSSIO
VSSIO
VDDIO
VSSIO
VSSIO
VSSIO
VDDIO
VSSIO
VSSIO
nPOR
nEXTPWR C
D
WRITE/
nSDRAS
EXPRDY
VSSIO
VDDIO
nCS[2]
nMWE/
nSDWE
nSDCS[0]
CL[2]
VSSRTC
D[4]
nPWRFL
MOSCIN
VDDIO
VSSIO
D[7]
D[8]
D
E
RXD[2]
PB[7]
TDI
WORD
VSSIO
nCS[0]
SDQM[2]
FRM
A[0]
D[5]
VSSOSC
VSSIO
nMEDCHG/
nBROM
VDDIO
D[9]
D[10]
E
F
PB[5]
PB[3]
VSSIO
TXD[2]
RUN/
CLKEN
VSSIO
SDCKE
DD[3]
A[1]
D[6]
VSSRTC
BATOK
nBATCHG
VSSIO
D[11]
VDDIO
F
G
PB[1]
VDDIO
TDO
PB[4]
PB[6]
VSSCore
VSSRTC
DD[0]
D[3]
VSSRTC
A[7]
A[8]
A[9]
VSSIO
D[12]
D[13]
G
H
PA[7]
PA[5]
VSSIO
PA[4]
PA[6]
PB[0]
PB[2]
VSSRTC
VSSRTC
A[10]
A[11]
A[12]
A[13]/
DRA[14]
VSSIO
D[14]
D[15]
H
J
PA[3]
PA[1]
VSSIO
PA[2]
PA[0]
TXD[1]
CTS
VSSRTC
VSSRTC
A[17]/
DRA[10]
A[16]/
DRA[11]
A[15]/
DRA[12]
A[14]/
DRA[13]
nTRST
D[16]
D[17]
J
PHDIN
VSSIO
DCD
nTEST[1]
EINT[3]
VSSRTC
ADCIN
COL[4]
TCLK
D[20]
D[19]
D[18]
VSSIO
VDDIO
VDDIO
K
DSR
VDDIO
nEINT[1]
PE[2]/
CLKSEL
VSSRTC
PD[0]/
LEDFLSH
VSSRTC
COL[6]
D[31]
VSSRTC
A[22]/
DRA[5]
A[21]/
DRA[6]
VSSIO
A[18]/
DRA[9]
A[19]/
DRA[8]
L
M nTEST[0]
nEINT[2]
VDDIO
PE[0]/
BOOTSEL[0]
TMS
VDDIO
SSITXFR
DRIVE[1]
FB[0]
COL[0]
D[27]
VSSIO
A[23]/
DRA[4]
VDDIO
A[20]/
DRA[7]
D[21]
M
N nEXTFIQ
PE[1]/
BOOTSEL[1]
VSSIO
VDDIO
PD[5]
PD[2]
SSIRXDA
ADCCLK
SMPCLK
COL[2]
D[29]
D[26]
HALFWORD
VSSIO
D[22]
D[23]
N
K LEDDRV
L
RXD[1]
14
15
MOSCOUT VDDOSC
16
VSSIO
A
P
VSSRTC
RTCOUT
VSSIO
VSSIO
VDDIO
VSSIO
VSSIO
VDDIO
VSSIO
VDDIO
VSSIO
VSSIO
VDDIO
VSSIO
D[24]
VDDIO
P
R
RTCIN
VDDIO
PD[4]
PD[1]
SSITXDA
nADCCS
VDDIO
ADCOUT
COL[7]
COL[3]
COL[1]
D[30]
A[27]/
DRA[0]
A[25]/
DRA[2]
VDDIO
A[24]\
DRA[3]
R
PD[7]/
SDQM[1]
PD[6]/
SDQM[0]
PD[3]
SSICLK
FB[1]
COL[5]
VDDIO
BUZ
D[28]
A[26]/
DRA[1]
D[25]
VSSIO
T
T VDDRTC
DS508F2
SSIRXFR VDDCORE DRIVE[0]
Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
39
EP7312
High-Performance, Low-Power System on Chip
256-Ball PBGA Ball Listing
The list is ordered by ball location.
Table 21. 256-Ball PBGA Ball Listing
†
Reset
State
Ball Location
Name
A1
VDDIO
A2
nCS[4]
1
High
O
Chip select 4
A3
nCS[1]
1
High
O
Chip select 1
A4
SDCLK
2
Low
O
SDRAM clock out
A5
SDQM[3]
2
Low
O
SDRAM byte lane mask
A6
DD[1]
1
Low
O
LCD serial display data
A7
M
1
Low
O
LCD AC bias drive
A8
VDDIO
A9
D[0]
1
Low
I/O
Data I/O
A10
D[2]
1
Low
I/O
Data I/O
A11
A[3]
2
Low
O
System byte address
A12
VDDIO
A13
A[6]
A14
MOSCOUT
O
A15
VDDOSC
Oscillator power
A16
VSSIO
B1
nCS[5]
B2
VDDIO
B3
40
Strength
Type
Pad power
Pad power
1
Low
Description
Digital I/O power, 3.3 V
Digital I/O power, 3.3 V
Pad power
Digital I/O power, 3.3V
O
System byte address
Pad ground
O
Main oscillator out
Oscillator power in, 2.5 V
I/O ground
1
Low
nCS[3]
1
High
B4
nMOE/nSDCAS
1
High
B5
VDDIO
B6
nSDCS[1]
1
High
O
SDRAM chip select 1
B7
DD[2]
1
Low
O
LCD serial display data
B8
CL[1]
1
Low
B9
VDDCORE
B10
D[1]
1
Low
I/O
B11
A[2]
2
Low
O
System byte address
B12
A[4]
1
Low
O
System byte address
B13
A[5]
1
Low
O
System byte address
B14
WAKEUP
Schmitt
I
System wake up input
B15
VDDIO
B16
nURESET
C1
VDDIO
C2
EXPCLK
C3
VSSIO
Pad ground
C4
VDDIO
Pad power
Digital I/O power, 3.3 V
C5
VSSIO
Pad ground
I/O ground
C6
VSSIO
Pad ground
I/O ground
C7
VSSIO
Pad ground
I/O ground
C8
VDDIO
Pad power
Digital I/O power, 3.3 V
C9
VSSIO
Pad ground
I/O ground
C10
VSSIO
Pad ground
I/O ground
C11
VSSIO
Pad ground
I/O ground
C12
VDDIO
Pad power
Digital I/O power, 3.3 V
C13
VSSIO
Pad ground
I/O ground
Pad power
O
O
Pad power
O
Core power
Pad power
Schmitt
1
I
Chip select 5
Digital I/O power, 3.3 V
Chip select 3
ROM, expansion OP enable/SDRAM CAS control signal
Digital I/O power, 3.3 V
LCD line clock
Digital core power, 2.5V
Data I/O
Digital I/O power, 3.3 V
User reset input
Pad power
Digital I/O power, 3.3V
I
Expansion clock input
I/O ground
Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
DS508F2
EP7312
High-Performance, Low-Power System on Chip
Table 21. 256-Ball PBGA Ball Listing (Continued)
†
Reset
State
Ball Location
Name
C14
VSSIO
C15
nPOR
C16
nEXTPWR
D1
WRITE/nSDRAS
1
D2
EXPRDY
1
D3
VSSIO
Pad ground
I/O ground
D4
VDDIO
Pad power
Digital I/O power, 3.3V
Strength
Type
Pad ground
Schmitt
Low
Description
I/O ground
I
Power-on reset input
I
External power supply sense input
O
Transfer direction / SDRAM RAS signal output
I
Expansion port ready input
D5
nCS[2]
1
High
O
Chip select 2
D6
nMWE/nSDWE
1
High
O
ROM, expansion write enable/ SDRAM write enable control signal
D7
nSDCS[0]
1
High
O
SDRAM chip select 2
D8
CL[2]
1
Low
O
LCD pixel clock out
1
Low
D9
VSSRTC
D10
D[4]
D11
nPWRFL
I
Power fail sense input
D12
MOSCIN
I
Main oscillator input
D13
VDDIO
Pad power
Digital I/O power, 3.3V
D14
VSSIO
Pad ground
I/O ground
D15
D[7]
1
Low
I/O
Data I/O
D16
D[8]
1
Low
I/O
Data I/O
E1
RXD[2]
I
UART 2 receive data input
PB[7]
1
‡
Input
I
GPIO port B
E3
TDI
with p/u*
I
JTAG data input
E4
WORD
1
Low
O
E5
VSSIO
E6
nCS[0]
E7
SDQM[2]
2
Low
O
SDRAM byte lane mask
E8
FRM
1
Low
O
LCD frame synchronization pulse
E2
Core ground
I/O
Pad ground
1
High
O
Real time clock ground
Data I/O
Word access select output
I/O ground
Chip select 0
E9
A[0]
2
Low
O
System byte address
E10
D[5]
1
Low
I/O
Data I/O
E11
VSSOSC
Oscillator ground
PLL ground
E12
VSSIO
Pad ground
I/O ground
E13
nMEDCHG/nBROM
I
E14
VDDIO
Pad power
Media change interrupt input / internal ROM boot enable
Digital I/O power, 3.3V
E15
D[9]
1
Low
I/O
Data I/O
E16
D[10]
1
Low
I/O
Data I/O
F1
PB[5]
1
Input
F2
PB[3]
1
Input
‡
I
GPIO port B
‡
I
GPIO port B
F3
VSSIO
F4
TXD[2]
1
High
Pad ground
F5
RUN/CLKEN
1
Low
F6
VSSIO
F7
SDCKE
2
Low
O
SDRAM clock enable output
F8
DD[3]
1
Low
O
LCD serial display data
O
O
Pad ground
I/O ground
UART 2 transmit data output
Run output / clock enable output
I/O ground
F9
A[1]
2
Low
O
System byte address
F10
D[6]
1
Low
I/O
Data I/O
F11
VSSRTC
RTC ground
F12
BATOK
I
DS508F2
Real time clock ground
Battery OK input
Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
41
EP7312
High-Performance, Low-Power System on Chip
Table 21. 256-Ball PBGA Ball Listing (Continued)
†
Reset
State
Ball Location
Name
F13
nBATCHG
I
F14
VSSIO
Pad ground
F15
D[11]
F16
VDDIO
42
Strength
Type
I/O
Description
Battery changed sense input
I/O ground
1
Low
1
‡
Input
‡
O
‡
I
GPIO port B
‡
I
GPIO port B
Pad power
Data I/O
Digital I/O power, 3.3V
G1
PB[1]
G2
VDDIO
G3
TDO
1
Input
G4
PB[4]
1
Input
G5
PB[6]
1
Input
G6
VSSCore
Core ground
Core ground
G7
VSSRTC
RTC ground
Real time clock ground
G8
DD[0]
1
Low
O
LCD serial display data
G9
D[3]
1
Low
I/O
Data I/O
G10
VSSRTC
G11
A[7]
1
Low
O
System byte address
G12
A[8]
1
Low
O
System byte address
G13
A[9]
1
Low
O
System byte address
G14
VSSIO
G15
D[12]
1
Low
I/O
Data I/O
G16
D[13]
1
Low
I/O
Data I/O
H1
PA[7]
1
Input
I/O
GPIO port A
H2
PA[5]
1
Input
H3
VSSIO
H4
PA[4]
1
Input
H5
PA[6]
1
Input
H6
PB[0]
1
Input
H7
PB[2]
1
Input
H8
VSSRTC
RTC ground
Real time clock ground
H9
VSSRTC
RTC ground
Real time clock ground
H10
A[10]
1
Low
O
H11
A[11]
1
Low
O
System byte address
H12
A[12]
1
Low
O
System byte address
H13
A[13]/DRA[14]
1
Low
O
System byte address / SDRAM address
H14
VSSIO
H15
D[14]
1
Low
I/O
Data I/O
H16
D[15]
1
Low
I/O
Data I/O
J1
PA[3]
1
Input
I/O
GPIO port A
J2
PA[1]
1
Input
J3
VSSIO
J4
PA[2]
1
Input
J5
PA[0]
1
Input
J6
TXD[1]
1
High
I
Pad power
RTC ground
Pad ground
‡
‡
I/O
Pad ground
GPIO port B
Digital I/O power, 3.3V
JTAG data out
Real time clock ground
I/O ground
GPIO port A
I/O ground
‡
I/O
GPIO port A
‡
I/O
GPIO port A
‡
I/O
GPIO port B
‡
I/O
GPIO port B
Pad ground
‡
‡
I/O
Pad ground
System byte address
I/O ground
GPIO port A
I/O ground
‡
I/O
GPIO port A
‡
I/O
GPIO port A
O
UART 1 transmit data out
Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
DS508F2
EP7312
High-Performance, Low-Power System on Chip
Table 21. 256-Ball PBGA Ball Listing (Continued)
Ball Location
Name
†
Strength
Reset
State
Type
Description
J7
CTS
I
J8
VSSRTC
RTC ground
Real time clock ground
J9
VSSRTC
RTC ground
Real time clock ground
J10
A[17]/DRA[10]
1
Low
O
J11
A[16]/DRA[11]
1
Low
O
System byte address / SDRAM address
J12
A[15]/DRA[12]
1
Low
O
System byte address / SDRAM address
J13
A[14]/DRA[13]
1
Low
O
System byte address / SDRAM address
J14
nTRST
J15
D[16]
1
Low
I/O
Data I/O
J16
D[17]
1
Low
I/O
Data I/O
K1
LEDDRV
1
Low
O
IR LED drive
K2
PHDIN
I
K3
VSSIO
Pad ground
K4
DCD
K5
nTEST[1]
I
With p/u*
UART 1 clear to send input
System byte address / SDRAM address
JTAG async reset input
Photodiode input
I/O ground
I
UART 1 data carrier detect
I
Test mode select input
K6
EINT[3]
I
K7
VSSRTC
RTC ground
Real time clock ground
K8
ADCIN
K9
COL[4]
K10
TCLK
K11
External interrupt
I
SSI1 ADC serial input
1
High
O
Keyboard scanner column drive
I
JTAG clock
D[20]
1
Low
I/O
Data I/O
K12
D[19]
1
Low
I/O
Data I/O
K13
D[18]
1
Low
I/O
Data I/O
K14
VSSIO
Pad ground
I/O ground
K15
VDDIO
Pad power
Digital I/O power, 3.3V
K16
VDDIO
Pad power
Digital I/O power, 3.3V
L1
RXD[1]
I
UART 1 receive data input
UART 1 data set ready input
L2
DSR
I
L3
VDDIO
Pad power
Digital I/O power, 3.3V
L4
nEINT[1]
I
External interrupt input
L5
PE[2]/CLKSEL
‡
1
Input
1
Low
I/O
RTC ground
GPIO port E / clock input mode select
L6
VSSRTC
L7
PD[0]/LEDFLSH
L8
VSSRTC
L9
COL[6]
1
High
O
Keyboard scanner column drive
L10
D[31]
1
Low
I/O
Data I/O
L11
VSSRTC
L12
A[22]/DRA[5]
1
Low
O
System byte address / SDRAM address
L13
A[21]/DRA[6]
1
Low
O
System byte address / SDRAM address
L14
VSSIO
L15
A[18]/DRA[9]
L16
M1
M2
I/O
Core ground
RTC ground
Pad ground
Real time clock ground
GPIO port D / LED blinker output
Real time clock ground
Real time clock ground
I/O ground
1
Low
O
System byte address / SDRAM address
A[19]/DRA[8]
1
Low
O
System byte address / SDRAM address
nTEST[0]
With p/u*
I
Test mode select input
nEINT[2]
I
External interrupt input
M3
VDDIO
Pad power
Digital I/O power, 3.3V
M4
PE[0]/BOOTSEL[0]
1
M5
TMS
with p/u*
DS508F2
Input
‡
I
GPIO port E / Boot mode select
I
JTAG mode select
Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
43
EP7312
High-Performance, Low-Power System on Chip
Table 21. 256-Ball PBGA Ball Listing (Continued)
Ball Location
44
Name
†
Strength
Reset
State
Type
M6
VDDIO
M7
SSITXFR
1
Low
I/O
DAI/CODEC/SSI2 frame sync
M8
DRIVE[1]
2
High /
Low
I/O
PWM drive output
M9
FB[0]
M10
COL[0]
1
High
O
Keyboard scanner column drive
M11
D[27]
1
Low
I/O
Data I/O
1
Low
M12
VSSIO
M13
A[23]/DRA[4]
Pad power
Description
I
Pad ground
O
Pad power
Digital I/O power, 3.3V
PWM feedback input
I/O ground
System byte address / SDRAM address
M14
VDDIO
M15
A[20]/DRA[7]
1
Low
O
System byte address / SDRAM address
M16
D[21]
1
Low
I/O
Data I/O
N1
nEXTFIQ
N2
PE[1]/BOOTSEL[1]
N3
VSSIO
N4
VDDIO
N5
PD[5]
1
Low
I/O
GPIO port D
N6
PD[2]
1
Low
I/O
GPIO port D
N7
SSIRXDA
I/O
DAI/CODEC/SSI2 serial data input
I
1
Input
‡
I/O
Pad ground
Pad power
Digital I/O power, 3.3V
External fast interrupt input
GPIO port E / boot mode select
I/O ground
Digital I/O power, 3.3V
N8
ADCCLK
1
Low
O
SSI1 ADC serial clock
N9
SMPCLK
1
Low
O
SSI1 ADC sample clock
N10
COL[2]
1
High
O
Keyboard scanner column drive
N11
D[29]
1
Low
I/O
Data I/O
N12
D[26]
1
Low
I/O
Data I/O
N13
HALFWORD
1
Low
O
N14
VSSIO
N15
D[22]
1
Low
N16
D[23]
1
Low
P1
VSSRTC
P2
RTCOUT
O
P3
VSSIO
Pad ground
I/O ground
P4
VSSIO
Pad ground
I/O ground
P5
VDDIO
Pad power
Digital I/O power, 3.3V
P6
VSSIO
Pad ground
I/O ground
P7
VSSIO
Pad ground
I/O ground
P8
VDDIO
Pad power
Digital I/O power, 3.3V
P9
VSSIO
Pad ground
I/O ground
P10
VDDIO
Pad power
Digital I/O power, 3.3V
P11
VSSIO
Pad ground
I/O ground
P12
VSSIO
Pad ground
I/O ground
P13
VDDIO
Pad power
Digital I/O power
P14
VSSIO
Pad ground
I/O ground
P15
D[24]
P16
VDDIO
Pad power
R1
RTCIN
I/O
R2
VDDIO
R3
PD[4]
1
Low
I/O
GPIO port D
R4
PD[1]
1
Low
I/O
GPIO port D
Pad ground
I/O
I/O
RTC ground
1
Low
I/O
Pad power
Halfword access select output
I/O ground
Data I/O
Data I/O
Real time clock ground
Real time clock oscillator output
Data I/O
Digital I/O power, 3.3V
Real time clock oscillator input
Digital I/O power, 3.3V
Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
DS508F2
EP7312
High-Performance, Low-Power System on Chip
Table 21. 256-Ball PBGA Ball Listing (Continued)
Reset
State
†
Ball Location
Name
R5
SSITXDA
1
Low
O
DAI/CODEC/SSI2 serial data output
R6
nADCCS
1
High
O
SSI1 ADC chip select
R7
VDDIO
Pad power
Digital I/O power, 3.3V
R8
ADCOUT
1
Low
O
R9
COL[7]
1
High
O
Keyboard scanner column drive
R10
COL[3]
1
High
O
Keyboard scanner column drive
R11
COL[1]
1
High
O
Keyboard scanner column drive
Strength
Type
Description
SSI1 ADC serial data output
R12
D[30]
1
Low
I/O
Data I/O
R13
A[27]/DRA[0]
2
Low
O
System byte address / SDRAM address
R14
A[25]/DRA[2]
2
Low
O
System byte address / SDRAM address
R15
VDDIO
R16
A[24]/DRA[3]
T1
VDDRTC
T2
PD[7]/SDQM[1]
1
Low
I/O
GPIO port D / SDRAM byte lane mask
T3
PD[6]/SDQM[0]
1
Low
I/O
GPIO port D / SDRAM byte lane mask
T4
PD[3]
1
Low
I/O
GPIO port D
I/O
DAI/CODEC/SSI2 serial clock
‡
I/O
DAI/CODEC/SSI2 frame sync
Pad power
1
Low
T5
SSICLK
1
‡
Input
T6
SSIRXFR
1
Input
T7
VDDCORE
2
High /
Low
T8
DRIVE[0]
T9
FB[1]
O
RTC power
1
High
Digital I/O power, 3.3V
System byte address / SDRAM address
Real time clock power, 2.5V
Core power
Core power, 2.5V
I/O
PWM drive output
I
PWM feedback input
O
Keyboard scanner column drive
T10
COL[5]
T11
VDDIO
T12
BUZ
1
Low
O
Buzzer drive output
T13
D[28]
1
Low
I/O
Data I/O
T14
A[26]/DRA[1]
2
Low
O
System byte address / SDRAM address
T15
D[25]
1
Low
I/O
Data I/O
T16
VSSIO
Pad power
Pad ground
Digital I/O power, 3.3V
I/O ground
*
“With p/u” means with internal pull-up of 100 KOhms on the pin.
†
Strength 1 = 4 ma
Strength 2 = 12 ma
‡Input. Port A,B,D,E GPIOs default to input at nPOR and URESET conditions.
JTAG Boundary Scan Signal Ordering
Table 22. JTAG Boundary Scan Signal Ordering
DS508F2
LQFP
Pin No.
PBGA
Ball
Signal
Type
Position
1
B1
nCS[5]
O
1
4
C2
EXPCLK
I/O
3
5
E4
WORD
O
6
6
D1
WRITE/nSDRAS
O
8
7
F5
RUN/CLKEN
O
10
8
D2
EXPRDY
I
13
Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
45
EP7312
High-Performance, Low-Power System on Chip
Table 22. JTAG Boundary Scan Signal Ordering (Continued)
46
LQFP
Pin No.
PBGA
Ball
Signal
Type
Position
9
F4
TXD2
O
14
10
E1
RXD2
I
16
13
E2
PB[7]
I/O
17
14
G5
PB[6]
I/O
20
15
F1
PB[5]
I/O
23
16
G4
PB[4]
I/O
26
17
F2
PB[3]
I/O
29
18
H7
PB[2]
I/O
32
19
G1
PB[1]
I/O
35
20
H6
PB[0]
I/O
38
23
H1
PA[7]
I/O
41
24
H5
PA[6]
I/O
44
25
H2
PA[5]
I/O
47
26
H4
PA[4]
I/O
50
27
J1
PA[3]
I/O
53
28
J4
PA[2]
I/O
56
29
J2
PA[1]
I/O
59
30
J5
PA[0]
I/O
62
31
K1
LEDDRV
O
65
32
J6
TXD1
O
67
34
K2
PHDIN
I
69
35
J7
CTS
I
70
36
L1
RXD1
I
71
37
K4
DCD
I
72
38
L2
DSR
I
73
39
K5
nTEST1
I
74
40
M1
nTEST0
I
75
41
K6
EINT3
I
76
42
M2
nEINT2
I
77
43
L4
nEINT1
I
78
44
N1
nEXTFIQ
I
79
45
L5
PE[2]/CLKSEL
I/O
80
46
N2
PE[1]/
BOOTSEL[1]
I/O
83
47
M4
PE[0]/BOOTSEL0
I/O
86
53
T2
PD[7]/SDQM[1]
I/O
89
54
T3
PD[6/SDQM[0]]
I/O
92
55
N5
PD[5]
I/O
95
56
R3
PD[4]
I/O
98
59
T4
PD[3]
I/O
101
60
N6
PD[2]
I/O
104
Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
DS508F2
EP7312
High-Performance, Low-Power System on Chip
Table 22. JTAG Boundary Scan Signal Ordering (Continued)
DS508F2
LQFP
Pin No.
PBGA
Ball
Signal
Type
Position
61
R4
PD[1]
I/O
107
62
L7
PD[0]/LEDFLSH
O
110
68
T6
SSIRXFR
I/O
122
69
K8
ADCIN
I
125
70
R6
nADCCS
O
126
75
M8
DRIVE1
I/O
128
76
T8
DRIVE0
I/O
131
77
N8
ADCCLK
O
134
78
R8
ADCOUT
O
136
79
N9
SMPCLK
O
138
80
T9
FB1
I
140
82
M9
FB0
I
141
83
R9
COL7
O
142
84
L9
COL6
O
144
85
T10
COL5
O
146
86
K9
COL4
O
148
87
R10
COL3
O
150
88
N10
COL2
O
152
91
R11
COL1
O
154
92
M10
COL0
O
156
93
T12
BUZ
O
158
94
L10
D[31]
I/O
160
95
R12
D[30]
I/O
163
96
N11
D[29]
I/O
166
97
T13
D[28]
I/O
169
99
R13
A[27]/DRA[0]
Out
172
100
M11
D[27]
I/O
174
101
T14
A[26]/DRA[1]
O
177
102
N12
D[26]
I/O
179
103
R14
A[25]/DRA[2]
O
182
104
T15
D[25]
I/O
184
105
N13
HALFWORD
O
187
106
R16
A[24]/DRA[3]
O
189
109
P15
D[24]
I/O
191
110
M13
A[23]/DRA[4]
O
194
111
N16
D[23]
I/O
196
112
L12
A[22]/DRA[5]
O
199
113
N15
D[22]
I/O
201
114
L13
A[21]/DRA[6]
O
204
115
M16
D[21]
I/O
206
117
M15
A[20]/DRA[7]
O
209
Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
47
EP7312
High-Performance, Low-Power System on Chip
Table 22. JTAG Boundary Scan Signal Ordering (Continued)
48
LQFP
Pin No.
PBGA
Ball
Signal
Type
Position
118
K11
D[20]
I/O
211
119
L16
A[19]/DRA[8]
O
214
120
K12
D[19]
I/O
216
121
L15
A[18]/DRA[9]
O
219
122
K13
D[18]
I/O
221
126
J10
A[17]/DRA[10]
O
224
127
J16
D[17]
I/O
226
128
J11
A[16]/DRA[11]
O
229
129
J15
D[16]
I/O
231
130
J12
A[15]/DRA[12]
O
234
131
H16
D[15]
I/O
236
132
J13
A[14]/DRA[13]
O
239
133
H15
D[14]
I/O
241
134
H13
A[13]/DRA[14]
O
244
135
G16
D[13]
I/O
246
136
H12
A[12]
O
249
137
G15
D[12]
I/O
251
138
H11
A[11]
O
254
141
F15
D[11]
I/O
256
142
H10
A[10]
O
259
143
E16
D[10]
I/O
261
144
G13
A[9]
O
264
145
E15
D[9]
I/O
266
146
G12
A[8]
O
269
147
D16
D[8]
I/O
271
148
G11
A[7]
O
274
150
D15
D[7]
I/O
276
151
F13
nBATCHG
I
279
152
C16
nEXTPWR
I
280
153
F12
BATOK
I
281
154
C15
nPOR
I
282
155
E13
nMEDCHG/nBROM
I
283
156
B16
nURESET
I
284
161
B14
WAKEUP
I
285
162
D11
nPWRFL
I
286
163
A13
A[6]
O
287
164
F10
D[6]
I/O
289
165
B13
A[5]
O
292
166
E10
D[5]
I/O
294
169
B12
A[4]
O
297
170
D10
D[4]
I/O
299
Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
DS508F2
EP7312
High-Performance, Low-Power System on Chip
Table 22. JTAG Boundary Scan Signal Ordering (Continued)
LQFP
Pin No.
PBGA
Ball
Signal
Type
Position
171
A11
A[3]
O
302
172
G9
D[3]
I/O
304
173
B11
A[2]
O
307
175
A10
D[2]
I/O
309
176
F9
A[1]
O
312
177
B10
D[1]
I/O
314
178
E9
A[0]
O
317
179
A9
D[0]
I/O
319
184
D8
CL2
O
322
185
B8
CL1
O
324
186
E8
FRM
O
326
187
A7
M
O
328
188
F8
DD[3]
O
330
189
B7
DD[2]
O
333
191
A6
DD[1]
O
336
192
G8
DD[0]
O
339
193
B6
nSDCS[1]
O
342
194
D7
nSDCS[0]
O
344
195
A5
SDQM[3]
I/O
346
196
E7
SDQM[2]
I/O
349
199
F7
SDCKE
I/O
352
200
A4
SDCLK
I/O
355
201
D6
nMWE/nSDWE
O
358
202
B4
nMOE/nSDCAS
O
360
204
E6
nCS[0]
O
362
205
A3
nCS[1]
O
364
206
D5
nCS[2]
O
366
207
B3
nCS[3]
O
368
208
A2
nCS[4]
O
370
1) See EP7312 Users’ Manual for pin naming / functionality.
2) For each pad, the JTAG connection ordering is input, output, then enable as applicable.
DS508F2
Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
49
EP7312
High-Performance, Low-Power System on Chip
CONVENTIONS
Table 23. Acronyms and Abbreviations (Continued)
Acronym/
Abbreviation
This section presents acronyms, abbreviations, units of
measurement, and conventions used in this data sheet.
Acronyms and Abbreviations
Table 23 lists abbreviations and acronyms used in this data
sheet.
Table 23. Acronyms and Abbreviations
Acronym/
Abbreviation
Definition
TAP
test access port
TLB
translation lookaside buffer
UART
universal asynchronous receiver
Units of Measurement
Table 24. Unit of Measurement
Definition
Symbol
Unit of Measure
A/D
analog-to-digital
ADC
analog-to-digital converter
C
degree Celsius
CODEC
coder / decoder
fs
sample frequency
D/A
digital-to-analog
Hz
hertz (cycle per second)
DMA
direct-memory access
kbps
kilobits per second
EPB
embedded peripheral bus
KB
kilobyte (1,024 bytes)
FCS
frame check sequence
kHz
kilohertz
FIFO
first in / first out
k
kilo Ohm
FIQ
fast interrupt request
Mbps
megabits (1,048,576 bits) per second
GPIO
general purpose I/O
MB
megabyte (1,048,576 bytes)
ICT
in circuit test
MBps
megabytes per second
IR
infrared
MHz
megahertz (1,000 kilohertz)
IRQ
standard interrupt request
A
microampere
IrDA
Infrared Data Association
F
microfarad
JTAG
Joint Test Action Group
W
microwatt
LCD
liquid crystal display
s
microsecond (1,000 nanoseconds)
LED
light-emitting diode
mA
milliampere
LQFP
low profile quad flat pack
mW
milliwatt
LSB
least significant bit
ms
millisecond (1,000 microseconds)
MIPS
millions of instructions per second
ns
nanosecond
MMU
memory management unit
V
volt
MSB
most significant bit
W
watt
PBGA
plastic ball grid array
PCB
printed circuit board
PDA
personal digital assistant
PLL
phase locked loop
p/u
pull-up resistor
RISC
reduced instruction set computer
RTC
Real-Time Clock
SIR
slow (9600–115.2 kbps) infrared
SRAM
static random access memory
SSI
synchronous serial interface
50
Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
DS508F2
EP7312
High-Performance, Low-Power System on Chip
General Conventions
Hexadecimal numbers are presented with all letters in
uppercase and a lowercase “h” appended or with a 0x at the
beginning. For example, 0x14 and 03CAh are hexadecimal
numbers. Binary numbers are enclosed in single quotation
marks when in text (for example, ‘11’ designates a binary
number). Numbers not indicated by an “h”, 0x or quotation
marks are decimal.
Registers are referred to by acronym, with bits listed in
brackets separated by a colon (:) (for example, CODR[7:0]),
and are described in the EP7312 User’s Manual. The use of
“TBD” indicates values that are “to be determined,” “n/a”
designates “not available,” and “n/c” indicates a pin that is a
“no connect.”
Pin Description Conventions
Abbreviations used for signal directions are listed in Table 25.
Table 25. Pin Description Conventions
Abbreviation
Direction
I
Input
O
Output
I/O
Input or Output
DS508F2
Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
51
EP7312
High-Performance, Low-Power System on Chip
Ordering Information
Model
Temperature
EP7312-CBZ
0 to +70 °C
EP7312-IBZ
-40 to +85 °C.
EP7312-CVZ
EP7312-CV-90Z (90 MHz)
EP7312-IVZ
Package
256-pin PBGA, 17mm X 17mm
0 to +70 °C
208-pin LQFP.
-40 to +85 °C.
Environmental, Manufacturing, & Handling Information
Model Number
Peak Reflow Temp
MSL Rating*
Max Floor Life
260 °C
3
7 Days
EP7312-CBZ
EP7312-CVZ
EP7312-CV-90Z (90 MHz)
EP7312-IBZ
EP7312-IVZ
* MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020.
All devices are now lead (Pb) free.
52
Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
DS508F2
EP7312
High-Performance, Low-Power System on Chip
Revision History
Revision
Date
Changes
PP5
JAN 2004
Preliminary release. Updated SDRAM timing.
F1
AUG 2005
Updated ordering information. Added MSL data.
F2
MAR 2011
Removed all lead-containing device ordering information. Removed 204-pin
TFBGA package option.
DS508F2
Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
53
EP7312
High-Performance, Low-Power System on Chip
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find the one nearest to you go to www.cirrus.com
IMPORTANT NOTICE
Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject
to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant
information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale
supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus
for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third
parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights,
copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent
does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
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IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
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Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks
or service marks of their respective owners.
SPI is a trademark of Motorola, Inc.
Microwire is a trademark of National Semiconductor Corporation.
LINUX is a registered trademark of Linus Torvalds.
Microsoft Windows and Microsoft are registered trademarks of Microsoft Corporation.
54
Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
DS508F2