REJ10J1941-0200 SuperH™ Family E10A-USB Emulator Additional Document for User’s Manual Supplementary Information on Using the SH72546RFCC, SH72544R, SH72543R, SH72531FCC, and SH72531 Renesas Microcomputer Development Environment System SuperH™ Family E10A-USB for SH72546RFCC, SH72544R, SH72543R, SH72531FCC, and SH72531 HS7250KCU01HE Rev.2.00 Revision Date: Jun. 08, 2009 Rev. 2.00 Jun. 08, 2009 Page ii of vi REJ10J1941-0200 Notes regarding these materials 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. 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Rev. 2.00 Jun. 08, 2009 Page iii of vi REJ10J1941-0200 Rev. 2.00 Jun. 08, 2009 Page iv of vi REJ10J1941-0200 Contents Section 1 Connecting the Emulator with the User System ..................................1 1.1 1.2 1.3 1.4 1.5 Components of the Emulator ............................................................................................ 1 Connecting the Emulator with the User System ............................................................... 3 Installing the H-UDI Port Connector on the User System ................................................ 4 Pin Assignments of the H-UDI Port Connector ................................................................ 5 Recommended Circuit between the H-UDI Port Connector and the MCU ...................... 9 1.5.1 Recommended Circuit (36-Pin Type) .................................................................... 9 1.5.2 Recommended Circuit (14-Pin Type) .................................................................... 11 1.5.3 Recommended Circuit (38-Pin Type) .................................................................... 13 Section 2 Software Specifications when Using the SH72546RFCC, SH72544R, SH72543R, SH72531FCC, and SH72531 ..............................15 2.1 2.2 Differences between the MCU and the Emulator ............................................................. 15 Specific Functions for the Emulator when Using the SH72546RFCC, SH72544R, SH72543R, SH72531FCC, and SH72531......................................................................... 20 2.2.1 Event Condition Functions..................................................................................... 20 2.2.2 Trace Functions...................................................................................................... 27 2.2.3 Notes on Using the JTAG (H-UDI) Clock (TCK) ................................................. 39 2.2.4 Notes on Setting the [Breakpoint] Dialog Box ...................................................... 39 2.2.5 Notes on Setting the [Event Condition] Dialog Box and the BREAKCONDITION_ SET Command .......................................................... 41 2.2.6 Performance Measurement Function ..................................................................... 41 2.2.7 Emulation RAM Setting Function ......................................................................... 46 Rev. 2.00 Jun. 08, 2009 Page v of vi REJ10J1941-0200 Rev. 2.00 Jun. 08, 2009 Page vi of vi REJ10J1941-0200 Section 1 Connecting the Emulator with the User System Section 1 Connecting the Emulator with the User System 1.1 Components of the Emulator The E10A-USB emulator supports the SH72546RFCC, SH72544R, SH72543R, SH72531FCC, and SH72531. Table 1.1 lists the components of the emulator. Rev. 2.00 Jun. 08, 2009 Page 1 of 46 REJ10J1941-0200 Section 1 Connecting the Emulator with the User System Table 1.1 Components of the Emulator Classification Component Hardware Emulator box Appearance Quantity 1 Remarks HS0005KCU01H: Depth: 65.0 mm, Width: 97.0 mm, Height: 20.0 mm, Mass: 72.9 g or HS0005KCU02H: Depth: 65.0 mm, Width: 97.0 mm, Height: 20.0 mm, Mass: 73.7 g Software User system interface cable 1 14-pin type: Length: 20 cm, Mass: 33.1 g User system interface cable 1 36-pin type: Length: 20 cm, Mass: 49.2 g (only for HS0005KCU02H) USB cable 1 Length: 150 cm, Mass: 50.6 g E10A-USB emulator setup program, TM SuperH Family E10AUSB Emulator User’s Manual, Supplementary Information on Using the SH72546RFCC, SH72544R, SH72543R, SH72531FCC, and SH72531*, and Test program manual for HS0005KCU01H and HS0005KCU02H 1 HS0005KCU01SR, HS0005KCU01HJ, HS0005KCU01HE, HS7250KCU01HJ, HS7250KCU01HE, HS0005TM01HJ, and HS0005TM01HE (provided on a CD-R) Note: Additional document for the MCUs supported by the emulator is included. Check the target MCU and refer to its additional document. Rev. 2.00 Jun. 08, 2009 Page 2 of 46 REJ10J1941-0200 Section 1 Connecting the Emulator with the User System 1.2 Connecting the Emulator with the User System To connect the E10A-USB emulator (hereinafter referred to as the emulator), the H-UDI port connector must be installed on the user system to connect the user system interface cable. When designing the user system, refer to the recommended circuit between the H-UDI port connector and the MCU. In addition, read the E10A-USB emulator user's manual and hardware manual for the related device. Table 1.2 shows the type number of the emulator, the corresponding connector type, and the use of AUD function. Table 1.2 Type Number, AUD Function, and Connector Type Type Number Connector AUD Function HS0005KCU02H 36-pin connector Available HS0005KCU01H, HS0005KCU02H 14-pin connector Not available HS0005KCU02H 38-pin connector Available The H-UDI port connector has the 36-pin, 14-pin, and 38-pin types as described below. Use them according to the purpose of the usage. 1. 36-pin type (with AUD function; compatible with the E200F emulator) The AUD trace function is supported. A large amount of trace information can be acquired in realtime. The window trace function is also supported for acquiring memory access in the specified range (memory access address or memory access data) by tracing. 2. 14-pin type (without AUD function) The AUD trace function cannot be used because only the H-UDI function is supported. Since the 14-pin type connector is smaller than the 36-pin type (1/2.5), the size of the area where the connector is installed on the user system can be reduced. 3. 38-pin type (with AUD function) The AUD trace function is supported. As well as the 36-pin type, a large amount of trace information can be acquired in realtime. Since the 38-pin type connector is smaller than the 36-pin type (1/2.5), the size of the area where the connector is installed on the user system can be reduced. To use the 38-pin type connector, however, an optional cable (HS0005ECK01H) is required. Rev. 2.00 Jun. 08, 2009 Page 3 of 46 REJ10J1941-0200 Section 1 Connecting the Emulator with the User System 1.3 Installing the H-UDI Port Connector on the User System Table 1.3 shows the recommended H-UDI port connectors for the emulator. Table 1.3 Recommended H-UDI Port Connectors Connector Type Number Manufacturer Specifications 36-pin connector DX10M-36S Hirose Electric Co., Ltd. Screw type Lock-pin type DX10M-36SE, DX10G1M-36SE 14-pin connector 2514-6002 Minnesota Mining & Manufacturing Ltd. 14-pin straight type 38-pin connector 2-5767004-2 Tyco Electronics AMP K.K. 38-pin Mictor type Note: When designing the 36-pin connector layout on the user board, do not connect any components under the H-UDI connector. When designing the 14-pin connector layout on the user board, do not place any components within 3 mm of the H-UDI port connector. When designing the 38-pin connector layout on the user board, reduce cross-talk noise etc. by keeping other signal lines out of the region where the H-UDI port connector is situated. As shown in figure 1.1, an upper limit (5 mm) applies to the heights of components mounted around the user system connector. Rev. 2.00 Jun. 08, 2009 Page 4 of 46 REJ10J1941-0200 Section 1 Connecting the Emulator with the User System E10A-USB optional 38-pin user system interface cable 50 mm 1 38 2 20 mm 37 5 mm 2-5767004-2 : Area to be kept free of other components Target system H-UDI port connector (top view) Figure 1.1 Restriction on Component Mounting 1.4 Pin Assignments of the H-UDI Port Connector Figures 1.2 through 1.4 show the pin assignments of the 36-pin, 14-pin, and 38-pin H-UDI port connectors, respectively. Note: Note that the pin number assignments of the H-UDI port connector shown on the following pages differ from those of the connector manufacturer. Rev. 2.00 Jun. 08, 2009 Page 5 of 46 REJ10J1941-0200 Section 1 Connecting the Emulator with the User System SH72546RFCC SH72544R SH72543R Pin No. Pin No. Signal Input/ Output*1 1 AUDCK Output G18 2 GND 3 AUDATA0 Output E18 4 GND 5 AUDATA1 6 GND 7 AUDATA2 8 GND 9 AUDATA3 Output Note E17 Output F18 Pin No. Signal Input/ Output*1 19 TMS Input D15 Input B17 Input A19 Output C16 20 GND 21 TRST# 22 GND 23 TDI 24 GND 25 TDO 26 GND 27 N.C. *2 Output D17 10 GND 28 GND 11 AUDSYNC#*2 Output D18 29 UVCC 30 GND D16 31 RES#*2 32 GND 33 GND *3 34 GND 35 N.C. 36 GND 12 GND 13 AUDRST# *2 14 GND 15 AUDMD 16 GND 17 TCK 18 GND Input Input C17 Input B18 SH72546RFCC SH72544R SH72543R Pin No. Note Output Output B12 User reset Output Notes: 1. Input to or output from the user system. 2. The symbol (#) means that the signal is active-low. 3. The emulator monitors the GND signal of the user system and detects whether or not the user system is connected. H-UDI port connector (top view) Edge of the board (connected to the connector) φ 0.7+0.1 0 36 3 1 9.0 1.905 1.1 4.5 2 φ 2.8+0.1 0 4 (Pin 1 mark) 35 1.27 4.09 M2.6 x 0.45 H-UDI port connector (front view) 4.8 H-UDI port connector (top view) 3.9 37.61 43.51 : Pattern inhibited area 0.3 9.0 21.59 Unit: mm Figure 1.2 Pin Assignments of the H-UDI Port Connector (36 Pins) Rev. 2.00 Jun. 08, 2009 Page 6 of 46 REJ10J1941-0200 Section 1 Connecting the Emulator with the User System Pin No. Input/ Output*1 Signal 1 TCK 2 TRST# 3 TDO 4 N.C. 5 TMS 6 TDI 7 RES# 8 N.C. 9 GND 11 UVCC 10, 12, GND *2 *2 SH72546RFCC SH72544R SH72543R Pin No. SH7253 Pin No. Input B18 87 Input B17 89 Output C16 83 Input D15 85 Input A19 84 Output B12 107 Note User reset Output and 13 14 GND *3 Output Notes: 1. Input to or output from the user system. 2. The symbol (#) means that the signal is active-low. 3. The emulator monitors the GND signal of the user system and detects whether or not the user system is connected. Pin 1 mark H-UDI port connector (top view) 25.0 23.0 6 x 2.54 = 15.24 (2.54) H-UDI port connector (top view) Pin 8 Pin 1 Pin 14 Pin 7 0.45 Pin 1 mark Unit: mm Figure 1.3 Pin Assignments of the H-UDI Port Connector (14 Pins) Rev. 2.00 Jun. 08, 2009 Page 7 of 46 REJ10J1941-0200 Section 1 Connecting the Emulator with the User System Pin No. Signal SH72546RFCC SH72544R SH72543R Note Pin No. Input/ Output*1 Pin No. Signal 1 N.C. 20 N.C. 2 N.C. 21 TRST# *2 3 N.C. 22 N.C. 4 N.C. 23 N.C. 5 UCON# (GND) *3 24 AUDATA3 6 AUDCK 25 N.C. 7 N.C. 26 AUDATA2 8 N.C. 27 N.C. 9 RES# *2 10 N.C. 11 TDO Output 12 UVCC_AUD Output 13 Output G18 Output B12 User reset 28 AUDATA1 29 AUDATA0 31 N.C. N.C. 32 AUDSYNC# 14 UVCC Output 33 N.C. 15 TCK Input 16 N.C. 17 TMS 18 N.C. 19 TDI B18 Input D15 A19 Input Input B17 Output D17 Output F18 Output E17 Output E18 Output D18 Input D16 Input C17 N.C. 30 C16 Input/ Output*1 SH72546RFCC SH72544R SH72543R Note Pin No. 34 AUDRST# 35 N.C. 36 AUDMD 37 N.C. 38 N.C. Notes: 1. Input to or output from the user system. 2. The symbol (#) means that the signal is active-low. 3. The emulator monitors the GND signal of the user system and detects whether or not the user system is connected. 4. The GND bus lead at the center of the H-UDI port connector must be grounded. 37 1 6.91 38 2 Unit: mm 25.4 H-UDI port connector (top view) Figure 1.4 Pin Assignments of the H-UDI Port Connector (38 Pins) Rev. 2.00 Jun. 08, 2009 Page 8 of 46 REJ10J1941-0200 Section 1 Connecting the Emulator with the User System 1.5 1.5.1 Recommended Circuit between the H-UDI Port Connector and the MCU Recommended Circuit (36-Pin Type) Figure 1.5 shows a recommended circuit for connection between the H-UDI and AUD port connectors (36 pins) and the MCU when the emulator is in use. Notes: 1. Do not connect anything to the N.C. pins of the H-UDI port connector. 2. The ASEMD pin must be 1 when the emulator is connected and 0 when the emulator is not connected, respectively. (1) When the emulator is used: ASEMD = 1 (2) When the emulator is not used: ASEMD = 0 Figure 1.5 shows an example of circuits that allow the ASEMD pin to be changed by switches, etc. 3. When a network resistance is used for pull-up, it may be affected by a noise. Separate TCK from other resistances. 4. The pattern between the H-UDI port connector and the MCU must be as short as possible. Do not connect the signal lines to other components on the board. 5. The AUD signals (AUDCK, AUDATA3 to AUDATA0, and AUDSYNC#) operate in high speed. Isometric connection is needed if possible. Do not separate connection nor connect other signal lines adjacently. 6. Since the H-UDI and the AUD of the MCU operate with the Vcc, supply only the Vcc to the UVCC pin. Make the emulator’s switch settings so that the user power will be supplied (SW2 = 1 and SW3 = 1). 7. The resistance value shown in figure 1.5 is for reference. 8. For the AUDCK pin, guard the pattern between the H-UDI port connector and the MCU at GND level. 9. The TRST# pin must be at the low level for a certain period when the power is supplied whether the H-UDI is used or not. 10. For the pin processing in cases where the emulator is not used, refer to the hardware manual of the related MCU. Rev. 2.00 Jun. 08, 2009 Page 9 of 46 REJ10J1941-0200 Section 1 Connecting the Emulator with the User System When the circuit is connected as shown in figure 1.5, the switches of the emulator are set as SW2 TM = 1 and SW3 = 1. For details, refer to section 3.8, Setting the DIP Switches, in the SuperH Family E10A-USB Emulator User’s Manual. Vcc = 3.3-V power supply All pulled-up at 4.7 kΩ or more Vcc Vcc Vcc H-UDI port connector (36-pin type) 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 GND GND AUDCK AUDATA0 GND AUDATA1 GND AUDATA2 GND AUDATA3 GND GND AUDSYNC AUDRST GND AUDMD GND TCK GND GND TMS TRST GND TDI GND TDO GND N.C. GND UVCC GND RES GND GND GND N.C. Target MCU 1 AUDCK 3 AUDATA0 5 AUDATA1 7 AUDATA2 9 AUDATA3 11 AUDSYNC 13 AUDRST 15 AUDMD 17 TCK 19 TMS 21 TRST 23 TDI 25 TDO 27 29 31 RES 33 35 1 kΩ ASEMD Reset signal User system Figure 1.5 Recommended Circuit for Connection between the H-UDI Port Connector and MCU when the Emulator is in Use (36-Pin Type) Rev. 2.00 Jun. 08, 2009 Page 10 of 46 REJ10J1941-0200 Section 1 Connecting the Emulator with the User System 1.5.2 Recommended Circuit (14-Pin Type) Figure 1.6 shows a recommended circuit for connection between the H-UDI port connector (14 pins) and the MCU when the emulator is in use. Notes: 1. Do not connect anything to the N.C. pins of the H-UDI port connector. 2. The ASEMD pin must be 1 when the emulator is connected and 0 when the emulator is not connected, respectively. (1) When the emulator is used: ASEMD = 1 (2) When the emulator is not used: ASEMD = 0 Figure 1.6 shows an example of circuits that allow the ASEMD pin to be changed by switches, etc. 3. When a network resistance is used for pull-up, it may be affected by a noise. Separate TCK from other resistances. 4. The pattern between the H-UDI port connector and the MCU must be as short as possible. Do not connect the signal lines to other components on the board. 5. Since the H-UDI of the MCU operates with the Vcc, supply only the Vcc to the UVCC pin. Make the emulator’s switch settings so that the user power will be supplied (SW2 = 1 and SW3 = 1). 6. The resistance value shown in figure 1.6 is for reference. 7. The TRST# pin must be at the low level for a certain period when the power is supplied whether the H-UDI is used or not. 8. For the pin processing in cases where the emulator is not used, refer to the hardware manual of the related MCU. Rev. 2.00 Jun. 08, 2009 Page 11 of 46 REJ10J1941-0200 Section 1 Connecting the Emulator with the User System When the circuit is connected as shown in figure 1.6, the switches of the emulator are set as SW2 TM = 1 and SW3 = 1. For details, refer to section 3.8, Setting the DIP Switches, in the SuperH Family E10A-USB Emulator User’s Manual. Vcc = 3.3-V power supply All pulled-up at 4.7 kΩ or more Vcc Vcc Vcc Vcc Vcc H-UDI port connector (14-pin type) TCK 9 GND TRST 10 GND TDO N.C. 12 13 GND TMS GND TDI 14 GND RES N.C. Target MCU 1 TCK 2 TRST 3 TDO 4 5 TMS 6 TDI 7 RES 8 11 1 kΩ UVCC Reset signal ASEMD User system Figure 1.6 Recommended Circuit for Connection between the H-UDI Port Connector and MCU when the Emulator is in Use (14-Pin Type) Rev. 2.00 Jun. 08, 2009 Page 12 of 46 REJ10J1941-0200 Section 1 Connecting the Emulator with the User System 1.5.3 Recommended Circuit (38-Pin Type) Figure 1.7 shows a recommended circuit for connection between the H-UDI and AUD port connectors (38 pins) and the MCU when the emulator is in use. Notes: 1. Do not connect anything to the N.C. pins of the H-UDI port connector. 2. The ASEMD pin must be 1 when the emulator is connected and 0 when the emulator is not connected, respectively. (1) When the emulator is used: ASEMD = 1 (2) When the emulator is not used: ASEMD = 0 Figure 1.7 shows an example of circuits that allow the ASEMD pin to be changed by switches, etc. 3. When a network resistance is used for pull-up, it may be affected by a noise. Separate TCK from other resistances. 4. The pattern between the H-UDI port connector and the MCU must be as short as possible. Do not connect the signal lines to other components on the board. 5. The AUD signals (AUDCK, AUDATA3 to AUDATA0, and AUDSYNC#) operate in high speed. Isometric connection is needed if possible. Do not separate connection nor connect other signal lines adjacently. 6. Since the H-UDI and the AUD of the MCU operate with the Vcc, supply only the Vcc to the UVCC pin. Make the emulator’s switch settings so that the user power will be supplied (SW2 = 1 and SW3 = 1). 7. The resistance value shown in figure 1.7 is for reference. 8. For the AUDCK pin, guard the pattern between the H-UDI port connector and the MCU at GND level. 9. The TRST# pin must be at the low level for a certain period when the power is supplied whether the H-UDI is used or not. 10. The GND bus lead at the center of the H-UDI port connector must be grounded. 11. For the pin processing in cases where the emulator is not used, refer to the hardware manual of the related MCU. Rev. 2.00 Jun. 08, 2009 Page 13 of 46 REJ10J1941-0200 Section 1 Connecting the Emulator with the User System When the circuit is connected as shown in figure 1.7, the switches of the emulator are set as SW2 TM = 1 and SW3 = 1. For details, refer to section 3.8, Setting the DIP Switches, in the SuperH Family E10A-USB Emulator User’s Manual. Vcc = 3.3-V power supply All pulled-up at 4.7 kΩ or more VCC VCC VCC H-UDI port connector (38-pin type) AUDCK AUDSYNC AUDATA0 AUDATA1 AUDATA2 AUDATA3 AUDRST AUDMD TCK TMS TRST TDI TDO RES Target MCU 6 AUDCK 32 AUDSYNC 30 AUDATA0 28 AUDATA1 26 AUDATA2 24 AUDATA3 34 AUDRST 36 AUDMD 15 TCK 17 TMS 21 TRST 19 TDI 11 TDO 9 RES ASEMD UVCC UVCC_AUD UCON(GND) 14 1 kΩ 12 5 Reset signal GND N.C. GND bus leads 1, 2, 3, 4, 7, 8, 10, 13, 16, 18, 20, 22, 23, 25, 27, 29, 31, 33, 35, 37, 38 User system Figure 1.7 Recommended Circuit for Connection between the H-UDI Port Connector and MCU when the Emulator is in Use (38-Pin Type) Rev. 2.00 Jun. 08, 2009 Page 14 of 46 REJ10J1941-0200 Section 2 Software Specifications when Using the SH72546RFCC, SH72544R, SH72543R, SH72531FCC, and SH72531 Section 2 Software Specifications when Using the SH72546RFCC, SH72544R, SH72543R, SH72531FCC, and SH72531 2.1 Differences between the MCU and the Emulator 1. When the emulator system is initiated, it initializes the general registers and part of the control registers as shown in table 2.1. The initial values of the MCU are undefined. When the emulator is initiated from the workspace, a value to be entered is saved in a session. Table 2.1 Register Initial Values at Emulator Link Up Register Emulator at Link Up R0 to R14 H'00000000 R15 (SP) Value of the SP in the power-on reset vector table PC Value of the PC in the power-on reset vector table SR H'000000F0 GBR H'00000000 VBR H'00000000 TBR H'00000000 MACH H'00000000 MACL H'00000000 PR H'00000000 FPSCR* H'00040001 FPUL* H'00000000 FPR0-15* H'00000000 Note: If the MCU does not incorporate the floating-point unit (FPU), these registers are not displayed. Note: When a value of the interrupt mask bit in the SR register is changed in the [Registers] window, it is actually reflected in that register immediately before execution of the user program is started. It also applies when the value is changed by the REGISTER_SET command. 2. The emulator uses the H-UDI; do not access the H-UDI. Rev. 2.00 Jun. 08, 2009 Page 15 of 46 REJ10J1941-0200 Section 2 Software Specifications when Using the SH72546RFCC, SH72544R, SH72543R, SH72531FCC, and SH72531 3. Low-Power States ⎯ When the emulator is used, the sleep state can be cleared with either the clearing function or with the [STOP] button, and a break will occur. ⎯ Emulation of the hardware stand-by mode is not supported. ⎯ Do not stop inputting the clock to the H-UDI module by using the module standby function. 4. Reset Signals The MCU reset signals are only valid during emulation started with clicking the GO or STEPtype button. If these signals are enabled on the user system in command input wait state, they are not sent to the MCU. Note: Do not break the user program when the /RES, /BREQ, or /WAIT signal is being low. A TIMEOUT error will occur. If the /BREQ or /WAIT signal is fixed to low during break, a TIMEOUT error will occur at memory access. 5. Direct Memory Access Controller (DMAC) The DMAC operates even when the emulator is used. When a data transfer request is generated, the DMAC executes DMA transfer. 6. Memory Access during User Program Execution During execution of the user program, memory is accessed by the following two methods, as shown in table 2.2. Table 2.2 Memory Access during User Program Execution Method Description H-UDI read/write The stopping time of the user program is short because memory is accessed by the dedicated bus master. Short break This method is not available for this product (do not set short break). The method for accessing memory during execution of the user program is specified by using the [Configuration] dialog box. Rev. 2.00 Jun. 08, 2009 Page 16 of 46 REJ10J1941-0200 Section 2 Software Specifications when Using the SH72546RFCC, SH72544R, SH72543R, SH72531FCC, and SH72531 Table 2.3 Stopping Time by Memory Access (Reference) Method Condition Stopping Time H-UDI read/write Reading of one longword for the internal RAM Reading: Maximum three bus clocks (Bφ) Writing of one longword for the internal RAM Writing: Maximum two bus clocks (Bφ) CPU clock: 160 MHz JTAG clock: 20 MHz About 50 ms Short break Reading or writing of one longword for the external area 7. Memory Access to the External Flash Memory Area The emulator can download the load module to the external flash memory area (for details, TM refer to section 6.22, Download Function to the Flash Memory Area, in the SuperH Family E10A-USB Emulator User’s Manual). Other memory write operations are enabled for the RAM area. Therefore, an operation such as memory write or BREAKPOINT should be set only for the RAM area. 8. ROM Cache For ROM cache in the MCU, the emulator operates as shown in table 2.4. Table 2.4 Operation for ROM Cache Function Operation Write and erase of the flash memory Writes or erases all contents of ROM cache. Download of the program to the flash memory Set an overlap of ERAM to the flash memory* Change of the setting of an overlap of ERAM to the flash memory* Download of a program to ERAM overlapped with the flash memory* Rewrite of the memory contents of ERAM overlapped with the flash memory* Set a software break to the flash memory and ERAM overlapped with the flash memory* Memory read Accesses the disabled cache area to read the content of internal flash memory. Rev. 2.00 Jun. 08, 2009 Page 17 of 46 REJ10J1941-0200 Section 2 Software Specifications when Using the SH72546RFCC, SH72544R, SH72543R, SH72531FCC, and SH72531 Note: If the target device is the SH72544R, SH72543R, or SH72531, the function for setting the emulation RAM is not supported. 9. Using WDT The WDT does not operate during break. 10. Loading Sessions Information in [JTAG clock] of the [Configuration] dialog box cannot be recovered by loading sessions. Thus the TCK value will be as follows: ⎯ When HS0005KCU01H or HS0005KCU02H is used: TCK = 10 MHz 11. [IO] Window ⎯ Display and modification For each watchdog timer register, there are two registers to be separately used for write and read operations. Table 2.5 Watchdog Timer Register Register Name Usage Register WTCR(W) Write Watchdog timer control register WTCNT(W) Write Watchdog timer counter WTCR(R) Read Watchdog timer control register WTCNT(R) Read Watchdog timer counter WTSR(W) Write Watchdog timer status register WTSR(R) Read Watchdog timer status register WRCR(W) Write Watchdog reset control register WRCR(R) Read Watchdog reset control register ⎯ Customization of the I/O-register definition file The internal I/O registers can be accessed from the [IO] window. After the I/O-register definition file is created, the MCU’s specifications may be changed. If each I/O register in the I/O-register definition file differs from addresses described in the hardware manual, change the I/O-register definition file according to the description in the hardware manual. The I/O-register definition file can be customized depending on its format. However, the emulator does not support the bit-field function. ⎯ Verify In the [IO] window, the verify function of the input value is disabled. Rev. 2.00 Jun. 08, 2009 Page 18 of 46 REJ10J1941-0200 Section 2 Software Specifications when Using the SH72546RFCC, SH72544R, SH72543R, SH72531FCC, and SH72531 12. Illegal Instructions Do not execute illegal instructions with STEP-type commands. 13. Reset Input During execution of the user program, the emulator may not operate correctly if a contention occurs between the following operations for the emulator and the reset input to the target device: ⎯ Setting an Event Condition ⎯ Setting an internal trace ⎯ Displaying the content acquired by an internal trace ⎯ Reading or writing of a memory Note that those operations should not contend with the reset input to the target device. 14. MCU Operating Mode Boot mode is not supported in the SH72546RFCC, SH72544R, SH72543R, SH72531FCC, and SH72531. When starting up in the user boot mode, do not set a software break point. Use an event point. Rev. 2.00 Jun. 08, 2009 Page 19 of 46 REJ10J1941-0200 Section 2 Software Specifications when Using the SH72546RFCC, SH72544R, SH72543R, SH72531FCC, and SH72531 2.2 2.2.1 Specific Functions for the Emulator when Using the SH72546RFCC, SH72544R, SH72543R, SH72531FCC, and SH72531 Event Condition Functions The emulator is used to set event conditions for the following three functions: • Break of the user program • Internal trace • Start or end of performance measurement Table 2.6 lists the types of Event Condition. Table 2.6 Types of Event Condition Event Condition Type Description Address bus condition (Address) Sets a condition when the address bus (data access) value or the program counter value (before or after execution of instructions) is matched. Data bus condition (Data) Sets a condition when the data bus value is matched. Byte, word, or longword can be specified as the access data size. Bus state condition (Bus State) There are two bus state condition settings: Bus state condition: Sets a condition when the data bus value is matched. Read/Write condition: Sets a condition when the read/write condition is matched. Count Sets a condition when the specified other conditions are satisfied for the specified counts. Reset point A reset point is set when the count and the sequential condition are specified. Action Selects the operation when a condition (such as a break, a trace halt condition, or a trace acquisition condition) is matched. Using the [Combination action (Sequential or PtoP)] dialog box specifies the sequential condition, the point-to-point of the internal trace, and the start or end of performance measurement. Table 2.7 lists the combinations of conditions that can be set under Ch1 to Ch11. Rev. 2.00 Jun. 08, 2009 Page 20 of 46 REJ10J1941-0200 Section 2 Software Specifications when Using the SH72546RFCC, SH72544R, SH72543R, SH72531FCC, and SH72531 Table 2.7 Dialog Boxes for Setting Event Conditions Function Dialog Box Address Bus Condition (Address) Data Bus Condition (Data) Bus State Count Condition (BusCondition Status) (Count) Action [Event Condition 1] Ch1 O O O O O (B, T1, and P) [Event Condition 2] Ch2 O O O X O (B, T1, and P) [Event Condition 3] Ch3 O X X X O (B and T2) [Event Condition 4] Ch4 O X X X O (B and T3) [Event Condition 5] Ch5 O X X X O (B and T3) [Event Condition 6] Ch6 O X X X O (B and T2) [Event Condition 7] Ch7 O X X X O (B and T2) [Event Condition 8] Ch8 O X X X O (B and T2) [Event Condition 9] Ch9 O X X X O (B and T2) [Event Ch10 Condition 10] O X X X O (B and T2) [Event Ch11 Condition 11] O (reset point) X X X X Notes: 1. O: Can be set in the dialog box. X: Cannot be set in the dialog box. 2. For the Action item, B: Setting a break is enabled. T1: Setting the trace halt and acquisition conditions are enabled for the internal trace. T2: Setting the trace halt is enabled for the internal trace. T3: Setting the trace halt and point-to-point is enabled for the internal trace. P: Setting a performance-measurement start or end condition is enabled. The [Event Condition 11] dialog box is used to specify the count of [Event Condition 1] and becomes a reset point when the sequential condition is specified. Rev. 2.00 Jun. 08, 2009 Page 21 of 46 REJ10J1941-0200 Section 2 Software Specifications when Using the SH72546RFCC, SH72544R, SH72543R, SH72531FCC, and SH72531 (1) Sequential Setting Using the [Combination action (Sequential or PtoP)] dialog box specifies the sequential condition and the start or end of performance measurement. Table 2.8 Conditions to Be Set Classification Item Description [Ch1, 2, 3] list box Sets the sequential condition and the start or end of performance measurement using Event Conditions 1 to 3 and 11. Don’t care Sets no sequential condition or the start or end of performance measurement. Break: Ch3-2-1 Breaks when a condition is satisfied in the order of Event Condition 3, 2, 1. Break: Ch3-2-1, Reset point Breaks when a condition is satisfied in the order of Event Condition 3, 2, 1. Enables the reset point of Event Condition 11. Break: Ch2-1 Breaks when a condition is satisfied in the order of Event Condition 2, 1. Break: Ch2-1, Reset point Breaks when a condition is satisfied in the order of Event Condition 2, 1. Enables the reset point. I-Trace stop: Ch3-2-1 Halts acquisition of an internal trace when a condition is satisfied in the order of Event Condition 3, 2, 1. I-Trace stop: Ch3-2-1, Halts acquisition of an internal trace when a Reset point condition is satisfied in the order of Event Condition 3, 2, 1. Enables the reset point. I-Trace stop: Ch2-1 Halts acquisition of an internal trace when a condition is satisfied in the order of Event Condition 2, 1. I-Trace stop: Ch2-1, Reset point Halts acquisition of an internal trace when a condition is satisfied in the order of Event Condition 2, 1. Enables the reset point. Ch2 to Ch1 PA Sets the performance measurement period during the time from the satisfaction of the condition set in Event Condition 2 (start condition) to the satisfaction of the condition set in Event Condition 1 (end condition). Rev. 2.00 Jun. 08, 2009 Page 22 of 46 REJ10J1941-0200 Section 2 Software Specifications when Using the SH72546RFCC, SH72544R, SH72543R, SH72531FCC, and SH72531 Table 2.8 Conditions to Be Set (cont) Classification Item Description [Ch1, 2, 3] list box (cont) Ch1 to Ch2 PA Sets the performance measurement period during the time from the satisfaction of the condition set in Event Condition 1 (start condition) to the satisfaction of the condition set in Event Condition 2 (end condition). [Ch4, 5] list box Sets the point-to-point of the internal trace (the start or end condition of trace acquisition) using Event Conditions 4 and 5. Don’t care Sets no start or end condition of trace acquisition. I-Trace: Ch5 to Ch4 PtoP Sets the acquisition period during the time from the satisfaction of the condition set in Event Condition 5 (start condition) to the satisfaction of the condition set in Event Condition 4 (end condition). I-Trace: Ch5 to Ch4 PtoP, power-on reset Sets the acquisition period during the time from the satisfaction of the condition set in Event Condition 5 (start condition) to the satisfaction of the condition set in Event Condition 4 (end condition) or the power-on reset. • After the sequential condition and the count specification condition of Event Condition 1 have been set, break and trace acquisition will be halted if the sequential condition is satisfied for the specified count. • If a reset point is satisfied, the satisfaction of the condition set in Event Condition will be disabled. For example, if the condition is satisfied in the order of Event Condition 3, 2, reset point, 1, the break or trace acquisition will not be halted. If the condition is satisfied in the order of Event Condition 3, 2, reset point, 3, 2, 1, the break and trace acquisition will be halted. • If the start condition is satisfied after the end condition has been satisfied by measuring performance, performance measurement will be restarted. For the measurement result after a break, the measurement results during performance measurement are added. • If the start condition is satisfied after the end condition has been satisfied by the point-to-point of the internal trace, trace acquisition will be restarted. Rev. 2.00 Jun. 08, 2009 Page 23 of 46 REJ10J1941-0200 Section 2 Software Specifications when Using the SH72546RFCC, SH72544R, SH72543R, SH72531FCC, and SH72531 (2) Usage Example of Sequential Break Extension Setting A tutorial program provided for the product is used as an example. For the tutorial program, refer TM to section 6, Tutorial, in the SuperH Family E10A-USB Emulator User’s Manual. The conditions of Event Condition are set as follows: 1. Ch3 Breaks address H’00001088 when the condition [Only program fetched address after] is satisfied. 2. Ch2 Breaks address H’000010B0 when the condition [Only program fetched address after] is satisfied. 3. Ch1 Breaks address H’000010F2 when the condition [Only program fetched address after] is satisfied. Note: Do not set other channels. 4. Sets the content of the [Ch1,2,3] list box to [Break: Ch 3-2-1] in the [Combination action (Sequential or PtoP)] dialog box. 5. Enables the condition of Event Condition 1 from the popup menu by clicking the right mouse button on the [Event Condition] sheet. Then, set the program counter and stack pointer (PC = H’00000800, R15 = H’FFF90000) in the [Registers] window and click the [Go] button. If this does not execute normally, issue a reset and execute the above procedures. The program is executed up to the condition of Ch1 and halted. Here, the condition is satisfied in the order of Ch3 -> 2 -> 1. Rev. 2.00 Jun. 08, 2009 Page 24 of 46 REJ10J1941-0200 Section 2 Software Specifications when Using the SH72546RFCC, SH72544R, SH72543R, SH72531FCC, and SH72531 Figure 2.1 [Source] Window at Execution Halted (Sequential Break) If the sequential condition, performance measurement start/end, or point-to-point for the internal trace is set, conditions of Event Condition to be used will be disabled. Such conditions must be enabled from the popup menu by clicking the right mouse button on the [Event Condition] sheet. Notes: 1. If the Event condition is set for the slot in the delayed branch instruction by the program counter (after execution of the instruction), the condition is satisfied before executing the instruction in the branch destination (when a break has been set, it occurs before executing the instruction in the branch destination). 2. Do not set the Event condition for the SLEEP instruction by the program counter (after execution of the instruction). 3. When the Event condition is set for the 32-bit instruction by the program counter, set that condition in the upper 16 bits of the instruction. 4. If the power-on reset and the Event condition are matched simultaneously, no condition will be satisfied. 5. Do not set the Event condition for the DIVU or DIVS instruction by the program counter (after execution of the instruction). 6. If a condition of which intervals are satisfied closely is set, no sequential condition will be satisfied. • Set the Event conditions, which are satisfied closely, by the program counter with intervals of two or more instructions. • After the Event condition has been matched by accessing data, set the Event condition by the program counter with intervals of 17 or more instructions. Rev. 2.00 Jun. 08, 2009 Page 25 of 46 REJ10J1941-0200 Section 2 Software Specifications when Using the SH72546RFCC, SH72544R, SH72543R, SH72531FCC, and SH72531 7. If the settings of the Event condition or the sequential conditions are changed during execution of the program, execution will be suspended. (The number of clocks to be suspended during execution of the program is a maximum of about 18 peripheral clocks (Pφ). If the peripheral clock (Pφ) is 66.6 MHz, the program will be suspended for 0.27 μs.) 8. If the settings of Event conditions or the sequential conditions are changed during execution of the program, the emulator temporarily disables all Event conditions to change the settings. During this period, no Event condition will be satisfied. 9. If the break condition before executing an instruction is set to the instruction followed by DIVU and DIVS, the factor for halting a break will be incorrect under the following condition: • If a break occurs during execution of the above DIVU and DIVS instructions, the break condition before executing an instruction, which has been set to the next instruction, may be displayed as the factor for halting a break. 10. If the break conditions before and after executing instructions are set to the same address, the factor for halting a break will be incorrectly displayed. The factor for halting a break due to the break condition after executing an instruction will be displayed even if a break is halted by the break condition before executing an instruction. 11. Do not set the break condition after executing instructions and BREAKPOINT (software break) to the same address. 12. When the emulator is being connected, the user break controller (UBC) function is not available. 13. The performance-measurement function is not available for the SH72544R, SH72543R, and SH72531, so do not make the settings “Ch2 to Ch1PA” and “Ch1 to Ch2PA” if this device is in use. 2.2.2 Trace Functions The emulator supports the trace functions listed in table 2.9. Table 2.9 Trace Functions Function Internal Trace AUD Trace Branch trace Supported Supported Memory access trace Supported Supported Software trace Not supported Supported Rev. 2.00 Jun. 08, 2009 Page 26 of 46 REJ10J1941-0200 Section 2 Software Specifications when Using the SH72546RFCC, SH72544R, SH72543R, SH72531FCC, and SH72531 Table 2.10 shows the type numbers that the AUD function can be used. Table 2.10 Type Number and AUD Function Type Number AUD Function HS0005KCU01H Not supported HS0005KCU02H Supported The internal and AUD traces are set in the [Acquisition] dialog box of the [Trace] window. (1) Internal Trace Function When [I-Trace] is selected for [Trace type] on the [Trace Mode] page of the [Acquisition] dialog box, the internal trace can be used. Figure 2.2 [Acquisition] Dialog Box – Internal Trace Function Rev. 2.00 Jun. 08, 2009 Page 27 of 46 REJ10J1941-0200 Section 2 Software Specifications when Using the SH72546RFCC, SH72544R, SH72543R, SH72531FCC, and SH72531 The following six items can be selected as the internal trace from [Type] of [I-Trace mode]. Table 2.11 Information on Acquiring the Internal Trace Item [M-Bus & Branch] Acquisition Information Acquires the data and branch information on the M-bus. • Data access (read/write) • PC-relative access • Branch information [I-Bus] Acquires the data on the I-bus. • Data access (read/write) • Selection of the bus master on the I-bus (CPU/DMA/A-DMA) • Instruction fetch [F-Bus] Acquires the instruction fetch information on the F-bus. • Instruction fetch [I-Bus, M-Bus & Branch] Acquires the contents of [M-Bus & Branch] and [I-Bus]. [F-Bus, M-Bus & Branch] Acquires the contents of [M-Bus & Branch] and [F-Bus]. [I-Bus, F-Bus] Acquires the contents of [I-Bus] and [F-Bus]. After selecting [Type] of [I-Trace mode], select the content to be acquired from [Acquisition]. Typical examples are described below (note that items disabled for [Acquisition] are not acquired). • Example of acquiring branch information only: Select [M-Bus & Branch] from [Type] and enable [Branch] on [Acquisition]. • Example of acquiring the read or write access (M-bus) only by a user program: Select [M-Bus & Branch] from [Type] and enable [Read] and [Write] on [Acquisition]. • Example of acquiring the read access only by DMA (I-bus): Select [I-Bus] from [Type] and enable [Read] and [DMA] on [Acquisition]. Rev. 2.00 Jun. 08, 2009 Page 28 of 46 REJ10J1941-0200 Section 2 Software Specifications when Using the SH72546RFCC, SH72544R, SH72543R, SH72531FCC, and SH72531 Using Event Condition restricts the condition; the following three items are set as the internal trace conditions. Table 2.12 Trace Conditions of the Internal Trace Item Acquisition Information Trace halt Acquires the internal trace until the Event Condition is satisfied. (The trace content is displayed in the [Trace] window after a trace has been halted. No break occurs in the user program.) Trace acquisition Acquires only the data access where the Event Condition is satisfied. Point-to-point Traces the period from the satisfaction of Event Condition 5 to the satisfaction of Event Condition 4. To restrict trace acquisition to access for only a specific address or specific function of a program, an Event Condition can be used. Typical examples are described below. • Example of halting a trace with a write access (M-bus) to H’FFF80000 by the user program as a condition (trace halt): Set the condition to be acquired on [I-Trace mode]. Set the following in the [Event Condition 1] or [Event Condition 2] dialog box: Address condition: Set [Address] and H’FFF80000. Bus state condition: Set [M-Bus] and [Write]. Action condition: Deselect the [Acquire Break] checkbox and select [Stop] from the [Acquire Trace] list box. • Example of acquiring the write access (M-bus) only to H’FFF80000 by the user program (trace acquisition condition): Select [M-Bus & Branch] from [Type] and enable [Write] on [Acquisition]. Set the following in the [Event Condition 1] or [Event Condition 2] dialog box: Address condition: Set [Address] and H’FFF80000. Bus state condition: Set [M-Bus] and [Write]. Action condition: Deselect the [Acquire Break] checkbox and select [Condition] from the [Acquire Trace] list box. For the trace acquisition condition, the condition to be acquired by Event Condition should be acquired by [I-Trace mode]. • Example of acquiring a trace for the period while the program passes H’1000 through H’2000 (point-to-point): Rev. 2.00 Jun. 08, 2009 Page 29 of 46 REJ10J1941-0200 Section 2 Software Specifications when Using the SH72546RFCC, SH72544R, SH72543R, SH72531FCC, and SH72531 Set the condition to be acquired on [I-Trace mode]. Set the address condition as H’1000 in the [Event Condition 5] dialog box. Set the address condition as H’2000 in the [Event Condition 4] dialog box. Set [I-Trace] as [Ch5 to Ch4 PtoP] in the [Combination action (Sequential or PtoP)] dialog box. When point-to-point and trace acquisition condition are set simultaneously, they are ANDed. Notes on Internal Trace (2) • Timestamp The timestamp is the clock counts of Pφ (48-bit counter). Table 2.13 shows the timing for acquiring the timestamp. Table 2.13 Timing for the Timestamp Acquisition Item Acquisition Information Counter Value Stored in the Trace Memory M-bus data access Counter value when data access (read or write) has been completed Branch Counter value when the next bus cycle has been completed after a branch I-bus F-bus Fetch Counter value when a fetch has been completed Data access Counter value when data access has been completed Fetch Counter value when a fetch has been completed • Point-to-point The trace-start condition is satisfied when the specified instruction has been fetched. Accordingly, if the trace-start condition has been set for the overrun-fetched instruction (an instruction that is not executed although it has been fetched at a branch or transition to an interrupt), tracing is started during overrun-fetching of the instruction. However, when overrun-fetching is achieved (a branch is completed), tracing is automatically suspended. If the start and end conditions are satisfied closely, trace information will not be acquired correctly. The execution cycle of the instruction fetched before the start condition is satisfied may be traced. When the I-bus is acquired, do not specify point-to-point. Memory access may not be acquired by the internal trace if it occurs at several instructions immediately before satisfaction of the point-to-point end condition. Rev. 2.00 Jun. 08, 2009 Page 30 of 46 REJ10J1941-0200 Section 2 Software Specifications when Using the SH72546RFCC, SH72544R, SH72543R, SH72531FCC, and SH72531 • Halting a trace Do not set the trace end condition for the sleep instruction and the branch instruction that the delay slot becomes the sleep instruction. • Trace acquisition condition Do not set the trace end condition for the sleep instruction and the branch instruction according to which the delay slot becomes the sleep instruction. When [F-Bus], [F-Bus, M-Bus & Branch], or [I-Bus, F-Bus] is selected, do not set the trace acquisition condition for [Event Condition 1] and [Event Condition 2]. If a trace acquisition condition is set, no trace will be acquired. When [I-Bus, M-Bus & Branch] is selected and the trace acquisition condition is set for the Mbus and I-bus with Event Condition, set the M-bus condition and the I-bus condition for [Event Condition 1] and [Event Condition 2], respectively. When matching of the program counter value is a condition of Event Condition for internal trace acquisition (i.e. [Only program fetched address] or [Only program fetched address after] is selected), do not specify addresses in the on-chip ROM or on-chip RAM as the address condition. If you specify a break (by selecting the [Acquire Break] checkbox) and trace acquisition (by selecting [Condition] from the [Acquire Trace] list box) on the [Action] page as the action to take when a condition of Event Condition is satisfied, setting of the trace acquisition will be ignored. If the settings of [I-Trace mode] are changed during execution of the program, execution will be suspended. (The number of clocks to be suspended during execution of the program is a maximum of about 24 peripheral clocks (Pφ). If the peripheral clock (Pφ) is 66.6 MHz, the program will be suspended for 0.36 μs.) • Displaying a trace If a trace is displayed during execution of the program, execution will be suspended to acquire the trace information. (The number of clocks to be suspended during execution of the program is a maximum of about 5120 peripheral clocks (Pφ). If the peripheral clock (Pφ) is 66.6 MHz, the program will be suspended for 76.87 μs.) • Branch trace If breaks occur immediately after executing non-delayed branch and TRAPA instructions and generating a branch due to exception or interrupt, a trace for one branch will not be acquired immediately before such breaks. However, this does not affect on generation of breaks caused by a BREAKPOINT and a break before executing instructions of Event Condition. Rev. 2.00 Jun. 08, 2009 Page 31 of 46 REJ10J1941-0200 Section 2 Software Specifications when Using the SH72546RFCC, SH72544R, SH72543R, SH72531FCC, and SH72531 • Writing memory immediately before generating a break If an instruction is executed to write memory immediately before generating a break, trace acquisition may not be performed. • Internal trace function is not available for the SH72544R, SH72543R, and SH72531. (3) AUD Trace Functions This function is operational when the AUD pin of the device is connected to the emulator. Table 2.14 shows the AUD trace acquisition mode that can be set in each trace function. Table 2.14 AUD Trace Acquisition Mode Type Mode Description Continuous trace occurs Realtime trace When the next branch occurs while the trace information is being output, all the information may not be output. The user program can be executed in realtime, but some trace information will be lost. Non realtime trace When the next branch occurs while the trace information is being output, the CPU stops operations until the information is output. The user program is not executed in realtime. Trace continue This function overwrites the latest trace information to store the oldest trace information. Trace stop After the trace buffer becomes full, the trace information is no longer acquired. The user program is continuously executed. Trace buffer full Rev. 2.00 Jun. 08, 2009 Page 32 of 46 REJ10J1941-0200 Section 2 Software Specifications when Using the SH72546RFCC, SH72544R, SH72543R, SH72531FCC, and SH72531 To set the AUD trace acquisition mode, click the [Trace] window with the right mouse button and select [Setting] from the pop-up menu to display the [Acquisition] dialog box. The AUD trace acquisition mode can be set in the [AUD mode1] or [AUD mode2] group box in the [Trace mode] page of the [Acquisition] dialog box. Figure 2.3 [Trace mode] Page Rev. 2.00 Jun. 08, 2009 Page 33 of 46 REJ10J1941-0200 Section 2 Software Specifications when Using the SH72546RFCC, SH72544R, SH72543R, SH72531FCC, and SH72531 When the AUD trace function is used, select the [AUD function] radio button in the [Trace type] group box of the [Trace mode] page. (a) Branch Trace Function The branch source and destination addresses and their source lines are displayed. Branch trace can be acquired by selecting the [Branch trace] check box in the [AUD function] group box of the [Trace mode] page. The branch type can be selected in the [AUD Branch trace] page. Rev. 2.00 Jun. 08, 2009 Page 34 of 46 REJ10J1941-0200 Section 2 Software Specifications when Using the SH72546RFCC, SH72544R, SH72543R, SH72531FCC, and SH72531 Figure 2.4 [AUD Branch trace] Page (b) Window Trace Function Memory access in the specified range can be acquired by trace. Two memory ranges can be specified for channels A and B. The read, write, or read/write cycle can be selected as the bus cycle for trace acquisition. Rev. 2.00 Jun. 08, 2009 Page 35 of 46 REJ10J1941-0200 Section 2 Software Specifications when Using the SH72546RFCC, SH72544R, SH72543R, SH72531FCC, and SH72531 [Setting Method] (i) Select the [Channel A] and [Channel B] check boxes in the [AUD function] group box of the [Trace mode] page. Each channel will become valid. (ii) Open the [Window trace] page and specify the bus cycle, memory range, and bus type that are to be set for each channel. Figure 2.5 [Window trace] Page Rev. 2.00 Jun. 08, 2009 Page 36 of 46 REJ10J1941-0200 Section 2 Software Specifications when Using the SH72546RFCC, SH72544R, SH72543R, SH72531FCC, and SH72531 Note: When [M-Bus] or [I-Bus] is selected, the following bus cycles will be traced. • M-Bus: A bus cycle generated by the CPU is acquired. • I-Bus: A bus cycle generated by the CPU or DMA is acquired. (c) Software Trace Function Note: This function can be supported with SHC/C++ compiler (manufactured by Renesas Technology Corp.; including OEM and bundle products) V7.0 or later. When a specific instruction is executed, the PC value at execution and the contents of one general register are acquired by trace. Describe the Trace(x) function (x is a variable name) to be compiled and linked beforehand. For details, refer to the SHC manual. When the load module is downloaded on the target system and is executed while a software trace function is valid, the PC value that has executed the Trace(x) function, the general register value for x, and the source lines are displayed. To activate the software trace function, select the [Software trace] check box in the [AUD function] group box of the [Trace mode] page. (4) Notes on AUD Trace 1. When the trace display is performed during user program execution, the mnemonics, operands, or source is not displayed. 2. The AUD trace function outputs the differences between newly output branch source addresses and previously output branch source addresses. The window trace function outputs the differences between newly output addresses and previously output addresses. If the previous branch source address is the same as the upper 16 bits, the lower 16 bits are output. If it matches the upper 24 bits, the lower 8 bits are output. If it matches the upper 28 bits, the lower 4 bits are output. The emulator regenerates the 32-bit address from these differences and displays it in the [Trace] window. If the emulator cannot display the 32-bit address, it displays the difference from the previously displayed 32-bit address. 3. If the 32-bit address cannot be displayed, the source line is not displayed. 4. If a completion-type exception occurs during exception branch acquisition, the next address to the address in which an exception occurs is acquired. 5. The AUD trace is disabled while the profiling function is used. 6. Set the AUD clock (AUDCK) frequency to 40 MHz or lower. If the frequency is higher than 40 MHz, the emulator will not operate normally. Rev. 2.00 Jun. 08, 2009 Page 37 of 46 REJ10J1941-0200 Section 2 Software Specifications when Using the SH72546RFCC, SH72544R, SH72543R, SH72531FCC, and SH72531 7. If breaks occur immediately after executing non-delayed branch and TRAPA instructions and generating a branch due to exception or interrupt, a trace for one branch will not be acquired immediately before such breaks. However, this does not affect on generation of breaks caused by a BREAKPOINT and a break before executing instructions of Event Condition. 8. For the result by software trace, a value in the [Data] item is not correct (that value is correct for window trace). 9. The AUD trace function is not available if the target device is the SH72531FCC or SH72531. 10. The CPU clock ratios 1:1 and 1:2 cannot be used for the AUD clock (AUDCK) with the SH72546RFCC, SH72544R, or SH72543R as the target device. 2.2.3 Notes on Using the JTAG (H-UDI) Clock (TCK) 1. Set the JTAG clock (TCK) frequency to lower than the frequency of the peripheral module clock. 2. The initial value of the JTAG clock (TCK) is 10 MHz. 3. A value to be set for the JTAG clock (TCK) is initialized after executing [Reset CPU] or [Reset Go]. Thus the TCK value will be the initial value. 2.2.4 Notes on Setting the [Breakpoint] Dialog Box 1. When an odd address is set, the next lowest even address is used. 2. A BREAKPOINT is accomplished by replacing instructions of the specified address. It cannot be set to the following addresses: ⎯ An area other than CS and the internal RAM ⎯ An instruction in which Break Condition 2 is satisfied ⎯ A slot instruction of a delayed branch instruction 3. During step operation, specifying BREAKPOINTs and Event Condition breaks are disabled. 4. When execution resumes from the address where a BREAKPOINT is specified and a break occurs before Event Condition execution, single-step operation is performed at the address before execution resumes. Therefore, realtime operation cannot be performed. 5. When a BREAKPOINT is set to the slot instruction of a delayed branch instruction, the PC value becomes an illegal value. Accordingly, do not set a BREAKPOINT to the slot instruction of a delayed branch instruction. 6. If an address of a BREAKPOINT cannot be correctly set in the ROM or flash memory area, a mark z will be displayed in the [BP] area of the address on the [Source] or [Disassembly] window by refreshing the [Memory] window, etc. after Go execution. However, no break will Rev. 2.00 Jun. 08, 2009 Page 38 of 46 REJ10J1941-0200 Section 2 Software Specifications when Using the SH72546RFCC, SH72544R, SH72543R, SH72531FCC, and SH72531 occur at this address. When the program halts with the event condition, the mark z disappears. 2.2.5 Notes on Setting the [Event Condition] Dialog Box and the BREAKCONDITION_ SET Command 1. When [Go to cursor], [Step In], [Step Over], or [Step Out] is selected, the settings of Event Condition 3 are disabled. 2. When an Event Condition is satisfied, emulation may stop after two or more instructions have been executed. 2.2.6 Performance Measurement Function The emulator supports the performance measurement function. Note: The performance measurement function is not available when the target device is the SH72544R, SH72543R, or SH72531. (1) Setting the Performance Measurement Conditions To set the performance measurement conditions, use the [Performance Analysis] dialog box and the PERFORMANCE_SET command. When any line in the [Performance Analysis] window is clicked with the right mouse button, a popup menu is displayed and the [Performance Analysis] dialog box can be displayed by selecting [Setting]. Note: For the command line syntax, refer to the online help. Rev. 2.00 Jun. 08, 2009 Page 39 of 46 REJ10J1941-0200 Section 2 Software Specifications when Using the SH72546RFCC, SH72544R, SH72543R, SH72531FCC, and SH72531 (a) Specifying the Measurement Start/End Conditions The measurement start/end conditions are specified by using Event Condition 1,2. The [Ch1,2,3] list box of the [Combination action (Sequential or PtoP)] dialog box can be used. Table 2.15 Measurement Period Classification Item Description Selection in the [Ch1, 2, 3] list box Ch2 to Ch1 PA The period from the satisfaction of the condition set in Event Condition 2 (start condition) to the satisfaction of the condition set in Event Condition 1 (end condition) is set as the performance measurement period. Ch1 to Ch2 PA The period from the satisfaction of the condition set in Event Condition 1 (start condition) to the satisfaction of the condition set in Event Condition 2 (end condition) is set as the performance measurement period. Other than above The period from the start of execution of the user program to the occurrence of a break is measured. Figure 2.6 [Performance Analysis] Dialog Box For measurement tolerance, • The measured value includes tolerance. • Tolerance will be generated before or after a break. Rev. 2.00 Jun. 08, 2009 Page 40 of 46 REJ10J1941-0200 Section 2 Software Specifications when Using the SH72546RFCC, SH72544R, SH72543R, SH72531FCC, and SH72531 Note: When [Ch2 to Ch1 PA] or [Ch1 to Ch2 PA] is selected, to execute the user program, specify conditions set in Event Condition 2 and Event Condition 1 and one or more items for performance measurement. (b) Measurement Item Items are measured with [Channel 1 to 4] in the [Performance Analysis] dialog box. Maximum four conditions can be specified at the same time. Rev. 2.00 Jun. 08, 2009 Page 41 of 46 REJ10J1941-0200 Section 2 Software Specifications when Using the SH72546RFCC, SH72544R, SH72543R, SH72531FCC, and SH72531 Table 2.16 Measurement Item Selected Name Option Disabled None Elapsed time AC (The number of execution cycles (Iφ).) Branch instruction counts BT Number of execution instructions I Number of execution 32bit-instructions I32 Exception/interrupt counts EA Interrupt counts INT Data cache-miss counts DC Instruction cache-miss counts IC All area access counts ARN All area instruction access counts ARIN All area data access counts ARND Cacheable area access counts CDN (data access) Cacheable area instruction access counts CIN Non cacheable area data access counts NCN URAM area access counts UN URAM area instruction access counts UIN URAM area data access counts UDN Internal I/O area data access counts IODN Internal ROM area access counts RN Internal ROM area instruction access counts RIN Internal ROM area data access counts RDN All area access cycle ARC All area instruction access cycle ARIC All area data access cycle ARDC All area access stall ARS All area instruction access stall ARIS All area data access stall ARDS Note: Selected names are displayed for CONDITION in the [Performance Analysis] window. Options are parameters for <mode> of the PERFORMANCE_SET command. Rev. 2.00 Jun. 08, 2009 Page 42 of 46 REJ10J1941-0200 Section 2 Software Specifications when Using the SH72546RFCC, SH72544R, SH72543R, SH72531FCC, and SH72531 Notes: 1. In the non-realtime trace mode of the AUD trace, normal counting cannot be performed because the generation state of the stall or the execution cycle is changed. 2. For SH72546RFCC or SH72531FCC do not set measurement items for the cache-miss counts, cacheable area, or non-cacheable area. 3. Even when [Exception/interrupt counts (EA)] is selected as the measurement item, no trap-instruction exception caused by TRAPA instructions will be counted. (2) Displaying the Measured Result The measured result is displayed in the [Performance Analysis] window or the PERFORMANCE_ANALYSIS command with hexadecimal (32 bits). Note: If a performance counter overflows as a result of measurement, “********” will be displayed. (3) Initializing the Measured Result To initialize the measured result, select [Initialize] from the popup menu in the [Performance Analysis] window or specify INIT with the PERFORMANCE_ANALYSIS command. Rev. 2.00 Jun. 08, 2009 Page 43 of 46 REJ10J1941-0200 Section 2 Software Specifications when Using the SH72546RFCC, SH72544R, SH72543R, SH72531FCC, and SH72531 2.2.7 Emulation RAM Setting Function The emulation RAM can be set in the [Memory Mapping] dialog box which is opened by selecting [Setup] -> [Emulator] -> [Memory…] from the menu. The emulator incorporates 8-block emulation RAM in each 64-kbyte unit, which can be set in each 64-kbyte boundary within the address ranges from H’00000000 to H’001FFFFF. The emulation RAM is overlapped with the address of the internal flash memory. Using the emulation RAM proceeds debugging without rewriting the program or data on the internal flash memory. When the emulation RAM is not used in the emulator, it can be used as the internal RAM for debugging. Figure 2.7 [Memory Mapping] Dialog Box Rev. 2.00 Jun. 08, 2009 Page 44 of 46 REJ10J1941-0200 Section 2 Software Specifications when Using the SH72546RFCC, SH72544R, SH72543R, SH72531FCC, and SH72531 The contents of the [Memory Mapping] dialog box are shown below. [Mode] [User] The emulator does not use the emulation RAM. [Emulator] The emulator uses the emulation RAM. [Edit…] Open the dialog box for setting [Memory Mapping] to change the address ranges and attributes of the emulation RAM. [Reset] Reset the selected emulation RAM as default. [Reset All] Reset all emulation RAMs as default. [ERAM Setting] [OK] Reflect changes and close the [Memory Mapping] dialog box. [Cancel] Reflect no changes and close the [Memory Mapping] dialog box. Figure 2.8 Dialog Box for Setting [Memory Mapping] Rev. 2.00 Jun. 08, 2009 Page 45 of 46 REJ10J1941-0200 Section 2 Software Specifications when Using the SH72546RFCC, SH72544R, SH72543R, SH72531FCC, and SH72531 The contents of the dialog box for setting [Memory Mapping] are shown below. [From:] Enter the start address for the ranges. [Setting:] [ERAM to FLASH] Reflect the contents of the emulation RAM in the internal flash memory when address allocation is cancelled. [ERAM not to FLASH] Reflect no contents of the emulation RAM in the internal flash memory when address allocation is cancelled. [Reset All] Reset all emulation RAMs as default. [OK] Reflect changes and close the dialog box for setting [Memory Mapping]. [Cancel] Reflect no changes and close the dialog box for setting [Memory Mapping]. Notes: 1. Operation is not guaranteed in cases where registers of the ERAM module are manipulated from the [IO] window or in some other way. 2. For command-line syntax, refer to the online help file. 3. If an area of emulation RAM is not being used by the emulator, the user must not allocate that emulation RAM to a ROM area; instead use the emulation RAM in its original address area. 4. When using the emulation RAM, make the setting to disable flash memory synchronization on halting the user program. 5. The function for setting of the emulation RAM is not available when the target device is the SH72544R, SH72543R, or SH72531. Rev. 2.00 Jun. 08, 2009 Page 46 of 46 REJ10J1941-0200 SuperH™ Family E10A-USB Emulator Additional Document for User's Manual Supplementary Information on Using the SH72546RFCC, SH72544R, SH72543R, SH72531FCC, and SH72531 Publication Date: Rev.1.00, November 18, 2008 Rev.2.00, June 8, 2009 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp. © 2009. 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