w WM8805_6152_DS28_EV1_REV3 Evaluation Board Example Configurations INTRODUCTION The WM8805 is a high performance S/PDIF transceiver which offers a state-of-the-art jitter attenuating S/PDIF receiver design. The WM8805 customer evaluation board provides full functionality for the evaluation of the WM8805 device. The purpose of this document is to detail common standard configurations for evaluation board operation. Contained in this document are: • WM8805 internal signal path details. • Register settings for internal configuration of the WM8805 device. • Details on evaluation board setup and configuration. This document can be used as a base line for evaluation board configuration when beginning to use the WM8805 customer evaluation board. Please note that all register settings supplied in this document are suitable to setup the required path but may not be optimised for quiet power up or other considerations that will be necessary for any end application. Please consult the latest datasheet for information on such considerations. Software to configure the evaluation board can be downloaded from http://www.wolfsonmicro.com/support/drivers WOLFSON MICROELECTRONICS plc To receive regular email updates, sign up at http://www.wolfsonmicro.com/enews/ September 2007, Rev 3.2 Copyright ©2007 Wolfson Microelectronics plc WM8805_6152_DS28_EV1_REV3 Preliminary Customer Information TABLE OF CONTENTS INTRODUCTION .............................................................................................................1 TABLE OF CONTENTS ..................................................................................................2 TERMINOLOGY ..............................................................................................................3 INPUTS AND OUTPUTS .................................................................................................3 BOARD POWER SUPPLIES...................................................................................................3 S/PDIF INPUTS.......................................................................................................................4 S/PDIF OUTPUT .....................................................................................................................4 WM8805 BASIC CONFIGURATION........................................................................................5 MCU CONTROL (VIA USB).....................................................................................................5 LED INDICATORS ..................................................................................................................6 EXAMPLE CONFIGURATIONS ......................................................................................8 HARDWARE MODE EXAMPLES ............................................................................................8 S/PDIF RECEIVER RX0 TO AIF ............................................................................................................8 S/PDIF RECEIVER RX0 TO S/PDIF TRANSMITTER..........................................................................10 AIF TO S/PDIF TRANSMITTER ...........................................................................................................12 SOFTWARE MODE EXAMPLES ..........................................................................................14 S/PDIF RECEIVER RX1 TO AIF ..........................................................................................................14 S/PDIF RECEIVER RX4 TO S/PDIF TRANSMITTER..........................................................................16 S/PDIF RECEIVER AUDIO DEMONSTRATION DAC ...........................................................18 APPLICATION SUPPORT ............................................................................................20 IMPORTANT NOTICE ...................................................................................................21 ADDRESS: ....................................................................................................................21 w Preliminary Customer Information September 2007, Rev 3.2 2 WM8805_6152_DS28_EV1_REV3 Preliminary Customer Information TERMINOLOGY AIF Audio Interface S/PDIF Sony/Philips Digital Interface Format USB Universal Serial Bus EVB Evaluation Board MCU Microprocessor Control Unit INPUTS AND OUTPUTS BOARD POWER SUPPLIES The WM8805 customer evaluation board can be powered using one of two sources: • External power supplies • Derived from the USB connection The evaluation board can be powered either from the 4mm power lead receptacles or from the USB host. Refer to Table 1. REF-DES J8 (PVDD_SEL) J9 (DVDD_SEL) J10 (DVDD_DAC_ SEL) J11 (+5V_SEL) LINK STATUS DESCRIPTION 1-2 2-3 PVDD Power Source Select PVDD 4mm power jack receptacle selected USB power source selected [default setting] 1-2 2-3 DVDD Power Source Select DVDD 4mm power jack receptacle selected USB power source selected [default setting] 1-2 2-3 S/PDIF Receiver DAC Power Source Select DVDD 4mm power jack receptacle selected USB power source selected [default setting] 1-2 2-3 +5V Power Source Select +5V 4mm power jack receptacle selected USB power source selected [default setting] Table 1 Power Supply Source Select Using appropriate power leads with 4mm connectors, supplies can be connected as described in Table 2 if the power supply is selected as the 4mm power jack receptacles. REF-DES SOCKET NAME SUPPLY J1 J2 J3 J4 J5 PVDD PGND DVDD DGND +5V +2.7V to +3.6V 0V +2.7V to +3.6V 0V +5V Table 2 Power Supply Connections Note: Refer to the datasheet for limitations on individual supply voltages. Important: Exceeding the recommended maximum voltage can damage EVB components. Under voltage may cause improper operation of some or all of the EVB components. w Preliminary Customer Information September 2007, Rev 3.2 3 WM8805_6152_DS28_EV1_REV3 Preliminary Customer Information S/PDIF INPUTS The WM8805 evaluation board supports both electrical and optical input of the S/PDIF stream. This signal may be input via a standard phono connector (J7 or J18) or via the optical receivers (U3 or U10). Refer to Table 3 for details. REF-DES J7 CONNECTOR TYPE Phono Connector DESCRIPTION S/PDIF_IN_0_ELECTRICAL J18 Phono Connector S/PDIF_IN_1_ELECTRICAL U3 Optical Receiver S/PDIF_IN_0_OPTICAL U10 Optical Receiver S/PDIF_IN_1_OPTICAL Table 3 S/PDIF Input Connections The S/PDIF input stream must then be routed to the appropriate WM8805 pins using the optical/electrical input selection jumpers (J29 and J30) and the routing headers (H1 and H7). Refer to Table 4 for details. REF-DES LINK STATUS DESCRIPTION J29 1-2 2-3 S/PDIF Input 0 Source Select Optical input selected Electrical input selected [default setting] J30 1-2 2-3 S/PDIF Input 1 Source Select Optical input selected Electrical input selected [default setting] H1 H7 1-2 5-6 9 - 10 13 - 14 S/PDIF Input 0 Routing Route input 0 to WM8805 Rx0 input [default setting] Route input 0 to WM8805 Rx4 input Route input 0 to WM8805 Rx2 input Route input 0 to WM8805 Rx6 input 1-2 5-6 9 - 10 13 - 14 S/PDIF Input 1 Routing Route input 1 to WM8805 Rx1 input [default setting] Route input 1 to WM8805 Rx5 input Route input 1 to WM8805 Rx3 input Route input 1 to WM8805 Rx7 input Table 4 S/PDIF Input and Routing Selection S/PDIF OUTPUT The WM8805 S/PDIF output can be output from the WM8805 evaluation board via a standard phono connector (J17). Refer to Table 5. REF-DES J21 SOCKET TYPE Phono Connector SIGNAL S/PDIF_OUT Table 5 S/PDIF Output Connections The evaluation board is also equipped with a Wolfson WM8726 received audio demonstration DAC. Refer to “S/PDIF Receiver Audio Demonstration DAC” section. w Preliminary Customer Information September 2007, Rev 3.2 4 WM8805_6152_DS28_EV1_REV3 Preliminary Customer Information WM8805 BASIC CONFIGURATION The following jumpers are provided to allow easy configuration of the WM8805 in both hardware and software mode. It is important that the jumpers are correctly configured for the desired WM8805 function. JUMPERS JUMPER STATUS DESCRIPTION Hardware Mode (selected by J15) Software Mode (selected by J15) Audio Interface Master/Slave Select Select master mode Select slave mode No function – remove link 1–2 2–3 1–2 2–3 Audio Interface Configuration 1 High Low Control Interface Mode Select Select 3-wire (SPI compatible) mode Select 2-wire (I2C compatible) mode 1–2 2–3 Hardware/Software Mode Select Software mode Hardware mode Hardware/Software Mode Select Software mode Hardware mode Audio Interface Configuration 0 High Low No function – remove link 1–2 2–3 1–2 2–3 S/PDIF Transmitter Source Select Audio interface received data S/PDIF received data J12 J13 J15 J16 J17 2 Wire/I2C Mode Device Address 0x76 0x74 3 Wire/SPI Mode No function – remove link Table 6 Jumpers MCU CONTROL (VIA USB) The WM8805 evaluation board is equipped with a USB interface MCU which allows interconnection with a PC in conjunction with the WM8805-EV1S evaluation software. To enable software control via the USB MCU, the pins in header H2 must be interconnected as shown in Table 7. The links must be removed as shown in hardware and 2-Wire/I2C mode. REF-DES LINK STATUS DESCRIPTION WM8005 to Control Interface MCU Connection 3-Wire/SPI Mode Connect WM8805 CSB to USB MCU 2-Wire/I2C Mode Do Not Fit Link Hardware Mode Do Not Fit Link 3–4 Connect WM8805 SCLK to USB MCU Connect WM8805 SCLK to USB MCU Do Not Fit Link 5–6 Connect WM8805 SDIN to USB MCU Connect WM8805 SDIN to USB MCU Do Not Fit Link 7–8 Connect WM8805 SDOUT to USB MCU Do Not Fit Link Do Not Fit Link 1–2 H2 Table 7 USB MCU Connections w Preliminary Customer Information September 2007, Rev 3.2 5 WM8805_6152_DS28_EV1_REV3 Preliminary Customer Information LED INDICATORS The WM8805 evaluation board has a number of LEDs. Their function is described in Table 8 LED Descriptions. LINK STATUS (IF APPLICABLE) LED HARDWARE MODE DESCRIPTION SOFTWARE MODE DESCRIPTION (DEFAULT SETTINGS) LED OFF LED OFF LED ON LED ON Not applicable LED1 USB firmware issue. USB firmware OK. USB firmware issue.. USB firmware OK. Not applicable LED2 USB power not present. USB interface power is OK. USB not present. USB interface power is OK. H4, 1 – 2 fitted (remove in s/w mode) LED3 S/PDIF Rx TRANS_ERR status. Indicates that the S/PDIF RX has not received a transmission error. S/PDIF Rx TRANS_ERR status. Indicates that the S/PDIF RX has received a transmission error. Not applicable – do not fit link. Not applicable– do not fit link. H4, 3 – 4 fitted LED4 No General Error occurred GEN_FLAG – indicates a general error has occurred (logical OR of TRANS_ERR, NON_AUDIO and UNLOCK) GPO0 – defaults to INT_N Indicates an interrupt has occurred due to change in S/PDIF Rx status GPO0 – defaults to INT_N Indicates no interrupt due to change in S/PDIF Rx status H4, 5 – 6 fitted LED5 S/PDIF Rx UNLOCK status indicating that the S/PDIF RX has locked. S/PDIF Rx UNLOCK status. Indicates that the S/PDIF RX has lost lock. GPO1 – defaults to S/PDIF Rx UNLOCK status indicating that the S/PDIF RX has locked. GPO1 – defaults to S/PDIF Rx UNLOCK status. Indicates that the S/PDIF RX has lost lock. H4, 7 – 8 fitted (remove in 3-wire s/w mode) LED6 S/PDIF Rx UNLOCK status indicating that the S/PDIF RX has locked. S/PDIF Rx UNLOCK status. Indicates that the S/PDIF RX has lost lock. 2-wire mode GPO2– defaults to S/PDIF Rx UNLOCK status. Indicates that the S/PDIF RX has locked. 3-wire mode NOT Available – remove link 2-wire mode GPO2– defaults to S/PDIF Rx UNLOCK status. Indicates that the S/PDIF RX has lost lock. 3-wire mode NOT Available – remove link H4, 9 – 10 fitted only if used as GPO3 LED7 NOT Available – remove link NOT Available – remove link GPO3 – defaults to S/PDIF Rx SFRM_CLK status indicating that the SFRM_CLK is LOW GPO3 – defaults to S/PDIF Rx SFRM_CLK status indicating that the SFRM_CLK is HIGH H4, 11 – 12 fitted only if used as GPO4 LED8 NOT Available – remove link NOT Available – remove link GPO4 – defaults to S/PDIF Rx 192BCLK status indicating that the 192BCLK is LOW GPO4 – defaults to S/PDIF Rx 192BCLK status indicating that the 192BCLK is HIGH H4, 13 – 14 fitted only if used as GPO5 LED9 NOT Available – remove link NOT Available – remove link GPO5 – defaults to S/PDIF Rx C bit status indicating that the ‘C’ bit is LOW GPO5 – defaults to S/PDIF Rx C bit status indicating that the ‘C’ bit is HIGH H4, 15 – 16 fitted only if used as GPO6 LED10 NOT Available – remove link NOT Available – remove link GPO6 – defaults to S/PDIF Rx U bit status indicating that the ‘U’ bit is LOW GPO6 – defaults to S/PDIF Rx U bit status indicating that the ‘U’ bit is HIGH w Preliminary Customer Information September 2007, Rev 3.2 6 WM8805_6152_DS28_EV1_REV3 Preliminary Customer Information LINK STATUS (IF APPLICABLE) H4, 17 – 18. (remove in 3-wire s/w mode) LED LED11 HARDWARE MODE DESCRIPTION SOFTWARE MODE DESCRIPTION (DEFAULT SETTINGS) LED OFF LED OFF TRANS_ERR status. Indicates that the S/PDIF RX has not received a transmission error. LED ON TRANS_ERR status. Indicates that the S/PDIF RX has received a transmission error. LED ON 2-wire mode GPO7– defaults to S/PDIF Rx TRANS_ERR status. Indicates that the S/PDIF RX has not received a transmission error. 3-wire mode NOT Available – remove link 2-wire mode GPO7– defaults to S/PDIF Rx TRANS_ERR status. Indicates that the S/PDIF RX has received a transmission error. 3-wire mode NOT Available – remove link Table 8 LED Descriptions w Preliminary Customer Information September 2007, Rev 3.2 7 WM8805_6152_DS28_EV1_REV3 Preliminary Customer Information EXAMPLE CONFIGURATIONS The following example configurations are independent of whether power is applied to the board from external power supplies or from the USB interface. HARDWARE MODE EXAMPLES In hardware control mode the WM8805 can only receive data from S/PDIF RX0. S/PDIF RECEIVER RX0 TO AIF The configuration is as follows:• Data path = S/PDIF RX0 (electrical input) to AIF DOUT • Hardware master mode. • Powered from the USB interface. • AIF format = 24 bit I2S • Figure 1 illustrates the data path. • Figure 2 illustrates the jumpers which must be made on the board. Figure 1 RX0 Input Path to Audio Interface Block Diagram w Preliminary Customer Information September 2007, Rev 3.2 8 WM8805_6152_DS28_EV1_REV3 Preliminary Customer Information To configure this path, with an audio interface format of 24 bit I2S, the external jumpers should be set as shown in Table 9. Do not fit H2 links. JUMPERS JUMPER STATUS J12 DESCRIPTION 1–2 Audio Interface Master/Slave Select Select master mode 1–2 Audio Interface Configuration 0 High 2–3 Audio Interface Configuration 1 Low 2–3 Hardware/Software Mode Select Hardware mode 1–2 S/PDIF Transmitter Source Select Audio interface received data 1–2 S/PDIF Input 0 Source Select Electrical input selected 1–2 S/PDIF Input 0 Routing Route input 0 to WM8805 Rx0 input J16 J13 J15 J17 J29 H1 Table 9 RX0 Input Path to Audio Interface Link Settings The jumpers, input signals and output signals are shown in Figure 2. The yellow jumpers are those that are required. The red jumpers are for power. Figure 2 RX0 Input Path to Audio Interface Evaluation Board Configuration Data is applied to the S/PDIF RX0 interface. The output data can be monitored at the AIF DOUT. MCLK is an output from the AIF. w Preliminary Customer Information September 2007, Rev 3.2 9 WM8805_6152_DS28_EV1_REV3 Preliminary Customer Information S/PDIF RECEIVER RX0 TO S/PDIF TRANSMITTER The configuration is as follows:• Data path = S/PDIF RX0 (optical input) to S/PDIF TX • Hardware slave mode. • Powered from the USB interface. • AIF format = 24 bit I2S • Figure 3 illustrates the data path. • Figure 4 illustrates the jumpers which must be made on the board. Figure 3 S/PDIF RX0 Input to S/PDIFTX0 Output Block Diagram w Preliminary Customer Information September 2007, Rev 3.2 10 WM8805_6152_DS28_EV1_REV3 Preliminary Customer Information To configure this path, with an audio interface format of 24 bit I2S, the external jumpers should be set as shown inTable 10. Do not fit H2 links. JUMPERS JUMPER STATUS J12 DESCRIPTION 2–3 Audio Interface Master/Slave Select Select slave mode 1–2 Audio Interface Configuration 0 High 2–3 Audio Interface Configuration 1 Low 2–3 Hardware/Software Mode Select Hardware mode 2–3 S/PDIF Transmitter Source Select S/PDIF received data 2–3 S/PDIF Input 0 Source Select Optical input selected 1–2 S/PDIF Input 0 Routing Route input 0 to WM8805 Rx0 input J16 J13 J15 J17 J29 H1 Table 10 S/PDIF RX0 Input Path to S/PDIF TX Link Settings The jumpers, input signals and output signals are shown in Figure 4. The yellow jumpers are those that are required. Channel RX0 (optical)selected USB input S/PDIF Rx Digital input. (Optical connection) Select Slave Mode AIF_CONF[1] Select hardware Mode AIF_CONF[0] SPDIFTx source = SPDIFRx S/PDIF Tx Digital output Figure 4 S/PDIF RX0 (optical) Input Path to S/PDIF TX Output Evaluation Board Configuration w Preliminary Customer Information September 2007, Rev 3.2 11 WM8805_6152_DS28_EV1_REV3 Preliminary Customer Information AIF TO S/PDIF TRANSMITTER The configuration is as follows :• Data path = AIF to S/PDIF TX • Hardware slave mode. • Powered from the USB interface. • AIF format = 24 bit I2S • Figure 5 illustrates the data path. • Figure 6 illustrates the jumpers which must be made on the board. Figure 5 Audio Interface to TX0 Block Diagram w Preliminary Customer Information September 2007, Rev 3.2 12 WM8805_6152_DS28_EV1_REV3 Preliminary Customer Information To configure this path, with an audio interface format of 24 bit I2S, the external jumpers should be set as shown in Table 11. Do not fit H2 links. JUMPERS JUMPER STATUS J12 DESCRIPTION 2–3 Audio Interface Master/Slave Select Select slave mode 1–2 Audio Interface Configuration 0 High 2–3 Audio Interface Configuration 1 Low 2–3 Hardware/Software Mode Select Hardware mode 1–2 S/PDIF Transmitter Source Select Audio interface received data J16 J13 J15 J17 Table 11 AIF Input Path to S/PDIF TX Link Settings The jumpers, input signals and output signals are shown in Figure 6. The yellow jumpers are those that are required. USB input Select Slave Mode AIF_CONF[1] Select hardware Mode AIF_CONF[0] SPDIFTx source = AIF MCLK LRCLK BCLK DIN (AIF Rx) S/PDIF Tx Digital output Figure 6 AIF Input Path to S/PDIF TX Output Evaluation Board Configuration w Preliminary Customer Information September 2007, Rev 3.2 13 WM8805_6152_DS28_EV1_REV3 Preliminary Customer Information SOFTWARE MODE EXAMPLES S/PDIF RECEIVER RX1 TO AIF The configuration is as follows:• Data path = S/PDIF RX1 (electrical input) to AIF DOUT • Software slave mode. 3-wire control interface • Powered from the USB interface. • AIF format = 24 bit I2S • Figure 7 illustrates the data path. • Figure 8 illustrates the jumpers which must be made on the board. CLKOUT XIN PLL and Clock Recovery XOP RX0 100n S/PDIF Receiver 75R RX1 S/PDIF Transmitter 100n TX0 75R 75R RX3 100n 75R RX4/GPO3 100n 75R RX5/GPO4 100n Input Selector RX2 100n 75R 100n GPIO Controller 75R 100n Digital Audio Interface Control Interface W PGND DIN BCLK LRCLK MCLK DOUT CSB / GPO2 SDOUT/GPO7 SDIN/HWMODE SCLK RESETB GPO1 GPO0 /SWIFMODE DVDD WM8805 75R DGND RX7/GPO6 PVDD RX6/GPO5 Figure 7 S/PDIF Rx1 to Audio Interface Block Diagram To configure this path, with an audio interface format of 24 bit I2S, the external jumpers should be set as shown in Table 12 and the registers programmed as in Table 13 JUMPERS JUMPER STATUS J13 DESCRIPTION 1–2 Control Interface Mode Select Select 3-wire (SPI compatible) mode 1–2 Hardware/Software Mode Select Software mode J15 Table 12 Jumper Settings for S/PDIF Rx1 to Audio Interface w Preliminary Customer Information September 2007, Rev 3.2 14 WM8805_6152_DS28_EV1_REV3 Preliminary Customer Information REGISTER SETTING 0x00 0x00 Reset device COMMENT 0x1E 0x04 Disable the S/PDIF Tx interface 0x08 0x01 Select S/PDIF Rx1 channel input 0x09 0x02 Select the comparator input mode for Rx1 0x1B 0x0A AIF Tx = 24 bit, I S 0x1C 0x0A Slave mode, AIF Rx = 24 bit, I S 2 2 Table 13 Register Settings for S/PDIF Rx1 to Audio Interface The jumpers, input signals and output signals are shown in Table 8. The yellow jumpers are those that are required. USB input H2 populated for s/ware control Channel RX1 selected 3-wire control Select software Mode S/PDIF Rx1 Digital input. (Electrical connection) MCLK LRCLK BCLK DOUT Figure 8 RX1 Input Path to Audio Interface Evaluation Board Configuration w Preliminary Customer Information September 2007, Rev 3.2 15 WM8805_6152_DS28_EV1_REV3 Preliminary Customer Information S/PDIF RECEIVER RX4 TO S/PDIF TRANSMITTER The configuration is as follows:• Data path = S/PDIF RX4 (electrical input) CMOS compatible to S/PDIF Tx • Software Mater mode. 2-wire control interface. Address=0x76. • Powered from external power supplies. • AIF format = 24 bit I2S • Figure 9 illustrates the data path. • Figure 10 illustrates the jumpers which must be made on the board. CLKOUT XIN PLL and Clock Recovery XOP RX0 100n S/PDIF Receiver 75R RX1 S/PDIF Transmitter 100n TX0 75R 100n 75R RX3 100n 75R RX4/GPO3 100n 75R RX5/GPO4 100n Input Selector RX2 75R 100n GPIO Controller 75R Digital Audio Interface Control Interface W PGND DIN BCLK LRCLK MCLK DOUT CSB / GPO2 SDOUT/GPO7 SDIN/HWMODE SCLK RESETB GPO1 GPO0 /SWIFMODE DVDD WM8805 75R DGND RX7/GPO6 100n PVDD RX6/GPO5 Figure 9 Rx4 to TX0 Block Diagram To configure this path, with an audio interface format of 24 bit I2S, the external jumpers should be set as shown in Table 14 and the registers programmed as in Table 15. JUMPERS JUMPER STATUS J13 DESCRIPTION 2–3 Control Interface Mode Select Select 2-wire (I2C compatible) mode 1–2 Hardware/Software Mode Select Software mode J15 J17 1–2 2 Wire/I2C Mode Device Address 0x76 Table 14 Jumper Settings for S/PDIF Rx4 to S/PDIF Tx w Preliminary Customer Information September 2007, Rev 3.2 16 WM8805_6152_DS28_EV1_REV3 Preliminary Customer Information REGISTER SETTING 0x00 0x00 Reset device COMMENT 0x1E 0x10 Disable the AIF 0x08 0x04 Select S/PDIF Rx4 channel input 0x09 0x00 Select the CMOS compatible input mode for Rx4 0x15 0x31 S/PDIF Tx source= S/PDIF Rx 0x1B 0x0A AIF Tx = 24 bit, I S 0x1C 0x4A Master mode, AIF Rx = 24 bit, I S 2 2 Table 15 Register Settings for S/PDIF Rx4 to S/PDIF Tx The jumpers, input signals and output signals are shown in Figure 10. The yellow jumpers are those that are required. +3.3V 0V +3.3V 0V +5V External power links selected USB input S/PDIF Rx4 Digital input. (Electrical connection) H1, link 5-6 Channel RX4 selected H2 populated for s/ware control. Remove link1-2 for 2-wire control 2-wire control H4, link 9-10 Removed Select software Mode 2-wire device address 0x76 S/PDIF Tx Digital output Figure 10 S/PDIF RX4 Input to S/PDIF Tx Configuration w Preliminary Customer Information September 2007, Rev 3.2 17 WM8805_6152_DS28_EV1_REV3 Preliminary Customer Information S/PDIF RECEIVER AUDIO DEMONSTRATION DAC The following configuration illustrates the S/PDIF Rx to analogue output via the WM8726 DAC. This can be used to view an analogue representation of the digital data received on the selected S/PDIF Rx interface. Note that the AIF should not be connected to any other test equipment if using this output. This example also illustrates the connections needed when using an external power source instead of powering the board from the USB interface. The configuration is as follows:• Data path = S/PDIF Rx2 to AIF • Software Mater mode. 2-wire control interface. Address=0x74. • Powered from external power supplies. • AIF format = 24 bit I2S Figure 11 illustrates the jumpers which must be made on the board. The jumpers needed for external power supply are detailed in Table 1. Other external jumpers should be set as shown in Table 16 and the registers programmed as in Table 17. JUMPERS JUMPER STATUS DESCRIPTION J13 CONTROL INTERFACE MODE SELECT Select 2-wire (I2C compatible) mode 2–3 J15 HARDWARE/SOFTWARE MODE SELECT Software mode 1–2 J17 2 WIRE/I2C MODE Device Address =0x74 2–3 Table 16 Jumper Settings for S/PDIF Rx1 to Audio Interface REGISTER SETTING 0x00 0x00 Reset device COMMENT 0x1E 0x04 Disable the S/PDIF Tx interface 0x08 0x02 Select S/PDIF Rx2 channel input 0x09 0x04 Select the comparator input mode for Rx2 0x1B 0x0A AIF Tx = 24 bit, I S 0x1C 0x4A Master mode, AIF Rx = 24 bit, I S 2 2 Table 17 Register Settings for S/PDIF Rx2 to Audio Interface w Preliminary Customer Information September 2007, Rev 3.2 18 Preliminary Customer Information WM8805_6152_DS28_EV1_REV3 Figure 11 DAC Evaluation Board Configuration w Preliminary Customer Information September 2007, Rev 3.2 19 WM8805_6152_DS28_EV1_REV3 Preliminary Customer Information APPLICATION SUPPORT If you require more information or require technical support, please contact the Wolfson Microelectronics Applications group through the following channels: Email: Telephone Apps: Fax: Mail: [email protected] +44 (0) 131 272 7070 +44 (0) 131 272 7001 Applications Engineering at the address on the last page or contact your local Wolfson representative. Additional information may be made available on our web site at: http://www.wolfsonmicro.com w Preliminary Customer Information September 2007, Rev 3.2 20 Preliminary Customer Information WM8805_6152_DS28_EV1_REV3 IMPORTANT NOTICE Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice. Customers should therefore obtain the latest version of relevant information from Wolfson to verify that the information is current. Testing and other quality control techniques are utilised to the extent Wolfson deems necessary to support its warranty. Specific testing of all parameters of each device is not necessarily performed unless required by law or regulation. In order to minimise risks associated with customer applications, the customer must use adequate design and operating safeguards to minimise inherent or procedural hazards. Wolfson is not liable for applications assistance or customer product design. The customer is solely responsible for its selection and use of Wolfson products. Wolfson is not liable for such selection or use nor for use of any circuitry other than circuitry entirely embodied in a Wolfson product. Wolfson’s products are not intended for use in life support systems, appliances, nuclear systems or systems where malfunction can reasonably be expected to result in personal injury, death or severe property or environmental damage. Any use of products by the customer for such purposes is at the customer’s own risk. Wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other intellectual property right of Wolfson covering or relating to any combination, machine, or process in which its products or services might be or are used. Any provision or publication of any third party’s products or services does not constitute Wolfson’s approval, licence, warranty or endorsement thereof. Any third party trade marks contained in this document belong to the respective third party owner. Reproduction of information from Wolfson datasheets is permissible only if reproduction is without alteration and is accompanied by all associated copyright, proprietary and other notices (including this notice) and conditions. Wolfson is not liable for any unauthorised alteration of such information or for any reliance placed thereon. Any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in this datasheet or in Wolfson’s standard terms and conditions of sale, delivery and payment are made, given and/or accepted at that person’s own risk. Wolfson is not liable for any such representations, warranties or liabilities or for any reliance placed thereon by any person. ADDRESS: Wolfson Microelectronics plc Westfield House 26 Westfield Road Edinburgh EH11 2QB United Kingdom Tel :: +44 (0)131 272 7000 Fax :: +44 (0)131 272 7001 Email :: [email protected] w Preliminary Customer Information September 2007, Rev 3.2 21