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AK5394A to CS5381 Conversion
by Kevin L Tretter
1. Introduction
The CS5381 is a complete analog-to-digital converter for digital audio systems. The CS5381 performs
sampling, analog-to-digital conversion and anti-alias filtering, generating 24-bit values for both left and
right channels.
The CS5381 offers some unique advantages over the AK5394A including:
-
Over 70% REDUCTION in package size (TSSOP)
-
50% less power consumption
-
Fewer external components required (See Section 2)
-
Overflow detect
-
Integrated level shifters
-
Over 80% less group delay (48kHz output sample rate)
Table 1 shows a comparison of the key specifications of these two devices.
AK5394A
CS5381
Conversion (Bits)
24
24
Dynamic Range (A-weighted)
dB
123*
120
THD+N
dB
-110*
-110
Analog Core Power Supply (VA)
V
+5.0 V
+5.0 V
Digital Core Power Supply (VD)
+3.3 V to +5.0 V
+3.3 V to +5.0 V
Digital Interface Power Supply (VL)
N/A
+2.5 V to +5.0 V
Maximum Power
mW
870
348
Maximum Sample Rate
kHz
216
200
Package
28-pin SOP
24-pin SOIC/TSSOP
* Dynamic Range and THD+N specified with different input buffer topologies
Table 1. Comparison of Key Specifications
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Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
JUL ‘03
AN234REV1
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2. Typical Connection Diagrams
+5 V to 3.3 V
+
1 µF
0.1 µF
*
+5V
+
1 µF
0.1 µF
VD
VL
FILT+
200 µF
+
VL
0.1 µF
10 k
REFGND
+
+5V to 2.5V
1 µF
0.1 µF
5.1 Ω
VA
+
0.1 µF
1 µF
0.1 µF
OVFL
RST
I2S/LJ
M/S
HPF
M0
M1
MDIV
VQ
Analog
Input
Buffer
(Section 8)
AINL+
CS5381
A/D CONVERTER
Power Down
and Mode
Settings
AINLAudio Data
Processor
SDOUT
Analog
Input
Buffer
(Section 8)
LRCK
AINR+
Timing Logic
and Clock
SCLK
MCLK
AINR-
* Resistor may only
GND
GND
be used if VD is
derived from VA. If
used, do not drive
any other logic
from VD.
Figure 1. CS5381 Typical Connection Diagram
+5V
+
10 µF
0.1µF
0.1µF
+5V to 3.3V
10µF
VD
VA
VREFL+
C* +
+
0.22 µF
C* +
VREFL-
0.22 µF
AINL+
Analog
Input
Buffer
(Section 8)
ZCAL
RST
CAL
VCOML
AK5394A
A/D CONVERTER
HPFE
SMODE2
SMODE1
DFS0
DFS1
Reset and
Calibration
Control
Mode
Control
AINLAudio Data
Processor
SDATA
AINR+
Analog
Input
Buffer
(Section 8)
LRCK
SCLK
FSYNC
AINRC* +
C* +
Timing Logic
and Clock
MCLK
VREFR+
0.22 µF
VREFR-
0.22 µF
* See Section 9
VCOMR
AGND
BGND
DGND
Figure 2. AK5394A Typical Connection Diagram
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3. Pin Compatibility
Table 1 shows the pins of the AK5394A and the corresponding pins of the CS5381. Please note that the
AK5394A has 28 pins, and the CS5381 has 24 pins.
AK5394A
Pin Number
1, 28
2, 27
3, 26
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Pin Name
VREFL+, VREFR+
VREFL-, VREFRVCOML, VCOMR
AINL+
AINLZCAL
VD
DGND
CAL
RST
SMODE2
SMODE1
LRCK
SCLK
SDATA
FSYNC
MCLK
DFS0
HPFE
DFS1
BGND
AGND
VA
AINRAINR+
CS5381
Pin Number
24
23
22
16
17
6
7
1
12
2
3
4
9
5
13
11
14
18
19
20
21
8
10
15
Description
Pin Name
FILT+
REFGND
VQ
AINL+
AINLVD
GND
RST
I2S/LJ
M/S
LRCK
SCLK
SDOUT
MCLK
M0
HPF
M1
GND
VA
AINRAINR+
VL
MDIV
OVFL
Positive reference voltage
Ground reference
Internal quiescent reference voltage
Differential Left Channel Input
Differential Left Channel Input
Zero Calibration Control
Digital power
Ground reference
Calibration Active Signal
Reset
Digital Interface Format Select
Master/Slave Mode Select
Left right clock
Serial clock
Serial data
Frame Synchronization Signal
Master clock
Mode selection
High Pass Filter Enable
Mode selection
Substrate Ground
Ground reference
Analog power
Differential Right Channel Input
Differential Right Channel Input
Logic Power
MCLK divider
Overflow
Table 2. Pin Compatibility Between AK5394A and CS5381
4. Offset Calibration
The CS5381, and AK5394A all have offset calibration capability. However, the calibration process varies
slightly between the AK5394A and the CS5381.
4.1 CS5381
The CS5381 implements a high pass filter that can be controlled via the HPF pin (pin 11). The high pass
filter continuously subtracts a measure of the DC offset from the output of the decimation filter. If the HPF
pin is taken high during normal operation, the current value of the DC offset register is frozen and this DC
offset will continue to be subtracted from the conversion result.
A system calibration can then be performed by first running the CS5381 with the high pass filter enabled
(HPF = LOW) until the filter settles. At this point, disable the high pass filter (HPF = HI), thereby freezing
the stored DC offset.
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4.2 AK5394A
The AK5394A will automatically initiate a calibration sequence following a reset. The CAL pin (pin 9) is an
output that indicates when a calibration sequence is in progress. This calibration technique is very similar
to that described above for the CS5381.
The AK5394A also has a ZCAL pin (pin 6) which allows the calibration input to be obtained from either
the analog input pins or the VCOM pins. The high pass filter can be controlled via the HPFE pin (pin 19).
In the AK5394A, the high pass filter is either continuously running or completely removed from the signal
path.
5. Master/Slave Selection and Digital Interface Format
The CS5381 and AK5394A are pin compatible in terms of selecting Master/Slave operation and digitial
interface format. The pins match up as noted in Table 2.
6. Speed Mode Selection
The AK5394A supports three speed modes, “normal”, “double”, and “quad” as determined by the DFS0
and DFS1 pins (pins 18 and 20 respectively). These pins are compatible with the M0 and M1 pins (pins
13 and 14) of the CS5381, as shown in Table 2.
7. System Clocking
The CS5381 is fully compatible with the clocking requirements of the AK5394A. However, there is a slight
difference when operating in Master mode. When operating in “normal” mode, the AK5394A will generate
an SCLK that is 128×Fs. The CS5381 generates an SCLK that is 64×Fs.
The CS5381 offers an integrated MCLK divider, which can be controlled via the MDIV pin (pin 10). This
pin allows multiple external MCLK/LRCK ratios to be supported. In order to maintain complete compatibility between the AK5394A and the CS5381, connect the MDIV pin (pin 10) of the CS5381 to GND.
8. Input Buffer Topology
The analog input buffers shown in Figures 9 and 10 of the AK5394A datasheet (dated January, 2002) will
also work for the CS5381. In this case, the “Bias” reference (in Figure 9) should be sourced from the VQ
pin of the CS5381. However, these input buffers require a large input voltage level at the input to the buffer
and attenuate the signal prior to the converter. This much signal swing is not always possible in a real
system, and not necessary to achieve the full performance of the CS5381.
The following sections contain a description of a single-ended to differential input buffer (comparable to
Figure 9 of the AK5394A datasheet) and a fully differential input buffer (comparable to Figure 10 of the
AK5394A datasheet). These two buffer topologies are unity gain, and therefore do not rely on a large input
voltage at the buffer input.
8.1 Single-Ended to Differential Input Buffer
Figure 3 shows a single-ended to differential analog input buffer. This buffer provides the proper biasing,
isolation from the switched capacitor currents, low output impedance, and anti-alias filtering. The second
op-amp stage is set up in an inverting configuration to produce the negative node of the differential input.
In the input buffer shown below, the second stage has unity gain, and the single-ended input level will
effectively be doubled when presented differentially to the converter. For example, a 2.8 Vpp single-ended input will provide a full-scale 5.6 Vpp differential input to the CS5381.
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634 Ω
470 pF
C0G
CS5381
91 Ω
-
1 µF
AIN+
+
634 Ω
634 Ω
100 kΩ
VA
2700 pF
C0G
470 pF
C0G
100 kΩ
3.3 kΩ
91 Ω
-
AIN-
+
3.3 kΩ
0.01 µF
100 µF
1 µF
0.01 µF
VQ
634 Ω
470 pF
C0G
91 Ω
-
1 µF
AIN+
+
634 Ω
634 Ω
100 kΩ
VA
2700 pF
C0G
470 pF
C0G
100 kΩ
3.3 kΩ
91 Ω
-
AIN-
+
3.3 kΩ
0.01 µF
100 µF
Figure 3. Single-Ended to Differential Input Buffer
8.2 Fully Differential Input Buffer
Figure 4 shows a fully differential analog input buffer. This buffer provides the proper biasing, isolation
from the switched capacitor currents, low output impedance, and anti-alias filtering. This input buffer is
unity gain, so a 5.6 Vpp differential input will provide a full-scale 5.6 Vpp differential input into the CS5381.
634 Ω
470 pF
C0G
10 µF
100 kΩ
CS5381
91 Ω
634 Ω
10 kΩ
2700 pF
C0G
470 pF
10 kΩ
100 kΩ
AIN+
+
0.01 µF
-
C0G
91 Ω
AIN-
+
10 µF
VQ
1 µF
0.01 µF
634 Ω
470 pF
10 µF
100 kΩ
C0G
91 Ω
AIN+
+
634 Ω
10 kΩ
2700 pF
C0G
470 pF
10 kΩ
0.01 µF
-
C0G
91 Ω
AIN-
+
100 kΩ
10 µF
Figure 4. Fully Differential Input Buffer
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9. Capacitor Size on Reference Voltage Pin(s)
The CS5381 and the AK5394A both require external capacitance on the internal reference voltage pin(s).
On the CS5381, the internal reference voltage is output on FILT+ (pin 24). The AK5394A has four such
pins, VREFL+, VREFL-, VREFR-, and VREFR+ (pins 1, 2, 27, and 28 respectively). Each of these pins
require a large capacitor for noise decoupling. Please refer to Figure 12 of the AK5394A datasheet (dated
January, 2002) for a plot of distortion versus frequency with various capacitor values on these reference
pins.
For comparison, the same plot has been generated using the CS5381, as can be seen in Figure 5. Please
note that the CS5381 requires ONE such capacitor, while the AK5394A requires FOUR such capacitors.
CS5381 THD+N vs Frequency
-1dBFS Input
-60
-70
220 µF
100 µF
-80
d
B
F
S
-90
10 µF
-100
-110
-120
1000 µF
-130
10
20
470 µF
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 5. CS5381 THD+N vs. Frequency
A comparison between Figure 12 of the AK5394A datasheet and the above plot of the CS5381 reveals
that the CS5381 has better low frequency distortion performance for a given capacitor value, and requires
only one capacitor as opposed to the four that are required for the AK5394A.
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Contacting Cirrus Logic Support
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http://www.cirrus.com/
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