AN 5950 - Dynex Semiconductor Ltd.

AN 5950
Understanding i2 Phase
Control Thyristor Datasheets
Application Note
AN5950-1 Sept 2009 LN26885
Authors: Dinesh Chamund, Colin Rout

INTRODUCTION
This note will guide you through the Dynex i2
Phase Control Thyristor data sheet format and
explain its contents. For the purpose of
discussion and illustration, Dynex datasheet
for the DCR3030V42 has been chosen and its
contents explained in sequence starting from
the first page.
The i2 Phase Control Thyristor datasheet
includes tables and graphs of data regarding
device ratings and characteristics. In order to
use the datasheet properly it is important that
the user has a good understanding of the
information presented in the datasheet. Also
when benchmarking with similar product from
a different supplier, allowance should be
made for any difference in the way the
parameters are defined, specified and
measured. Hopefully this will promote an
efficient and reliable use of the device and
also help the user to make a correct choice of
device for the intended application.
The datasheet is organised in the following
sections:







PART NUMBER
FEATURES
APPLICATIONS
TABLE OF VOLTAGE RATINGS
ORDERING INFORMATION
KEY PARAMETERS/PACKAGE OUTLINE
TABLES OF RATINGS
o CURRENT RATINGS
o SURGE RATINGS
o THERMAL AND MECHANICAL
RATINGS


TABLES OF CHARACTERISTICS
o DYNAMIC CHARACTERISTICS
o GATE CHARACTERISTICS
CURVES
PACKAGE DETAILS
PART NUMBER
DCR3030V42
The part numbering scheme for the Dynex i2
Phase Control Thyristor is as follows:
DCR
= Dynex Control Rectifier
3030
= Headline average current rating (A)
V
= Package code
42
=
Maximum
repetitive
voltage
rating (V)/100
A Dynex datasheet is a controlled document
with a specific document number, issue
number, and date. This information appears
below the device type in the header on the
right hand side of the first page . Dynex
reserves the right to change the data without
notice and so the users are advised to refer to
the latest version by visiting Dynex web site:
http://www.dynexsemi.com
KEY PARAMETERS/PACKAGE OUTLINE
This is a summary of main parameters unique
to the part number. The full description of
these parameters is found with appropriate
test conditions in the main body of the
Page 1 of 23
AN 5950
datasheet. It is important that when
comparing the key parameters with other
similar product a full description of the
parameters should be considered as
manufacturers often specify different test
conditions.
TABLE OF VOLTAGE RATINGS
This table provides the repetitive peak voltage
ratings of the device given under specified
conditions.
Fig.1 gives the package outline and its code
(V).
Fig. 1 Package outline
FEATURES
The features section provides a list of specific
key attributes of the device design and
technologies.
APPLICATIONS
A few examples of possible application are
indicated here. It should be noted that
inclusion in this section does not imply that
Dynex has fully tested the device under all
application conditions. The suitability of a
device for a given application rests solely with
the user.
Page 2 of 23
VDRM, VRRM are the peak repetitive voltages in
the (direct) forward and reverse directions.
The rating is for 50Hz half sine waves of
voltage and assumes that the device is
maintained at the maximum rated junction
temperature of 125°C by suitable heatsinking,
if required. VDRM & VRRM are the voltages that
the device reaches when the leakage currents
IRDM &IRRM reach their test limits as given in the
datasheet, or the maximum rated voltage
whichever is reached first. The device may
well be capable of reaching a higher voltage
but excessively large leakage currents will
make temperature control difficult and failure
through thermal run-away may occur for all
but the shortest pulses.
As the temperature of the device is reduced,
the natural avalanche voltage of the silicon
wafer reduces. In some cases, at very low
temperatures and at the lower limit of the
tolerance on the silicon specification the full
voltage rating of the device may not be
achieved. Where this is the case, this is
annotated on the datasheet.
Because of transient voltage spikes generated
by switching devices on the supply, thyristors
are usually operated at nominal peak line
voltages of VDRM divided by a safety factor of
1.5 to 2.5, depending on the transient
voltages. A low safety factor is used when the
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transients are largely determined, usually in
the case of self commutated converters with
large energy storage elements. If the
transients on the mains supply are unknown
then a safety factor of 2 to 2.5 should be
used.
VDSM & VRSM are the peak non-repetitive
voltages in the forward and reverse directions
and are the voltages that can be applied
occasionally and non-repetitively and should
not be exceeded under any circumstances.
ORDERING INFORMATION
This specifies the correct part number for
ordering the device, for example:
DCR3030V42 (4200V part)
Other voltage grades can be selected as given
in the table of voltage ratings.
TABLES OF RATINGS

CURRENT RATINGS
IT(AV) – Mean on-state current
IT(AV) is the average value of a half sine wave
current flowing in a thyristor such that the
peak junction temperature is limited to the
rated temperature of 125°C with the case
temperature specified. The average current
rating of the device is related to the thermal
rating of the device package and thus by
equating the power generated within the
device to the power dissipated in the package,
the average current rating can be calculated.
A more thorough analysis of the current rating
derivation is given in the Appendix 1.
There is no industry standard definition for
IT(AV), manufacturers quote IT(AV) with case
temperatures of 60°C, 65°C, 70°C and 85°C .
Others quote with respect to a heatsink
temperature of 55°C (see Fig.17 Appendix 1).
Thus direct comparison of headline ratings is
very difficult. Even if all manufacturers quoted
at the same case temperature this would still
not resolve the problem because, in reality,
what is really important in the application is
how the device performs on the heatsink.
Some manufacturers quote low values of
thermal resistance junction to case with
correspondingly higher values for thermal
resistance case to heatsink but with similar
thermals junction to heatsink. Therefore their
headline IT(AV) at a given case temperature may
be quoted as being higher than competitors’
devices but when rated on the same heatsink
there is no appreciable difference in
performance.
Dynex quotes a headline IT(AV) at 60°C case
temperature but gives full de-rating curves for
both half sine and rectangular waves to
enable the user to make direct and
meaningful comparisons.
IT(RMS) – RMS current rating
For today’s capsule devices IT(RMS) = π. IT(AV) /2.
Historically IT(RMS) could have been different
because, for single sided devices with a
flexible lead for the load current terminal, the
current carrying capability of the connections
could be less than the capability of the silicon.
For capsule (puk) devices, the cross sectional
area of the electrodes is the same as the
silicon so no allowance needs to be made. The
limitation is now the equipment busbars.
IT – Continuous (direct) on-state current
IT is the maximum continuous current that the
thyristor can conduct while maintaining the
junction temperature to its maximum rated
value of 125°C. Note that, like IT(AV) , this figure
depends upon the stated reference case
temperature.
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
SURGE RATING
ITSM – Surge (non-repetitive) on-state current
ITSM is the maximum 10ms half sine wave of
current, following maximum load current ( i.e.
the thyristor junction temperature is at Tj max)
that the thyristor can conduct without the
device experiencing thermal run-away and the
silicon melting. ITSM is determined by the
manufacturer by viewing the forward voltage
characteristic of the thyristor at high currents
and observing the onset of thermal run-away.
Exceeding this limit will damage the device
and the rating should only be used for the
selection of fuses. Because the device is so
hot following the surge current pulse it loses
its ability to block voltage, this rating is for
zero reverse re-applied voltage. Also the
temperature excursion is so high that the
device will fail due to temperature cycling
wear out if this level of current is repeated
several times in the life of the device. In
practice, Dynex derates the surge current limit
of its i2 thyristors by 10% which means that
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the device can survive about 100 occurrences
of the stated current in its life.
I2t – for fusing
I2t for fusing is
∫i dt and is calculated for a
2
half sine wave as
I2TSM.base width/2
As well as the single 10 ms half sine wave
rating, Dynex gives a graph showing the
ratings for shorter and longer pulses of
current with the corresponding I2t values;
figure 11 of the datasheet. These are derived
by calculating the current that gives the same
peak temperature as the 10ms half sine wave
derived from the physical rating of the device.
Again 100 occurrences in the life of the device
are permissible.
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
THERMAL AND MECHANICAL RATINGS
Rth(j-c) – Thermal resistance – junction to case
The thermal resistance enables the
calculation of the temperature rise of the
silicon in the device above the external case
temperature. It has the dimensions of °C/W
or K/W. In other words, if the device is
generating DC power losses P, then the
temperature rise of the junction above the
case temperature is P x R th(j-c). Values of the
thermal resistance are given for double side
cooling and cooling via either the anode or
cathode electrode.
Rth(c-h) – Thermal resistance – case to heatsink
Of course the reference point for temperature
rise for the user is the ultimate cooling
medium air, water, oil etc. The total thermal
resistance will include the thermal resistance
of the heat sink (fin) to ambient, which is the
user’s design choice and the contact thermal
resistance between the device contact surface
and the heat sink (Fig. 17 Appendix 1). This
resistance depends upon the quality of the
interface and the value quoted is with the
inclusion of a good quality thermally and
electrically conductive compound and with
the joint clamped to the median
recommended force.
Tvj – Virtual junction temperature
The device junction temperature cannot be
directly measured but is usually calculated
from a measured reference temperature e.g.
case or heat sink using the product of thermal
resistance value and the power dissipation.
Hence it is referred to as the virtual junction
temperature. The maximum value of Tvj is
limited by the blocking capability of the
device. This is set at 125°C. If this limit is
exceeded then the subsequent reliability of
the device operation cannot be guaranteed.
Tstg – Storage temperature range
During the storage of the device there are no
application stresses applied (blocking stress,
power losses etc) and hence the storage
temperature range is determined purely by
the withstand capability of the materials used
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in the construction of the device. The storage
temperature range is conservatively set at 55°C to 125°C.
Fm – Clamping force
Correct clamping of the device is necessary to
assure the electrical and thermal contact to
the active part of the device. The
recommended maximum and minimum force
is stated for each device type (see Appendix 3
and Application note AN4839).

DYNAMIC CHARACTERISTICS
IRRM/IDRM – Peak reverse and off-state current
IRRM and IDRM are the maximum blocking
currents when VRRM and VDRM are applied to
the device respectively. These currents are
temperature dependant and specified at Tcase
= 125°C and tp= 10ms. Note that for high
voltage devices the blocking current can
contribute substantially to the power losses.
dV/dt – Maximum Linear rate of rise of offstate voltage
This is the maximum value for the linear rate
of rise of forward voltage (from 0V to
67%VDRM) that can be applied without
initiating turn-on in the thyristor with the gate
open circuit. It is not advisable to exceed this
value as it will cause uncontrolled turn-on in
the device and may cause damage. It is usual
practice to protect the device against
excessive values of dV/dt by use of an
additional snubber circuit (RC or RCD snubber
circuit). The dV/dt capability of a thyristor
reduces with increasing temperature. This is
because triggering of the thyristor is initiated
by the sum of the junction leakage current,
the Cdv/dt displacement current and the gate
current. dV/dt is specified at Tcase = 125°C
which should be the worst case.
Page 6 of 23
dI/dt – Rate of rise of on-state current
This is the maximum rate of rise of on-state
current (load current) for which two values
are specified; repetitive @50Hz and nonrepetitive. These values are specified under
the conditions of forward blocking voltage of
67%VDRM, peak forward current of twice the
rated average current (2xIT(AV)), Tj = 125°C and
the gate conditions for each device type (gate
source voltage, gate resistance and the gate
current rise time). When a thyristor is
triggered on the initial conduction area is
small and hence the current carrying capacity
is limited. If the dI/dt rating is exceeded then
damage to the thyristor may occur. It is
advisable to control the dI/dt of the load
current by use of turn-on snubber circuit
(usually a clamped reactor). Note that the
dI/dt snubber discharge current should be
included in dI/dt considerations.
VT(TO) – Threshold voltage
For a simple calculation of conduction losses
of a thyristor, the on state IV characteristic is
approximated to a straight line and an
intercept on the voltage - axis. The intercept is
called the threshold voltage. Two values of
VT(TO) are given on the datasheets to give more
accurate approximations by splitting the IV
curve into a low level current range and a high
level current range.
rT – On-state slope resistance
The straight line in the above approximation is
also defined by a slope (dIT/dVT) = 1/rT where
rT is called the slope resistance (dVT/dIT). Once
again rT is specified for low and high level
current range respectively.
A full explanation of how VT(TO) and rT are
derived is given in the Appendix 2.
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tgd – Delay time
This is the gate controlled delay time defined
as the time interval during turn-on between
10% of the peak gate current IGT and 90% of
the anode voltage VD (see Fig.22 in Appendix
4). The value is specified under the conditions
of VD = 67%VDRM, Tj = 125°C, and gate
conditions for the given thyristor (gate source
= 30V, 10Ω and tr = 0.5µs).
tq – Turn-off time
The turn-off time tq is defined as the time
interval between the anode current reaching
zero value after the conduction period and
when the thyristor can withstand reapplied
positive anode voltage (see Fig. 23 Appendix
5). Assuming the dI/dt is slow then tq is a
function of Tvj, dI/dt, and dV/dt (see Figures
26, 27 and 28 in Appendix 6). tq is specified
under the conditions of Tj = 125°C, VR = 200V,
dI/dt = 1A/µs, and dVDR/dt = 20V/µs linear.
QS – Stored charge
This is defined as the time integral of the
reverse recovery current which flows when a
thyristor is reverse biased after forward
conduction (see Fig. 23 Appendix 5). The
value of QS is specified at Tj=125°C, the falling
rate of current (- dI/dt), reverse peak voltage
VRpk, and the reverse blocking voltage VRM.
The measurement is done with a suitable RC
snubber circuit to limit the peak voltage to the
specified limit. For practical reason the
integral is taken over the first 150µs of
recovery. Note that QS has the same meaning
as Qrr (reverse recovery charge) used
elsewhere. Qs is a function of dI/dt (Fig.12)
and Tvj (Fig. 24 in Appendix 6) assuming dI/dt
is slow.
IL – Latching current
The latching current is the minimum anode
current required to maintain the thyristor in
forward conduction state after turn-on has
been initiated and the gate signal is then
removed. Therefore the gate trigger current
should be maintained or repeated until the
anode current reaches this value under all
conditions.
IH – Holding current
The holding current is the minimum anode
current required to sustain the thyristor in
conduction after latching. The thyristor will
turn-off suddenly if the current through the
thyristor drops below the holding current. For
this reason care should be taken to eliminate
oscillations at low value of anode current.

GATE TRIGGER CHARACTERISTICS AND
RATINGS
VGT – Gate trigger voltage
This defines the minimum gate voltage
required to trigger the thyristor. The VGT is
specified at VDRM = 5V and Tcase = 25°C when
the thyristor is most immune to triggering.
VGD – Gate non-trigger voltage
The gate non-trigger voltage is defined as the
maximum gate voltage which will not trigger
the thyristor. It is specified at VDRM and Tcase =
125°C when the thyristor is most sensitive to
triggering.
IGT – Gate trigger current
This defines the minimum gate current
required to trigger the thyristor. IGT is a
function of anode to cathode voltage and
junction temperature. In the datasheet IGT is
specified at VDRM = 5V and Tcase = 25°C.
IGD – Gate non-trigger current
The gate non-trigger current is the maximum
gate current which will not trigger the
Page 7 of 23
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thyristor and is specified at VDRM and Tcase =
125°C.
Note that both VGD and IGD ratings are
important when operating a thyristor in a
Page 8 of 23
“noisy” environment where it is possible to
trigger the thyristor spuriously. Any
uncontrolled triggering of the thyristor can
lead to malfunction of the circuit operation
and possible damage to the device.
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CURVES
Maximum and
characteristics:
minimum
on-state
On-state power dissipation
7000
min 125°C
max 125°C
25°C
max 25°C
6000
Instantaneous on-state current IT - (A)
note that in contrast to the linear model using
VTO and rT this model gives an accurate
estimation of conduction losses over the
entire quoted current range.
Fig.3 and Fig.6 show maximum on-state
power dissipation as a function of mean onstate current IT(AV) for sinusoidal and
rectangular waves respectively. These are
based
on
the
maximum
on-state
characteristics at 125°C in Fig.2. A family of
curves is given for conduction angles ranging
from 30° to 180° and DC. The power loss
curves do not include any switching losses
(turn-on and turn-off losses).
5000
4000
3000
2000
1000
0
0.0
0.5
1.0
1.5
2.0
2.5
Instantaneous on-state voltage VT - (V)
Fig.2 Maximum & minimum on-state characteristics
Fig. 2 shows the graph of maximum and
minimum on-state characteristics of the
thyristor when it is in full conduction. The
instantaneous on-state currents and voltages
are plotted against each other at temperature
of 25°C and 125°C. These characteristics are
used for calculation of on-state power losses.
To facilitate the use of a computer for these
calculations, an analytical model equation is
also given for the voltage drop as a function of
current for a specified temperature. The
model is valid for a given range of thyristor
current and Tj = 125°C (isothermal operation).
The voltage drop model used here is:
 =  +  × ln  +  ×  +  × √
where A, B, C and D are the constants of the
curve fit of the equation to the measured
values. Note that in the model VTM is a
function of IT alone because isothermal
operation (no self heating due to device loss)
is assumed for the given current range. Also
Maximum permissible case temperature
Fig. 4 and Fig. 7 depict maximum permissible
case temperature for double side cooled
arrangement as a function of average current
for sine and rectangular waves respectively
and for conduction angles ranging from 30° to
180° and DC. These curves have been derived
for the maximum junction temperature of
125°C using the junction to case thermal
resistances for the appropriate waveforms
(see Table 9).
Maximum permissible heatsink temperature
Fig. 5 and Fig. 8 show the maximum
permissible heatsink temperature for double
side cooling, for sine and rectangular waves
with conduction angles ranging from 30° to
180° and DC. These curves are calculated for
the maximum junction temperature of 125°C
and using the junction to heatsink thermal
resistances for the given waveforms.
Thus from the curves of maximum power
dissipation and maximum permissible case
temperature, it is possible to calculate the
required heatsink thermal resistance for a
given ambient temperature.
Page 9 of 23
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Maximum
(limit)
transient
thermal
impedance – junction to case (°C/kW)
Fig. 9 gives the maximum transient thermal
impedance curve, junction to case, for double
side, anode side and cathode side cooling
arrangements. Note that the unit is in °C/kW.
The transient thermal impedance curve (Zth(jc)) gives the temperature response to a unit
power step (1 kW). If the time interval is
sufficiently long then the curve reaches the
steady state DC value given in the table of
Thermal and Mechanical Ratings. The Zth(j-c)
curve is obtained by thermal modelling of the
device using finite element (FE) method and is
verified by measurements. An analytical
equation of the curve is also given
represented by the sum of four exponential
terms:
=4
ℎ
 −
() =
 1 − 
−

=1
The curve fit parameters Ri and τi are given in
the table of Fig. 9. Zth(j-c)(t) is used to calculate
the device junction temperature for time
dependant power dissipation.
The two simplest and most common
waveforms are the half sine and rectangular
wave. With these repetitive wave shapes the
peak junction temperature reached is slightly
above that calculated using the average
power dissipation and increases with
decreasing conduction angle. To allow for this,
incremental values ΔZth dependent upon wave
shape are given in a table within Fig. 9. These
values should be added to the values of
appropriate Z th(j-c) (t) curve. Please note that
ΔZth values are given in °C/W.
Multi-cycle surge current
Fig. 10 shows the surge current, ITSM, as a
function of the number of 10ms half sine
wave pulses (50Hz) at Tcase = 125°C and with
Page 10 of 23
no reverse voltage applied (VR = 0 V). This
curve is derived by calculating the value of the
repetitive 50Hz current pulses that gives the
same peak temperature as the rated single
cycle surge current.
Single-cycle surge current
Fig. 11 shows the single-cycle, half-sine wave
surge current capability, ITSM, for varying pulse
width. Also on the same graph the
corresponding I2t values are given. These
variations are derived by calculating the
current that gives the same peak junction
temperature as the 10ms half-sine wave
derived from the physical rating of the device.
The test conditions are; Tcase = 125°C and VR =
0 V. Note that the device rating has been
derated by 10% so that about 100 pulses can
be tolerated over the life of the device.
Stored Charge
Fig. 12 gives the variation of stored charge
(same as recovered charge) as a function of
the rate of decay of on-state current (dI/dt).
The measurement conditions are Tj = 125°C,
VR(peak) = ~ 60% VDRM and VR = ~ 40% VDRM with
appropriate snubber to control the reverse
voltage. The maximum and the minimum
curves with model equations are given.
Reverse Recovery Current
In Fig. 13 the reverse recovery current
associated with the stored charge of Fig. 12 is
given. IRR is also a function of junction
temperature (see Fig. 26 in Appendix 6).
Gate Characteristics
Fig. 14 and Fig. 15 depict the gate
characteristics. These are the graphs of gate
voltage VGT v the gate current IGT with upper
and lower limit curves.
In Fig. 14 the regions of uncertain triggering
for -40°C, 25°C and 125°C are shown at the
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left of the area defined by the upper and
lower gate characteristic curves. Any areas on
the right of the dividing lines are the
preferred area of operation for each
respective temperature. The upper limit curve
gives the maximum values of VGT and IGT as
appear in the table of Gate Characteristics
and Ratings (e.g. VGT = 1.5V and IGT = 0.25A at
Tj = 25°C for DCR3030V42). The embedded
table in the Fig.14 gives the maximum
permitted peak gate power dissipation PGM
(Watts) for various pulse widths and
repetition rates.
For dynamic triggering, much higher peak
gate current is recommended and Fig. 15
gives extended gate characteristics to include
higher current and voltage range. Also on the
graph are lines of constant peak power. These
lines are the power limits corresponding to
the values in the table embedded in the Fig.
14. For further details on thyristor gate
triggering and characteristics please refer to
Application Note AN4840.
PACKAGE DETAILS
The outline drawing of the package is given in
the Fig. 16. Note that the same package type
is used for devices with different voltage
ratings. The particular device is highlighted in
the table provided, which gives the maximum
and minimum thickness appropriate to the
device type.
Page 11 of 23
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130
16
180
120
90
60
30
Mean power dissipation - (kW)
12
110
Maximum case temperature, T case ( o C )
14
180
120
90
60
30
120
10
8
6
4
2
100
90
80
70
60
50
40
30
20
10
0
0
0
1000
2000
3000
4000
5000
0
Mean on-state current, IT(AV) - (A)
1000
2000
3000
4000
5000
Mean on-state current, IT(AV) - (A)
Fig.3 On-state power dissipation – sine wave
Fig.4 Maximum permissible case temperature,
double side cooled – sine wave
12
180
120
90
60
30
100
10
Mean power dissipation - (kW)
Maximum heatsink temperature, T Heatsink - ( ° C)
125
75
50
25
8
6
d.c.
180
120
90
60
30
4
2
0
0
0
1000
2000
3000
4000
Mean on-state current, IT(AV) - (A)
Fig.5 Maximum permissible heatsink temperature,
double side cooled – sine wave
Page 12 of 23
0
1000
2000
3000
4000
5000
6000
Mean on-state current, IT(AV) - (A)
Fig.6 On-state power dissipation – rectangular wave
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125
d.c.
180
120
90
60
30
120
110
100
Maximum heatsink temperature Theatsink -( o C)
Maximum permissible case temperature , Tcase -(° C)
130
90
80
70
60
50
40
30
20
100
75
50
25
10
0
0
0
2000
4000
6000
Mean on-state current, IT(AV) - (A)
0
8000
1000
2000
3000
4000
5000
6000
Mean on-state current, IT(AV ) - (A)
Fig.7 Maximum permissible case temperature,
Fig.8 Maximum permissible heatsink temperature,
double side cooled – rectangular wave
double side cooled – rectangular wave
Double side cooled
20
18
16
Anode side cooled
Ri (°C/kW)
Ti (s)
Cathode side cooled Ri (°C/kW)
Cathode Sided Cooling
Ti (s)
14
1
0.9206
2
1.8299
3
3.4022
4
1.3044
0.00768
0.05795
0.40786
1.2085
0.9032
1.6719
3.0101
7.4269
0.00759
0.05365
0.31445
5.624
0.9478
2.0661
1.6884
13.0847
0.00784
0.06455
0.38944
4.1447
i 4
Z th   [ Ri  (1  exp(T / Ti )]
12
i 1
DRth(j-c) Conduction
10
Tables show the increments of thermal resistance Rth(j-c) when the device
operates at conduction angles other than d.c.
8
6
4
2
0
0.001
Ri (°C/kW)
Ti (s)
Double Side Cooling
Anode Side Cooling
Thermal Impedance ( °C/kW)
d.c.
180
120
90
60
30
0.01
0.1
1
10
Double side cooling
DZth (z)°C/W
q°
sine.
rect.
180
1.34
0.88
120
1.57
1.30
90
1.83
1.54
60
2.08
1.81
30
2.27
2.11
15
2.36
2.28
Anode Side Cooling
DZth (z)°C/w
q°
sine.
rect.
180
1.34
0.88
120
1.57
1.30
90
1.84
1.54
60
2.08
1.81
30
2.28
2.11
15
2.37
2.28
Cathode Sided Cooling
DZth (z)°C/W
q°
sine.
rect.
180 1.33
0.88
120 1.57
1.29
90
1.83
1.53
60
2.07
1.80
30
2.26
2.10
15
2.35
2.26
Time ( s )
Fig.9 Maximum (limit) transient thermal impedance – junction to case (°C/kW)
Page 13 of 23
AN 5950
100
25
Conditions:
Tcase= 125 C
VR = 0
half-sine wave
90
Conditions:
Tcase = 125 C
VR =0
Pulse width = 10ms
Surge current, ITSM- (kA)
Surge current, ITSM - (kA)
80
20
70
I2t
ITSM
60
15
50
40
10
I2t (MA2s)
100
30
20
5
10
0
10
1
10
Number of cycles
0
1
100
Fig.10 Multi-cycle surge current
10
Pulse width, tP - (ms)
100
Fig.11 Single-cycle surge current
600
18000
QSmax = 3397.4*(di/dt) 0.5061
16000
IRRmax = 48.236*(di/dt) 0.7553
500
Reverse recovery current, IRR - (A)
14000
Stored Charge, Q S - (uC)
12000
10000
8000
QSmin = 1357.3*(di/dt) 0.6271
6000
Conditions:
Tj = 125oC
VRpeak ~ 2500V
VRM ~ 1700V
snubber as appropriate to
control reverse voltages.
4000
2000
10
20
300
IRRmin = 29.853*(di/dt) 0.8222
200
Conditions:
Tj=125oC
VRpeak ~ 2500V
VRM ~ 1700V
snubber as approriate to control
reverse voltages
100
0
0
400
30
Rate of decay of on -state current, di/dt - (A/us)
0
0
10
20
Rate of decay of on-state current, di/dt - (A/us)
Fig. 12 Stored Charge
Page 14 of 23
Fig. 13 Reverse Recovery Current
30
AN 5950
10
9
8
Gate trigger voltage, VGT - (V)
7
Upper Limit
6
5
Preferred gate drive area
4
3
2
Tj = -40oC
Tj = 25oC
1
Lower Limit
Tj = 125o C
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Gate trigger current IGT, - (A)
Fig14 Gate Characteristics
30
Lower
Limit
Upper
Limit
5W
25
10W
20W
50W
Gate trigger voltage, VGT - (V)
20
100W
150W
-40C
15
10
5
0
0
1
2
3
4
5
6
7
8
9
Gate trigger current, IGT - (A)
Fig. 15 Gate characteristics
Page 15 of 23
10
AN 5950
PACKAGE DETAILS
For further package information, please contact Customer Services. All dimensions in mm, unless
stated otherwise. DO NOT SCALE.
3rd ANGLE PROJECTION
DO NOT SCALE
IF IN DOUBT ASK
HOLE Ø3.60 X 2.00
DEEP (IN BOTH
ELECTRODES)
20° OFFSET (NOM.)
TO GATE TUBE
Ø110.0 MAX.
Ø73.0 NOM.
Ø1.5
CATHODE
Device
DCR1474SV18
DCR1475SV28
DCR1476SV42
DCR1478SV48
DCR1574SV28
DCR1575SV42
DCR1576SV52
DCR4060V22
DCR3780V28
DCR3030V42
DCR2720V52
DCR2290V65
DCR1910V85
GATE
ANODE
Ø73.0 NOM.
FOR PACKAGE HEIGHT
SEE TABLE
NOMINAL WEIGHT 1160g
Lead length: 420mm
Lead terminal connector: M4 ring
Package outline type code: V
Fig.16Package outline
Page 16 of 23
Maximum Minimum
Thickness Thickness
(mm)
(mm)
27.265
26.515
27.34
26.59
27.57
26.82
27.69
26.94
27.34
26.59
27.57
26.82
27.69
26.94
27.265
26.515
27.34
26.59
27.57
26.82
27.69
26.94
27.95
27.2
28.31
27.56
AN 5950
APPENDIX 1:
() =
The Derivation of Average Current v Case
Temperature Curves using the linear
approximation to the Forward Volt Drop
curve.
The Forward voltage drop curve of a thyristor
can be approximated by the simple equation
 = () +  × 
(1)
−( ) + ( ) 2 −4  2 .  .( − ) ℎ ( −)
2 2 . 
Note that this is the average current rating
ignoring any reverse recovery losses or turnon losses that might need to be considered at
higher frequencies or high di/dt at turn-on or
turn-off. Also average current rating is
referenced to the case temperature.
Sometime the heatsink temperature (Fig. 17)
is used for the reference temperature and in
this case Rth(j-hs) is used in the calculations.
where VT(TO) is the threshold voltage and rT is
the slope resistance (see Appendix 2).
2
 = () × () + 
× 
(2)
2
 = () × () +  2 × ()
× 
(3)
where k is the form factor of the waveform,
IT(AV) is the average current and IRMS is the
RMS current.
The rise in junction temperature Tj above the
case temperature Tcase is given by
 −  =  × ℎ( −)
Junction Temperature (Tj)
Heat
The Power dissipated in the thyristor is given
by :
(7)
Rthj-c)
Case Temperature (Tc)
Rth(j-hs)
Rth(c-hs)
Heatsink Temperature (Ths)
Rth(hs-a)
Ambient Temperature Ta
(4)
Fig.17 Thermal Circuit
where Rth(j-c) is the thermal resistance from
junction to case corresponding to the form
factor k.
Re-arranging this give
=
 −
(5)
ℎ ( −)
Substituting this in equation (3) and rearranging
2
( 2 ×  ) × ()
+ () × () −
 −
ℎ ( −)
=0
(6)
Therefore, solving the quadratic equation (6)
for IT(AV) we have
Page 17 of 23
AN 5950
APPENDIX 2:
Linear model
characteristics:
of
Thyristor
on-state
IT
ΔIT
rT = ΔVT/ΔIT
ΔVT
IT(AV)
VT
3. A variation of Fig. 19 which uses two
straight lines instead of one to
approximate to the true curve. In this
version the lines pass through 1/6IT(AV)
and IT(AV) and also IT(AV)and 20 x
IT(AV).
4. As Fig 20. A tangential point
constructed such that the value of
IT(AV) calculated from IT(AV) = (-VT(TO)
(VT(TO)2 + 4*k2*rT*P))/2*k2*rT is the
same as that calculated by more
exacting methods. This method is a
variation of method 1). It has been
used to retrospectively calculate
meaningful values of VT0 and rT
where more accurate current rating
data already exists.
IT
VT(TO)
ΔIT
Fig.18 VT(TO) and rT @ tangent to IT(AV)
ΔVT
The linear approximation of the on-state
characteristics of a thyristor is modelled by a
straight line (piece-wise linear model) defined
by an intercept on the x-axis VT(TO) (called the
threshold voltage) and an inverse slope of the
line rT (called the slope resistance) as shown
in the Fig. 18. The construction of the straight
line leads to different definitions. Here are the
four variations:
1. As illustrated in Fig. 18 where the line
is tangent to the IV curve at the
average current.
2. As shown in Fig. 19 where a chord is
drawn through IT(AV) and 3xIT(AV). The
definition is commonly used for
thyristors. For rectifier diodes a chord
through 3IT(AV) and 5xIT(AV) sometimes
gives a better result.
Page 18 of 23
rT = ΔVT/ΔIT
3xIT(AV
)
IT(AV)
VT
VT(TO)
Fig. 19 VT(TO) and rT represented by a chord
Dynex uses a variant of (3) with two straight
lines; the first is a best fit straight line to the
actual high current part of the forward
voltage drop curve. A second line is then
calculated for the best fit to the remaining
low current part of the curve.
AN 5950
IT
APPENDIX 3:
ΔIT
ΔVT
Clamping force requirements:
rT = ΔVT/ΔIT
IT(AV)
VT
VT(TO)
Fig. 20 Variation of tangent method
Fig. 21 shows the dependence of the thermal
resistance Rth(j-c) as a function of clamping
force for a pressure contact thyristor. The
minimum and the maximum values are
chosen to be on the relatively flat portion of
the curve. It is recommended to clamp the
device using the value of the force between
the minimum and maximum values quoted on
the datasheets. Low value of clamping force
results in increase in the thermal resistance
and hence decreases in the device current
carrying capability. Too high clamping force
may reduce the device of thermal cycling
capability and hence the product life.
Limitations of VT(TO) and rT model
curve, ie where the straight line meets the
true curve. It can be seen that depending on
where a point is taken on the curve the
answers will be optimistic or pessimistic.
Definitions 1, 2 and 4 give adequate accuracy
up to 3 x IT(AV). The Dynex method gives
reasonable accuracy at low currents and very
good at the high current part of the curve and
lesser accuracy in the intermediate region.
For improved accuracy a mathematical model
is needed which approximates better to the
true curve. This is the four coefficient curve
for the equation given in the datasheet.
Rth(j-c)
Using any one of the first four models gives
the correct value of the conduction losses at
one or at most two points on the VTM vs IT
Fmin
Fmax
Clamping force Fm
Fig. 21 Dependence of Rth(j-c) on clamping
force Fm
Please also refer to Application Note AN4839
for further details on clamping of power
semiconductor devices.
Page 19 of 23
AN 5950
APPENDIX 4:
APPENDIX 5:
Thyristor turn-on Characteristics
Thyristor turn-off characteristics
IT
dIT/dt
VD
90%
IT(t)
VD(t)
t
tgd
IG
dIG/dt
IG(t)
90%
IGM
10%
t
tr
Fig. 22 Thyrisror turn-on waveforms
Fig. 23 Thyristor turn-off waveforms
The turn-on process in a thyristor from its
blocking state begins with the application of a
gate signal. The thyristor current cannot flow
instantaneously. A physical process called
conductivity modulation takes place before
the current is established in the thyristor. The
time taken to undergo this process is called
the turn-on delay time (td). This delay time is a
function of gate signal (gate current
amplitude IGM, rise time of the gate current
pulse tr and the pulse-width of the gate
current), the junction temperature Tj and offstate voltage Vd. For measurement purpose it
is defined as the time interval between the
gate current reaching 10% of its peak value
and when the anode voltage drops to 90% of
the applied forward blocking voltage VD (see
Fig. 22). On the datasheets it is called the gate
controlled delay time tgd.
Fig. 23 shows the schematic presentation of
the turn-off waveforms for a thyristor and
defines the dynamic parameters tq and QS
specified in the datasheets.
Page 20 of 23
The turn-off process in a thyristor begins
when the anode current falls below the
holding current. However the thyristor cannot
revert to the blocking state instantaneously
because of the charge storage phenomenon.
The stored charge in the thyristor has to be
removed by carrier recombination and the
reverse recovery process before a thyristor
can resume the blocking state. The time
taken to revert back to the blocking state is
called the turn-off time (tq). For measurement
purpose it is defined as shown in Fig. 23. For a
given switching application the off time
should be longer than the tq for a proper
circuit function. Recovery charge QS
AN 5950
contributes towards the switching loss per
pulse (see Application Note AN5951).
26 to 28 show the typical, normalised
dependence of tq on these conditions.
APPENDIX 6:
1.2
Dependence of Tq, Qs, and Irr on temperature
and commutation conditions
For most Phase Control Thyristor applications,
the turn-off di/dt can be classed as “slow”,
therefore the Stored Charge is independent of
the initial current. Curves of the variation of
Stored Charge and Reverse Recovery Current
on di/dt are given in the data sheet at a Tvj of
125°C. Figure 24 shows the typical normalised
dependence of Stored Charge on Tvj, while
figure 25 is the corresponding curve for the
Reverse Recovery Current.
Similarly (2) it can be shown that the time
needed for the thyristor to regain the ability
to block forward current ( tq) is dependent
upon temperature, di/dt and dV/dt. . Figures
Normalised Stored Charge Value
During conduction, current flow is achieved
through the injection of excess carriers
(charge) from the electrodes. As the forward
current decreases towards extinction, a
number of the excess carriers recombine at a
rate governed by the carrier lifetime. It can
be shown (1) that for fast rates of fall of the
forward current (di/dt) the Stored Charge is
dependent on the value of the forward
current and independent of the di/dt and
conversely, at slow values of di/dt the Stored
Charge is independent of the forward current
and dependent on the di/dt. The terms “fast”
and “slow” are relative and are determined by
the length of the current fall time relative to
the carrier lifetime.
0.8
0.6
0.4
0.2
0
0
20
40
60
80
100
120
140
Virtual Junction Temperature, Tvj - (oC)
Fig. 24 Variation of stored charge with
temperature
1.2
1.1
Normalised Reverse recovery current
The turn-off process in a thyristor begins
when the anode current falls below the
holding current. However the thyristor cannot
revert to the blocking state instantaneously
because of the stored charge phenomenon.
1
1
0.9
0.8
0.7
0.6
0
50
100
150
200
Junction temperature, Tvj - (oC)
Fig.25 Dependence of reverse recovery
current on junction temperature
Page 21 of 23
AN 5950
1.6
2.5
y = 0.2791e0.0102x
R² = 1
1.4
1.2
Normalised turn-off time
Normalised turn-off time
2
1.5
1
1
0.8
0.6
0.4
0.5
0.2
0
y = 0.178ln(x) + 0.4721
R² = 0.9976
0
0
50
100
150
200
Junction temperature TVJ (oC)
0
100
200
300
400
Rate of change of re-applied forward voltagedv/dt (V/us)
Fig. 26 Variation of tq with temperature
Fig. 28 Variation of tq with dV/dt
References:
(1) P.D.Taylor (1987) ‘Thyristor Design
and Realization’,Wiley, England. P. 67
(2) Fukui, H., Naito, M., and Terasawa, Y.
(1980). ‘One dimensional analysis of
reverse receovery and dV/dt
triggering characteristics of a
thyristor’. IEEE Trans. Elelctron.
Devices,ED-27, 596-602
1.6
Normalised Turn-off time
1.5
1.4
1.3
1.2
1.1
y = 0.119ln(x) + 1
R² = 1
1
0
20
40
60
80
100
Rate of decay of on-state current di/dt (A/us)
Fig. 27 Variation of tq with dI/dt
Page 22 of 23
AN 5950
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DYNEX SEMICONDUCTOR LIMITED
Phone: +(0) 1522 502753 / 502901
Doddington Road, Lincoln, Lincolnshire, LN6 3LF
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e-mail: [email protected]
Phone: +44 (0) 1522 500500
© Dynex Semiconductor 2003 TECHNICAL
DOCUMENTATION-NOT FOR RESALE.
Fax: +44 (0) 1522 500550
PRODUCED IN UNITED KINGDOM
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