An Embedded 90nm SONOS Flash EEPROM Utilizing Hot Electron Injection Programming and 2-Sided Hot Hole Injection Erase E. J. Prinz, G. L. Chindalore, K. Harber, C. M. Hong, C. B. Li, C. T. Swift Motorola Embedded Memory Center, 6501 William Cannon Dr., MD: OE341, Austin, Texas 78735, U.S.A. (512) 895-8443, Fax: (512) 895-8605, [email protected] Abstract A SONOS thin film storage non-volatile memory bitcell is programmed with hot electron injection, and erased with 2-sided hot hole injection from both the source and drain sides. Application of source-to-well reverse bias during programming reduces the programming current, and also enables peripheral voltage scaling to +/- 6V while maintaining a 1-10µsec byte programming time. The programmed charge in the thin film includes a secondary electron distribution above the channel area, reducing asymmetry between forward and reverse read currents. Erase is performed with band-toband tunneling induced hot hole injection from both source and drain sides. The bitcell effective channel length is less than twice the width of the hot hole profile injected into the storage film, such that both the primary and secondary electron peaks formed during programming can be compensated with holes during erase. The bitcell has been integrated into a common source NOR Flash EEPROM architecture and embedded into a 90nm high performance CMOS process with fully silicided sources and drains and a copper backend [1, 2]. Bitcell size can approach that of a diffusion ROM. Introduction Microcontrollers with embedded fast access time non-volatile memory (NVM) are utilized in applications such as automotive engine control for code and data storage. The established technology for these applications is floating gate bitcells in a common source NOR architecture, operated with various combinations of Fowler-Nordheim tunneling and hot electron injection . Voltage scaling has largely leveled off at ~9V due to the onset of stress-induced leakage current (after write/erase cycling) in tunnel oxides below 90Å [4, 5]. Fast byte programming time favors hot electron injection as a program mechanism. Parasitic drain current can be reduced somewhat by applying a source/well reverse bias . Due to simpler processing, NVM bitcells based on charge storage in non-conducting films such as SONOS have recently been considered, utilizing HCI programming and hot hole erase . Multi-bit storage has been shown in the NROM, requiring charge to be fully localized at the junction edges . In this work, an embedded NVM combining the process simplicity of thin film storage with reduced peripheral voltages, fast programming time, and reduced programming current is demonstrated. Bitcell Operation A bitcell (see Fig. 1) is operated with the voltages shown in Fig. 2. Programming is performed by hot electron injection with a source/well reverse bias of 2V. Erase is performed by 2-sided hot hole injection resulting from band-to-band tunneling with positive source/drain and negative gate voltages. Hot hole injection can be simultaneous from source and drain, or sequential. The bitcell is read and programmed in the same direction. The bitcell length is shorter than twice the width of the distribution of injected holes, such that the entire channel area can be covered by hot hole injection, as shown in Fig. 3. The programming time with 3V drain bias and -2V well-to-source reverse bias is in the 1-10µsec range, similar to what can be achieved with no reverse bias and increased drain and/or gate biases (see Fig. 4). The highest peripheral voltage required during program and erase factors prominently into Flash EEPROM module size. Therefore, a 6V gate voltage level is preferred over 9V. Among the three cases shown, the 3V drain and -2V well-to-source bias has the lowest programming current, as shown from the drain current/ drain voltage data in Fig. 5. Applying a back bias reduces the programming current by 40%. Programming with a reverse source/well bias results in a charge distribution in the nitride which is less localized as compared to the case with no reverse bias. Therefore, due to the limited extent of the distribution of injected hot holes, hot hole erase becomes less efficient with longer bitcells (see Fig. 6). For the bitcell considered, a bitcell length of less than 0.22µm is required for efficient 2-sided hot hole erase. The maximum erase current per side for 2-sided hot hole erase is in the 1-10nA range, as shown in the erase current curve of Fig. 7. The bitcell (W/L=0.27µm/0.22µm) has a read current at 1V gate overdrive of about 20µA, see Fig. 8. The localization of the charge distribution in the nitride can be assessed by comparing forward to reverse read operations (compared to the direction of HCI programming). It is shown in Fig. 8 that application of a reverse well-to-source bias greatly reduces the asymmetry, so the bitcell is operated with forward read. Even with fixed program/erase voltages and times, no charge is accumulated above the channel of the device, resulting in approximately flat program/erase cycling curves (see Fig. 9). Data retention and read disturb at 150°C after write/erase cycling demonstrates an operating window, as shown in Fig. 10. Preliminary data from a 0.25µm test chip (1024 bits of 3 parts) show an acceptable 0.7V charge loss (with no write/erase cycling) of the programmed state after 24 hours at 250°C (see Fig. 11). In the Flash EEPROM module, the bitcells are arranged in a common source NOR architecture with silicided active area source connections, similar to a diffusion ROM layout, as shown in Fig. 1. The bitcell size is reduced compared to a floating gate bitcell due to the absence of the floating gate pattern over field oxide separating two floating gates. Also, the application of reverse well-to-source bias enables further channel length scaling. Process Integration The bitcell shown above has been embedded into a 90nm high performance logic host process [1, 2]. The bitcell trench isolation module is shared with logic and peripheral transistors. The bitcell is located in a P-well which is fully isolated from the P-type substrate by a high energy implanted deep N-well. The charge-storing film consists of a 70Å-thick thermally grown bottom oxide, 150Å CVD nitride, and a 50Å top oxide thermally grown in steam ambient. All NVM-related high temperature processing steps are done before the low voltage logic well implants to maintain the logic transistor characteristics. The bitcell source/drains are implanted with prespacer arsenic extension and optional boron halo implants. The SONOS nitride in the bitcell source/drain areas is removed simultaneously with the gate poly antireflective coating, such that all sources, wordlines, and drains are fully silicided with cobalt silicide, resulting in a sheet resistance of about 10 /sq. A copper backend with 4 layers of metal has been used in this work. The bitcell processing adds 2-3 masks to the process. Conclusion An embedded non-volatile memory based on a common source NOR array of SONOS bitcells, operated with HCI programming with reverse source-to-well bias, and erased by 2-sided hot hole injection, has been proposed for the first time, and has been integrated into a 90nm high performance logic technology. Peripheral voltage reduction to +/- 6V has been achieved. The proposed memory is suitable for fast read access time even with large block sizes due to low source/drain resistance. Acknowledgments We acknowledge Bryan Acred, Jerry Peschke, and Sandra Altmeyer for technician support; Motorola MOS12, Dan Noble Center, and MOS13, for silicon fabrication; and Ko-Min Chang for managerial support. contact to bitline Program Erase Read -6V 2.5V hot hole injection from source secondary hot el. Injection hot hole injection from drain primary hot el. Injection drain 6V gate 435nm 0V wordline active area S source 360nm Fig. 1: Bitcell layout. W -2V 3V 5.5V D S G 5.5V 0V D W 0V 6V/3V/-2V/70Å 6V/5V/0V/70Å 9V/3.55V/0V/70Å 6V/3V/-2V/35Å 6V/5V/0V/35Å 9V/3.55V/0V/35Å 3 2 1 1.E-06 1.E-05 Programming Time (sec) Drain Current (µA) 4 3 "short" bitcells 2 1.E-05 1.E-03 Erase Time (sec) 2 3 4 Gate Voltage (V) 5 6 F: Vt(erased) R: Vt(erased) F: 6V/3V/-2V R: 6V/3V/-2V F: 6V/5V/0V R: 6V/5V/0V F: 9V/3.5V/0V R: 9V/3.5V/0V Vt (V) 1 2 3 4 Drain Voltage (V) 5 2-HHI Erase Bitcell Gate Length Vs=5V, Vg=-6V Bitcell Gate Length: 3 2 0.18µm 0.20µm 1 0.22µm 0.24µm 0 1 2 3 4 5 Fig. 7: Erase current vs. source/drain voltage (one shot curve) with and without negative gate bias. 6 4 2 0 -2 10000 100000 R/D: Vg=3.2V R/D: Vg=1.0V D/R: Vg=0.0V Fig. 10: Data retention and read disturb at 150°C vs. time after 10,000 program/erase cycles. References  S. Parihar et al., 2001 IEDM Tech. Dig., p. 11.4.1, 2001.  D. Burnett et al., 2000 NVSM Workshop, p. 59, 2000.  H.P. Belgal et al., Proc. 2002 Reliability Physics Symposium, p. 7.  T. Y. Chan et al., IEEE Elec. Dev. Lett. 8, p. 93, 1987. Program/Erase Cycling Vg/Vd/Vw/Prg. Or Ers. Time 5 6V/3V/-2V/4µs 4 6V/3V/-2V/4µs 3 -6V/5.5V/0V/250ms 2 1 10 100 1000 10000 Program/Erase Cycle # -8V/5.5V/0V/100ms Fig. 9: Write/erase cycling of bitcell, programmed with (Vg/Vd/Vw)=(6V/3V/-2V), and 2-HHI-erased with (Vg/Vd/Vw)=(-6V/5.5V/0V). 1000 # of Bits / 0.7V Data Retention and Read Disturb after 10,000 P/E Cycles 6 Stress Time (sec) 9V/3.5V/0V/70Å 0 4 Threshold Voltage (V) Drain Current (A) 8 1000 6V/5V/0V/70Å 5 Fig. 8: Bitcell forward and reverse read currents for the erased bitcell and bitcells programmed with various voltages. 100 50 6 F: forward read R: reverse read Vg/Vd/Vw/70Å Prog. 10 D Drain Voltage (V) 1.E-12 1 W Fig. 3: Charge distribution after hot hole injection for a “long” and a “short” bitcell. 0 1.E-09 1 S 6V/3V/-2V/70Å 1.E-01 Erased 0 D W Fig. 5: Programming current vs. drain voltage (one shot curve) with and without back bias. Fig. 6: Erased threshold voltage (Vt) vs. time with and without negative gate bias. 1.E-06 S 100 Drain Current (nA) Threshold Voltage (V) 0.18µm 0.20µm 0.22µm 0.24µm 0.26µm 0.28µm 0.30µm D HCI Program Vg/Vd/Vw/Bot. Ox. 2-HHI Erase Vg=-6V, Vd=Vs=5.5V Bitcell Gate Length 4 1.E-07 W 0V 0 Fig. 4: Programmed threshold voltage (Vt) vs. time with and without back bias. "long" bitcells 0.5V 150 1.E-04 5 G 200 HCI Program Vg/Vd/Vw/Bot. Ox. 1.E-07 S Fig. 2: Schematic of write, erase, and read operations. 5 Threshold Voltage (V) G 250°C Data Retention for 3072 Bitcells 100 Before Bake 10 1 4 5 6 7 Wordline Threshold Voltage (V) After 24-hour Bake Fig. 11: Programmed threshold voltage distribution from a 0.25µm test chip before and after a 24hr, 250°C bake.  G. Yeap et al., 2002 VLSI Tech. Symp., p. 16, 2002.  A. Hoefler et al., Proc. 2002 Reliability Physics Symposium, p.21.  J. Bude et al., 1995 IEDM Tech. Dig., p. 989, 1995.  B. Eitan et al., IEEE Elec. Dev. Lett. 21, p, 543, 2000.