An Embedded 90nm SONOS Nonvolatile Memory Utilizing Hot Electron Programming and Uniform Tunnel Erase C. T. Swift, G. L. Chindalore, K. Harber, T. S. Harp, A. Hoefler, C. M. Hong, P. A. Ingersoll, C. B. Li, E. J. Prinz, J. A. Yater Embedded Memory Center, Motorola 6501 William Cannon Dr., MD: OE341, Austin, Texas 78735 U.S.A. SONOS technology has been considered as a replacement for floating gate nonvolatile memory due to the simplicity of the bitcell structure and process, low voltage operation, and its immunity to extrinsic charge loss. SONOS devices with a thin bottom oxide (<30Å) typically utilize uniform tunneling for both program and erase operations resulting in programming times in the 1ms range, slower than desired for many high density embedded Flash EEPROM applications (3, 4). Charge retention and read disturb can be improved by employing a thick bottom oxide. These devices must employ mechanisms that are insensitive to the bottom oxide thickness such as hot electron injection (HEI) and hot hole injection (HHI) for program and erase, respectively (5). This technique is commonly used to locally store two bits per nonvolatile memory transistor (6). HHI has also been studied as a fast program mechanism with a tunneling erase (7). Local storage involving hot hole injection can lead to reliability concerns (8). This is a concern for embedded Flash EEPROM in automotive applications. Also, the injected holes during erase may not completely annihilate all of the stored electrons, leading to a build up of residual charge limiting the useful life of the device. The SONOS technology introduced here overcomes these problems by employing a uniform tunnel erase leading to high reliability and achieves fast programming by utilizing hot electron injection. RESULTS AND DISCUSSION The layout of the SONOS bitcell suitable for a common source NOR architecture and a cross sectional view across the (b) Gate L = 0.22µm Gate Source Active Area ONO 0.36µm Drain Fig. 1: (a) 0.157µm2 Flash EEPROM bitcell layout and (b) TEM cross sectional view across the gate. An oxide-nitride-oxide stack with a polysilicon gate forms the memory device. The bottom oxide is 22Å thick. A 100Å thick silicon nitride layer forms the charge storage layer. A 50Å thermal oxide is used as the top blocking dielectric. The drive current characteristics of the high performance CMOS logic devices processed concurrently with the SONOS memory array are shown in Fig. 2. The drive current of these -2 10 -3 10 (a) PMOS (b) NMOS -4 10 -5 10 -6 10 ds INTRODUCTION Cont. (a) 0.435µm In this work, a new compact SONOS Flash EEPROM device with fast programming, high reliability, and uniform erase is demonstrated. This device has been embedded into a 90nm high performance CMOS logic process with an advanced copper backend (1, 2). This device utilizes hot electron injection for programming and uniform channel tunneling for erase. Uniform tunnel erase prevents residual electron build up over the channel and avoids the reliability concerns of hot hole erase. A single bit is stored in each nonvolatile memory transistor. gate are shown in Fig. 1. The bitcell area is 0.157µm2. The bitcell layout observes the 90nm logic design rules, thus permitting the embedded SONOS nonvolatile memory (NVM) array to be readily processed with the high performance logic circuitry. |I /W| (A/µm) ABSTRACT -7 10 -8 10 -9 10 10 -10 |V | = 1.2V ds L poly -2 = 0.10µm -1 0 V (V) 1 2 gs Fig. 2: Low voltage logic transistor drive current characteristics for a 1.2V supply voltage (a) PMOS, (b) NMOS. ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ - Embedded SONOS NVM requires only four additional non critical masking steps over the base logic process, a substantial reduction as compared to embedded floating gate NVM. Due to its low operating voltages, embedded SONOS does not require dedicated high voltage transistors as does traditional floating gate NVM. Fig. 3 shows the SONOS module area savings as compared to floating gate NVM. The substantial area savings is primarily due to decreased row and column decoder area enabled by low voltage operation. The process simplicity and decreased module area results in significant cost savings for SONOS NVM. The charge neutral threshold (Vt,nat) of this SONOS technology is low so that disturb during read can be minimized. Hence, the HEI programming is enhanced through the application of back bias. A program time of 10µs can be achieved, as shown by the program characteristics in Fig. 4. With the application of 2V back bias, the programming performance of a device with a low charge Module Area (mm2) 50 100 45 SONOS 0.157um 2 10-1 100 40 101 10 2 10 3 Array Density (K Bytes) 104 Fig. 3: Embedded SONOS and floating gate NVM array module area vs. array density. 6 Circles: V = 5V, V = 0V ds 5 t,nat ♦ 55 101 4 bs Squares: V = 3V, V = -2V ds bs V = 6V gs 3 t Isolation Formation High Voltage Wells NVM Array Well (1 mask) Tunnel Oxidation Floating Gate Deposition/Patterning ONO Deposition/Patterning Low Voltage Wells DGO Wells High Voltage Oxidation/Paterning DGO Oxidation/Patterning Low Voltage Oxide Growth Gate Depostion NVM Stack Patterning NVM Source Halo Implant NVM Drain Implant Gate Patterning High Voltage LDD Implants DGO LDD Implants S/D and Backend Processing Masking Step Adder Embedded Embedded Floating SONOS Gate NVM NVM ♦ ♦ 2 masks 1 mask 1 mask ♦ 1 mask 1 mask 1 mask ♦ ♦ ♦ ♦ 1 mask 1 mask ♦ ♦ ♦ ♦ ♦ ♦ 1 mask 1 mask 1 mask 1 mask ♦ ♦ 2 masks ♦ ♦ ♦ ♦ +11 +4 60 Floating Gate 0.22um 2 (V) Process Step Logic Only 102 V -V Table 1: Logic-only, embedded floating gate NVM and embedded SONOS NVM process comparison. neutral threshold (Vt,nat < 0.5V) is equivalent to a SONOS device with Vt,nat = 2V. Area Savings (%) low leakage logic devices is unchanged from the logic-only process, indicating that the embedded SONOS memory does not impact the high performance logic CMOS devices. This SONOS technology requires minimum processing steps over the base 90nm logic process, enabling low cost. Table 1 summarizes the additional processing required for embedded floating gate and SONOS nonvolatile memories as compared to a logic-only process. 2 Low V 1 0 -7 10 t,nat V -6 10 -5 -4 10 10 Time (s) t,nat = 2V -3 10 -2 10 Fig. 4: SONOS bitcell programming vs. time with a low and 2V charge neutral threshold. A program time of 10µs is accomplished with a low charge neutral threshold. The uniform tunnel erase characteristics are shown in Fig. 5. The erase bias is evenly divided between the gate and the isolated well. Erase is accomplished within 10ms with a maximum applied voltage magnitude of 6V. The maximum voltage magnitude during program and erase is 6V, allowing for significant scaling of the decoding circuitry. The forward and reverse drive current characteristics after program and erase shown in Fig. 6 indicate that a charge asymmetry exists after HEI programming as expected, while a uniform channel tunnel erase is capable of completely erasing the nitride. 5 Program b t V (V) 4 t 0 g b |V | = V = 6V 2 g 1 b Low V t,nat t V = 1V ds After HEI Program -6 10 Model 3 10 4 V g,stress - V = 1V te Decreasing V 1.5 t,nat 1 0 -0.5 -7 10 Forward Reverse ds I /W (A/µm) 2 0.5 -5 10 -8 10 -9 10 10 1 10 10 10 Program/Erase Cycles 2 Delta V (V) -3 10 0 2.5 Fig. 5: SONOS bitcell erase vs. time. Erase can be accomplished within 10ms with a maximum erase voltage of 6V. -4 10 3 0 -7 -6 -5 -4 -3 -2 -1 0 10 10 10 10 10 10 10 10 Time (s) 10 Erase The change in erased threshold voltage due to read disturb for this SONOS technology is shown in Fig. 8 as a function of charge neutral threshold. As the charge neutral threshold is decreased, the read disturb is eliminated. A proprietary read architecture further ensures limited read disturb and adequate read margin over the life of the device. |V | = V = 5.5V 3 2 Fig. 7: Program/erase endurance with HEI program/tunnel erase and HEI program/hot hole erase. Hot hole erase can be insufficient to prevent electron build up over the channel. |V | = V = 5V g 3 1 6 5 Tunnel Erase Hot Hole Erase 4 V (V) The program/erase cycling endurance characteristics are shown in Fig. 7. In this figure, the endurance characteristics of both HEI program/tunnel erase and HEI program/HHI erase are shown. The Vt window for HEI program/tunnel erase as a function of program/erase cycle is very stable, indicating that there is no residual charge build up in the nitride due to an incomplete erase. The Vt window for HEI program/HHI erase drifts up due to electron build up in the nitride over the middle of the channel. This residual charge build up is largely due to small differences in the location of the injected electrons during program and the injected holes during HHI erase. This drift in the Vt window for HHI erase can significantly degrade the usable lifetime of the device. 0 1 2 3 4 V (V) 0 10 1 10 2 3 4 10 10 10 Time (s) 5 10 6 10 7 Fig. 8: Change in erased threshold vs. time due to read disturb as a function of charge neutral threshold. After Tunnel Erase -10 10 5 6 gs Fig. 6: Drive current asymmetry after HEI program and uniform tunnel erase. Uniform tunnel erase results in no drive current asymmetry. As the charge neutral threshold is reduced, the electric field across the bottom oxide is reduced during read. This in turn reduces the read disturb. The reduction of the bottom oxide electric field during read due to decreased charge neutral threshold is shown in shown in Fig. 9 for a fixed nitride charge and applied gate voltage. The charge retention performance is sufficient to obtain a 15 year lifetime at 150°C as shown in Fig. 10. 6 18 Channel Doping 4 extrinsic tails are demonstrated for charge retention and read disturb following 10,000 program/erase cycles in a 90nm 4 megabit array. -3 1x1016cm-3 1x10 cm Sub. 10 6 Bottom Oxide 10 5 10 4 10 3 10 2 10 1 10 0 Nitride -2 Gate -4 Top Oxide -6 18 -3 -8 V = V + 2V N = 5x10 cm g t trap -10 -0.01 0 0.01 0.02 0.03 Depth (µm) Fig. 9: SONOS conduction and valence bands during read for 1016cm-3 and 1018cm-3 net channel acceptor concentration. 168hr 25°C Stress 3000hr 150°C V - V = 1V Bake g te Each curve is one sector. (a) (b) (512K bits). -1 5 15 years V -V 25°C 85°C 150°C 1/-1 1 t,median (V) 20 31 Fig. 11: (a) Read disturb of erased bits and (b) charge retention of programmed bits in a 4 megabit array following 10,000 program/erase cycles. 3 AKNOWLEDGEMENTS t V (V) 0 t 4 The authors wish to thank Bryan Acred, Sandra Altmeyer, and Jerry Peschke for measurement support, the members of the Embedded Memory Center, the Dan Noble Center process engineering group, the Advanced Module Integration and Development Laboratory, MOS-12, and Ko-Min Chang. 2 1 0 800mV 7 580mV 10 0 Number of Bits Energy (eV) 2 10 4 10 5 6 10 10 Time (s) 7 10 8 10 REFERENCES 9 Fig. 10: SONOS bitcell charge retention as a function of time and temperature. A 15 year charge retention lifetime is demonstrated. This SONOS technology has been demonstrated in a 4 megabit array. Fig. 11 shows the array charge retention and read disturb performance following 10,000 program/erase cycles. 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