TM September 2013 • eFlexPWM – Freescale’s most advance timer for Digtial Power Conversion with up to 8ch and 312pico-sec resolution, supported by 4 independent time bases, with half cycle reloads for increased flexibility and best in class performance 100MHz DSP 32-BIT 56800EX Hawk V3 core •NanoEdge placer to implement fractional delays • Fastest DSC in its class with 100 MHz of performance • FIR Filter 6x faster than ARM CortexM3 • The highest number of operations per cycle of any MCU in its class • Fractional arithmetic High Performance DSC Core High Performance Peripherals •Intermodule Cross-Bar directly connecting any input and/or output with flexibility for additional logic functions (AND/OR/XOR/NOR) •DAC with hardware Waveform generation support •Very high speed ADCs capture events real time. • Nested looping • Superfast interrupt Advanced Integration & development speed The lowest power DSC available on the market • Less than 0.4mA/Mhz at full speed run Lowest Power Lowest Cost of Design • • Concurrent operations offer best-inclass execution times and overall low power run rates. TM • 2 • A high level of on-chip integration lowers external Op Amp and capacitor costs. Motor Control, Power Control, Safety (IEC60730) Libraries, PMBus software stack, PLC software stack. Motor control with integrated Power Factor Correction (PFC) reducing chip count. • Proven 5 volt tolerant I/O and Peripheral Crossbar enable greater flexibility and system cost reduction. • Development tools, including FREEMaster, enable real-time debug monitoring, data visualization, advanced modeling, rapid application design, and more. 180MHz 56F85xx 512K Flash 56F85xx 512K Flash 56F85xx 512K Flash 56F85xx 512K Flash 56F85xx 256K Flash 56F85xx 256K Flash 56F85xx 256K Flash 56F85xx 256K Flash 100MHz - Digital Power Microcontrollers Based on 32-bit Hawk 56800EX core in Freescale’s 90nm TFS 56F847xx 256K Flash 56F847xx 256K Flash 56F847xx 256K Flash 56F847xx 128K Flash 56F847xx 128K Flash 56F847xx 128K Flash - Starting below $1.00 @ 10K - Cost & Performance optimized for …. Integration - And critical high speed timing applications 56F8454x 96K Flash 56F8455x 96K Flash 56F84585 256K Flash 56F84587 256K Flash 56F8454x 64K Flash 56F8455x 64K Flash 56F8465 128K Flash 56F8467 128K Flash 56F8446x 128K Flash LQFP 60MHz - Motor Control 56F8445x 96K Flash 56F8445x 96K Flash 56F827x 56F8444x 64K Flash 64K Flash 56F827x 56F8444x 64K Flash 64K Flash 50MHz Flash / 100MHz SRAM 56F827x 64K56F827xx Flash 64K Flash QFN 56F827x 48K56F827xx Flash 48K Flash 56F827xx 48K Flash 56F827xx 48K Flash 56F827x 32K56F827xx Flash 32K Flash 56F827xx 32K Flash 56F827xx 32K Flash 56F827x 16K56F823x Flash 16K Flash 50MHz LQFP LQFP QFN 25MHz Flash / 50MHz SRAM 56F820x 16K Flash 56F820x 16K Flash 56F820x 16K Flash 56F820x 16K Flash 56F820x 12K Flash 56F820x 12K Flash 56F820x 12K Flash 56F820x 12K Flash 24pin 32pin 44 pin Execution Production LQFP Target Applications - Solar Inverters, Converters & Micro-inverters -Server & Telecom Power Supplies - Advanced Motor Control (Sensorless FOC) - Power Factor Correction - Resonant Converters - UPS (Online & Offline) - Power Adapters - Board Level Power Supplies - Low Cost Power Line Communications - And much more 3 TM WLCSP Planning 80MHz – Dual Motor Control 80MHz - Digital Power - Advanced control loop algorithm development Proposal 48pin 64pin 80pin 100pin 144pin 121pin Freescale DSC Key Features: Core Core • 56800EX @ 50/100MHz supporting fractional arithmetic with 4 accumulators, 8 cycle pipeline, separate program and data memory maps for parallel moves, single cycle math instructions, nested looping, and superfast interrupts that far outpace any competitive core on the market. System • Inter-module crossbar directly connecting any input and/or output with flexibility for additional logic functions (AND/OR/XOR/NOR) • DMA controller for reduced core intervention when shifting data from peripherals • Memory resource protection unit to ease safety certification Timers • eFlexPWM – Freescale’s most advance timer for Digtial Power Conversion, up to 8ch and 312 pico-sec resolution, 4 independent time bases, with half cycle reloads for increased flexibility, automatic complimentary mode for ease of use and best in class performance Analog • 2x12-bit high-speed ADCs each with 800ns conversion rates • 4 analog comparators with integrated 6-bit DACs that can enable emergency shutdown of the PWMs • Integrated PGAs to increase the accuracy of ADC conversions on small voltages and currents Power Consumption: • Best in class Power Consumption – 50% better than nearest competitor TM 56800EX Up to 100 MHz System Memories Clocks Memory Resource Protection Program Flash Up to 64KB Phase Locked Loop SRAM 8KB Crystal OSC Instruction Shadow Registers Fast Nested Interrupts 4-ch DMA 32bit Instruction Set Parallel Instruction Moves InterModule Crossbar 32b Instr Cache & Prefetch eOnCE Interface Vref Security & Integrity Timers Cyclic Redundancy Check (CRC) eFlexPWM Dual Watchdog w/ ext source NanoEdge Placer Deadtime Input Capture Fault detect 8MHz OSC 200KHz OSC Communication Interfaces Analog 8ch 12bit 8ch 12bit ADC @800ns with PGA ADC @800ns with PGA 12bit DAC 12bit DAC Band-Gap Ref & Temp Sensor 4 x ACMP w/ 6b DAC 2xUART 2xSPI 4Ch 16b Timer 2 x PITs I2C/SMBus CAN Others: 5-volt tolerant I/O for cost-effective board design Packages: 32QFN (5x5), 32LQFP, 48LQFP, 64LQFP Temperature: -40 to +105C across all packages, with -40 to +125C option on 64LQFP 4 Freescale DSC Core Key Features: Core • 56800EX @ 50MHz supporting fractional arithmetic with 4 accumulators, 8 cycle pipeline, separate program and data memory maps for parallel moves, single cycle math instructions, nested looping, and superfast interrupts that far outpace any competitive core on the market. System • Inter-module crossbar directly connecting any input and/or output with flexibility for additional logic functions (AND/OR/XOR/NOR) • DMA controller for reduced core intervention when shifting data from peripherals • Memory resource protection unit to ease safety certification Timers • eFlexPWM – Freescale’s most advance timer for Digtial Power Conversion, up to 8ch and 312 pico-sec resolution, 4 independent time bases, with half cycle reloads for increased flexibility, automatic complimentary mode for ease of use and best in class performance Analog • 2x12-bit high-speed ADCs each with 800ns conversion rates • 4 analog comparators with integrated 6-bit DACs that can enable emergency shutdown of the PWMs • Integrated PGAs to increase the accuracy of ADC conversions on small voltages and currents Power Consumption: • Best in class Power Consumption – 50% better than nearest competitor TM 56800EX Up to 50 MHz System Memories Clocks Memory Resource Protection Program Flash Up to 32KB Phase Locked Loop SRAM 6KB Crystal OSC Instruction Shadow Registers Fast Nested Interrupts 4-ch DMA 32bit Instruction Set Parallel Instruction Moves InterModule Crossbar 32b Instr Cache & Prefetch eOnCE Interface Vref Security & Integrity Timers Cyclic Redundancy Check (CRC) eFlexPWM Deadtime Input Capture Fault detect Dual Watchdog w/ ext source 8MHz OSC 200KHz OSC Communication Interfaces Analog 8ch 12bit 8ch 12bit ADC @800ns with PGA ADC @800ns with PGA 12bit DAC 12bit DAC Band-Gap Ref & Temp Sensor 3 x ACMP w/ 6b DAC Others: 5-volt tolerant I/O for cost-effective board design Packages: 32QFN (5x5), 32LQFP, 48LQFP Temperature: -40 to +105C across all packages 5 2xUART SPI 4Ch 16b Timer 2 x PITs I2C/SMBus Freescale DSC Core Key Features: Core • 56800EX @ 100MHz supporting fractional arithmetic with 4 accumulators, 8 cycle pipeline, separate program and data memory maps for parallel moves, single cycle math instructions, nested looping, and superfast interrupts that far outpace any competitive core on the market. System • Inter-module crossbar directly connecting any input and/or output with flexibility for additional logic functions (AND/OR/XOR/NOR) • DMA controller for reduced core intervention when shifting data from peripherals • Memory resource protection unit to ease safety certification Timers • eFlexPWM – Freescale’s most advance timer for Digtial Power Conversion, up to 8ch and 312 pico-sec resolution, 4 independent time bases, with half cycle reloads for increased flexibility, automatic complimentary mode for ease of use and best in class performance Analog • 2x12-bit high-speed ADCs each with 800ns conversion rates • 16 ch 16b SAR ADC that enables external sensors inputs and accurate system measurements • 4 analog comparators with integrated 6-bit DACs that can enable emergency shutdown of the PWMs • Integrated PGAs to increase the accuracy of ADC conversions on small voltages and currents TM 56800EX Up to 100 MHz Instruction Shadow Registers Fast Nested Interrupts 32bit Instruction Set Parallel Instruction Moves 32b Instr Cache & Prefetch eOnCE Interface System Memories Clocks Memory Resource Protection Program Flash Up to 256KB Phase Locked Loop SRAM 32KB Crystal OSC FlexMemory 32KB Flash or 2KB EEPROM 8MHz OSC 4-ch DMA InterModule Crossbar Vref Security & Integrity Timers Cyclic Redundancy Check (CRC) eFlexPWM Dual Watchdog w/ ext source NanoEdge Placer Deadtime Input Capture Fault detect Quadrature Decoder Communication Interfaces Analog 8ch 12bit 8ch 12bit ADC @800ns with PGA ADC @800ns with PGA 12bit DAC 12bit DAC Band-Gap Ref & Temp Sensor 4 x ACMP w/ 6b DAC 3xUART CAN Others: 5-volt tolerant I/O for cost-effective board design Freescale FlexMemory for simplified data storage Packages: 48LQFP, 64LQFP, 80LQFP, 100LQFP Temperature: -40 to +105C across all packages 6 2x I2C/SMBus 3xSPI 4Ch 16b Timer 2 x PITs 200KHz OSC Run Time Software FreeMASTER - Tower Development Kit Real-Time Debug, Monitoring and Visualization GUI development Tool TWR-56F8400 - High Voltage and Low Voltage Motor Control & Power Conversion Boards Comprehensive IDE that provides a highly visual, automated framework to accelerate development of some of the most complex embedded applications Processor Expert & QuickStart Init Tools QEDesign Lite Complimentary graphical filtering tool used to autogenerate coefficients that drop into any project. Ideal for designing any type of filter TM Rapid Init Code Generation as well as more advanced design tool features that combines easy-to-use component-based application creation with an expert knowledge system Reference Designs Complimentary code and schematics for : • FOC PMSM motor control • LLC resonant converter • Solar power conversion • Wireless Charging • Lighting 7 Digital Power Library Motor Control Library Filter Library Safety Library PMBUS Stack CAN Stack & more……… SFIO Matlab Plugin via FreeMaster S-Function Input Output (SFIO) Toolbox -smart simulation using the Matlab/Simulink tool for inthe-loop simulation & automatic testing tool • • • • • • • • • • • • Dual PMSM Vector Control Demo with PFC Application based on C-callable library functions (GFLIB, MCLIB, GDFLIB, ACLIB) Application software in C (CodeWarrior®) FreeMASTER visualization tool 3-in-1 high voltage power stage Kinetis K70 Touch Graphic LCD Tower Reference design manual AC/DC SMPS using 56F825x and 56F800x − Interleaved Power Factor Correction and AC/DC conversion are implemented by the 56F8006 − LLC resonant half-bridge converter together with synchronous rectifier converts high voltage DC bus voltage to low voltage DC (12V) − Buck Converter lowers DC voltage to 12v and 5v LLC resonant half-bridge converter, synchronous rectifier and buck converter are controlled by the 56F8247 DSC DC to AC inverter consists of main power parts: − MPP Tracking for solar panel output – software implemented − DC low voltage to DC high voltage converter − DC high voltage to AC sine output voltage inverter − Output filter − Isolated RS-485 line Associated control and fault detection circuits Both DC-DC converter and DC-AC inverter is controlled by one DSC MC56F8023 TM 8 Tools CodeWarrior Development Tools for MCUs (Eclipse IDE) USB TAP for ONCE DSC P&E USB Multilink Universal (P&E DSC product support) P&E Cyclone MAX Processor Expert Software FreeMASTER – Debug Monitor and Data Visualization Tool for application development and information management – (Training Overview) Quick Start – Initialization and Development Tool DSC Development Boards http://www.freescale.com/TWR-56F8400 http://www.freescale.com/TWR-56F827x TWR-MC-LV3PH: Low-Voltage, 3-Phase Motor Control Tower System Module RTOS Support MQX FreeRTOS uCOS II / Micrium Software 56800E_FSLESL_R2.0 : 56800E Freescale Embedded Software Libraries PMBUS – Freescale Power Management Bus (PMBus) Library Embedded Component: FreescaleCAN - DLP-568-FLXCN-CX support for MC56F84xxx Embedded Component: FreescaleCAN - DLP-568-MSCAN-CX support for MC56F827xx Services enabling Telephony Feature Library (DLP-568-FPHON-CX) Implementation of G.723.1A speech codec (DLP-568-G723-CX) Implementation of G.729AB speech codec (DLP-568-G729A-CX) 9 Services to support Voice Recognition (DLP-568-VRLIT-CX) TM 9 Application Notes ANxxxx-Using eFlexPWM with MC56F82xx DSC AN4675 - eFlexPWM Module for ADC Synchronization for MC56F84xxx and MC56F82xxx AN4656 - PMSM FOC of Industrial Drives using the 56F84789 AN4642 - Motor Control Application Tuning Tool for 3-Phase PMSM AN4625 - DSC MC56F84xxx in Motor Control Applications AN4615 – Freescale DSC in PV Solar Inverter Applications AN4612 - Sensorless Sinusoidal Vector Control of BLDC Ceiling Fan on MC56F8006 AN4611 - Freescale Embedded Software and Motor Control Libraries AN4608 - PWM and ADC on MC56F84789 to Drive Dual PMS Motor FOC AN4598 - Using DMA Transfers with Enhanced Flexible PWM on MC56F84xxx AN4583 - MC56F84789 Peripherals Synchronization for Interleaved PFC Control AN4485 - Using eFlexPWM with MC56F82xx DSC AN4429 - Using Motor Control eFlexPWM for BLDC Motors AN4413 “BLDC Motor Control with Hall Sensors Driven by DSC (using TWR-56F8257 and TWR-MC-LV3PH Boards) (AN4413SW) AN4386 – Single Phase Two Channel Interleaved Critical Conduction Mode AN4381 - Configuring the FlexTimer for Position and Speed Measurement with an Encoder AN4275 : Serial Bootloader for 56F82xx AN3843 : Single Phase Two-Channel Interleaved PFC Converter Using MC56F8006 AN3815 : Implementing a Modular High Brightness RGB LED Network AN3814 : Static Serial Bootloader for MC56F800x/801x/802x/803x AN3118 : Production Flash Programming for the 56F8000 Family AN3115 - Implementing a Digital AC-DC SMPS using 56F8300 DSC AN3113 : Network-Enabled high Performance Triple Conversion UPS AN1965 : AN1965 Design of Indirect Power Factor Correction White Papers and User Guides 56800E754FPL04UG : 56800E Family IEEE-754 Compliant Floating-Point Library WP8000 : Benefits and Applications Enabled by 56F8000 Digital Signal Controllers LVMCDBLDCPMSMUG : 3-Phase BLDC/PMSM Low-Voltage Motor Control Drive 10 TM Reference Designs DRM137 - Low Power Wireless Transmitter User’s Guide DRM126 - Inverter for the Solar Panel Using an MC56F8023 DRM119 - LLC Resonant ACDC SMPS using the MC56F8013 and MC56F8257 DRM110 - Sensorless PMSM Control for an H-axis Washing Machine Drive DRM108 : BLDC Sensorless Reference Design Using MC56F8006 DRM102 : PMSM Vector Control with Single-Shunt Current-Sensing Using MC56F8013/23 DRM100 - Sensorless High Speed SR Motor Drive for Vacuum Cleaners using an MC56F8013 DRM099 : Sensorless PMSM Vector Control with Sliding Mode Observer for Compressors DRM098 - Direct PFC Using the MC56F8013 DRM092 - 3Ph AC Induction Vector Control Drive with Single Shunt Current Sensing DRM087 - Spread FSK Power Line Modem for CENELEC Band-A DRM078 - 3-Phase BLDC Drive Using Variable DC Link Six-Step Inverter DRM075 - Design of an ACIM Vector Control Drive using the 56F8013 Device DRM077 - Design of PMSM and BLDC Sensorless Motor Control using the 56F8013 Device DRM074 - Design of a Digital AC/DC SMPS Using the 56F8323 Device DRM070 - Three-Phase BLDC Motor Sensorless Control Using MC56F8013/23 DRM069 - Online UPS using the 56F8300 TM 11 Freescale Value Proposition ► Dynamic Performance - The greatest number of operations per cycle of any MCU in it’s class Attribute Freescale DSC TI Piccolo Microchip dsPIC STMicro STM32 Core / Speed 56800EX Up to 100MHz C28x Up to 80MHz dsPIC33F/E Up to 70MHz CortexM4 Up to 168MHz Data Types Integer & Fractional Integer Integer & Fractional Integer Buses 3 address / 4 data 3 address / 3 data 3 address / 4 data 3 (I-bus/D-bus/S-bus) Memory Maps Separate program & data Unified program and data Separate program & data Unified program and data Pipeline Depth 8 8 3 3 Math Operations per Instruction 6 4 6 5 Accumulators 4 ACCs (36 bits) 1 ACC (32 bits) 2 ACCs (40 bits) N/A (0-8 reg) DMA Up to 4-ch Up to 6-ch Up to 15-ch Up to 16-ch Interrupt Controller Hardware Priority Fast ISR Intermodule Crossbar Switch, Nested Interrupts (no need for CLA) No Hardware Priority Hardware Priority Hardware Priority Architecture Advantages Flash CLA, VCU, FPU Peripheral Pin Select (PPS) ART Accelerator, FPU, Multifor pin function remap level AHB bus matrix Up to 1MB +512B OTP Up to 288KB TFS 90nm Up to 256KB + 2KB OTP Requires Paging Up to 536KB Multiple Incompatible Technology Nodes Cache Yes No No Yes (ART Accelerator) RAM Dual Port Single Port Single Port Single Port EEPROM Yes, up to 2KB No No No Memory Corruption Protection Yes – memory resource protection No No Yes – memory protection unit TM 12 No Flexibility to respond to different loads • Continuous ( Analog) Expression Competitors can copy Command Xi(t) Feedback Xf(t) Output M(t) + e(t) = Xi(t) – Xf(t) ----- (1) d e(t) ----- (2) M(t) = Kp*e(t) + Ki*e(t)dt + Kd * ---dt Where -- e(t): Error signal; Kp: Proportional Gain; Ki: Integral Gain; Derivative Gain • Difference ( digital ) Expression n e(n) – e(n-1) m(n) = Kp e(n) + Ki e(i) t + Kd ---------------t i=0 Software Flexibility Not easy to copy - (3) e(n) – e(n-1) e(n-1) – e(n-2) m(n)= m(n-1) + Kp [e(n)-e(n-1)] + Ki e(n) t + Kd [---------------- - ------------------- -] (4) t t Math required includes 5 Mul/Acum – Freescale DSC can accomplish in 5 cycles 13 CortexM4 takes 30 cycles - 6 times slower TM Freescale Value Proposition ► High Performance on-chip Peripherals - A high level of on-chip integration to reduce software overhead and total BOM cost. Attribute Freescale DSC TI Piccolo Microchip dsPIC STMicro STM32 Analog CMP response time 25ns 30ns 20ns None CMP 4 w/6-bit DAC 3 4 None DAC Up to 2x12-bit w/ Hardware Slope Compensation 3x10-bit 4x10-bit 2x12-bit ADC Blocks 2 (w/ one S&H for each ADC) 1 w/ High Input Impedance (enabling lower cost ext. Op Amp & Cap) 1 (w/dual S&H) 2 (w/up to five S&H for one SAR, one S&H for another SAR) 3 (w/ dual S&H for regular group and injected group in each ADC) ADC conversion Up to 300ns @ 12-bit Up to 217ns @ 12-bit Up to 500ns @ 10-bit 2,000ns @ 12-bit 417ns @ 12-bit ADC channels 16-ch 12-bit 8ch 16-bit 16-ch 12-bit 32-ch 10-/12-bit 24-ch 12-bit Temp Sensor Yes Yes No Yes PWM Total 16-ch / 8-ch with 312.5ps resolution Total 19-ch / 8-ch with 150ps resolution Total 18-ch with1.04ns resolution Total 14-ch with 5.95ns resolution PWM Features Multiple time base, enhanced capture functionality Multiple time base, PWM chopper Multiple time base, capture and chopper functionality Capture functionality Edge locked loop for stable PWM edge control Open loop delay, no stable edge over temp Fractional clock calculation and tracking, effectively reducing the software workloads. Fractional clock calculation is handled manually 9-ch 16-bit timer / 1-ch RTCC 12-ch 16-bit Timer / 1-ch RTC 5V Tolerance 14 on digital I/O 5V Tolerance on all I/O submodule to submodule synchronization has no delay Timer 8-ch 16-bit QTimer / 2-ch 16-bit PIT / 2-ch 16-bit PDB 2 clock delay to sync modules 3-ch 32-bit CPU timer 14 TM I/O 5V Tolerance on all I/O Only 3v Freescale Value Proposition ► Low Power - The most compelling uA/MHz performance available today for applications requiring arithmetic functions. Low power similar to CortexM0 & MSP430, Higher performance than the CortexM4 and C2000. Attribute Freescale DSC MC56F82748 (100Mhz, 32bit) Attribute IDD Full Run Mode 25.18mA With MAC operation in while loop IDDA WAIT mode 17.3mA 0.4uA IDLE mode STOP mode 4.94mA 0.04uA VLSTOP 500uA 0.01uA TI Piccolo TI Piccolo TMS320F28069 TMS320F28035 (90Mhz, 32bit) (60Mhz, 32bit) IDD 174mA Full RUN Mode With MAC operation in while loop 8.9mA Attribute Microchip dsPIC Microchip dsPIC dsPIC33FJ16GS504 dsPIC33EP64MC206 (40Mhz, 16bit) (60Mhz, 16bit) IDDA IDD IDDA IDD IDDA IDD IDDA 15.5mA 114mA 12.7mA Full Run Mode With MAC operation in while loop 100mA 38mA 38mA 2.5mA 6.16mA 8.2uA 5.09mA 8.2uA Idle mode 57mA 20mA 17mA 2.5mA STANDBY mode 3.36mA 8.2uA 2.69mA 8uA HALT mode 473uA 8.2uA 1.15mA 8uA Power Down mode 300uA 100uA ADC 12bit ADC 12bit 12bit ADC 10bit 10bit/12bit PWM resolution 320psec PWM resolution 150psec 150psec PWM resolution 1.04nsec 7.14nsec RUN, WAIT, STOP, LPSTOP,VLPSTOP, LPWAIT, VLPWAIT RUN, IDLE, STANDBY, HALT RUN, IDLE, DOZE, SLEEP Example code: 0x00000000 0xE584 move.w 0x00000001 0x00000002 0x00000003 0x00000004 0x00000005 0x00000007 0x00000008 move.w X:(R0)+N,Y1 move.w X:(R3)+N,X0 macr Y1,X0,A X:(R0)+,Y1 lsrac Y1,Y0,A move.w A,X:(R1+3) 15 nop jmp 0x000001 TM 0xF754 0xF457 0x7618 0x7476 0xD0C10003 0xE700 0xE1540001 #4,Y0 X:(R3)+,X0 15 TM CPU MIPS DSP56800E Up to 200MIPS # Interrupt Priorities Registers 5 7 Data 8 Address Data Types Program Memory Adr Space Data Memory Adr Space 8-bit, 16-bit 32-bit 4 MB 32 MB 56800/E MCU Functionality Fully Synthesizable and Scanable 56800/E DSP Functionality Multiplier - Accumulator (MAC) Single And Dual Parallel Move Instructions True Software Stack and Pointer 16-bit Program Word No Overhead Hardware Looping Nested Looping Capability 20 Addressing Modes and Atomic Read-Modify-Write Instructions Modulo arithmetic (For Circular Buffers) Integer and Fractional Arithmetic Support General Purpose Register Files and Orthogonal Instructions to Data and Address Register Files Full Set of Bit and Bitfield Manipulation Instructions and 16- and 32-bit Shifting Nested Interrupt with HW priority Fast Interrupt Support Superfast Interrupt TM Technology 17 Program (4 MB) Data (32 MB) “P:” “X:” 15 0 15 221 $1FFFFF x 16 224 x 16 $FFFFFF PROGRAM MEMORY SPACE 0 X DATA MEMORY SPACE $xxFFFF $xxFFC0 Optimized for IP-BUS PERIPHERALS (64 locations) (Relocatable) $0 INTERRUPT VECTORS Accessible with X:<<pp Addressing (Relocatable) 0 $0 (short addressing) 0 (64 locations) => 16-Bit Accesses Only TM => 8, 16, 32-Bit Accesses 18 Instruction Fetch: PROGRAM CONTROLLER AGU PC LA LA2 INSTRUCTION DECODER HWS FIRA FISR INTERRUPT UNIT SR OMR LC LC2 M 01 N3 LOOPING UNIT ALU1 PAB PDB ALU2 R0 R1 R2 R3 R4 R5 N SP Program Memory XAB2 PAB Data Memory CDBW CDBR XDB2 EOnCE/JTAG TAP MAC and ALU TM XAB1 CDBR CDBW - 24 bits - 32 bits - 32 bits XAB2 XDB2 IP-Bus Interface 1st 2nd 3rd DATA ALU External Bus Interface Multi-bit Shifter 19 - 24 bits - 16 bits Operations Performed: PDB BIT MANIPULATION UNIT 1st Data Access: 2nd Data Access: XAB1 A B C D Y0 Y1 X0 - 21 bits - 16 bits - PAB / PDB - XAB1 / CDBRCDBW - XAB2 / XDB2 TM The eFlexPWM architecture is configurable, up to 4 sub-modules (shown) TM 21 TM 22 VAL1 ($0100) VAL3 VAL5 ($0000) VAL4 VAL2 INIT ($FF00) Ch0a Ch0b When the Init value is the signed negative of the Modulus value, the PWM module works in signed mode. Center-aligned operation is achieved when the turn-on and turn-off values are the same number, but just different signs. TM 23 VAL1 ($0100) VAL5 ($0000) VAL3 INIT ($FF00) VAL2, VAL4 = $FF00 CH0b CH0a All PWM-on values are set to the init value, and never changed again. Positive PWM-off values generate pulse widths above 50% duty cycle. Negative PWM-off values generate pulse widths below 50% duty cycle. This works well for bipolar waveform generation. TM 24 VAL1 ($0100) VAL5 VAL3 ($0000) VAL4 VAL2 INIT ($FF00) PWMAx PWMBx PWMAx PWMBx (DBLPWM) In this example, both PWMs have the same duty-cycle. However, the edges are shifted relative to each other by simply biasing the compare values of one waveform relative to the other. TM Alternatively, if the waveforms are generated by different sub-modules, the waveforms can be shifted by simply changing the Init value of one sub-module relative to the other. 25 TM 26 PWMAx 0 1 DTCNT0 1 rising edge detect DBLPWM start down counter PWMAx 0 0 DBLEN 1 0 1 IPOL PWMBx 0 falling edge detect start down counter 1 INDEP DTCNT1 TM 27 PWMBx • Challenge: ̶ ̶ Wide range of PWM switching frequency from 100KHz up to 1Mhz Need to make a change to the PWM period without changing the duty cycle for up to 4 channels of PWM within one period of the existing PWM PWM period change must be in a few nanosecond ̶ • Solution: ̶ ̶ ̶ High speed digital PWM plus Analog edge delay PWM duty cycles are calculated by high speed controller Special circuit is used to automatically increment the PWM period by repositioning edges Modification to both PWM edges New PWM Original PWM Initial PWM period New PWM period PWM period requires small incremental adjustment TM 28 PWMAx 0 1 DTCNT0 DBLPWM 0 DBLEN rising edge detect 1 start down counter 0 1 0 1 PWMBx Fractional Delay A IPOL 0 falling edge detect start down counter DTCNT1 1 INDEP INDEP=1: Fractional Delays A & B are separate INDEP=0 & IPOL=0: Delay B (dependent variable) = Inverse Delay A (controlling) => T FB = TRA AND TRB = TFA INDEP=0 & IPOL=1: Delay A (dependent variable) = Inverse Delay B (controlling) => T FA = TRB AND TRA = TFB TM 29 Fractional Delay B • • • Need to calculate the next edge position for rising and falling edges within very short period. Software not fast enough so need hardware adder Diagram shows 21 bit adder to control both edges automatically setting new comparator values after each edge has been triggered TM Ideal timing 16 bits at IP Bus timing resolution 5 bits NanoEdge timing resolution 16 bit + 5 bit adder PWM Period N Actual timing Timer 16 bits at IP Bus timing resolution 16 bits at IP Bus timing resolution 5 bits NanoEdge timing resolution 5 bits NanoEdge timing resolution PWM Period N-1 PWM Period N 5 bits from previous Nano Edge Placement calculation PWM reload times are restricted to 16-bit IP Bus timing (truncation of 21 bit value). Any residual left over from PWM period N-1 needs to be added back to period N. 30 • • • • • The Nano-Edge Placer allows us to control edge placement to subnanosecond resolution. The actual block is based uses a dual-slope method to calibrate individual time slices to fractions of a digital clock period. U.S. Patent # 7288977: High resolution pulse width modulator <include reference to Martin & Pavels patent application> When using the nano-edge placer, delay values change from 16-bit resolution to 21-bit resolution or better: 16-bit digital value 16-bit digital value 5-bit nanoedge value Include patent app from Roznov. TM 31 Motor Drive Converter Inverter 32 Filter Capacitor Motorola 230V or 460V Dave’s Control Center M Fault 1 Fault 2 Fault 3 56F801x Fault 4 • Fault inputs can independently monitor critical system parameters, and generate an interrupt when asserted. • Each input is mappable to immediately disable any or all PWMs • Each input is programmable to allow Automatic or Manual PWM restart TM 32 DISMAP3 DISMAP2 DISMAP1 DISMAP0 Fault 0 Fault 1 Digital Filter AND Digital Filter AND OR Fault 2 Fault 3 AND Digital Filter Disable PWM 0 AND Digital Filter PWM Value PWM Modulo PWM Output Fault Input PWM Enable PWM Disable PWM Enable PWM Disable *When Fault logic returns to logic 0, the PWM restart at beginning of the next half cycle. TM 33 PWM Enable TM • • • • • Once − The ADC starts to sample just one time whether you use the START bit or by a sync pulse. This mode must be re-armed by writing to the ADCR1 register again if you want to go capture another scan Triggered − Sampling begins with every recognized START command or sync pulse Loop − The ADC continuously take samples as long as power is on and the STOP bit has not been set Sequential Mode − Sequential will sample SampleN one after another. Channel ANAx are sampled by ADCA and Channel ANBx are sampled by ADCB Parallel Mode − Simultaneous: Parallel can sample SampleN from Group1 and SampleN from Group 2 at the same time. − Independent:: ADCA and ADCB can operate independently. At end of scan of each ADC, they generate separate interrupt request. TM VRETH VREFLO ANA0 ANA1 ANA2 ANA3 ANA4 ANA5 ANA6 ANA7 Voltage Reference Circuit Result Reg 0 Result Reg 1 Result Reg 2 MUX S/H & Scaling Cyclic Converter A Result Reg 3 12 Result Reg 8 Result Reg 9 Result Reg 10 SYNC0 SYNC1 Result Reg 11 Controller Result Reg 4 Result Reg 5 ANB0 ANB1 ANB2 ANB3 ANB4 ANB5 ANB6 ANB7 MUX S/H & Scaling Result Reg 6 Cyclic Converter B Result Reg 7 12 Result Reg 12 Result Reg 13 Result Reg 14 Result Reg 15 35 • Do you need more than 12bit if PGA is included? Does 500ns conversion time meet power supplies needs? > LOW LIMIT Option Gain Setting X1, x2, x4 < V+ PGA V- 12Bit ADC Vrefl RESULT MUX MUX … ANx Below Zero Crossing Logic AN0 AN1 Above ADC RESULT ADC OFFSET Channel Select Single Ended or Differential TM 36 IRQ Logic • HIGH LIMIT IRQ PWM Period Temp Inductor Current I1 Sampled and Average Currents Inductor Current I2 Voltage PWM 0 PWM 1 T1 ADC trigger Signal end of scan interrupt end of scan interrupt calc. Calculation ADC Sampling helps to filtering the measured current - antialiasing. Noise free ADC sampling when the power switch is not acting ADC sample is taken at middle of PWM pulse which is equal to average Current But second phase samples are difficult to be located in middle of PWM Pulse TM 37 Temp Inductor Current I1 Inductor Current I2 Voltage PWM 0 PWM 1 ADC trigger Signal T0 T1 T2 T0 T1 T2 end of scan interrupt end of scan interrupt calc. Calculation Trigger 0 (T0) starts 1st conversion which ADC takes two conversions then wait next trigger Trigger 1 (T1) starts 2nd conversion which ADC takes one conversion then wait next trigger Trigger 2 (T2) starts 3rd conversion which ADC takes three conversions then generates INT TM 38 ADC Module Control Module Sample Disable Register Sample DISn … Sample DIS1 Sample DIS0 Sample Result Register Address ADC Conversion Result ADC Sample SCn … Sample SC1 Sample 1 Sample (n) Result ADC Analog Input Channel List ( Select ) Registers … Sample (2) Result Sample SC0 ADC Scan Control register Sample n Sample (1) Result … ADC trigger ADC Scan Controller Sample (0) Result IN0 IN2 Sample 0 IN3 … Multiplexer Select ADC Start Signal T0, T1, T2, … INn Programmable Delay Module … Comparators Transistor Power Stage Trigger Selector Timers Energy Source PWM TM 39 Motor or other Loads OFF Limit and Threshold Detection Programmable Upper limit Over-voltage shut-down level Programmable Threshold limit Programmable Lower limit Optional ADC Interrupt (can be selected) ISR ISR ISR ISR ISR • ISR The ADC can perform limit checking and zero crossing detection with NO CPU intervention. • Each channel has its own upper, lower, and threshold comparators. TM 40 PWM Output PWM Synch signal TM 41 PWM values Updated Control Algorithm Execution PWM values Written to registers ADC Convert ADC Interrupt PWM synch pulse 56F801x Solution Timer Delay ADC start signal Traditional Solution ISR Latency VDDA Less Than 3mA MUX Pad With ESD ADC 10nF -100nF VSSA TM To Other Mux VSSA 42 1 12 R1 110K 1 2 R2 110K 430V Close to ADC pin as possible 1 2 + - R3 110K DC_Bus R4 24.9K 2 R6 1 100ohm ~ 1K C1 1 1 1 TO A DC input R5 2.2K 43 C2 1nF ~ 10n F 2 2 0.1uF ~ 0.47uF 2 TM 2 TM 5-bit VREF Trigger[1:0] 12-bit DAC output 0 1 2 3 Pin HSCMP Pin ADC_In DAC input for test only Crossbar Fabric 3 12-bit DAC output Dual 12bit ADC 3 0 2 1 To comparators 12-bit DAC Output Pin 3 Window / Sample[2:0] X3 SYNC_IN 4 Quad Timer B 12-Bit DAC 4 X4 Pin TB[3:0] OUT_TRIG0[2,0] OUT_TRIG1[2,0] OR Functions 6 8-ch X9 GHzPWM X6 4 I/O Muxing 2 OUT_TRIG0[3] OUT_TRIG1[3] X6 14 PWMA[3:0] PWMB[3:0] PWMX[3] EXTA[3:0] EXT_SYNC[3:0] EXT_FORCE EXT_CLK FAULT[3:0] TM I/O Module Pin I/O Module peripheral functions 45 XBAR_OUT20 XBAR_OUT21 XBAR_OUT22 XBAR_OUT23 XBAR_OUT24 XBAR_OUT25 XBAR_OUT15 XBAR_OUT19 EXT_CLK FAULT0 FAULT1 FAULT2 FAULT3 EXT_FORCE EXTA EXT_SYNC Submodule OUT_TRIG0 OUT_TRIG1 3 Enhanced Flex PWM Module Submodule 1 EXTA EXT_SYNC OUT_TRIG0 OUT_TRIG1 Submodule 0 EXTA EXT_SYNC OUT_TRIG0 OUT_TRIG1 XBAR_OUT14 XBAR_OUT18 OR XBAR_IN18 XBAR_OUT13 XBAR_OUT17 OR XBAR_IN17 XBAR_OUT9 Crossbar XBAR_IN10 Switch XBAR_OUT10 XBAR_IN11 CMPA + COUT Window /Sample CMPB+ COUT Window /Sample CMPC+ - - XBAR_OUT12 XBAR_OUT16 OR XBAR_IN16 XBAR_IN12 XBAR_OUT26 XBAR_IN19 XBAR_OUT6 ANB0-7 ADCB TRIGGER ADCB SYNC_IN DAC XBAR_IN13 XBAR_OUT27 XBAR_OUT7 OUT 1 0 IN TB0 OUT 1 0 IN TB1 XBAR_OUT8 VSS XBAR_IN0 VDD XBAR_IN1 XBAR_IN14 XBAR_OUT28 XBAR_IN15 XBAR_OUT29 TM COUT Window /Sample ADCA TRIGGER ADCA DAC0 XBAR_IN9 XBAR_OUT11 OR ANA0-7 XBAR_OUT0 XBAR_OUT1 XBAR_OUT2 XBAR_OUT3 XBAR_OUT4 XBAR_OUT5 46 OUT 1 0 IN OUT 1 0 IN TB2 TB3 GPIO MUX GPIO MUX Submodule 2 EXTA EXT_SYNC OUT_TRIG0 OUT_TRIG1 XBAR_IN20 XBAR_IN21 XBAR_IN2 XBAR_IN3 XBAR_IN4 XBAR_IN5 XBAR_IN6 XBAR_IN7 • Continuous demand for high power density and low profile in power converters leads to increasing switching frequency • The higher switching frequency ensures smaller power transformer include all passive components at given output power • On the other hand the higher switching frequency brings higher switching losses • To solve this issue several resonant converter topologies have been introduced • The resonant converter topology allows to use switching frequency above 1MHz TM 47 TM Iin I I2 1800 1800 1800 1800 1800 1800 1800 I1 D2 PWM0A I2 I D1 1 T1 T2 PWM0B C Iin I Application Notes AN1919 - Design of Indirect Power Factor Correction Using DSP56F80X AN1965 - Design of Indirect Power factor Correction Using the 56F800/E AN3115 - Implementing a Digital AC/DC Switched-Mode Power Supply using a 56F8300 Digital Signal Controller AN3843 - Single Phase Two-Channel Interleaved PFC Converter Using MC56F8006 PWM0A PWM0B MC56F8000 ADC Reference Design DRM069 - Online UPS using the 56F8300 DRM074 - Design of a Digital AC/DC SMPS using the 56F8323 Device DRM098 - Direct PFC Using the MC56F8013 Recommended Devices MC56F800x, MC56F80xx, MC56F82xx, MC56F83xx , MC82F84xx TM 49 Description Peripheral Resources Gate drive for MOSFETS PWM0A, PWM0B Line current ADC Line voltage ADC Output voltage ADC T1 current ADC T2 current ADC TM 50 ANx VAC ANx VDC Voltage decouple Voltage Error Current Error Compensator Compensator VDC VDCref + VAC VPI * * VERR VCOMP * 1/Vavg VAC TM Vavg 51 IACref + IAC IERR PWM PDC IAC ANx ADC PWM pulses PFC Boost Converter Iac IS k3 Vac D C S PWM Load L k2 Vdc ID k1 Vdc Iac DSC Voltage Error Current Error Compensator Compensator VDC - VDCref + * * IAC VAC IACref VPI VERR VCOMP + * 1 / VAVG TM Voltage decouple 52 - IERR PWM TM 53 Half the power, twice the performance The MC56F827xx digital signal microcontroller uses half the power and achieves twice the performance as the competition in a compact 5x5 mm package. For real engineers doing real work. • • • • Unrivalled Low Power Dynamic Performance Lowest Cost of Design The lowest power DSC available on the market Fastest DSC in its class with 100 MHz of performance Advanced integration with invaluable tools and software speed development and lower BOM costs Power consumption is minimized while servicing advanced mathematical algorithms with minimal cycles. Ultra low power ADC block reduces overall run-time power consumption by over 40% when compared to existing solutions. Concurrent operations offer best-in-class execution times and overall low power run rates. Switches from high performance code at100MHz to background code at 50Mhz, lowering power consumption. • The highest number of operations per cycle of any MCU in its class • • Low load efficiencies are able to easily meet new power conversion regulations. Achieves motor control with integrated Power Factor Correction (PFC) reducing chip count. • Motor and Power Control Libraries, PMBus software stack, and applicationfocused reference designs reduce development time and provide marketfocused building blocks. • A high level of on-chip integration lowers external Op Amp and capacitor costs. • Proven 5 volt tolerant I/O and Peripheral Crossbar enable greater flexibility and system cost reduction. • Development tools, including FREEMaster, enable real-time debug monitoring, data visualization, advanced modeling, rapid application design, and more. • High resolution PWMs with precise and stable control across a wide range of loads and temperatures. • PWM automatically synchronizes complimentary channels with no delay on independent time bases • • TM Improved real-time control, accuracy and power consumption with dual 12-bit ADCs sampling up to 1.25 mega samples per second (Msps). Peripheral Crossbar increases signal integrity, adds additional HW logic flexibility and eliminates 54unnecessary core intervention. TM 55 TM