Qorivva MPC5604E - Freescale Semiconductor

32-bit Microcontrollers
Qorivva MPC5604E
MPC5604E for automotive video compression
and transmission over Ethernet
Overview
Highlights
The MPC5604E is part of the Qorivva MPC5500/560 family of microcontrollers (MCUs) and
The advanced driver assistance
contains a Book E-compliant core, built on Power Architecture® technology, with variable-
market is growing fast. As
length encoding (VLE). This core complies with the Power Architecture technology embedded
historically premium applications
category, and is 100% user mode-compatible with the original PowerPC user instruction set
such as camera based park
architecture (UISA).
assist systems proliferate into
The MPC5604E MCU is a gateway system designed to move data from different sources via
Ethernet to a receiving system and vice versa. The supported data sources and sinks are:
the mid range, there is a need
to reduce system cost (volumes
grow, competition increases, price
pressure increases). In order to
• Video data (with 8/10/12 bits per data word)
reduce costs, auto makers are
• Audio data (6 x stereo channels)
motivated to move away from
• RADAR data (2 x 12-bit with <1 us per sample, digitized externally and read in via DSPI)
costly screened cable networks to
• Other serial communication interfaces, including FlexCAN, LINFlex and DSPI
less expensive two-wire systems.
Ethernet has a bandwidth of 10/100 Mb/s supporting precision time stamping (IEEE® 1588).
The Qorivva MPC5604E MCU,
Unshielded twisted pair cables are then used to transfer information via Eithernet throughout
with its embedded Motion J-PEG
the car, resulting in reduced wiring costs achieved through high bandwidth data links.
compression engine, precision time
stamping hardware (IEEE 1588)
MPC5604E
MPC5604E
and fast Ethernet controller (FEC),
System
Integration
Crossbar Masters
Debug
e200 Core
JTAG
VReg
Nexus
Osc/PLL
Interrupt
Controller
Ethernet
+ PTP
VLE
eDMA
M-JPEG
Crossbar Switch
I/O
Bridge
512 KB
Flash
Boot
Assisted
Module
(BAM)
64 KB
DATA Flash
96 KB
SRAM
Crossbar Slaves
Communications I/O System
6-ch.
eTimer
FlexCAN
2x
LINFlex
3x
DSPI
2 x I2C
I2S
4-ch.
ATD
enables real-time broadcast of
video and audio data over Ethernet.
A comprehensive suite of hardware and
software development tools is available to
Feature
MPC5604E
100-pin LQFP1
help simplify and speed system design.
CPU
e200z0h, 64 MHz, VLE only, no SPE
Development support is available from leading
Flash with ECC
CFlash: 512 KB (LC) DFlash: 64 KB (LC, area optimized)
tools vendors providing compilers, debuggers
RAM with ECC
96 KB
and simulation development environments.
DMA
16 channels
PIT
Yes
SWT
Yes
• Development tools
FCU
Yes
• Compilers
Ethernet
100 MB MII
Freescale CodeWarrior IDE, visit
freescale.com/CodeWarrior for more
information
Video Encoder
8/12 BPP
Audio Interface
6x Stereo (4x synchronous + 2x synchronous/asynchronous)
ADC (10-bit)
4 channels + VDD_IO + VDDCore + TSens + VGate Current
Green Hills
Timer I/O (eTimer)
6 channels
Wind River Diab
SCI (LINFlex)
2x
SPI (DSPI)
DSPI_0: 2 chip selects
Development Support Section
• Debuggers
DSPI_2: 4 chip selects
Lauterbach
CAN (FlexCAN)
1x
Green Hills
I 2C
2x
Supply
3.3 V IO
1.2 V core with dedicated ballast source pin in two modes:
Flash and FEE drivers
• Internal ballast
Software core self test
• External supply (using power on reset pin)
AUTOSAR microcontroller abstraction
layer
Phase Lock Loop (PLL)
FMPLL
Internal RC Oscillator
16 MHz
AUTOSAR™ Operating System
External Cyrstal
Oscillator
4 MHz­–40 MHz
CRC
Yes
Debug
JTAG, Nexus2+
Ambient Temperature
–40 °C to +125 °C
Specifications
• Book E-compliant core built on Power
Architecture technology
• Up to 64 MHz PowerPC ISA e200 zen0h
core
100 MB MII-Lite
DSPI_1: 2 chip selects
P&E Micro
• Runtime software
64-pin LQFP
JTAG
Note: 1 The 100-pin package is not a production package. It is used for software development only.
Memory
• 2 x LinFlex
System
• 512 KB program flash with ECC
• 2 x I C interface
• PLL
• 4 x 16 KB data flash with ECC
• 1 x I S/I8S/TDM audio interface
• 16-ch. eDMA
• 96 KB SRAM with ECC
• 3 x DSPI (four independent chip selects
each)
• 16 MHz internal RC OSC
I/O
• 1 x MJPEG video encoder with image
sensor interface supporting up to 1.2 Mpx
• 1 x 10/100 Ethernet MAC, including IEEE
1588 PTP support
2
2
• 1 x eTimer (six general-purpose channels)
• 1 x ADC (5 V capable)
• Channels TBD, 10-bit, conversion time
<1 us
• 2- or 5-pin JTAG/Nexus Class 1
• 3.3 V single supply
• 64-pin LQFP package
• 1 x FlexCAN
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Document Number: MPC5604EFS REV 1