1/4 Structure Silicon monolithic integrated circuit Product Name PCM CODEC IC Product No. BU8925MUV Physical dimentions Figure1 (VQFN032V5050) Features · 16bit Linear ·μ/A-Law codec · Built-in PLL circuit for system clock generation · Support for below frequency about PCM data transmission clock. μ/A-Law 64kHz - 2048 kHz Linear 128 kHz - 2048 kHz · Built-in Output amplifier for line drives (600Ω) · Power down control using NRST pin ○ Absolute Maximum Ratings Parameter Symbol Rating Unit Digital supply voltage ＤＶＤＤ －０．３～４．５ Ｖ Analog supply voltage ＡＶＤＤ －０．３～４．５ Ｖ Input voltage for digital terminal ＶＴＤ ＤＶＳＳ－０．３～４．５ Ｖ ＶＴＡ ＡＶＳＳ－０．３～ＡＶＤＤ＋０．３ Ｖ Input current ＩＩＮ －１０～＋１０ ｍＡ Power dissipation *1 Ｐｄ ３００ ｍＷ Storage temperature range Ｔｓｔｇ －５５～１２５ ℃ Input voltage for analog terminal (*1) Note: Reduce to ３mW/℃ when Ta = 25℃ or above ○ Recommended Operating Power Supply Voltage and temperature Range ＤＶＤＤ Min １．６５ Rating Typ １．８０ Max １．９５ ＡＶＤＤ ２．７００ ２．８００ ３．４６５ Ｖ Ｔopr －３０ - ８５ ℃ Parameter Symbol Digital supply voltage Analog supply voltage Operating temperature range Unit Ｖ This product is not designed to protect itself against radioactive rays. Status of this document The Japanese version of this document is the formal specification. A customer may use this translation version only for a reference to help reading the formal version. If there are any differences in translation version of this document, formal version takes priority. REV. A 2/4 ○ Electrical Characteristics Unless otherwise noted, Ta = 25℃, AVDD=2.8, DVDD=1.8V, FSYNC=8kHz, DCLK=256kHz. Parameter Symbol Min Specified Value Typ Max - 0.1 3.0 Unit Condition Current consumption NRST=DVSS and Standby current consumption IDD1 uA FSYNC,DCLK=DVSS Full Operation IDD2 - 2.5 3.8 mA Digital H level input voltage VIH DVDDｘ0.75 4.5 Ｖ Digital L level input voltage VIL DVDDｘ0.25 Ｖ Digital H level input current IIH Digital L level input current IIL -0.3 - Digital H level output voltage VOH DVDDｘ0.8 Digital L level output voltage VOL ０ - NRST,BST=DVDD and No input signal DC Characteristics 1 uA -1 uA VIH=DVDD VIL=DVSS ＤＶＤＤ Ｖ IOH= -1mA DVDDｘ0.2 Ｖ IOL= 1mA Unless otherwise noted, Ta=25°C, AVDD=2.8Ｖ, ＤＶＤＤ＝1.8Ｖ, FSYNC=8kHz, DCLK=256kHz and linear mode. Parameter symbol Transmit signal-to-distortion Specified Value Condition 1020Hz Unit Min Typ Max 0dBm0 45 - - -30dBm0 -40dBm0 -45dBm0 0dBm0 -30dBm0 -40dBm0 -45dBm0 +3.0～0.5dBm0 +0.5～-40dBm0 -40～-50dBm0 -50～-55dBm0 +3.0～-40dBm0 -40～-50dBm0 -50～-55dBm0 0.500 3.0 1.0 2.0 2.0 1.0 2.0 2.0 0.667 Ｖｒｍｓ 0.564 Ｖｒｍｓ Transmit reference level ＶＩＴＸ１ 1020Hz，0dBm0 AUX1IN→PCMOUT 35 29 24 45 35 29 24 -3.0 -1.0 -2.0 -2.0 -1.0 -2.0 -2.0 0.375 Receive reference level ＶＯＲＸ 1020Hz，0dBm0 PCMIN→AUDOUT 0.400 0.475 0.06kHz 24 - - 0 -0.3 -0.3 -0.3 0 6.5 24 0 -0.3 -0.3 -0.3 0 6.5 - - 2.5 0.5 0.3 0.9 2.5 0.3 0.5 0.9 -76 dBV - - -85 dBV ratio ＳＤＴ ＊2,＊3 (AUX1IN→PCMOUT) Receive signal-to-distortion ratio ＳＤＲ 1020Hz ＊2 (PCMIN→AUDOUT) Transmit Gain Tracking (ＡＵＸ1ＩＮ→ＰＣＭＯＵＴ) Receive Gain Tracking (PCMIN→AUDOUT) 1020Hz，Reference ＧＴＸ ＊3 1020Hz，Reference ＧＲＸ Transmit Gain Loss relative to Frequency ＧＲＴＸ (AUX1IN→PCMOUT) Receive Gain Loss relative to Frequency level=-10ｄＢｍ0 ＧＲＲＸ (PCMIN→AUDOUT) Transmit noise level VNTX Receive noise level VNRX level=-10ｄＢｍ0 0.2kHz 0.3～0.4kHz 1020Hz 0.4～3.0kHz 3.4kHz 3.6kHz 3.78kHz 0.06kHz 0.2kHz 0.3～2.8kHz 1020Hz 2.8～3.0kHz 3.4kHz 3.6kHz 3.78kHz AUX1IN= AGND level. ＊2 PCMIN=”L”, Using A-Weight filter. ＊2 Using C-MESSAGE filter ＊3 Specified that 0dBm0 is 0.5Vrms. REV. A ｄＢ ｄＢ ｄＢ ｄＢ ｄＢ ｄＢ 3/4 ○ Physical dimentions (Figure1) ○Pin assignment Pin No 1 BU8925 LOT No NC Pin No 17 2 DVSS 18 AVSS 3 DVDD 19 AVDD 4 BST 20 AUDOUT 5 NRST 21 AVDD 6 DSEL 22 AVSS 7 FRM2 23 BGFLT Pin name Pin name AUX1IN 8 TEST 24 NC 9 FRM1 25 AGND 10 NC 26 VREF 11 NC 27 PLLCAP 12 NC 28 PCMSEL 13 NC 29 FSYNC 14 NC 30 DCLK 15 NC 31 PCMIN 16 NC 32 PCMOUT Power down control using only NRST pin. NRST = L : Power down mode NRST = H : Active mode VQFN032V5050 （Unit: mm） NC : This pin is not connected with internal. ○ Block diagram (Figure2) AVDD (19,21) BGFLT (23) DVDD (3) NRST (5) BIAS BST (4) AUX1IN (17) AAF S to D ADC PCM P to S BPF PCMOUT (32) FSYNC (29) VREF (26) DCLK (30) System clock AGND (25) AUDOUT (20) PLL + SMF D to S + TEST (8) DAC PCM S to P BPF PCMSEL DSEL FRM1 FRM2 AVSS (28) (6) (9) (7) (18,22) DVSS (2) REV. A PLLCAP (27) PCMIN (31) （） : Pin NO 4/4 ○ Cautions on use (1) Absolute Maximum Ratings An excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc., can break down devices, thus making impossible to identify breaking mode such as a short circuit or an open circuit. If any special mode exceeding the absolute maximum ratings is assumed, consideration should be given to take physical safety measures including the use of fuses, etc. (2) Operating conditions These conditions represent a range within which characteristics can be provided approximately as expected. The electrical characteristics are guaranteed under the conditions of each parameter. (3) Reverse connection of power supply connector The reverse connection of power supply connector can break down ICs. Take protective measures against the breakdown due to the reverse connection, such as mounting an external diode between the power supply and the IC’s power supply terminal. (4) Power supply line Design PCB pattern to provide low impedance for the wiring between the power supply and the GND lines.In this regard, for the digital block power supply and the analog block power supply, even though these power supplies has the same level of potential, separate the power supply pattern for the digital block from that for the analog block, thus suppressing the diffraction of digital noises to the analog block power supply resulting from impedance common to the wiring patterns. For the GND line, give consideration to design the patterns in a similar manner. Furthermore, for all power supply terminals to ICs, mount a capacitor between the power supply and the GND terminal. At the same time, in order to use an electrolytic capacitor, thoroughly check to be sure the characteristics of the capacitor to be used present no problem including the occurrence of capacity dropout at a low temperature, thus determining the constant. (5) GND voltage Make setting of the potential of the GND terminal so that it will be maintained at the minimum in any operating state. Furthermore, check to be sure no terminals are at a potential lower than the GND voltage including an actual electric transient. (6) Short circuit between terminals and erroneous mounting In order to mount ICs on a set PCB, pay thorough attention to the direction and offset of the ICs. Erroneous mounting can break down the ICs. Furthermore, if a short circuit occurs due to foreign matters entering between terminals or between the terminal and the power supply or the GND terminal, the ICs can break down. (7) Operation in strong electromagnetic field Be noted that using ICs in the strong electromagnetic field can malfunction them. (8) Inspection with set PCB On the inspection with the set PCB, if a capacitor is connected to a low-impedance IC terminal, the IC can suffer stress. Therefore, be sure to discharge from the set PCB by each process. Furthermore, in order to mount or dismount the set PCB to/from the jig for the inspection process, be sure to turn OFF the power supply and then mount the set PCB to the jig. After the completion of the inspection, be sure to turn OFF the power supply and then dismount it from the jig. In addition, for protection against static electricity, establish a ground for the assembly process and pay thorough attention to the transportation and the storage of the set PCB. (9)Input terminals In terms of the construction of IC, parasitic elements are inevitably formed in relation to potential. The operation of the parasitic element can cause interference with circuit operation, thus resulting in a malfunction and then breakdown of the input terminal. Therefore, pay thorough attention not to handle the input terminals, such as to apply to the input terminals a voltage lower than the GND respectively, so that any parasitic element will operate. Furthermore, do not apply a voltage to the input terminals when no power supply voltage is applied to the IC. In addition, even if the power supply voltage is applied, apply to the input terminals a voltage lower than the power supply voltage or within the guaranteed value of electrical characteristics. (10) Ground wiring pattern If small-signal GND and large-current GND are provided, It will be recommended to separate the large-current GND pattern from the small-signal GND pattern and establish a single ground at the reference point of the set PCB so that resistance to the wiring pattern and voltage fluctuations due to a large current will cause no fluctuations in voltages of the small-signal GND. Pay attention not to cause fluctuations in the GND wiring pattern of external parts as well. (11) External capacitor In order to use a ceramic capacitor as the external capacitor, determine the constant with consideration given to a degradation in the nominal capacitance due to DC bias and changes in the capacitance due to temperature, etc. (12) Others In case of use this LSI, please peruse some other detail documents, we called ,Technical note, Functinal description, Application note. REV. A Notice Notes No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. 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