Table of Contents Revisions Page 1. 5 5 4 4 3 3 2 2 1 1

5
4
3
2
1
Table of Contents
D
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Revisions
TITLE PAGE
PCI SLOT 1 & 2
PCI SLOT 3 & 4
POWER SUPPLIES-2
POWER SUPPLIES-1
ETHERNET
CPLD
BOOT-SBF-BDM
ATA
FLASH
SERIAL
CLOCKING
SDRAM
FPGA
PROBES
AUDIO-USB
USB-BDM INTERFACE
Rev
Description
Date
X1
Original Draft
11/08/06
J.W.
X2
Fixed Flash1, serial
port interfaces, etc.
07/03/07
M.N.
Approved
D
C
C
B
B
A
Transportation & Standard Products Group
6501 William Cannon Drive West
Austin, TX 78735-8598
This document contains information proprietary to Freescale Semiconductor and shall not be used for
engineering design, procurement or manufacture in whole or in part without the express written permission
of Freescale Semiconductor.
Designer:
Drawing Title:
M.Norman & J.Smith
M54455EVB
5
4
3
2
Drawn by:
DEVTECH CAD - RO
Page Title:
Approved:
JOHN WEIL
Size
C
Document Number
PDF: SPF-22131 SOURCE: SCH-22131
Date:
Monday, November 05, 2007
TITLE PAGE
Sheet
1
Rev
C
1
of
17
A
5
4
3
2
1
PCI SLOT #0
ATX3V3
ATX3V3
ATX5V
ATX5V
-12V
PCI SLOT #1
ATX3V3
ATX3V3
ATX5V
+12V
ATX5V
-12V
ATX3V3
+12V
ATX3V3
R134
1
10K
R133
2
1
2
10K
C
G4
E4
D1
B1
F2
B2
B7
C8
C9
A9
D5
C3
C4
B4
C7
D7
C5
A2
B6
A6
A7
C10
SKT360
RN10A
RN10B
RN10C
RN10D
RN11A
RN11B
RN11C
RN11D
RN12A
RN12B
RN12C
RN12D
RN13A
RN13B
RN13C
RN13D
RN14A
RN14B
RN14C
RN14D
RN15A
RN15B
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
22OHM
22OHM
22OHM
22OHM
22OHM
22OHM
22OHM
22OHM
22OHM
22OHM
22OHM
22OHM
22OHM
22OHM
22OHM
22OHM
22OHM
22OHM
22OHM
22OHM
22OHM
22OHM
22OHM
22OHM
22OHM
22OHM
22OHM
22OHM
22OHM
22OHM
22OHM
22OHM
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
22OHM
22OHM
22OHM
22OHM
22OHM
22OHM
22OHM
22OHM
22OHM
22OHM
22OHM
22OHM
22OHM
22OHM
22OHM
22OHM
22OHM
22OHM
22OHM
22OHM
22OHM
22OHM
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
1
2
5.1K
PCI_IRQ0
C133
0.01UF
C132
0.01UF
PCI_CLK0
PCI_REQ0
PCI_AD31
PCI_AD29
PCI_AD27
PCI_AD25
PCI_C_BE3
PCI_AD23
PCI_AD21
PCI_AD19
R969
75 OHM
PCI_AD17
PCI_C_BE2
PCI_C_BE3
PCI_C_BE2
PCI_C_BE1
PCI_C_BE0
PCI_DEVSEL
PCI_FRAME
PCI_GNT3
PCI_GNT2
PCI_GNT1
PCI_GNT0
PCI_IDSEL
PCI_IRDY
PCI_PAR
PCI_PERR
PCI_REQ3
PCI_REQ2
PCI_REQ1
PCI_REQ0
PCI_RESET
PCI_SERR
PCI_STOP
PCI_TRDY
PCI_IRDY
PCI_DEVSEL
PCI_LOCK
PCI_PERR
PCI_SERR
PCI_C_BE1
PCI_AD14
PCI_AD12
PCI_AD10
M66EN
PCI_AD8
PCI_AD7
PCI_AD5
PCI_AD3
PCI_AD1
PCI
ACK64N
2 C120
0.1 UF
1
CT1
1
B
1
0 OHM
SLOT_PCI_REQ0
3
3
4
2
2
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
2
5.1K
PCI_IRQ1
C131
0.01UF
3V3_STANDBY0
PCI_RESET
C130
0.01UF
PCI_CLK1
PCI_GNT0
PCI_REQ1
PCI_AD30
PCI_AD31
PCI_AD29
PCI_AD28
PCI_AD26
PCI_AD27
PCI_AD25
PCI_AD24
PCI_C_BE3
PCI_AD23
PCI_AD22
PCI_AD20
PCI_AD21
PCI_AD19
PCI_AD18
PCI_AD16
PCI_AD17
PCI_C_BE2
PCI_FRAME
PCI_IRDY
PCI_TRDY
PCI_DEVSEL
PCI_STOP
PCI_LOCK
PCI_PERR
PCI0_SDONE
PCI0_SBO
PCI_SERR
PCI_PAR
PCI_AD15
PCI_C_BE1
PCI_AD14
PCI_AD13
PCI_AD11
PCI_AD12
PCI_AD10
M66EN
PCI_AD9
PCI_C_BE0
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD4
PCI_AD5
PCI_AD3
PCI_AD2
PCI_AD0
PCI_AD1
REQ64N
ACK64N
-12V
TCK
GND
TDO
+5V
+5V
INTB
INTD
PRSNT1
Reserved1
PRSNT2
TRST
+12V
TMS
TDI
+5V
INTA
INTC
+5V
Reserved6
+3.3V (I/O)
Reserved5
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
B50
B51
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
Reserved2
GND
CLK
GND
REQ
3.3V (I/O)
AD31
AD29
GND
AD27
AD25
+3.3V
C/BE3
AD23
GND
AD21
AD19
+3.3V
AD17
C/BE2
GND
IRDY
+3.3V
DEVSEL
GND
LOCK
PERR
+3.3V
SERR
+3.3V
C/BE1
AD14
GND
AD12
AD10
M66EN
GND
GND
AD08
AD07
+3.3V
AD05
AD03
GND
AD01
+3.3V (I/O)
ACK64
+5V
+5V
+3.3V (AUX)
RST
+3.3V (I/O)
GNT
GND
PME
AD30
+3.3V
AD28
AD26
GND
AD24
IDSEL
+3.3V
AD22
AD20
GND
AD18
AD16
+3.3V
FRAME
GND
TRDY
GND
STOP
+3.3V
Reserved4
Reserved3
GND
PAR
AD15
+3.3V
AD13
AD11
GND
AD09
GND
GND
C/BE0
+3.3V
AD06
AD04
GND
AD02
AD00
+3.3V (I/O)
REQ64
+5V
+5V
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
PCI 32BIT/3.3V
2
1
D
5.1K
PCI1_TMS
PCI1_TDI
3V3_STANDBY1
PCI_RESET
PCI_GNT1
PCI_AD30
PCI_AD28
PCI_AD26
PCI_AD24
PCI_AD22
PCI_AD20
75 OHM
R146
PCI_AD18
PCI_AD16
PCI_FRAME
PCI_TRDY
PCI_STOP
C
PCI1_SDONE
PCI1_SBO
PCI_PAR
PCI_AD15
PCI_AD13
PCI_AD11
PCI_AD9
PCI_C_BE0
PCI_AD6
PCI_AD4
PCI_AD2
PCI_AD0
REQ64N
PCI 32BIT/3.3V
Cut-Trace Options - Slot 1
By default, PCI_REQ1 and PCI_GNT1 routed
directly to PCI Slot 1 from U1.
To route through FPGA, cut trace between
1 and 2 on CT5 and solder 1 to 3. Then, cut
trace between 1 and 2 on CT6 and solder
1 to 3.
4
4
1
1
4
0 OHM
CF_PCI_REQ0
3 3
ATX3V3
1
1
0 OHM
SLOT_PCI_GNT0
3
3
CT4
2
4
2
2
4
4
+
PCI_GNT0
PCI_GNT1
PCI_FRAME
PCI_REQ0
PCI_REQ1
PCI_LOCK
PCI_STOP
PCI_IRDY
1
2
1
4
0 OHM
CF_PCI_GNT0
3 3
1C252
33UF
ATX3V3
RP10
PCI0_TMS
PCI0_TDI
PCI0_SBO
PCI0_SDONE
PCI1_SBO
PCI1_SDONE
PCI1_TMS
PCI1_TDI
ATX3V3
RP3
PCI_GNT0
2 C271
0.1 UF
2
+3.3V (AUX)
RST
+3.3V (I/O)
GNT
GND
PME
AD30
+3.3V
AD28
AD26
GND
AD24
IDSEL
+3.3V
AD22
AD20
GND
AD18
AD16
+3.3V
FRAME
GND
TRDY
GND
STOP
+3.3V
Reserved4
Reserved3
GND
PAR
AD15
+3.3V
AD13
AD11
GND
AD09
GND
GND
C/BE0
+3.3V
AD06
AD04
GND
AD02
AD00
+3.3V (I/O)
REQ64
+5V
+5V
1
5.1K
PCI0_TMS
PCI0_TDI
R123
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
R141
75 OHM
2
CT3
1
Reserved2
GND
CLK
GND
REQ
3.3V (I/O)
AD31
AD29
GND
AD27
AD25
+3.3V
C/BE3
AD23
GND
AD21
AD19
+3.3V
AD17
C/BE2
GND
IRDY
+3.3V
DEVSEL
GND
LOCK
PERR
+3.3V
SERR
+3.3V
C/BE1
AD14
GND
AD12
AD10
M66EN
GND
GND
AD08
AD07
+3.3V
AD05
AD03
GND
AD01
+3.3V (I/O)
ACK64
+5V
+5V
J15
R450
1
CT2
2
2 C272
0.1 UF
1
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
B50
B51
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
2
PCI_REQ0
2 C119
0.1 UF
1
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
2
ATX5V
1
Cut-Trace Options - Slot 0
By default, PCI_REQ0 and PCI_GNT0 routed
directly to PCI Slot 0.
To route through FPGA, cut trace between
1 and 2 on CT1 and solder 1 to 3. Then, cut
trace between 1 and 2 on CT2 and solder
1 to 3. Repeat this process for CT3 and CT4.
TRST
+12V
TMS
TDI
+5V
INTA
INTC
+5V
Reserved6
+3.3V (I/O)
Reserved5
1
PCICBE3b
PCICBE2b
PCICBE1b
PCICBE0b
PCIDEVSELb
PCIFRAMEb
PCIGNT3BATADMACKb
PCIGNT2b
PCIGNT1b
PCIGNT0BPCIEXTREQb
PCIIDSEL
PCIIRDYb
PCIPAR
PCIPERRb
PCIREQ3ATAINTRQ
PCIREQ2b
PCIREQ1b
PCIREQ0PCIEXTGNTb
PCIRSTb
PCISERRb
PCISTOPb
PCITRDYb
RN2A
RN2B
RN2C
RN2D
RN3A
RN3B
RN3C
RN3D
RN4A
RN4B
RN4C
RN4D
RN5A
RN5B
RN5C
RN5D
RN6A
RN6B
RN6C
RN6D
RN7A
RN7B
RN7C
RN7D
RN8A
RN8B
RN8C
RN8D
RN9A
RN9B
RN9C
RN9D
-12V
TCK
GND
TDO
+5V
+5V
INTB
INTD
PRSNT1
Reserved1
PRSNT2
2
C1
D2
C2
F3
E1
E2
E3
D3
D4
B3
A3
A4
B5
A5
B8
A8
D10
D9
B9
B11
A11
B12
C12
D12
F1
G3
G2
J4
B10
A10
D11
C11
1
PCIAD0
PCIAD1
PCIAD2
PCIAD3
PCIAD4
PCIAD5
PCIAD6
PCIAD7
PCIAD8
PCIAD9
PCIAD10
PCIAD11
PCIAD12
PCIAD13
PCIAD14
PCIAD15
PCIAD16
PCIAD17
PCIAD18
PCIAD19
PCIAD20
PCIAD21
PCIAD22
PCIAD23
PCIAD24
PCIAD25
PCIAD26
PCIAD27
PCIAD28
PCIAD29
PCIAD30
PCIAD31
2
D
R124
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
PCI Connector 32 Bit / 3.3V
R115
PCI Connector 32 Bit / 3.3V
J14
U1C
RP9
1
CT5
1
2
3
4
5
7
8
9
10
2
3
4
5
7
8
9
10
PCI_TRDY
PCI_PERR
PCI_SERR
PCI_DEVSEL
REQ64N
ACK64N
PCI_REQ1
1
CT6
PCI_GNT1
1
2
2
0 OHM
3 3
4
4 F_PCI_REQ1
1
1
2
2
0 OHM
3 3
4
4 F_PCI_GNT1
1
2
3
4
5
7
8
9
10
B
6
10K
6
6
10K
10K
ATX3V3
PCI SLOT #1
ATX3V3
1
1
C152
0.1 UF
C139
0.1 UF
C144
0.1 UF
2
C260
0.1 UF
2
1
1
C159
0.1 UF
2
2
C194
0.1 UF
2
1
1
C179
0.1 UF
2
C212
0.1 UF
2
2
C223
0.1 UF
1
1
1
C250
0.1 UF
2
1
C136
0.1 UF
2
1
C261
0.1 UF
2
1
C255
33UF
2
C180
0.1 UF
2
+
1
C213
0.1 UF
2
C195
0.1 UF
2
2
C224
0.1 UF
2
C262
0.1 UF
1
1
1
1
C237
0.1 UF
2
1
C153
0.1 UF
2
1
C160
0.1 UF
2
C251
0.1 UF
2
C263
0.1 UF
1
1
1
C145
0.1 UF
2
2
C140
0.1 UF
2
1
1
C253
33UF
PCI Notes:
2
+
2
1
1
PCI SLOT #0
1. CF_PCI_GNTn and CF_PCI_REQn signals connect to
the FPGA. PCI_GNTn and PCI_REQn signals are
connected from the FPGA to the PCI slots.
-12V
H8
HDR_1X2_M
A
1
R116
2
0 OHM
3V3_STANDBY1
1
R117
2
0 OHM
2. PCI
PCI
PCI
PCI
Slot
Slot
Slot
Slot
#0
#1
#2
#3
uses
uses
uses
uses
PCI_REQ0
PCI_REQ1
PCI_REQ2
PCI_REQ3
and
and
and
and
PCI_GNT0
PCI_GNT1
PCI_GNT2
PCI_GNT3
1
2 C118
0.1 UF
1
2 C269
0.1 UF
1
2 C270
0.1 UF
1
2 C117
0.1 UF
H36
A
3. MCF5445x
PCI Slot
PCI Slot
PCI Slot
PCI Slot
3
2
2
1
3V3_STANDBY0
+12V
ATX5V
1
IDSEL connected to
#0 IDSEL connected
#1 IDSEL connected
#2 IDSEL connected
#3 IDSEL connected
PCI_AD16
to PCI_AD17
to PCI_AD18
to PCI_AD19
to PCI_AD20
HDR_1X3
4. The FPGA gathers interrupts from the PCI slots.
3V3_STANDBY2
3V3_STANDBY3
1
1
R118
2
0 OHM
R119
2
0 OHM
5
4
5. JTAG is unusable on PCI connectors
Drawing Title:
M54455EVB
Page Title:
2
+
The ATX power supply provides
+/- 12V power to the connectors.
This header can be used to monitor
the supply.
3
2
1C254
33UF
PCI SLOT #0 AND #1
Size
C
Document Number
Date:
Monday, November 05, 2007
Rev
C
870012704-100
1
Sheet
2
of
17
5
4
3
ATX3V3
2
ATX3V3
PCI SLOT #2
ATX5V
ATX3V3
ATX5V
-12V
+12V
1
-12V
1
10K
PCI_CLK2
PCI_REQ2
PCI_AD31
PCI_AD29
PCI_AD27
PCI_AD25
PCI_C_BE3
PCI_AD23
PCI_AD21
PCI_AD19
PCI_AD17
PCI_C_BE2
PCI_IRDY
PCI_DEVSEL
PCI_LOCK
PCI_PERR
PCI_SERR
PCI_C_BE1
PCI_AD14
PCI_AD12
PCI_AD10
M66EN
PCI Notes:
PCI_AD8
PCI_AD7
PCI_REQ0
PCI_REQ1
PCI_REQ2
PCI_REQ3
and
and
and
and
IDSEL connected to
#0 IDSEL connected
#1 IDSEL connected
#2 IDSEL connected
#3 IDSEL connected
PCI_AD1
PCI_GNT0
PCI_GNT1
PCI_GNT2
PCI_GNT3
ACK64N
1
uses
uses
uses
uses
PCI_AD16
to PCI_AD17
to PCI_AD18
to PCI_AD19
to PCI_AD20
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
B50
B51
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
Reserved2
GND
CLK
GND
REQ
3.3V (I/O)
AD31
AD29
GND
AD27
AD25
+3.3V
C/BE3
AD23
GND
AD21
AD19
+3.3V
AD17
C/BE2
GND
IRDY
+3.3V
DEVSEL
GND
LOCK
PERR
+3.3V
SERR
+3.3V
C/BE1
AD14
GND
AD12
AD10
M66EN
GND
GND
AD08
AD07
+3.3V
AD05
AD03
GND
AD01
+3.3V (I/O)
ACK64
+5V
+5V
+3.3V (AUX)
RST
+3.3V (I/O)
GNT
GND
PME
AD30
+3.3V
AD28
AD26
GND
AD24
IDSEL
+3.3V
AD22
AD20
GND
AD18
AD16
+3.3V
FRAME
GND
TRDY
GND
STOP
+3.3V
Reserved4
Reserved3
GND
PAR
AD15
+3.3V
AD13
AD11
GND
AD09
GND
GND
C/BE0
+3.3V
AD06
AD04
GND
AD02
AD00
+3.3V (I/O)
REQ64
+5V
+5V
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
J17
2
PCI2_TMS
PCI2_TDI
R452
1
1
5.1K
2
5.1K
PCI_IRQ3
C141
0.01UF
3V3_STANDBY2
PCI_RESET
C137
0.01UF
PCI_CLK3
PCI_GNT2
PCI_REQ3_JMP
PCI_AD30
PCI_AD31
PCI_AD29
PCI_AD28
PCI_AD26
PCI_AD27
PCI_AD25
PCI_AD24
PCI_C_BE3
PCI_AD23
PCI_AD22
PCI_AD20
PCI_AD21
PCI_AD19
PCI_AD18
PCI_AD16
PCI_AD17
PCI_C_BE2
PCI_FRAME
PCI_IRDY
PCI_TRDY
PCI_DEVSEL
PCI_STOP
PCI_LOCK
PCI_PERR
PCI2_SDONE
PCI2_SBO
PCI_SERR
PCI_PAR
PCI_AD15
PCI_C_BE1
PCI_AD14
PCI_AD13
PCI_AD11
PCI_AD12
PCI_AD10
M66EN
PCI_AD9
PCI_C_BE0
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD4
PCI_AD5
PCI_AD3
PCI_AD2
PCI_AD0
PCI_AD1
REQ64N
ACK64N
R154
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
-12V
TCK
GND
TDO
+5V
+5V
INTB
INTD
PRSNT1
Reserved1
PRSNT2
TRST
+12V
TMS
TDI
+5V
INTA
INTC
+5V
Reserved6
+3.3V (I/O)
Reserved5
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
B50
B51
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
Reserved2
GND
CLK
GND
REQ
3.3V (I/O)
AD31
AD29
GND
AD27
AD25
+3.3V
C/BE3
AD23
GND
AD21
AD19
+3.3V
AD17
C/BE2
GND
IRDY
+3.3V
DEVSEL
GND
LOCK
PERR
+3.3V
SERR
+3.3V
C/BE1
AD14
GND
AD12
AD10
M66EN
GND
GND
AD08
AD07
+3.3V
AD05
AD03
GND
AD01
+3.3V (I/O)
ACK64
+5V
+5V
+3.3V (AUX)
RST
+3.3V (I/O)
GNT
GND
PME
AD30
+3.3V
AD28
AD26
GND
AD24
IDSEL
+3.3V
AD22
AD20
GND
AD18
AD16
+3.3V
FRAME
GND
TRDY
GND
STOP
+3.3V
Reserved4
Reserved3
GND
PAR
AD15
+3.3V
AD13
AD11
GND
AD09
GND
GND
C/BE0
+3.3V
AD06
AD04
GND
AD02
AD00
+3.3V (I/O)
REQ64
+5V
+5V
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
PCI 32BIT/3.3V
2
1
D
5.1K
PCI3_TMS
PCI3_TDI
3V3_STANDBY3
PCI_RESET
PCI_GNT3
PCI_AD30
PCI_AD28
PCI_AD26
PCI_AD24
PCI_AD22
PCI_AD20
75 OHM
R152
PCI_AD18
PCI_AD16
PCI_FRAME
PCI_TRDY
PCI_STOP
C
PCI3_SDONE
PCI3_SBO
PCI_PAR
PCI_AD15
PCI_AD13
PCI_AD11
PCI_AD9
PCI_C_BE0
PCI_AD6
PCI_AD4
PCI_AD2
PCI_AD0
REQ64N
PCI 32BIT/3.3V
R147
75 OHM
2
3. MCF5445x
PCI Slot
PCI Slot
PCI Slot
PCI Slot
#0
#1
#2
#3
PCI_AD5
PCI_AD3
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
1
C134
0.01UF
TRST
+12V
TMS
TDI
+5V
INTA
INTC
+5V
Reserved6
+3.3V (I/O)
Reserved5
2
PCI_IRQ2
-12V
TCK
GND
TDO
+5V
+5V
INTB
INTD
PRSNT1
Reserved1
PRSNT2
PCI Connector 32 Bit / 3.3V
2
5.1K
1. CF_PCI_GNTn and CF_PCI_REQn signals connect to
the FPGA. PCI_GNTn and PCI_REQn signals are
connected from the FPGA to the PCI slots.
2
R131
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
PCI Connector 32 Bit / 3.3V
1
Slot
Slot
Slot
Slot
+12V
10K
J16
R451
2. PCI
PCI
PCI
PCI
ATX5V
R153
2
C
PCI SLOT #3
ATX3V3
R135
C135
0.01UF
ATX3V3
ATX5V
ATX3V3
D
1
4. The FPGA gathers interrupts from the PCI slots.
5. JTAG is unusable on PCI connectors
B
B
Cut-Trace Options - Slot 3
By default, PCI_REQ3 and PCI_GNT3 routed
directly to PCI Slot 3 from U1.
To route through FPGA, cut trace between
1 and 2 on CT9 and solder 1 to 3. Then, cut
trace between 1 and 2 on CT10 and solder
1 to 3.
Cut-Trace Options - Slot 2
By default, PCI_REQ2 and PCI_GNT2 routed
directly to PCI Slot 2 from U1.
To route through FPGA, cut trace between
1 and 2 on CT7 and solder 1 to 3. Then, cut
trace between 1 and 2 on CT8 and solder
1 to 3.
ATX3V3
RP4
CT9
CT7
PCI_REQ2
1
1
0 OHM
3 3
CT8
PCI_GNT2
2
2
4
4 F_PCI_REQ2
1
1
0 OHM
3 3
PCI_REQ3_JMP
2
2
4
4 F_PCI_GNT2
1
1
CT10
2
0 OHM
3 3
4
PCI_GNT3
2
4 F_PCI_REQ3
1
1
2
2
0 OHM
3 3
4
4 F_PCI_GNT3
1
PCI_GNT2
PCI_GNT3
PCI_REQ2
PCI_REQ3_JMP
2
3
4
5
7
8
9
10
6
10K
ATX3V3
RP7
ATX5V
ATX5V
ATX3V3
ATX3V3
A
C150
0.1 UF
1
C167
0.1 UF
2
1
1
C234
0.1 UF
2
C248
0.1 UF
2
1
1
C192
0.1 UF
2
C177
0.1 UF
2
1
1
C210
0.1 UF
2
C280
0.1 UF
2
C279
0.1 UF
1
1
1
C284
0.1 UF
2
C221
0.1 UF
2
C408
33UF
2
+
1
1
2 C278
0.1 UF
C157
0.1 UF
1
2
3
4
5
7
8
9
10
6
2
C259
0.1 UF
2
C249
0.1 UF
1
1
1
2 C277
0.1 UF
2
C258
0.1 UF
2
1
1
C235
0.1 UF
2
C178
0.1 UF
2
1
1
C211
0.1 UF
2
C193
0.1 UF
2
1
1
C222
0.1 UF
2
C158
0.1 UF
2
1
1
C143
0.1 UF
2
C151
0.1 UF
2
1
1
C138
0.1 UF
2
C265
33UF
PCI SLOT #3
1
2
+
2
2 C115
0.1 UF
2
1
1
2 C116
0.1 UF
1
PCI SLOT #2
1
PCI3_TMS
PCI3_TDI
PCI3_SBO
PCI3_SDONE
PCI2_SBO
PCI2_SDONE
PCI2_TMS
PCI2_TDI
1
2 C100
0.1 UF
1
2 C267
0.1 UF
1
2 C102
0.1 UF
2
1C264
33UF
2
1C407
33UF
+
2 C268
0.1 UF
+
1
10K
A
Drawing Title:
M54455EVB
Page Title:
PCI SLOTS #2 & #3
5
4
3
2
Size
C
Document Number
Date:
Monday, November 05, 2007
Rev
C
870012704-100
1
Sheet
3
of
17
2
1
D
VDD
2 C232
0.1uF
1
2 C218
0.1uF
1
1
2 C241
0.1uF
1
1
2 C217
0.1uF
1
1
2 C208
0.1uF
1
2 C276
0.1uF
1
2 C207
0.1uF
1
2 C188
0.1uF
1
2 C206
0.1uF
1
2 C172
0.1uF
1
2 C205
0.1uF
1
2 C677
0.1uF
1
2 C204
0.1uF
1
2 C173
0.1uF
1
2 C216
0.1uF
1
2 C220
0.1uF
1
2C25
33UF
2C15
33UF
VCC
VCC
VCC
2C21
33UF
2C17
33UF
D
1
VCC
1
TP5
Power Indicators
VCC
VDD
+
V1.5P
+
3
+
4
+
5
R193
1.0K
R192
1.0K
R190
1.0K
R188
1.0K
R57
1.0K
Jumper for LED
on case ON/OFF
switch
1
1
D17
LED RED
2
D14
LED RED
2
VTT
Q4
MMBT3904LT1G
1.0K
C
U1I
3
1.0K
MMBT3904LT1G
1.0K
C
1
2 C230
0.1uF
1
2 C266
0.1uF
1
2 C229
0.1uF
1
2 C215
0.1uF
1
2 C240
0.1uF
1
2 C244
0.1uF
1
2 C231
0.1uF
1
2 C228
0.1uF
1
2 C243
0.1uF
1
2 C233
0.1uF
1
2 C242
0.1uF
1
2 C257
0.1uF
1
2 C176
0.1uF
1
2 C219
0.1uF
1
2 C191
0.1uF
1
2 C190
0.1uF
1
2 C209
0.1uF
1
2 C256
0.1uF
1
2 C189
0.1uF
VDDP
VDDE1
VDDE2
VDDE3
VDDE4
VDDE5
VDDE6
VDDE7
VDDE8
VDDE9
VDDE10
VDDE11
VDDE12
VDDE13
VDDE14
VDDE15
VDDE16
VDDE17
D13
D19
J7
G8
G11
G14
G16
J16
L7
L16
P7
N16
R16
T8
T12
T14
T16
SDVDD1
SDVDD2
SDVDD3
SDVDD4
SDVDD5
SDVDD6
F19
H19
K19
M19
R19
U19
VEEP
microATX Mouting Holes
V1.5P
C316
0.01UF
C317
0.01UF
C318
0.01UF
C319
0.01UF
C320
0.01UF
C321
0.01UF
C322
470PF
C323
470PF
MNT_HOLE
MH2
F
C
C327
0.01UF
C328
0.01UF
C329
0.01UF
C330
0.01UF
C333
0.01UF
C334
0.01UF
L2
100MHZ
2
C331
470PF
C332
470PF
1
C325
0.01UF
1
C324
0.01UF
1
2
B13
B15
C15
D16
Y21
AA9
AA20
MNT_HOLE
MH3
2
VDDP
NC1
NC2
NC3
NC4
NC5
NC6
NC7
L35
100MHZ
L37
100MHZ
2
1
VEEP
L36
100MHZ
1
L1
100MHZ
1
C315
470PF
2
2
C314
470PF
2
C313
0.01UF
J
1
C312
0.01UF
MNT_HOLE
MH6
H
2
C311
0.01UF
MNT_HOLE
MH5
R
B
L22
100MHZ
1
C310
0.01UF
MNT_HOLE
MH4
2
C309
0.01UF
MNT_HOLE
MH1
B
2
C308
0.01UF
1
2
V1.5P
1
CVDD1
CVDD2
CVDD3
CVDD4
CVDD5
CVDD6
CVDD7
CVDD8
CVDD9
CVDD10
CVDD11
CVDD12
CVDD13
F4
D6
D8
D14
H4
N4
R4
W4
W7
W8
W12
W16
W19
2
B
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
GND11
GND12
GND13
GND14
GND15
GND16
GND17
GND18
GND19
GND20
GND21
GND22
GND23
GND24
GND25
GND26
GND27
GND28
GND29
GND30
GND31
GND32
GND33
GND34
GND35
GND36
GND37
GND38
GND39
GND40
GND41
GND42
GND43
GND44
GND45
GND46
GND47
GND48
GND49
GND50
GND51
GND52
GND53
GND54
GND55
GND56
GND57
GND58
GND59
GND60
GND61
GND62
R58
Q1
1
MMBT3904LT1G
1
N7
R7
N9
P9
N10
P10
P11
P12
P13
P14
N11
N12
N13
N14
P16
K7
K9
K10
K11
K12
K13
K14
K16
L9
L10
L11
L12
L13
L14
M7
M9
M10
M11
M12
M13
M14
M16
T7
T9
T10
T11
T13
T15
AB1
AB22
H16
H7
B14
J9
J10
J11
J12
J13
J14
A1
A22
G7
G9
G10
G12
G13
G15
R207
Q5
1
2
2
1
V1.2
2
3
R206
3
V1.5P
1
HDR_1X3_M
D9
LED RED
2
2
D5
LED RED
2
D3
LED RED
1
2
3
1
1
H9
1
2
R194
220 OHM
SKT360
POWER
A
A
Drawing Title:
M54455EVB
Page Title:
POWER SUPPLIES 2
5
4
3
2
Size
C
Document Number
Date:
Monday, November 05, 2007
Rev
C
870012704-100
1
Sheet
4
of
17
5
4
ATX3V3
3
2
ATX5V
1
VCC
F1
D
+12V +5VSB
PWR_OK
1
2
R70
100 OHM
R71
100 OHM
2
R69
100 OHM
C274
100UF
2
+
2
2
C198
0.1uF
3
3
1
1
1
1
D22
MBRD835L
D21
MBRD835L
1SMC5.OAT3
1
4
4
D16
1
R68
100 OHM
C
1
R67
100 OHM
A
2
1
R66
100 OHM
C273
100UF
+
2
5A
2
C197
0.1uF
2
11
12
13
14
15
16
17
18
19
20
2
3.3V
-12V
GND
PS-ON
GND
GND
GND
-5V
5V
5V
2
-12V
3.3V
3.3V
GND
5V
GND
5V
GND
PW-OK
5VSB
12V
1
J50
1
2
3
4
5
6
7
8
9
10
1
1
1
D
Default is not populated.
Default is not populated.
ATX3V3
HDR2X10
(Powered by 5V standby supply)
C406
10UF
+5VSB
2
C410 +
100UF
2
2
+
2
H12
HDR_1X2_M
1
VCC
1
D1
R162
28K
RLS4148
L23
1
10uH
2
2
1.0UF
C22
H11
HDR_1X2_M
U21
NTD20N03L27T4G
1
PS_ON_b
C
VDD
VDDP
+5VSB
R72
.022 OHM
MC34702
2
1
1
0 OHM
C281
100UF
3
2
4
PWRBTN_b
C297
0.01UF
TL3301AF160QG
1
2
NC VCC
A
5
3
GND
4
Y
1
2
SN74LVC1G14DBVR
R164
10.0K
1
2
C294
6.8nF
+5VSB
U922
2
+
1
2
1
1
2
C18
4.7UF
2
2
2
C295
0.01UF
C201
10UF
+
2
1
11
1
2
R157
2
1.50K
1
R662
4.7K
SW4
R163
31.6K
C200
10UF
Note: All power rails ending in "P" are dedicated
MCF5445x supplies. The header and 0 ohm
resistor facilitate current measurement on
these supplies.
C411
22UF NOTE: DEFAULT
IS NOT POPULATED
1
R665
+
1
1
1
R656
2
0 OHM
R657
2
0 OHM
NOTE: DEFAULT
IS NOT POPULATED
1
VCC
4
1
5.11K
C214
10UF
1
1
+
2
1
2
1
C293
470PF
C
1
1
2
R165 5.11K
+
2
2
C199
0.1uF
1
2 R230
10.0K
SN74LVC2G74DCTR
R659
0 OHM
2
1
1
1
R161
330K
2
2
2
R160
300 OHM
12
R159
39K
C275
100UF
+
1
1
1
1
1
2
C16
4.7UF
2
C196
10UF
2
CLKSYN
CLKSEL
RST
RT
EN2
EN1
ADDR
GND3
GND4
VDD1
VIN1
LDRV
CS
LDO
LFB
LCMP
8
7
6
5
R167
3
L25
FREQ
INV
VOUT
VIN21
VIN22
SW1
SW2
GND1
GND2
PGND1
PGND2
VBD
VBST
BOOT
SDA
SCL
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
CLK VCC
D
PRE
Q
CLR
GND Q
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
0 OHM
4.7UH
3.3 VDC REGULATOR
U100
R158 49.9K
1
2
1
R166
5.10K
2
VCC
1.8 VDC REGULATOR
1
2
3
4
2
2
1
PWR_OK
R660
15.0K
2
VEEP
R664
+
R661
4.7K
U921
2
VEE
2
C409
100UF
+
1
1
1
ATX Power Supply On/Off Switch
PS_ON_b
H15
HDR_1X2_M
VDD
H13
HDR_1X2_M
2
VDD
2
R184
1.00K
1
1.5 VDC REGULATOR
C225
0.1uF
2
1
1
VCC
D2
R175
40.2K
RLS4148
L24
1
10uH
2
R231
2
1
1
10.0K
R181
2
5.11K
C238
10UF
HDR_1X2_M
VCC
C356
470PF
2
VCC
4
TL3301AF160QG
B
JP917
F2
PWR_OK
2 C29
1.0UF
1
1
H14
+
3
2
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
2
CLKSYN
CLKSEL
RST
RT
EN2
EN1
ADDR
GND3
GND4
VDD1
VIN1
LDRV
CS
LDO
LFB
LCMP
1
1
2
5A
barreljack_vcc 1
3
2
RAPC722
U22
NTD20N03L27T4G
1
1.2 VDC REGULATOR
R73
.022 OHM
MC34702
V1.2
VCC
VDD
VCC
1
1
1
+
C282
100UF
1
2
3
4
5
6
2
2
C24
4.7UF
2
2
1
C299
0.01UF
C227
10UF
R183
C298 20.0 K
6.8nF
C30
10UF
+
1x6
1
2
2.5 VDC REGULATOR
R177 2
1.50K
2
1
1
+
2
R182
10.0K
C226
10UF
2
+
1
11
1
2
2
J21
2
R176
330K
1
1
1
C296
470PF
2
2
R174
300 OHM
12
R173
39K
C283
100UF
+
2
C23
4.7UF
L26 2
4.7UH
2
1
1
C239
10UF
2
+
2
1
1
1
FREQ
INV
VOUT
VIN21
VIN22
SW1
SW2
GND1
GND2
PGND1
PGND2
VBD
VBST
BOOT
SDA
SCL
1
2
3
0 OHM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
R172 2
49.9K
2
1
2
R658
H10
HDR_1X2_M
SW2
U24
V1.5
B
BRD_RESET
4
2
1
VCC
1
R180
5.10K
V1.5P
Power barrel connector.
Note that the PCI slots are only operational
if an ATX power supply (J50) is used.
VDD
U920
LD1117DT25CTR
2
C1
0.1uF
GND/ADJ
+
1
C1012
10UF
A
2
2
A
J21 in intended for Freescale use only.
The ATX connector (J50) is the preferred
power supply method.
1
VOUT
1
3 VIN
V2.5
Drawing Title:
M54455EVB
Page Title:
POWER SUPPLIES 1
5
4
3
2
Size
C
Document Number
Date:
Monday, November 05, 2007
Rev
C
870012704-100
1
Sheet
5
of
17
2
1
VDD
VDD
C952
0.1 UF
C765
0.1 UF
2
220 OHM
VDD
2
2
R950
2
2
2
2
2
VDD
1
C766
R952
R953
0.1 UF
49.9 OHM49.9 OHM
R951
R765
C950
49.9 OHM49.9 OHM 0.1 UF
VDD
1
1
1
VDD
1
1
1
VDD
1
3
2
4
1
5
D
D
R946
4.7K
R945
4.7K
VDD
PFBOUT
Upper Port
CLK2MAC
TRD1TRCT1
TRD1+
RJ1
RJ2
TRP1-
ETH1_RXD5
ETH1_RXD_CT 12
ETH1_RXD+
11
TRD2TRCT2
TRD2+
RJ3
TRP2+
RJ6
TRP2-
10
4
3
TRD3TRCT3
TRD3+
RJ4
TRP3+
RJ5
TRP3-
2
9
8
TRD4TRCT4
TRD4+
RJ7
TRP4+
RJ8
TRP4-
1
GND2
68
To ATA Interface
FEC1_RMII_TXD1
FEC1_RMII_TXD0
R301 1
R302 1
FEC1_RMII_TXEN
R303 1
45
46
22
OHM
47
2
2 22 OHM48
TXD3_B/SNI_MODE_B
TXD2_B
TXD1_B
TXD0_B
2 22 OHM49
50
TX_EN_B
TX_CLK_B
FEC1_RMII_RXD1
FEC1_RMII_RXD0
R304 1
R305 1
53
56
22
OHM
57
2
2 22 OHM58
FEC1_RMII_RXER
FEC1_RMII_CRS_DV
R306 1
R307 1
59
2 22 OHM60
22
OHM
61
2
C
PHY1_PWRDN
PWRDOWN_INT_A
18
PHY0_PWRDN
ETH1_LED_LINK- 31
ETH1_LED_LINK+ 32
LED_LINK_B/AN0_B
LED_SPEED_B/FXSD_B/AN1_B
LED_ACT/COL_B/AN_EN_B
RXD3_B/ED_EN_B
RXD2_B/EXTENDER_EN
RXD1_B/PHYAD4
RXD0_B/PHAD3
COL_B/FX_EN_B
RX_ER_B/MDIX_EN_B
CRS_B/CRS_DV_B/LED_CFG_B
43
42
41
1
R587 2
LED3_C
LED3_A
ETH1_LED_SC- 33
ETH1_LED_SC+ 34
LED4_GC
LED4_GA
220 OHM
0845-2R1T-E4
62
63
RX_DV_B/MII_MODE_B
RX_CLK_B
TPTDM_B/FXTDM_B
TPTDP_B/FXTDP_B
36
35
79
80
RX_CLK_A
RX_DV_A/MII_MODE_A
TPTDP_A/FXTDP_A
TPTDM_A/FXTDM_A
27
26
CRS_A/CRS_DV_A/LED_CFG_A
RX_ER_A/MDIX_EN_A
COL_A/FX_EN_A
TPRDP_A/FXRDP_A
TPRDM_A/FXRDM_A
24
23
1
TPRDM_B/FXRDM_B
TPRDP_B/FXRDP_B
39
38
LED_ACT/COL_A/AN_EN_A
LED_SPEED_A/FXSD_A/AN1_A
LED_LINK_A/AN0_A
21
20
19
2
FEC1_RMII_REF_CLK
RMIICLK2
PWRDOWN_INT_B
44
TRP1+
TDI
TRSTN
TMS
TDO
TCK
76
75
74
73
72
Ethernet Channel 1
LED1 indicates a LINK and
blinks for activity.
LED2 indicates Speed (10/100
Mbps) and Collision (when in
10 Mbps mode). LED2 is GREEN
for 100Mbps mode, OFF for
10Mbps, and blinking ORANGE
for Collisions.
Chassis_GND
Chassis_GND
28
34
7
54
PFBIN2
PFBIN3
PFBIN1
PFBIN4
PFBOUT
11
51
65
78
IOVDD1
IOVDD2
IOVDD3
IOVDD4
MDIO
MDC
ANA33VDD
66
67
30
U901
31
2
2
2
P5B
ETH1_TXD13
ETH1_TXD_CT 7
ETH1_TXD+
6
S3
S4
R944
4.7K
1
1
1
VDD
C
TXD0_A
TXD1_A
TXD2_A
TXD3_A/SNI_MODE_A
69
70
FECO/RMII
22
29
33
40
R948
4.7K
2
2
R949
4.87K
R954
RMIICLK1
RMIICLK0
CPU_RSTOUT
1
2
VDD
VDD
2
2
C9
0.1 UF
C3
10UF
1
1
1
C8
0.1 UF
2
1
C7
0.1 UF
2
1
C6
0.1 UF
2
1
C2
0.1 UF
2
1
C31
0.1 UF
2
1
C14
0.1 UF
2
1
C12
0.1 UF
2
1
2
1
2
C11
0.1 UF
+
C4
0.1 UF
VDD
1
1
2
2
TRD1TRCT1
TRD1+
RJ1
TRP1+
RJ2
TRP1-
ETH0_RXD16
ETH0_RXD_CT 22
ETH0_RXD+
23
TRD2TRCT2
TRD2+
RJ3
TRP2+
C956
0.1 UF
RJ6
TRP2-
24
17
18
TRD3TRCT3
TRD3+
RJ4
TRP3+
RJ5
TRP3-
19
25
26
TRD4TRCT4
TRD4+
RJ7
TRP4+
RJ8
TRP4-
20
GND1
ETH0_LED_SC- 29
ETH0_LEC_SC+ 30
Ethernet Channel 0
B
LED1_C
LED1_A
LED2_GC
LED2_GA
LED1 indicates a LINK and
blinks for activity.
LED2 indicates Speed (10/100
Mbps) and Collision (when in
10 Mbps mode). LED2 is GREEN
for 100Mbps mode, OFF for
10Mbps, and blinking ORANGE
for Collisions.
S1
S2
0845-2R1T-E4
A
VDD
Lower Port
ETH0_TXD21
ETH0_TXD_CT 14
ETH0_TXD+
15
220 OHM
PFBOUT
VDD
C955
0.1 UF
2
1
1
R959
220 OHM
R958
R957
C954
49.9 OHM49.9 OHM0.1 UF
ETH0_LED_LINK- 27
ETH0_LED_LINK+ 28
2
DP83849
2
R947
4.7K
2
RBIAS
32
1
RESET_N
VDD
P5A
X2
X1
1
1
71
VDD
Chassis_GND
Chassis_GND
14
15
16
17
COREGND1
COREGND2
SKT360
TX_CLK_A
TX_EN_A
6
55
B
FEC_RMII_TXD0
FEC_RMII_TXD1
FEC0_RMII_TXEN
12
13
25
37
FEC0MDC
FEC0MDIO
FEC0RXDVFEC0RMIICRSDV
FEC0RXD0FECRMIIRXD0
FEC0RXD1FEC0RMIIRXD1
FEC0RXERFECRMIIRXER
FEC0TXCLKFEC0RMIIREFCLK
FEC0TXD0FEC0RMIITXD0
FEC0TXD1FECRMIITXD1
FEC0TXENFEC0RMIITXEN
FEC0_MDC
FEC0_MDIO
FEC0_RMII_CRS_DV
FEC_RMII_RXD0
FEC0_RMII_RXD1
FEC_RMII_RXER
RXD0_A/PHYAD1
RXD1_A/PHYAD2
RXD2_A/CLK2MAC_DIS
RXD3_A/ED_EN_A
CDGND1
CDGND2
U1B
4
5
8
9
IOGND1
IOGND2
IOGND3
IOGND4
FEC1_RMII
AB8
Y7
Y8
AB10
W9
AA10
Y10
Y11
AA11
W11
R955
R956
C957
49.9 OHM49.9 OHM0.1 UF
VDD
2
331 OHM
331 OHM
1
R7422
R7432
1
2
3
1
331 OHM
331 OHM
2
R7402
R7412
1
VDD
2
FEC1_RMII_REF_CLK
FEC1_RMII_TXEN
FEC1_RMII_TXD0
FEC1_RMII_TXD1
FEC1_RMII_CRS_DV
FEC1_RMII_RXER
FEC1_RMII_RXD0
FEC1_RMII_RXD1
10
52
64
77
SKT360
AB19
AA21
Y20
AA19
AB15
W17
Y17
AA17
ANAGND1
ANAGND2
ANAGND3
ANAGND4
FEC1TXCLKFEC1RMIIREFCLKATADATA11
FEC1TXENFEC1RMIITXENATADATA8
FEC1TXD0FEC1RMIITXD0ATADATA9
FEC1TXD1FEC1RMIITXD1ATADATA10
FEC1RXDVFEC1RMIICRSDVATADATA15
FEC1RXERFEC1RMIIRXERATADATA12
FEC1RXD0FEC1RMIIRXD0ATADATA13
FEC1RXD1FEC1RMIIRXD1ATADATA14
1
U1Q
Both ports of the Ethernet PHY are placed into
RMII mode. The MII management channel is
connected to the FEC0 MDC/MDIO interface only
(e.g. all MII management communications must go
through FEC0). The default PHY addresses of
0x0 (FEC0) and 0x1 (FEC1) are used.
A
Drawing Title:
M54455EVB
Page Title:
ETHERNET
5
4
3
2
Size
C
Document Number
Date:
Monday, November 05, 2007
Rev
C
DP83849-100
1
Sheet
6
of
17
5
4
3
2
1
1
C171
0.1 UF
2
1
C187
0.1 UF
2
1
C166
0.1 UF
2
2
1
VDD
SW1
C170
0.1 UF
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CPLD_MODE0
CPLD_MODE1
CPLD_MODE2
CPLD_MODE3
CPLD_MODE4
CPLD_MODE5
CPLD_MODE6
CPLD_MODE7
D
D
78RB08ST
VDD
VDD
CPLD_SPARE2
CPLD_SPARE4
CPLD_SPARE6
CPLD_SPARE8
CPLD_SPARE10
CPLD_SPARE12
CPLD_SPARE14
CPLD_SPARE16
CPLD_SPARE18
CPLD_SPARE20
CPLD_SPARE22
CPLD_SPARE24
CPLD_SPARE26
CPLD_SPARE28
CPLD_SPARE30
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
CPLD_SPARE1
CPLD_SPARE3
CPLD_SPARE5
CPLD_SPARE7
CPLD_SPARE9
CPLD_SPARE11
CPLD_SPARE13
CPLD_SPARE15
CPLD_SPARE17
CPLD_SPARE19
CPLD_SPARE21
CPLD_SPARE23
CPLD_SPARE25
CPLD_SPARE27
CPLD_SPARE29
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
HDR_2X16
B
42
141
8
84
VCCINT1
VCCINT2
VCCINT3
VCCINT4
28
81
27
82
26
83
25
24
85
23
86
22
87
21
88
20
19
91
17
92
16
93
15
94
14
95
13
96
12
97
11
98
10
9
100
101
7
102
6
103
5
104
4
105
3
106
2
107
143
142
140
139
138
137
136
135
134
I/O_28
I/O_81
I/O_27
I/O_82
I/O_26
I/O_83
I/O_25
I/O_24
I/O_85
I/O_23
I/O_86
I/O_22
I/O_87
I/O_21
I/O_88
I/O_20
I/O_19
I/O_91
I/O_17
I/O_92
I/O_16
I/O_93
I/O_15
I/O_94
I/O_14
I/O_95
I/O_13
I/O_96
I/O_12
I/O_97
I/O_11
I/O_98
I/O_10
I/O_9
I/O_100
I/O_101
I/O_7
I/O_102
I/O_GTS2
I/O_103
I/O_GTS1
I/O_104
I/O_4
I/O_105
I/O_GTS4
I/O_106
I/O_GTS3
I/O_107
I/O_GSR
I/O_142
I/O_140
I/O_139
I/O_138
I/O_137
I/O_136
I/O_135
I/O_134
CPLD_SPARE5
FB_AD22
CPLD_SPARE6
FB_AD21
CPLD_SPARE7
FB_AD20
CPLD_SPARE8
CPLD_SPARE9
FB_AD19
CPLD_SPARE10
FB_AD18
CPLD_SPARE11
FB_AD17
CPLD_SPARE12
FB_AD16
CPLD_SPARE13
CPLD_SPARE14
FB_AD15
CPLD_SPARE15
FB_AD14
CPLD_SPARE16
FB_AD13
CPLD_SPARE17
FB_AD12
CPLD_SPARE18
FB_AD11
CPLD_SPARE19
FB_AD10
CPLD_SPARE20
FB_AD9
CPLD_SPARE21
FB_AD8
CPLD_SPARE22
CPLD_SPARE23
FB_AD7
FB_AD6
BOOTMOD0
FB_AD5
BOOTMOD1
FB_AD4
REV_JUMPER1
FB_AD3
REV_JUMPER2
FB_AD2
REV_JUMPER3
FB_AD1
REV_JUMPER4
FB_AD0
SDRAM_ODT0
SDRAM_ODT1
CPLD_SPARE30
CPLD_SPARE29
CPLD_SPARE28
CPLD_SPARE27
CPLD_SPARE26
CPLD_SPARE25
CPLD_SPARE24
2
3
4
5
7
8
9
10
6
4.7K
VDD
D30
LED0
1
2
1
R972
2
220 OHM
APT3216SEC
C
D31
LED1
1
2
1
R201
2
220 OHM
1
R202
2
220 OHM
1
R9080
2
220 OHM
1
R968
2
220 OHM
1
R964
2
220 OHM
APT3216SEC
D32
LED2
1
2
APT3216SEC
D33
LED3
1
2
APT3216SEC
D34
LED4
1
2
APT3216SEC
D35
LED5
1
2
B
APT3216SEC
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
GND11
GND12
GND13
H900
FLASH1_WP
FLASH1_CS
FLASH0_CS
ATA_ENABLE
PHY1_PWRDN
PHY0_PWRDN
SYSRESET
CPU_RSTOUT
BDM_RESET
BRD_RESET
DSCLK
CPLD_TDI
JTAG_EN
CPLD_TMS
RMIICLK2_EN
CPLD_TCK
FB_BS2
FB_BS3
FB_AD31
FB_AD30
CPLD_SPARE2
FB_AD29
CPLD_SPARE3
FB_AD28
CPLD_SPARE4
FB_AD27
FB_CLK
FB_AD26
FPGA_DONE
FB_AD25
FPGA_CLK
FB_AD24
FB_AD23
FB_RWB
FB_CS2
FB_CS1
FB_CS0
LED7
LED6
LED5
LED4
LED3
LED2
LED1
LED0
T3IN
CPLD_TDO
T2IN
T1IN
T0IN
TEST
FB_TA
FB_TS
FB_OE
I/O_GCK3
I/O_39
I/O_40
I/O_41
I/O_43
I/O_44
I/O_45
I/O_46
I/O_48
I/O_49
I/O_50
I/O_51
I/O_52
I/O_53
I/O_54
I/O_56
I/O_57
I/O_58
I/O_59
I/O_60
I/O_61
TDI
I/O_64
TMS
I/O_66
TCK
I/O_68
I/O_69
I/O_70
I/O_71
I/O_35
I/O_74
I/O_34
I/O_75
I/O_33
I/O_76
I/O_GCK2
I/O_77
I/O_31
I/O_78
I/O_GCK1
I/O_79
I/O_80
I/O_113
I/O_112
I/O_111
I/O_110
I/O_133
I/O_132
I/O_131
I/O_130
I/O_129
I/O_128
I/O_126
I/O_125
I/O_124
TDO
I/O_121
I/O_120
I/O_119
I/O_118
I/O_117
I/O_116
I/O_115
RP56
1
XC95144XL-7TQG144C
D36
LED6
72
36
62
47
99
29
18
90
89
108
144
114
123
C
38
39
40
41
43
44
45
46
48
49
50
51
52
53
54
56
57
58
59
60
61
63
64
65
66
67
68
69
70
71
35
74
34
75
33
76
32
77
31
78
30
79
80
113
112
111
110
133
132
131
130
129
128
126
125
124
122
121
120
119
118
117
116
115
VCCI/O1
VCCI/O2
VCCI/O3
VCCI/O4
VCCI/O5
VCCI/O6
CPLD_SPARE1
ULPI_RESET
73
55
109
37
1
127
VDD
U15
1
2
1
R965
2
220 OHM
1
R967
2
220 OHM
APT3216SEC
D37
LED7
1
2
APT3216SEC
VDD
R212
10.0K
R210
10.0K
1
CPLD_TDI
CPLD_TDO
2
HDR_2X5
REV_JUMPER3
REV_JUMPER4
R209
10.0K
R204
10.0K
2
REV_JUMPER1
REV_JUMPER2
2
2
4
6
8
10
2
CPLD_TMS
CPLD_TCK
1
1
H26
1
3
5
7
9
2
R203
10.0K
R208
10.0K
1
VDD
2
2
2
VDD
R213
10.0K
R211
10.0K
CPLD Program Header
1
1
1
A
1
A
Resistors populated appropriately to indicate current board revision.
Drawing Title:
M54455EVB
Page Title:
CPLD
5
4
3
2
Size
C
Document Number
Date:
Monday, November 05, 2007
Rev
C
870012704-100
1
Sheet
7
of
17
5
4
3
2
1
SERIAL BOOT FLASH
VDD
1
VDD
1
VDD
DSPI_SCK
DSPI_SOUT
DSPI_SIN
2
3
4
5
6
7
8
9
16
15
14
13
12
11
10
9
1
19
78RB08ST
A0
A1
A2
A3
A4
A5
A6
A7
OE1
OE2
74LV541/SO
D
U1E
VCC
1
2
3
4
5
6
7
8
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
18
17
16
15
14
13
12
11
FB_AD0
FB_AD1
FB_AD2
FB_AD3
FB_AD4
FB_AD5
FB_AD6
FB_AD7
DSPISCKSBFCK
DSPISINSBFDI
DSPISOUTSBFDO
DSPIPCS0DSPISSb
DSPIPCS1SCFCSb
DSPIPCS2
DSPIPCS5DSPIPCSSb
SKT360
GND
U902
U905
A20
B19
C20
D17
B20
A19
D18
DSPI_PCS1
DSPI_SIN
DSPI_PCS0
DSPI_PCS1
DSPI_PCS2
DSPI_PCS5
DSPI/SBF
1
2
3
4
5
6
7
8
HOLD
VCC
DU1
DU2
DU3
DU4
S
Q
C
D
DU8
DU7
DU6
DU5
VSS
W
16
15
14
13
12
11
10
9
DSPI_SCK
DSPI_SOUT
M25P16-SO16
10
SW3
20
D
2
VDD
VDD
R970
4.7K
2
R971
4.7K
RN16
1
2
3
4
5
7
8
9
10
VDD
U906 8
6
4.7K
PARALLEL BOOT CONFIGURATION
VCC
5
D
6
C
1
S
3
W
Q
2
HOLD
7
VSS
C
C
M25P16-VMW6G
4
CPU_RSTOUT
ALTERNATIVE PART, DNP
VDD
DSI
U1D
RESETb
RSTOUTb
BOOTMOD0
BOOTMOD1
TEST
DSI
J24
Y18
B17
AB21
AB17
AB20
CPU_RSTOUT
1
3
5
7
9
11
13
15
17
19
21
23
25
BDM_RESET
SKT360
PSTDDATA6
PSTDDATA4
PSTDDATA2
PSTDDATA0
RESET/BOOT MODE
U1F
SKT360
R9084
100 OHM
HDR_2X13
Default
is DNP
JP904
1
2
3
TCLK_PSTCLK
R9083
VDD
TP1
B
HDR_1X3
DSCLK
22 OHM
BDM/JTAG
RN17
R976
4.7K
2
3
4
5
7
8
9
10
BDM
HDR_1X3
1
2
3
FB_TA
JP903
R979
10K
2
1
JTAG_EN
1
VDD
PSTCLK
FB_TA
1
B
AA6
AB6
AB5
W6
Y6
AA5
AB4
Y5
C21
C22
C19
A21
B21
B22
EXTERNAL_DSI
2
PSTDDATA7
PSTDDATA6
PSTDDATA5
PSTDDATA4
PSTDDATA3
PSTDDATA2
PSTDDATA1
PSTDDATA0
JTAGEN
TCLKPSTCLK
TDIDSI
TDODSO
TMSBKPTb
TRSTBDSCLK
BKPT
DSCLK
TCLK
EXTERNAL_DSI
DSO
PSTDDATA7
PSTDDATA5
PSTDDATA3
PSTDDATA1
1
TEST
BOOTMOD1
BOOTMOD0
SYSRESET
2
4
6
8
10
12
14
16
18
20
22
24
26
6
R977
4.7K
BKPT
DSO
2
4.7K
PSTDDATA0
PSTDDATA1
PSTDDATA2
PSTDDATA3
TCLK_PSTCLK
A
A
Drawing Title:
M54455EVB
Page Title:
BOOT, SBF & BDM
5
4
3
2
Size
C
Document Number
Date:
Monday, November 05, 2007
Rev
C
870012704-100
1
Sheet
8
of
17
5
4
3
2
1
D
D
1
VCC
R907
220 OHM
1
R903
220 OHM
ATA_BUFFER_EN
Connector for front
panel HDD activity LED.
VDD
2
H_ATA_DATA8
H_ATA_DATA9
H_ATA_DATA10
ATA
H_ATA_DATA11
H_ATA_DATA12
H_ATA_DATA13
H_ATA_DATA14
H_ATA_DATA15
From MCF5445x FEC1_RMII
FEC1_RMII_TXEN
FEC1_RMII_TXD0
FEC1_RMII_TXD1
FEC1_RMII_REF_CLK
FEC1_RMII_RXER
FEC1_RMII_RXD0
FEC1_RMII_RXD1
FEC1_RMII_CRS_DV
R309
R310
R311
R312
R313
R314
R315
R316
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
22 OHM
22 OHM
22 OHM
22 OHM
22 OHM
22 OHM
22 OHM
22 OHM
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
2
R901
1
10.0K
H_ATA_DA0
H_ATA_DA1
H_ATA_DA2
SN74CBTD16211
R904 R905
10.0K 10.0K
R906
10.0K
35
33
36
17
15
13
11
9
7
5
3
4
6
8
10
12
14
16
18
21
23
25
27
29
31
DA0
DA1
DA2
DD0
DASP
DD1
PDIAG
DD2 IOCS16
DD3
CSFI
DD4
DD5
KEY
DD6
DD7
DD8
DD9
DD10
DD11
DD12
DD13
DD14 GND7
DD15 GND6
GND5
DMARQ GND4
DIOW GND3
DIOR GND2
IORDY GND1
DMACK
INTRQ
37
38
CS0
CS1
1
APT3216MGC
39
34
32
28
H16
1
NC
1OE
1A1
2OE
1A2
1B1
1A3
1B2
1A4
1B3
1A5
1B4
1A6
1B5
GND1GND3
1A7
1B6
1A8
1B7
1A9
1B8
1A10 1B9
1A11 1B10
1A12 1B11
2A1 1B12
2A2
2B1
VCC
2B2
2A3
2B3
GND2GND4
2A4
2B4
2A5
2B5
2A6
2B6
2A7
2B7
2A8
2B8
2A9
2B9
2A10 2B10
2A11 2B11
2A12 2B12
2
H_ATA_DATA6
H_ATA_DATA7
H_ATA_DMARQ
H_ATA_IORDY
H_ATA_INTRQ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
1
U25
H_ATA_DATA0
H_ATA_DATA1
H_ATA_DATA2
H_ATA_DATA3
H_ATA_DATA4
H_ATA_DATA5
D23
U26
R900
10.0K
2
C
Y13
V21
V20
V19
AA22
W18
Y19
Y15
AA15
W14
AA18
AB18
AA14
Y22
W20
Y14
W13
W21
W22
2
ATABUFFEREN
ATADA0
ATADA1
ATADA2
FEC1TXERATADATA0
FEC1TXD2ATADATA1
FEC1TXD3ATADATA2
FEC1RXD2ATADATA3
FEC1RXD3ATADATA4
FEC1RXCLKATADATA5
FEC1CRSATADATA6
FEC1COLATADATA7
ATADMARQ
FEC1MDIOATADIOWB
FEC1MDCATADIORB
ATAIORDY
ATARESETb
ATACS1B
ATACS0B
2
ATA_ENABLE
U1A
SKT360
2
VDD
2
VDD
2
1
HDR_1X2_M
20
C
40
30
26
24
22
19
2
RESET
1
1
1
ATA CONNECTOR
From MCF5445x PCI
H_ATA_DIOW
H_ATA_DIOR
H_ATA_DMACK
H_ATA_RESET
H_ATA_CS0
H_ATA_CS1
PCI_GNT3
PCI_REQ3
PCI_REQ3_JMP
J911
B
B
3
2
1
HDR_1X3
A
A
Drawing Title:
M54455EVB
Page Title:
ATA
5
4
3
2
Size
C
Document Number
Date:
Monday, November 05, 2007
Rev
C
870012704-100
1
Sheet
9
of
17
5
4
3
2
1
D
D
Flash 1
U1S
FBAD31
FBAD30
FBAD29
FBAD28
FBAD27
FBAD26
FBAD25
FBAD24
FBAD23
FBAD22
FBAD21
FBAD20
FBAD19
FBAD18
FBAD17
FBAD16
FBAD15
FBAD14
FBAD13
FBAD12
FBAD11
FBAD10
FBAD9
FBAD8
FBAD7
FBAD6
FBAD5
FBAD4
FBAD3
FBAD2
FBAD1
FBAD0
FBCLK
FBBS3BFBTSIZ1
FBBS3BFBTSIZ0
FBBS1B
FBBS0B
FBCS3B
FBCS2B
FBCS1B
FBCS0B
FBOEB
FBRWB
FBTSBFBALE
FBTAB
U903
Flash 0
FB_AD1
FB_AD2
FB_AD3
FB_AD4
FB_AD5
FB_AD6
FB_AD7
FB_AD8
FB_AD9
FB_AD10
FB_AD11
FB_AD12
FB_AD13
FB_AD14
FB_AD15
FB_AD16
FB_AD17
FB_AD18
FB_AD19
FB_AD20
FB_AD21
FB_AD22
FB_AD23
FB_AD0
U12
FB_AD0
FB_AD1
FB_AD2
FB_AD3
FB_AD4
FB_AD5
FB_AD6
FB_AD7
FB_AD8
FB_AD9
FB_AD10
FB_AD11
FB_AD12
FB_AD13
FB_AD14
FB_AD15
FB_AD16
FB_AD17
FB_AD18
20
19
18
17
16
15
14
13
3
2
31
1
12
4
5
11
10
6
9
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
FB_AD24
FB_AD25
FB_AD26
FB_AD27
FB_AD28
FB_AD29
FB_AD30
FB_AD31
21
22
23
25
26
27
28
29
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
VDD
1
FB_OE
FB_RWB
FLASH0_CS
VDD
32
7
30
OE
WE
CE
8
VCC
24
GND
C126
0.1 UF
VCC_9
VCC_37
VCCQ
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
33
35
38
40
44
46
49
51
34
36
39
41
45
47
50
52
STS
53
31
54
55
14
2
29
RFU
BYTE
OE
WE GND_21
CE0 GND_42
CE1 GND_48
CE2
56
15
16
VPEN
RP
28
27
26
25
24
23
22
20
19
18
17
13
12
11
10
8
7
6
5
4
3
1
30
32
FB_OE
FB_RWB
FLASH1_CS
AT49BV040/LCC
FLASH1_WP
SYSRESET
VDD
9
37
43
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A0
FB_AD24
FB_AD25
FB_AD26
FB_AD27
FB_AD28
FB_AD29
FB_AD30
FB_AD31
C
21
42
48
28F128J3D
The CPLD_MODE[2] setting determines which flash
device gets which chip-select (FB_CS0 or
FB_CS1). The device connected to FB_CS0 is the
boot device.
SKT360
B
VDD
VDD
2
3
4
5
7
8
9
10
FB_AD0
FB_AD1
FB_AD2
FB_AD3
FB_AD4
FB_AD5
FB_AD6
FB_AD7
6
2
3
4
5
7
8
9
10
6
4.7K
RP19
1
1
FB_AD8
FB_AD9
FB_AD10
FB_AD11
FB_AD12
FB_AD13
FB_AD14
FB_AD15
2
3
4
5
7
8
9
10
6
4.7K
FB_AD16
FB_AD17
FB_AD18
FB_AD19
FB_AD20
FB_AD21
FB_AD22
FB_AD23
2
3
4
5
7
8
9
10
FB_AD24
FB_AD25
FB_AD26
FB_AD27
FB_AD28
FB_AD29
FB_AD30
FB_AD31
C123
0.1 UF
1
1
C124
0.1 UF
2
RP18
1
1
B
VDD
VDD
RP17
1
VDD
RP16
2
VDD
VDD
2
C
J2
K4
J1
K1
K2
K3
L1
L4
L2
L3
M1
M2
M3
M4
N1
N2
P1
P2
R1
R2
R3
P4
T1
T2
T3
T4
U1
U2
U3
V1
V2
W1
J3
Y1
W2
W3
Y2
W5
AA4
AB3
Y4
AA1
AA3
Y3
AB2
2
FB_AD31
FB_AD30
FB_AD29
FB_AD28
FB_AD27
FB_AD26
FB_AD25
FB_AD24
FB_AD23
FB_AD22
FB_AD21
FB_AD20
FB_AD19
FB_AD18
FB_AD17
FB_AD16
FB_AD15
FB_AD14
FB_AD13
FB_AD12
FB_AD11
FB_AD10
FB_AD9
FB_AD8
FB_AD7
FB_AD6
FB_AD5
FB_AD4
FB_AD3
FB_AD2
FB_AD1
FB_AD0
FB_CLK
FB_BS3
FB_BS2
FB_BS1
FB_BS0
FB_CS3
FB_CS2
FB_CS1
FB_CS0
FB_OE
FB_RWB
FB_TS
FB_TA
C125
0.1 UF
6
4.7K
4.7K
A
A
Drawing Title:
M54455EVB
Page Title:
FLASH
5
4
3
2
Size
C
Document Number
Date:
Monday, November 05, 2007
Rev
C
870012704-100
1
Sheet
10
of
17
5
4
3
2
1
VDD
D
D
UART1 RS-232 Interface
2 C962
0.1 UF
1
1
1
2
U1CTS
U1RTS
U1RXD
U1TXD
HDR_1X2_M
JP908
U1K
1
1
2
HDR_1X2_M
JP907
U1H
I2CSCLU2TXD
I2CSDAU2RXD
AA12
Y12
U1RXD
U1TXD
U1RTSb
U1CTSb
SKT360
I2C
P3
N3
U4
V3
20
16
VCC
6
2
5
4
3
1
VV+
C2C2+
C1C1+
11
10
DIN1
DIN2
DOUT2
DOUT1
7
14
8
13
R2IN
R1IN
R2OUT
R1OUT
9
12
GND
2 C961
0.1 UF
2 C960
0.1 UF
2 C959
0.1 UF
2 C958
0.1 UF
1
15
19
14
18
13
17
12
16
11
DB9_CTS1
DB9_TXD1
DB9_RTS1
DB9_RXD1
P1B
DB9
Silkscreen
21
U907
15
1
MAX3232
U1RTS_RS232
U1CTS_RS232
SKT360
UART1
VDD
J908
T3INT3OUTU2RXD
T2INT2OUTU2TXD
T1INT1OUTU2CTSb
T0INT0OUTU2RTSb
SKT360
H2
H1
H3
G1
DSPI_SCK
DSPI_SIN
DSPI_SOUT
DSPI_PCS5
TIMERS
C963
0.1 UF
1
2
U0TXD
U0RXD
U0RTS
U0CTS
C
U908
I2C_SCL
I2C_SDA
2 C967
0.1 UF
2 C966
0.1 UF
2 C965
0.1 UF
2 C964
0.1 UF
1
1
1
1
DSPI_PCS0
DSPI_PCS1
DSPI_PCS2
DACK0
DREQ0
HDR_2X20
U1N
U0RXD
U0TXD
U0RTSb
U0CTSb
U0RTS_RS232
U0TXD_RS232
U0CTS_RS232
U0RXD_RS232
AB16
W15
AA16
Y16
10
SYSRESET
CPU_RSTOUT
U1J
VDD
16
VCC
6
2
5
4
3
1
VV+
C2C2+
C1C1+
11
10
DIN1
DIN2
DOUT2
DOUT1
7
14
8
13
R2IN
R1IN
R2OUT
R1OUT
9
12
5
9
4
8
3
7
2
6
1
DB9_CTS0
DB9_TXD0
DB9_RTS0
DB9_RXD0
P1A
DB9
Silkscreen
22
C
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
15
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
GND
T3IN
T2IN
T1IN
T0IN
MAX3232
HDR_1X3
SKT360
UART0
HDR_1X3
1
2
3
UART0 RS-232 and USB Interface
VDD
JP912
HDR_1X3
1
1
2
3
R978
4.7K
JP911
IRQ7b
IRQ4bSSICLKIN
IRQ3b
IRQ1bPCIINTA
AB13
AA13
AB14
C6
HDR_1X3
IRQ7
IRQ4
IRQ3
IRQ1
9
12
11
JP910
1
2
3
SKT360
INTERRUPTS
JP909
VDD
C968
1.0UF
1
2
U909
2
U1L
B
1
2
3
U0RXD_USB
U0TXD_USB
U0CTS_USB
U0RTS_USB
2
1
28
27
26
25
24
23
7
6
1
8
5
4
B
2
C969
0.1 UF
10
13
14
15
16
17
18
19
20
21
22
J907
1
USB-B_VBUS
-D
+D
G
V
2
USB-B_P
USB-B_N
4
S2
2
3
4
1
S1
3
3
29
30
RST
REGIN
SUSPEND
VDD
SUSPEND
VBUS
RI
DDCD
D+
DTR
DSR
TXD
NC1
RXD
NC2
RTS
NC3
CTS
NC4
NC5
NC6
GND1
NC7
GND2
NC8
GND3
NC9
NC10
NC11
USB_TYPE_B
CP2102
USB to serial converter
A
A
Drawing Title:
M54455EVB
Page Title:
SERIAL
5
4
3
2
Size
C
Document Number
Date:
Monday, November 05, 2007
Rev
C
870012704-100
1
Sheet
11
of
17
5
4
3
2
1
CT11
EXTAL
CPUCLK
1
1
2
2
3
3
4
4
EXTAL_OSC
0 OHM
U1G
D
X1
R137
2
18M
1
X2
R138
2
10.0 OHM
1
2
1
1
1
2
4
C1011
15PF
2
L27 2
100MHZ
C1010
15PF
2
C556
0.1 UF
1
2
C555
1.0UF
1
32.768MHz
1
CLOCKING
2
25MHZ
1
1
VDDP
2
1
3
R136
2
1.0M
1
1
SKT360
XTAL32K
EXTAL32K
EXTAL
XTAL
VDD_OSC
VDD_RTC
VDD_A_PLL
VSS_OSC
2
D
A12
A13
A16
A17
B16
C13
C14
C16
D15
C975
33PF
2
XTAL32K
EXTAL32K
EXTAL
XTAL
VDDOSC
VDDRTC
VDDAPLL
VSSOSC
PLLTEST
C974
33PF
V1.5P
H4
HDR 2X2
1
C557
1.0UF
R139
2
10.0 OHM
C559
0.1 UF
2
2
1
1
V1.5P
2
VDD
25MHZ
2
1
2
0.1 UF
C335
0.1 UF
VDD
4
5
U3
8
6
CY22393
CPUCLK
4
13
1
USBCLK_60
8
9
USBCLK_24
5
12
VDD CLKOUT
VDD CLKA1
CLKA2
REF CLKA3
CLKA4
S2
S1
CLKB1
CLKB2
GND CLKB3
GND CLKB4
16
2
3
14
15
22OHM
22OHM
22OHM
22OHM
8
7
6
5
1
2
3
4
RN59A
RN59B
RN59C
RN59D
R122
0 OHM
J10
RMIICLK0
RMIICLK1
RMIICLK2
2
1 R128
2
22 OHM
1 R318
2
22 OHM
1 R35
2
22 OHM
R126
1
2
22 OHM
1 R317
2
22 OHM
10
9
1
7
SMA
1
2
CPUCLK
R142
51 OHM
6
7
10
11
1
2
14
3
11
SDAT/S0
XTALIN
SCLK/S1
XTALOUT
S2/SUSPEND
SHUTDOWN/OE
CLKA
CLKB
VDD
CLKC
AVDD
CLKD
AGND
GND
CLKE
XBUF
C128
2
X3
1
U8
12
13
15
16
2
2
0.1 UF
VDD
C560
0.1 UF
C
C326
0.1 UF
1
C127
R140
2
10.0 OHM
1
C
1
VDD
C558
1.0UF
2
CLK_GEN_S2
I2C_SCL
I2C_SDA
1
1
1
CY2309ZXC-1H
R125
0 OHM
2
J11
RMIICLK2_EN
SMA
VDD
1
2
R143
51 OHM
1
RP78
1
2
3
4
5
7
8
9
10
R127
0 OHM
J12
TP4
6
2
B
SMA
B
1
2
USBCLK_24
2
USBCLK_60
R144
51 OHM
4.7K
1
C96
0.1 UF
2
0.1 UF
2
C84
1
1
VDD
VDD
R129
0 OHM
2
J13
1
8
9
5
12
VDD CLKOUT
VDD CLKA1
CLKA2
REF CLKA3
CLKA4
S2
S1
CLKB1
CLKB2
GND CLKB3
GND CLKB4
RN57A1
RN57B2
RN57C3
RN57D4
16
2
3
14
15
6
7
10
11
RN58A
RN58B
RN58C
RN58D
1
2
3
4
8
7
6
5
22OHM
22OHM
22OHM
22OHM
PCI_CLK0
PCI_CLK1
PCI_CLK2
PCI_CLK3
8
7
6
5
22OHM
22OHM
22OHM
22OHM
PCI_CLK4
FPGA_CLK
PCI_CLK5
TP3
CY2309ZXC-1H
R145
51 OHM
R130
0 OHM
J18
SMA
1
2
R149
51 OHM
1
C85
47PF
1
2
1
1
4
13
SMA
2
U2
A
A
PCI CLOCK BUFFER
Drawing Title:
M54455EVB
Page Title:
CLOCKING
5
4
3
2
Size
C
Document Number
Date:
Monday, November 05, 2007
Rev
C
870012704-100
1
Sheet
12
of
17
4
3
DDR2 Parallel Termination - place near DDR2 devices
1
RN110A
51 OHM
T37
SD_D31
8
1
DDR2 SDRAMs
VTT
8
VEE
VTT
SD_D22
SD_D20
3
SD_D18
SD_D21
5
1
SD_D19
SD_CS0
SD_A12
SD_A5
7
3
VTT
SD_RAS
5
SD_D26
6
4
SD_D28
5
B3
B7
A8
A2
DM
DQS
DQS#
RDQS#
SD_CLK_N
SDRAM_ODT0
F9
ODT
R555
4.7K
SD_CLK_P
MT47H64M8
4
VEE
5
2 22OHM
4 22OHM
SD_DM3
SD_DM2
H22
E22
RN94A 8
RN93C 6
1 22OHM
3 22OHM
SD_DQS3
SD_DQS2
SDRASb
SDCASb
SDWEb
SDCS0b
SDCS1b
N21
L19
N20
M20
L20
RN100C
RN100D
RN100A
RN95C
RN95D
6
5
8
6
5
3
4
1
3
4
22OHM
22OHM
22OHM
22OHM
22OHM
SD_RAS
SD_CAS
SD_WE
SD_CS0
SD_CS1
SDA13
SDA12
SDA11
SDA10
SDA9
SDA8
SDA7
SDA6
SDA5
SDA4
SDA3
SDA1
SDA2
SDA0
V22
U20
U21
U22
T19
T20
T21
T22
R20
R21
R22
P20
N19
P21
RN96A
RN97D
RN96B
RN96C
RN97C
RN99A
RN96D
RN98A
RN99B
RN98B
RN98C
RN99C
RN95B
RN98D
8
5
7
6
6
8
5
8
7
7
6
6
7
5
1
4
2
3
3
1
4
1
2
2
3
3
2
4
22OHM
22OHM
22OHM
22OHM
22OHM
22OHM
22OHM
22OHM
22OHM
22OHM
22OHM
22OHM
22OHM
22OHM
SD_A13
SD_A12
SD_A11
SD_A10
SD_A9
SD_A8
SD_A7
SD_A6
SD_A5
SD_A4
SD_A3
SD_A1
SD_A2
SD_A0
SDBA0
SDBA1
P19
P22
RN95A 8
RN99D 5
1 22OHM
4 22OHM
SD_BA0
SD_BA1
SDCKE
SDCLK
SDCLKb
N22
L22
M22
RN100B 7
R148
1
R150
1
22OHM
2
2 22 OHM
2 22 OHM
SD_CKE
SD_CLK_P
SD_CLK_N
SDVREF
M21
2 22OHM
RN97A 8
1 22OHM
SD_DM2
SD_DQS2
B3
B7
A8
A2
DM
DQS
DQS#
RDQS#
SDRAM_ODT0
F9
ODT
MT47H64M8
SD_D31
SD_D30
SD_D29
SD_D28
SD_D27
SD_D26
SD_D25
SD_D24
C8
C2
D7
D3
D1
D9
B1
B9
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
SD_RAS
SD_CAS
SD_WE
SD_CS1
F7
G7
F3
G8
RAS#
CAS#
WE#
CS#
SD_DM3
SD_DQS3
B3
B7
A8
A2
DM
DQS
DQS#
RDQS#
SDRAM_ODT1
F9
ODT
VEE
SD_CKE
SD_CLK_P
SD_CLK_N
BA0
BA1
BA2
G2
G3
G1
SD_BA0
SD_BA1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
H8
H3
H7
J2
J8
J3
J7
K2
K8
K3
H2
K7
L2
L8
L3
L7
SD_A0
SD_A1
SD_A2
SD_A3
SD_A4
SD_A5
SD_A6
SD_A7
SD_A8
SD_A9
SD_A10
SD_A11
SD_A12
SD_A13
VREF
2
D
C19
1
0.1 UF
U914
CKE
CK
CK#
F2
E8
F8
SD_CKE
SD_CLK_P
SD_CLK_N
BA0
BA1
BA2
G2
G3
G1
SD_BA0
SD_BA1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
H8
H3
H7
J2
J8
J3
J7
K2
K8
K3
H2
K7
L2
L8
L3
L7
SD_A0
SD_A1
SD_A2
SD_A3
SD_A4
SD_A5
SD_A6
SD_A7
SD_A8
SD_A9
SD_A10
SD_A11
SD_A12
SD_A13
R557
4.7K
SD_D23
SD_D22
SD_D21
SD_D20
SD_D19
SD_D18
SD_D17
SD_D16
C8
C2
D7
D3
D1
D9
B1
B9
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
SD_RAS
SD_CAS
SD_WE
SD_CS1
F7
G7
F3
G8
RAS#
CAS#
WE#
CS#
SD_DM2
SD_DQS2
B3
B7
A8
A2
DM
DQS
DQS#
RDQS#
SDRAM_ODT1
F9
ODT
R558
4.7K
MT47H64M8
2
0.1 UF
CKE
CK
CK#
F2
E8
F8
SD_CKE
SD_CLK_P
SD_CLK_N
BA0
BA1
BA2
G2
G3
G1
SD_BA0
SD_BA1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
H8
H3
H7
J2
J8
J3
J7
K2
K8
K3
H2
K7
L2
L8
L3
L7
SD_A0
SD_A1
SD_A2
SD_A3
SD_A4
SD_A5
SD_A6
SD_A7
SD_A8
SD_A9
SD_A10
SD_A11
SD_A12
SD_A13
MT47H64M8
B
DDR2 termination and reference voltage regulator.
J906
HDR_1X2_M
2
100 OHM
VDD
Vsense should be
connected to the
center of the Vtt
termination bus.
R687
Place R687 close to
the DDR2 devices
R922
4.7K
U900
1
5
7
Vddq Vsense
PVin
Vtt
3
8
5
4
3
C920
0.01UF
LP2997MR NOPB
C922
47UF
Drawing Title:
+
2
C1002
10UF
Vref
C921
220UF
M54455EVB
Page Title:
SDRAM
2
C1009 +
0.1 UF
SD
AVin
2
+
1
1
C1008
1000PF
2
1
C1007
100PF
2
1
C1006
0.1 UF
2
1
C1001
1000PF
2
1
C998
100PF
2
1
C997
100PF
2
1
C1000
1000PF
2
1
C1005
1000PF
2
1
C999
0.1 UF
2
1
C1004
0.1 UF
2
1
C996
1000PF
2
1
C978
100PF
2
1
C992
1000PF
2
1
C995
1000PF
2
1
C994
0.1 UF
2
1
C993
0.1 UF
2
1
C1003
1000PF
2
1
2
1
C980
100PF
2
6
1
VTT
A
4
1
VEE
9
C979
10UF
2
C991 +
0.1 UF
GND1GND2
C990
1000PF
2
C987
100PF
2
C989
0.1 UF
2
C988
1000PF
2
C986
100PF
2
C977
100PF
2
2
2
C984
0.1 UF
2
C983
0.1 UF
2
2
A
C976
100PF
VREF
2
VTT
1
1
1
1
1
C982
1000PF
1
1
C985
1000PF
1
1
1
1
C981
1000PF
1
1
2
1
VDD
2
RAS#
CAS#
WE#
CS#
C13
VEE
2
F7
G7
F3
G8
F2
E8
F8
1
SKT360
RN97B 7
SD_RAS
SD_CAS
SD_WE
SD_CS0
R556
4.7K
2
1
1
VREF
SD_A0
SD_A1
SD_A2
SD_A3
SD_A4
SD_A5
SD_A6
SD_A7
SD_A8
SD_A9
SD_A10
SD_A11
SD_A12
SD_A13
CKE
CK
CK#
1
RN94B 7
RN93D 5
B
H8
H3
H7
J2
J8
J3
J7
K2
K8
K3
H2
K7
L2
L8
L3
L7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
VSS1
VSS2
VSS3
VSS4
VSSDL
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
SDDQS3
SDDQS2
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
C8
C2
D7
D3
D1
D9
B1
B9
1
H21
E21
SD_BA0
SD_BA1
1
2
SDDM3
SDDM2
G2
G3
G1
VREF
VTT
SD_D31
SD_D30
SD_D29
SD_D28
SD_D27
SD_D26
SD_D25
SD_D24
SD_D23
SD_D22
SD_D21
SD_D20
SD_D19
SD_D18
SD_D17
SD_D16
1
2
1
2
4
3
3
4
1
3
4
2
3
1
2
4
BA0
BA1
BA2
SD_D23
SD_D22
SD_D21
SD_D20
SD_D19
SD_D18
SD_D17
SD_D16
C
6
22OHM
22OHM
22OHM
22OHM
22OHM
22OHM
22OHM
22OHM
22OHM
22OHM
22OHM
22OHM
22OHM
22OHM
22OHM
22OHM
8
7
8
7
5
6
6
5
8
6
5
7
6
8
7
5
SD_CKE
SD_CLK_P
SD_CLK_N
VTT
U1O
RN91A
RN90B
RN90A
RN91B
RN91D
RN91C
RN90C
RN90D
RN92A
RN94C
RN94D
RN92B
RN92C
RN93A
RN93B
RN92D
F2
E8
F8
0.1 UF
SDRAM_ODTn signals are controlled by the CPLD
and are for test purposes only. The MCF5445x
does not provide control signals for DDR2
on-die termination. Discrete parallel
terminators are used in this design.
Place series termination resistors
as close to U1 as possible
L21
K22
K21
K20
J20
J19
J21
J22
H20
G22
G21
G20
G19
F22
F21
F20
CKE
CK
CK#
VTT
U913
SDD31
SDD30
SDD29
SDD28
SDD27
SDD26
SDD25
SDD24
SDD23
SDD22
SDD21
SDD20
SDD19
SDD18
SDD17
SDD16
A1
E9
H9
L1
E1
A9
C1
C3
C7
C9
E2
SD_DM3
SD_DQS3
VTT
RN109D
51 OHM
T36
RAS#
CAS#
WE#
CS#
U912
7
3
VTT
F7
G7
F3
G8
T44
RN109C
51 OHM
T35
SD_RAS
SD_CAS
SD_WE
SD_CS0
7
0.1 UF
8
2
VTT
RN106D
51 OHM
T24
SD_D29
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
VTT
RN109B
51 OHM
T34
2
VTT
C8
C2
D7
D3
D1
D9
B1
B9
T43
5
1
VTT
RN106C
51 OHM
T23
6
4
8
2
VTT
RN103D
51 OHM
T12
SD_BA1
SD_D27
8
SD_D31
SD_D30
SD_D29
SD_D28
SD_D27
SD_D26
SD_D25
SD_D24
VTT
RN109A
51 OHM
T33
SD_D25
6
4
VTT
RN106B
51 OHM
T22
7
3
5
1
VTT
RN103C
51 OHM
T11
SD_A1
SD_CS1
VTT
RN111B
51 OHM
T42
RN108D
51 OHM
T32
5
1
VTT
7
3
VTT
RN106A
51 OHM
T21
8
2
6
4
VTT
RN103B
51 OHM
T10
SD_A9
SD_A13
VTT
RN111A
51 OHM
SD_D24
U911
6
4
T41
RN108C
51 OHM
T31
SD_DQS3
8
2
VTT
RN105D
51 OHM
T20
SD_A8
VTT
RN110D
51 OHM
VTT
RN108B
51 OHM
T30
3
T40
5
1
VTT
SD_DM3
VTT
RN108A
51 OHM
SD_A4
7
3
VTT
RN103A
51 OHM
T9
SD_WE
4
T29
RN105C
51 OHM
T19
6
4
2
VTT
RN102D
51 OHM
T8
SD_A6
7
SD_A0
8
T39
2
7
RN110C
51 OHM
6
RN107D
51 OHM
VTT
RN105B
51 OHM
T18
3
T28
5
1
VTT
RN102C
51 OHM
T7
SD_BA0
SD_A2
VTT
RN105A
51 OHM
T17
8
2
4
VTT
RN102B
51 OHM
SD_D23
SD_CAS
5
1
T6
RN104D
51 OHM
T16
RN102A
51 OHM
T5
T27
6
C10
1
1
4
3
VTT
VREF
2
2
SD_DM2
SD_A10
RN107C
51 OHM
2
1
2
RN101D
51 OHM
T4
C
T15
6
VTT
SD_D30
7
VEE
C5
VSS1
VSS2
VSS3
VSS4
VSSDL
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
D
RN104C
51 OHM
2
T38
VREF
VTT
A3
E3
J1
K9
E7
A7
B2
B8
D2
D8
3
VTT
SD_CKE
7
RN110B
51 OHM
A3
E3
J1
K9
E7
A7
B2
B8
D2
D8
SD_DQS2
2
T26
VTT
VDD1
VDD2
VDD3
VDD4
VDDL
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VREF
RN101C
51 OHM
T3
SD_A3
7
RN107B
51 OHM
A1
E9
H9
L1
E1
A9
C1
C3
C7
C9
E2
2
T14
VTT
VDD1
VDD2
VDD3
VDD4
VDDL
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VREF
SD_D16
RN104B
51 OHM
1
T2
VTT
2
RN101B
51 OHM
VSS1
VSS2
VSS3
VSS4
VSSDL
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
SD_A11
8
VTT
A3
E3
J1
K9
E7
A7
B2
B8
D2
D8
1
RN107A
51 OHM
T25
VSS1
VSS2
VSS3
VSS4
VSSDL
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
SD_A7
8
VTT
A3
E3
J1
K9
E7
A7
B2
B8
D2
D8
1
RN104A
51 OHM
T13
A1
E9
H9
L1
E1
A9
C1
C3
C7
C9
E2
SD_D17
VTT
VDD1
VDD2
VDD3
VDD4
VDDL
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VREF
T1
1
A1
E9
H9
L1
E1
A9
C1
C3
C7
C9
E2
RN101A
51 OHM
2
VDD1
VDD2
VDD3
VDD4
VDDL
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VREF
5
2
Size
C
Document Number
Date:
Monday, November 05, 2007
Rev
C
870012704-100
1
Sheet
13
of
17
4
1
VDD
V2.5
VDD
MRAM
8
CEO
13
D0
CF
CE
1
7
10
NC1
NC2
NC3
NC4
NC5
NC6
GND
FPGA_INIT_b
XPF_D0
XPF_CF_b
FPGA_DONE
MEM_DATA29
FPGA_DONE R2 1
MEM_ADDR16
MEM_BE1_b
FPGA_CFG3
FPGA_CFG1
2 56 OHM
CF_PCI_REQ0
FB_AD27
FB_AD23
FB_AD15
FB_AD3
11
XCF02SVOG20C
M66EN
MEM_DATA25
CLK_GEN_S2
BRD_RESET
MEM_DATA18
MEM_DATA22
MEM_DATA30
FPGA_CFG0
VDD
H20
1
3
5
7
9
XPF_TMS
XPF_TCK
2
4
6
8
10
XPF_TDI
FPGA_TDO
FPGA_CLK
PCI_IRQ0
FB_CS3
FB_AD31
FPGA_M2
FPGA_M0
DREQ0
HDR_2X5
C
MEM_DATA17
MEM_RW
FPGA Program Header
MEM_DATA26
FPGA_M2
1
R673
2
0 OHM
FPGA_M1
1
R674
2
0 OHM
FPGA_M0
1
R675
2
0 OHM
FPGA_INIT_b
PCI_IRQ1
FB_TS
FB_BS3
LED2_SEG7
DACK0
FB_AD30
MEM_BE0_b
MEM_DATA21
VDD
FPGA_UDTR
RN114
1
2
3
4
5
7
8
9
10
XPF_D0
PCI_IRQ2
XPF_TDO
XPF_TMS
XPF_TCK
XPF_CF_b
FPGA_INIT_b
FPGA_DONE
FPGA_CCLK
PCI_IRQ3
CF_PCI_GNT0
LED2_SEG6
LED2_SEG5
FB_AD26
FB_AD10
6
4.7K
VDD
B
MEM_ADDR15
FPGA_UTXD
FPGA_UDSR
FPGA_UCLK
D958
FPGA_LED0
1
2
1
R444
2
220 OHM
APT3216MGC
D957
FPGA_LED1
1
2
1
R445
2
220 OHM
1
R446
2
220 OHM
APT3216MGC
LED2_SEG4
LED2_SEG3
FB_TA
FB_AD22
P16
P15
P14
P13
P12
P11
P10
P9
P8
P7
P6
P5
P4
P3
P2
P1
1
2
APT3216MGC
56 OHM
XPF_TDO R3 1
FB_AD8
FB_AD4
FB_AD0
2
FPGA_TDI
PCI_FRAME
FPGA_LED1
FPGA_LED2
H21
I2C_SCL
I2C_SDA
ATA_BUFFER_EN
DSPI_PCS2
1
3
5
7
2
4
6
8
XPF_TCK
XPF_TMS
XPF_TDI
FPGA_TDO
HDR_2X4
A
These jumpers provide connections from
GPIO signals on the MCF5445x to the JTAG
interface of the FPGA platform flash.
MEM_ADDR17
MEM_ADDR9
MEM_ADDR1
FPGA_TDO
FB_AD1
56 OHM
XPF_CF_b R1 1
FB_AD16
FB_AD12
FB_AD28
SLOT_PCI_GNT0
FB_CLK
2
FPGA_PROG_b
FPGA_LED0
MEM_DATA27
MEM_CS_b
MEM_ADDR13
MEM_ADDR5
MEM_ADDR2
IO13
IO_L24P_2
IO_L24N_2
IO_L23P_2
IO_L23N_2/VREF_2
VCCO_2
GND27
GND28
GND29
GND30
VCCO_7
IO_L23N_7
IO_L24P_7
IO_L24N_7
IO14
IO_L40P_7
G16
G15
G14
G13
G12
G11
G10
G9
G8
G7
G6
G5
G4
G3
G2
G1
IO_L01N_3/VRP_3
IO_L16N_3
IO_L16P_3
IO/VREF_42
IO_L25N_4
IO_L28N_4
IO_L30N_4/D2
IO_L31P_4/DOUT/BUSY
IO_L32N_5/GCLK3
IO4
IO_L29P_5/VREF_5
IO_L27P_5
M2
MO
IO_L16N_6
IO_L01P_6/VRN_6
IO_L40P_2/VREF_2
IO_L40N_2
IO_L39P_2
IO_L39N_2
VCCO_2
VCCO_2
GND22
GND23
GND24
GND25
VCCO_7
VCCO_7
IO_L39P_7
IO_L39N_7
GND26
IO_L40N_7/VREF_7
H16
H15
H14
H13
H12
H11
H10
H9
H8
H7
H6
H5
H4
H3
H2
H1
MEM_OE_b
SW6
MEM_DATA28
UB
LB
These spare test points
should be placed in a row.
Preferably 0.1 inch spacing.
IRQ1
MEM_ADDR7
MEM_ADDR11
FPGA_URXD
FPGA_UDCD
FPGA_URI
M5
L16
L15
L14
L13
L12
L11
L10
L9
L8
L7
L6
L5
L4
L3
L2
L1
VCCINT2
VCCAUX3
IO_L22N_3
IO_L22P_3
IO_L21N_3
IO_L23P_3/VREF_3
GND6
VCCO_4
VCCO_4
VCCO_5
VCCO_5
GND7
IO_L21N_6
IO_L21P_6
IO_L22N_6
IO_L22P_6
VCCAUX4
IO_L20P_2
IO_L20N_2
IO_L19P_2
IO_L19N_2
VCCINT5
IO_L28P_1
IO_L30P_1
VCCO_1
VCCO_0
IO_L29N_0
IO_L27N_0
VCCINT6
IO_L21P_7
IO_L19N_7/VREF_7
IO_L20P_7
IO_L20N_7
E16
E15
E14
E13
E12
E11
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
MEM_ADDR18
MEM_DATA20
MEM_ADDR14
MEM_DATA16
FPGA_URTS
FPGA_UCTS
2 C883
0.1 UF
1
TP6
VDD
TP7
1
2 C880
0.1 UF
1
2 C881
0.1 UF
1 R809
2
4.7K
R808
1
2
4.7K
2 C884
0.1 UF
1
28
D
256k x 16 bit 3.3V
14
13
12
DIN1
DIN2
DIN3
DOUT1
DOUT2
DOUT3
9
10
11
DB9_UDTR
DB9_URTS
DB9_UTXD
4
5
6
7
8
R1IN
R2IN
R3IN
R4IN
R5IN
R1OUT
R2OUT
R3OUT
R4OUT
R5OUT
19
18
17
16
15
FPGA_URXD
FPGA_UDSR
FPGA_UDCD
FPGA_UCTS
FPGA_URI
28
24
1
2
27
3
C1+
C1C2+
C2V+
V-
R2OUTB
20
INVALID
21
23
22
FORCEON
FORCEOFF
26
VCC
DB9_URXD
DB9_UDSR
DB9_UDCD
DB9_UCTS
DB9_URI
LED1_SEG7
LED1_SEG6
NC
MEM_DATA16
MEM_DATA17
MEM_DATA18
MEM_DATA19
MEM_DATA20
MEM_DATA21
MEM_DATA22
MEM_DATA23
MEM_DATA24
MEM_DATA25
MEM_DATA26
MEM_DATA27
MEM_DATA28
MEM_DATA29
MEM_DATA30
MEM_DATA31
U916
FPGA_UDTR
FPGA_URTS
FPGA_UTXD
K16
K15
K14
K13
K12
K11
K10
K9
K8
K7
K6
K5
K4
K3
K2
K1
C16
C15
C14
C13
C12
C11
C10
C9
C8
C7
C6
C5
C4
C3
C2
C1
40
39
FPGA RS-232 Interface
IO_L40P_3
IO11
IO_L24N_3
IO_L24P_3
IO_L23N_3
VCCO_3
GND13
GND14
GND15
GND16
VCCO_6
IO_L23N_6
IO_L23P_6
IO_L24N_6/VREF_6
IO_L24P_6
IO12
IO_L01P_2/VRN_2
IO_L16N_2
TCK
TMS
IO_L27P_1
IO_L29P_1
IO10
IO_L32N_1/GCLK5
IO_L31P_0/VREF_0
IO_L30N_0
IO_L28N_0
IO_L25N_0
HSWAP_EN
IO_L16P_7/VREF_7
IO_L16N_7
IO_L01N_7/VRP_7
MEM_BE0_b
MEM_BE1_b
4
LED1_SEG5
LED1_SEG4
LED1_SEG3
IRQ7
IRQ3
IO_L20N_3
IO_L20P_3
IO_L19N_3
IO_L21P_3
VCCINT1
IO_L27N_4/DIN/D0
IO_L29N_4
VCCO_4
VCCO_5
IO_L30P_5
IO_L28P_5/D7
IO_L19N_6
IO_L19P_6
IO_L20N_6
IO_L20P_6
IO_L01P_7/VRN_7
GND10
PROG_B
IO_L01N_0/VRP_0
IO_L25P_0
IO_L28P_0
IO_L30P_0
IO_L32N_0/GCLK7
GND11
IO_L31P_1
IO_L29N_1
IO_L27N_1
IO_L10P_1
IO_L01P_1/VRN_1
GND12
IO_L01N_2/VRP_2
E
G
W
TL3301AF160QG
M16
M15
M14
M13
M12
M11
M10
M9
M8
M7
M6
M4
M3
M2
M1
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
6
41
17
3
2
J16
J15
J14
J13
J12
J11
J10
J9
J8
J7
J6
J5
J4
J3
J2
J1
IO_L17P_2/VREF_2
IO_L17N_2
IO_L16P_2
VCCINT3
IO/VREF_1
IO_L28N_1
IO_L30N_1
IO_L32P_1/GCLK4
IO_L31N_0
IO_L29P_0
IO_L27P_0
IO/VREF_02
VCCINT4
IO_L19P_7
IO_L17P_7
IO_L17N_7
MEM_CS_b
MEM_OE_b
MEM_RW
SW7
IO_L40N_3/VREF_3
GND17
IO_L39N_3
IO_L39P_3
VCCO_3
VCCO_3
GND18
GND19
GND20
GND21
VCCO_6
VCCO_6
IO_L39N_6
IO_L39P_6
IO_L40N_6
IO_L40P_6/VREF_6
GND8
TDI
IO/VREF_01
IO_L01P_0/VRN_0
IO6
VCCAUX5
IO7
IO_L32P_0/GCLK6
IO8
IO_L31N_1/VREF_1
VCCAUX6
IO9
IO_L10N_1/VREF_1
IO_L01N_1/VRP_1
TDO
GND9
4
1
IO_L17N_3
IO_L17P_3/VREF_3
IO_L19P_3
VCCINT7
IO/VREF_43
IO_L27P_4/D1
IO_L29P_4
IO_L31N_4/INIT_B
IO_L32P_5/GCLK2
IO_L30N_5
IO_L28N_5/D6
IO5
VCCINT8
IO_L16P_62
IO_L17N_6
IO_L17P_6/VREF_6
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
3
TL3301AF160QG
N16
N15
N14
N13
N12
N11
N10
N9
N8
N7
N6
N5
N4
N3
N2
N1
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
1
2
MEM_ADDR3
D956
FPGA_LED2
IO_L01P_3/VRN_3
GND3
DONE
IO_L01N_4/VRP_4
IO_L25P_4
IO_L28P_4
IO_L30P_4/D3
IO_L32N_4/GCLK1
GND4
IO_L31P_5/D5
IO_L29N_5
IO_L27N_5/VREF_5
IO_L10P_5/VRN_5
IO_L01P_5/CS_B
GND5
IO_L01N_6/VRP_6
VDD1
VDD2
R16
R15
R14
R13
R12
R11
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
7
8
9
10
13
14
15
16
29
30
31
32
35
36
37
38
MAX3243CDB
C882
0.1 UF
LED2_SEG0
FB_BS2
FB_AD14
FB_AD2
C
VDD
S2
2
9
12
14
15
16
OE/RESET
U?
mr2a16a
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU8
DQU9
DQU10
DQU11
DQU12
DQU13
DQU14
DQU15
R655
10K
U918
4
FPGA_UCLK
3
VDD
OE
1
OUT
GND
2
5
9
4
8
3
7
2
6
1
DB9_URI
DB9_UDTR
DB9_UCTS
DB9_UTXD
DB9_URTS
DB9_URXD
DB9_UDSR
DB9_UDCD
18.432MHZ
LED2_SEG2
LED2_SEG1
FB_CS2
FB_AD18
FB_AD6
P3
DB9_M
Silkscreen
S1
TDI
TDO
TMS
TCK
LED1_SEG2
LED1_SEG1
LED1_SEG0
IRQ4
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
GND
4
17
5
6
FB_AD19
FB_AD11
FB_AD7
FPGA_M1
1
2
3
4
5
18
19
20
21
22
23
24
25
26
27
42
43
44
12
34
XPF_TDI
XPF_TDO
XPF_TMS
XPF_TCK
CLK
MEM_ADDR1
MEM_ADDR2
MEM_ADDR3
MEM_ADDR4
MEM_ADDR5
MEM_ADDR6
MEM_ADDR7
MEM_ADDR8
MEM_ADDR9
MEM_ADDR10
MEM_ADDR11
MEM_ADDR12
MEM_ADDR13
MEM_ADDR14
MEM_ADDR15
MEM_ADDR16
MEM_ADDR17
MEM_ADDR18
2
D
3
18
19
20
MEM_DATA24
SW5
1
2
3
4
PCI_RESET
FPGA_CFG0
FPGA_CFG1
FPGA_CFG2
FPGA_CFG3
8
7
6
5
B
SW_DIP-4_SM
VDD
SLOT_PCI_REQ0
FB_OE
RP97
1
2
3
4
5
7
8
9
10
FB_RWB
FB_CS1
FB_AD29
FB_AD21
PCI_IRDY
F_PCI_GNT3
FB_CS0
FB_AD24
LED1_SEG0
LED1_SEG1
LED1_SEG2
LED1_SEG3
1
2
3
4
R4 1
R5 1
MEM_ADDR6
MEM_ADDR10
56
OHM
XPF_TCK
2
56
OHM
XPF_TMS
2
MEM_DATA19
MEM_DATA31
F_PCI_REQ1
8
470OHM
7
470OHM
6
470OHM
5
1
2
3
4
XC3S400-4FTG256C
1
2
3
4
14
16
15
3
2
1
18
17
4
COM1_D1
A1
B1
C1
D1
E1
F1
G1
DP1
COM_2
A2
B2
C2
D2
E2
F2
G2
DP2
13
11
10
8
6
5
12
7
9
470OHM
RP96A
RP96B
RP96C
RP96D
30mA
8
470OHM
7
470OHM
6
470OHM
5
LED2_SEG0
LED2_SEG1
LED2_SEG2
LED2_SEG3
8
470OHM
7
470OHM
6
470OHM
5
1
2
3
4
7-segment Display
LED2_SEG4
LED2_SEG5
LED2_SEG6
LED2_SEG7
8
470OHM
7
470OHM
6
470OHM
5
A
VDD
F_PCI_GNT2
F_PCI_GNT1
FB_BS0
FB_AD20
HSWAP_EN
FB_AD25
FB_AD13
FB_AD5
VDD
U28
RP94A
RP94B
RP94C
RP94D
LED1_SEG4
LED1_SEG5
LED1_SEG6
LED1_SEG7
RP95A
RP95B
RP95C
RP95D
4.7K
VDD
470OHM
FB_BS1
FB_AD17
FB_AD9
M66EN
6
RP93A
RP93B
RP93C
RP93D
MEM_DATA23
F_PCI_REQ2
F_PCI_REQ3
470OHM
1
2
470OHM
TP2
JP906
HDR_1X2_M
Drawing Title:
R810
4.7K
M54455EVB
Page Title:
2
FPGA_CCLK
VCCINT
VCCO
VCCJ
F16
F15
F14
F13
F12
F11
F10
F9
F8
F7
F6
F5
F4
F3
F2
F1
1
FPGA_CFG2
PCI_CLK4
FPGA_SPARE0
FPGA_SPARE1
U917
U915
VCCAUX7
IO_L22P_2
IO_L22N_2
IO_L21P_2
IO_L21N_2
GND31
VCCO_1
VCCO_1
VCCO_0
VCCO_0
GND32
IO_L23P_7
IO_L21N_7
IO_L22P_7
IO_L22N_7
VCCAUX8
FPGA_SPARE1
VDD
GND1
CCLK
IO1
IO_L01P_4/VRN_4
IO2
VCCAUX1
IO/VREF_41
IO_L32P_4/GCLK0
IO/VREF_5
IO_L31N_5/D4
VCCAUX2
IO3
IO_L10N_5/VRP_5
IO_L01N_5/RDWR_B
M1
GND2
1
FPGA Platform Flash
T16
T15
T14
T13
T12
T11
T10
T9
T8
T7
T6
T5
T4
T3
T2
T1
FPGA_SPARE0
FPGA_CCLK
MEM_ADDR4
MEM_ADDR8
MEM_ADDR12
25
V1.2
11
33
VDD
U919
VSS1
VSS2
V1.2
2
1
V2.5
3
2
5
FPGA
5
4
3
2
Size
C
Document Number
Date:
Monday, November 05, 2007
Rev
C
870012704-100
1
Sheet
14
of
17
5
4
3
2
1
Probe 1
Probe2
J56
J57
PCI_AD15
PCI_AD14
PCI_AD11
D
PCI_AD10
PCI_AD7
B12
B11
B10
B12
B11
B10
B9
B8
B7
B9
B8
B7
B6
B5
B4
PCI_AD6
PCI_AD3
A12
A11
A10
B6
B5
B4
B3
B2
B1
PCI_AD2
A15
A14
A13
B3
B2
B1
A15
A14
A13
A12
A11
A10
PCI_CLK5
PCI_AD13
PCI_AD31 B12
B11
PCI_AD30 B10
PCI_AD12
PCI_AD27
A9
A8
A7
A9
A8
A7
PCI_AD9
PCI_AD26
PCI_AD8
PCI_AD23
A6
A5
A4
A6
A5
A4
PCI_AD5
PCI_AD22
PCI_AD4
PCI_AD19
A3
A2
A1
A3
A2
A1
PCI_AD1
PCI_AD18
B12
B11
B10
B9
B8
B7
B9
B8
B7
B6
B5
B4
B6
B5
B4
B3
B2
B1
B3
B2
B1
PCI_AD0
A15
A14
A13
A15
A14
A13
A12
A11
A10
A12
A11
A10
PCI_AD29
A9
A8
A7
A9
A8
A7
PCI_AD25
PCI_AD24
PCI_GNT0
A6
A5
A4
A6
A5
A4
PCI_AD21
PCI_REQ0
PCI_AD20
PCI_GNT2
A3
A2
A1
A3
A2
A1
PCI_AD17
PCI_DEVSEL
PCI_AD28
PCI_REQ2
B12
B11
B10
B12
B11
B10
B9
B8
B7
B9
B8
B7
B6
B5
B4
B6
B5
B4
B3
B2
B1
B3
B2
B1
Probe 3
Probe 4
J58
J59
A15
A14
A13
A15
A14
A13
A12
A11
A10
A12
A11
A10
A9
A8
A7
A9
A8
A7
A6
A5
A4
A6
A5
A4
PCI_GNT3
A3
A2
A1
A3
A2
A1
PCI_GNT1
PCI_AD16
PCI_REQ3
B12
B11
B10
B12
B11
B10
B9
B8
B7
B9
B8
B7
B6
B5
B4
B6
B5
B4
B3
B2
B1
B3
B2
B1
A15
A14
A13
A15
A14
A13
A12
A11
A10
A12
A11
A10
A9
A8
A7
A9
A8
A7
A6
A5
A4
A6
A5
A4
A3
A2
A1
A3
A2
A1
PCI_REQ1
D
P6860/6880_28pins
P6860/6880_28pins
P6860/6880_28pins
B12
B11
B10
M66EN
PCI_AD20
B9
B8
B7
PCI_AD19
C
ACK64N
CF_PCI_GNT0
PCI_IRQ0
B6
B5
B4
B3
B2
B1
PCI_IRQ3
Probe 5
Probe 6
J60
J61
A15
A14
A13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
A15
A14
A13
PCI_SERR
PCI_AD17
A12
A11
A10
A12
A11
A10
REQ64N
A9
A8
A7
A9
A8
A7
PCI_AD18
A6
A5
A4
A6
A5
A4
CF_PCI_REQ0
A3
A2
A1
A3
A2
A1
PCI_C_BE3
PCI_C_BE2
PCI0_SBO
PCI_LOCK
PCI_STOP
PCI_AD16
PCI_TRDY
PCI_IRQ2
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
Probe 7
Probe 8
J62
VREF
J63
A15
A14
A13
A15
A14
A13
A12
A11
A10
A12
A11
A10
A9
A8
A7
A9
A8
A7
PCI_C_BE1
PCI_C_BE0
SD_A8
A6
A5
A4
A6
A5
A4
PCI_PERR
SD_A12
PCI_PAR
SD_A9
A3
A2
A1
PCI_IRQ1
P6860/6880_28pins
A3
A2
A1
PCI_RESET
SD_A1
SD_A2
SD_A5
B12
B11
B10
B12
B11
B10
B9
B8
B7
B9
B8
B7
B6
B5
B4
B6
B5
B4
B3
B2
B1
B3
B2
B1
A15
A14
A13
A15
A14
A13
A12
A11
A10
A12
A11
A10
SD_A0
SD_DQS2
SD_A3
SD_DM3
A9
A8
A7
A9
A8
A7
SD_A4
SD_DQS3
SD_A6
SD_CAS
A6
A5
A4
A6
A5
A4
SD_A7
SD_RAS
SD_A10
SD_CKE
A3
A2
A1
A3
A2
A1
SD_A11
SD_WE
PCI_IRDY
PCI_FRAME
SD_DM2
B12
B11
B10
B12
B11
B10
B9
B8
B7
B9
B8
B7
B6
B5
B4
B6
B5
B4
B3
B2
B1
B3
B2
B1
A15
A14
A13
A15
A14
A13
A12
A11
A10
A12
A11
A10
A9
A8
A7
A9
A8
A7
SD_CLK_P
A6
A5
A4
A6
A5
A4
SD_CS1
A3
A2
A1
A3
A2
A1
SD_BA0
SD_A13
C
SD_CLK_N
SD_CS0
SD_BA1
P6860/6880_28pins
P6860/6880_28pins
P6860/6880_28pins
P6860/6880_28pins
Probe 9
J64
Probe 10
Probe 11
J65
SD_D17
SD_D18
SD_D21
SD_D22
SD_D24
B
SD_D25
SD_D30
B12
B11
B10
B12
B11
B10
B9
B8
B7
B9
B8
B7
B6
B5
B4
B6
B5
B4
B3
B2
B1
SD_D29
B3
B2
B1
A15
A14
A13
A12
A11
A10
A9
A8
A7
A15
A14
A13
A12
A11
A10
A9
A8
A7
FB_AD16
SD_D16
FB_AD17
SD_D19
FB_AD20
SD_D20
FB_AD21
SD_D23
FB_AD24
A6
A5
A4
A6
A5
A4
SD_D27
A3
A2
A1
A3
A2
A1
SD_D28
FB_AD25
SD_D26
FB_AD28
FB_AD29
SD_D31
B12
B11
B10
B12
B11
B10
B9
B8
B7
B9
B8
B7
B6
B5
B4
B6
B5
B4
B3
B2
B1
B3
B2
B1
Probe 12
J67
J66
A15
A14
A13
A15
A14
A13
A12
A11
A10
A12
A11
A10
FB_AD18
A9
A8
A7
A9
A8
A7
FB_AD22
A6
A5
A4
A6
A5
A4
FB_AD26
A3
A2
A1
A3
A2
A1
FB_AD30
FB_AD0
FB_CLK
FB_AD1
FB_AD4
FB_AD19
FB_AD5
FB_AD8
FB_AD23
FB_AD9
FB_AD12
FB_AD27
FB_AD13
FB_AD31
B12
B11
B10
B12
B11
B10
B9
B8
B7
B9
B8
B7
B6
B5
B4
B6
B5
B4
B3
B2
B1
B3
B2
B1
A15
A14
A13
A15
A14
A13
A12
A11
A10
A12
A11
A10
FB_AD2
A9
A8
A7
A9
A8
A7
FB_AD6
A6
A5
A4
A6
A5
A4
FB_AD10
A3
A2
A1
A3
A2
A1
FB_AD14
IRQ1
SYSRESET
IRQ3
FB_TS
FB_AD3
FB_TA
FB_CS0
FB_AD7
FB_CS1
FB_BS0
FB_AD11
FB_BS1
B12
B11
B10
B12
B11
B10
B9
B8
B7
B9
B8
B7
B6
B5
B4
B6
B5
B4
B3
B2
B1
B3
B2
B1
FB_AD15
A15
A14
A13
A15
A14
A13 CPU_RSTOUT
A12
A11
A10
A12
A11
A10
IRQ4
A9
A8
A7
A9
A8
A7
FB_RWB
A6
A5
A4
A6
A5
A4
FB_CS2
A3
A2
A1
A3
A2
A1
FB_BS2
IRQ7
B
FB_OE
FB_CS3
FB_BS3
P6860/6880_28pins
P6860/6880_28pins
P6860/6880_28pins
P6860/6880_28pins
A
A
Drawing Title:
M54455EVB
Page Title:
PROBES
5
4
3
2
Size
C
Document Number
Date:
Monday, November 05, 2007
Rev
C
870012704-100
1
Sheet
15
of
17
5
4
3
2
VDDA
VDD
2
VDD
1
MIC_IN
G1
H1
MICBIAS
MICIN
F1
VMID
J3
J2
LLINEIN
RLINEIN
CODEC_INL
CODEC_INR
TLV320AIC23B
3.5MM
1
LOUT
ROUT
B1
C1
C236
22UF
HDR_2X3
D20
D21
D22
E19
E20
SSIMCLK
SSIRXDU1RXD
SSITXDU1TXD
SSIBCLKU1CTSB
SSIFSU1RTSB
SSI
D
SKT360
U923B
B2
B3
B4
B5
B6
B7
B8
C2
C4
C5
C6
C7
C8
D2
D3
D4
D5
D6
D7
D8
E2
E3
E4
E5
C247
0.1 UF
2
2
+
U1R
SSI_MCLK
SSI_RXD
SSI_TXD
SSI_BCLK
SSI_FS
CODEC_OUTR
CODEC_OUTL
AUDIO
NC_B2
NC_B3
NC_B4
NC_B5
NC_B6
NC_B7
NC_B8
NC_C2
NC_C4
NC_C5
NC_C6
NC_C7
NC_C8
NC_D2
NC_D3
NC_D4
NC_D5
NC_D6
NC_D7
NC_D8
NC_E2
NC_E3
NC_E4
NC_E5
NC_E6
NC_E7
NC_E8
NC_F2
NC_F3
NC_F4
NC_F5
NC_F6
NC_F7
NC_F8
NC_G2
NC_G3
NC_G4
NC_G5
NC_G6
NC_G7
NC_G8
NC_H2
NC_H3
NC_H4
NC_H5
NC_H6
NC_H7
NC_H8
E6
E7
E8
F2
F3
F4
F5
F6
F7
F8
G2
G3
G4
G5
G6
G7
G8
H2
H3
H4
H5
H6
H7
H8
VDD
VDDA
1
L38 2
600OHM
1
CS
SCLK
SDIN
BCLK
DIN
DOUT
LRCIN
LRCOUT
2
4
6
C285
0.1 UF
2
J4
J7
J6
DSPI_PCS5
DSPI_SCK
DSPI_SOUT
2
3
4
5
1
NC1
NC2
NC3
MIC_IN
AGND
XTO
CLKOUT
C9
B9
A7
A8
A6
J910
1
3
5
1
C
PINK
MIC-IN
H9
D9
RHPOUT
LHPOUT
A3
A4
NC_A1
NC_A9
NC_J9
NC_J1
CODEC_OUTR
IN3
IN4
CODEC_OUTL
22
23
24
25
G4
G3
G2
G1
GND4
GND3
GND2
GND1
1 AGND
32
33
34
35
J5
A1
A9
J9
J1
1 AGND
B
LIME GREEN
LINE-OUT
CODEC_INR
IN1
IN2
CODEC_INL
DGND
AGND
HPGND
D
A
BLUE
LINE-IN
XTI/MCLK
MODE
1
1 AGND
J8
F9
E1
A2
U924
1
DVDD
BVDD
AVDD
HPVDD
U923A
R735
10K
2
C287
0.01UF
G9
E9
D1
A5
C288
0.01UF
1
C286
0.1 UF
L39 2
600OHM
TLV320AIC23B
C
C
R1004 and R1005 should be
placed as close to U928 as
possible.
U1M
VDD
VDD
1
1
DMA
10K
2
R1004
C306
0.1 UF
R1005
2
DREQ0
DACK0
10K
S1
VCC
1
VBUS D-
1
33
2
1
GND1
GND2
GND3
RBIAS
32
ID
S2
4
3
10
U928
5
1
R151 2
0 OHM
STP
DIR
CLKOUT
NXT
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
13
12
14
11
1
ENA
FLGA
2
4
ENB
FLGB
3
7
IN
OUTA
8
GND
OUTB
5
6
C305
1.0UF
MIC2026-1YM
P4
USB_TYPE_A
JP918
XO
XI
1
2
3
27
28
2
R739 1
0 OHM
RESET
R738
12.0K
9
HDR_1X3
+
C307
47UF
2
ULPI_RESET
USBCLK_24
USBCLK_60
R736
R737
33 OHM 33 OHM
1
R9081
15K
1
R9082
15K
1
USB3300
USB
FS/LS Host via
MCF5445x on-chip
transceiver
A1
A2
A3
A4
S2
1V8VDDA
VBUS
CPEN
EXTVBUS
B
5
1
29
DP
DM
1
1V8VDD1
1V8VDD2
24
23
22
21
20
19
18
17
2
SKT360
26
15
2
USBVBUSENUSBPULLUPULPINXT
USBVBUS-OCULPISTP
USBDEVDMNS
USBDEVDPLS
FEC0TXERULPIDATA0
FEC0RXCLKULPIDATA1
FEC0TXD2ULPIDATA2
FEC0TXD3ULPIDATA3
FEC0RXD2ULPIDATA4
FEC0RXD3ULPIDATA5
FEC0CRSULPIDATA6
FEC0COLULPIDATA7
USB_VBUS_EN
USB_VBUS_OC
USB_DEV_DMNS
USB_DEV_DPLS
ULPI_DATA0
ULPI_DATA1
ULPI_DATA2
ULPI_DATA3
ULPI_DATA4
ULPI_DATA5
ULPI_DATA6
ULPI_DATA7
3V3VDD1
3V3VDD2
3V3VDD3
3V3VDD4
3V3VDD5
2
C303
0.01UF
U1P
AA2
V4
A14
A15
AB12
AA8
AB11
W10
Y9
AB9
AA7
AB7
4
7
8
2
1
2
C302
0.01UF
31
30
25
16
6
OTG/dual-role
USB via ULPI
interface
G
C301
0.01UF
3
ID
C304
0.01UF
USB-AB_P
U927
B
C300
4.7UF
2
D+
VDD
PLACE CAPACITORS
CLOSE TO VDD3.3 PINS
ON USB3300
USB-AB_N
J909
USB_MINI_AB_SKT
S1
SKT360
ULPIDIR
USBCLKIN
2
DACK1bULPIDIR
DREQ1bUSBCLKIN
DACK0bDSPIPCS3
DREQ0b
C17
C18
A18
B18
USB-A_N
USB-A_P
5
1
C290
4.7UF
2
C291
0.1 UF
2
2
1
2
C289
4.7UF
1
A
Layout Notes:
* The required 33 ohm series source termination resistors should be placed as
closely to the USB_DEV_DMNS and USB_DEV_DPLS outputs as possible.
* Route D- and D+ signals on the top or bottom layer of the board keeping
them as short as possible with a minimum amount of vias and corners.
* Use 45deg turns instead of 90deg turns.
* The trace width and spacing of the D- and D+ signals should be such that
the differential impedance is 90 Ohms.
* Maintain the parallelism (skew matching) between D- and D+. These traces
should be the same overall length.
1
A
C292
0.1 UF
Drawing Title:
M54455EVB
Page Title:
AUDIO AND USB
USB
4
3
2
Size
C
Document Number
Date:
Monday, November 05, 2007
Rev
C
870012704-100
1
Sheet
16
of
17
5
4
3
2
1
D
D
C
C
CF_RESET
CF_TEA
CF_DSO
P&E Microcomputer Systems
USB ColdFire Multilink BDM Interface
CF_FREEZE
CF_DSCLK
CF_BKPT
PST0
PST1
PST2
PST3
CF_DSI
EXTERNAL_DSI
BDM_RESET
FB_TA
DSO
TCLK_PSTCLK
DSCLK
BKPT
PSTDDATA0
PSTDDATA1
PSTDDATA2
PSTDDATA3
DSI
EXTERNAL_DSI
B
B
A
A
Drawing Title:
P&E CONFIDENTIAL INFORMATION
Page Title:
USB TO BDM COLDFIRE REFERENCE DESIGN
5
4
3
2
Size
C
Document Number
Date:
Monday, November 05, 2007
Rev
C
PDF: SPF-22131 SOURCE: SCH-22131
1
Sheet
17
of
17