NOTE: This product has been replaced with UT28F256QLE or SMD 5962-96891 device types 09 and 10. 1 Standard Products UT28F256 Radiation-Hardened 32K x 8 PROM Data Sheet December 2002 FEATURES Programmable, read-only, asynchronous, radiationhardened, 32K x 8 memory - Supported by industry standard programmer 45ns and 40ns maximum address access time (-55 oC to +125 oC) TTL compatible input and TTL/CMOS compatible output levels Three-state data bus Total dose: 1E6 rad(Si) LETTH(0.25) ~ 100 MeV-cm2/mg SEL Immune >128 MeV-cm2/mg Saturated Cross Section cm2 per bit, 1.0E-11 - 1.2E-8 errors/device-day, Adams 90% geosynchronous heavy ion DECODER QML Q & V compliant part - AC and DC testing at factory Packaging options: - 28-lead 50-mil center flatpack (0.490 x 0.74) - 28-lead 100-mil center DIP (0.600 x 1.4) - contact factory VDD: 5.0 volts + 10% PRODUCT DESCRIPTION Radiation-hardened process and design; total dose irradiation testing to MIL-STD-883, Method 1019 A(14:0) Memory cell LET threshold: >128 MeV-cm2/mg Standard Microcircuit Drawing 5962-96891 Low operating and standby current - Operating: 125mA maximum @25MHz • Derating: 3mA/MHz - Standby: 2mA maximum (post-rad) - - The UT28F256 amorphous silicon anti-fuse PROM is a high performance, asynchronous, radiation-hardened, 32K x 8 programmable memory device. The UT28F256 PROM features fully asychronous operation requiring no external clocks or timing strobes. An advanced radiation-hardened twin-well CMOS process technology is used to implement the UT28F256. The combination of radiation-hardness, fast access time, and low power consumption make the UT28F256 ideal for high speed systems designed for operation in radiation environments. MEMORY ARRAY SENSE AMPLIFIER CE PE CONTROL LOGIC DQ(7:0) OE PROGRAMMING Figure 1. PROM Block Diagram 2 DEVICE OPERATION PIN NAMES The UT28F256 has three control inputs: Chip Enable (CE), Program Enable (PE), and Output Enable (OE); fifteen address inputs, A(14:0); and eight bidirectional data lines, DQ(7:0). CE is the device enable input that controls chip selection, active, and standby modes. Asserting CE causes IDD to rise to its active value and decodes the fifteen address inputs to select one of 32,768 words in the memory. PE controls program and read operations. During a read cycle, OE must be asserted to enable the outputs. A(14:0) Address CE Chip Enable OE Output Enable PE Program Enable DQ(7:0) Data Input/Data Output PIN CONFIGURATION Table 1. Device Operation Truth Table 1 A14 1 28 VDD A12 2 27 PE A7 3 26 A6 A5 4 5 A4 6 A3 OE PE CE I/O MODE MODE A13 X 1 1 Three-state Standby 25 A8 0 1 0 Data Out Read 24 23 A9 A11 1 0 0 Data In Program 7 22 OE 1 1 0 Three-state Read 2 A2 8 21 A10 A1 9 20 CE A0 10 19 DQ7 DQ0 11 18 DQ6 DQ1 DQ2 12 17 13 16 DQ5 DQ4 VSS 14 15 DQ3 Notes: 1. “X” is defined as a “don’t care” condition. 2. Device active; outputs disabled. ABSOLUTE MAXIMUM RATINGS 1 (Referenced to VSS) SYMBOL PARAMETER LIMITS UNITS VDD DC supply voltage -0.3 to 7.0 V VI/O Voltage on any pin -0.5 to (VDD + 0.5) V TSTG Storage temperature -65 to +150 °C 1.5 W +175 °C Thermal resistance, junction-to-case 2 3.3 °C/W DC input current ±10 mA PD Maximum power dissipation TJ Maximum junction temperature ΘJC II Notes: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. Test per MIL-STD-883, Method 1012, infinite heat sink. 3 RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER LIMITS UNITS VDD Positive supply voltage 4.5 to 5.5 V TC Case temperature range -55 to +125 °C VIN DC input voltage 0 to VDD V DC ELECTRICAL CHARACTERISTICS (Pre/Post-Radiation)* (VDD = 5.0V ±10%; -55°C < TC < +125°C) SYMBOL PARAMETER CONDITION MINIMUM MAXIMUM VIH High-level input voltage (TTL) VIL Low-level input voltage (TTL) 0.8 V VOL1 Low-level output voltage IOL = 4.0mA, VDD = 4.5V (TTL) 0.4 V VOL2 Low-level output voltage IOL = 200µA, VDD = 4.5V (CMOS) VSS + 0.10 V VOH1 High-level output voltage IOH = -200µA, VDD = 4.5V (CMOS) VOH2 High-level output voltage IOH = -2.0mA, VDD = 4.5V (TTL) CIN 1 Input capacitance ƒ = 1MHz, VDD = 5.0V VIN = 0V 15 pF Bidirectional I/O capacitance ƒ = 1MHz, VDD = 5.0V VOUT = 0V 15 pF IIN Input leakage current VIN = 0V to VDD -5 5 µA IOZ Three-state output leakage current VO = 0V to VDD VDD = 5.5V OE = 5.5V -10 10 µA IOS 2,3 Short-circuit output current VDD = 5.5V, VO = VDD VDD = 5.5V, VO = 0V 90 mA mA IDD1(OP)5 Supply current operating @25.0MHz (40ns product) @22.2MHz (45ns product) TTL inputs levels (IOUT = 0), VIL = 0.2V VDD, PE = 5.5V 125 117 mA mA IDD2(SB) post-rad Supply current standby CMOS input levels VIL = VSS +0.25V CE = VDD - 0.25 VIH = VDD - 0.25V 2 mA CIO 1, 4 2.4 UNIT VDD -0.1 V 2.4 V -90 Notes: * Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019 at 1E6 rad(Si). 1. Measured only for initial qualification, and after process or design changes that could affect input/output capacitance. 2. Supplied as a design limit but not guaranteed or tested. 3. Not more than one output may be shorted at a time for maximum duration of one second. 4. Functional test. 5. Derates at 3.0mA/MHz. 4 V READ CYCLE A combination of PE greater than VIH(min), and CE less than VIL(max) defines a read cycle. Read access time is measured from the latter of device enable, output enable, or valid address to valid data output. An address access read is initiated by a change in address inputs while the chip is enabled with OE asserted and PE deasserted. Valid data appears on data output, DQ(7:0), after the specified tAVQV is satisfied. Outputs remain active throughout the entire cycle. As long as device enable and output enable are active, the address inputs may change at a rate equal to the minimum read cycle time. The chip enable-controlled access is initiated by CE going active while OE remains asserted, PE remains deasserted, and the addresses remain stable for the entire cycle. After the specified tELQV is satisfied, the eight-bit word addressed by A(14:0) appears at the data outputs DQ(7:0). Output enable-controlled access is initiated by OE going active while CE is asserted, PE is deasserted, and the addresses are stable. Read access time is tGLQV unless tAVQV or tELQV have not been satisfied. AC CHARACTERISTICS READ CYCLE (Post-Radiation)* (VDD = 5.0V ±10%; -55°C < TC < +125°C) SYMBOL PARAMETER 28F256-45 MIN MAX 28F256-40 MIN MAX tAVAV1 Read cycle time 45 40 tAVQV Read access time tAXQX2 Output hold time 0 0 ns tGLQX2 OE-controlled output enable time 0 0 ns tGLQV OE-controlled access time 15 15 ns tGHQZ OE-controlled output three-state time 15 15 ns tELQX2 CE-controlled output enable time tELQV CE-controlled access time 45 40 ns tEHQZ CE-controlled output three-state time 15 15 ns 45 0 Notes: * Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019 at 1E6 rads(Si). 1. Functional test. 2. Three-state is defined as a 400mV change from steady-state output voltage. 5 UNIT ns 40 0 ns ns tAVAV A(14:0) CE tAVQV tELQX tEHQZ tELQV OE DQ(7:0) tGHQZ tAXQX tGLQV tGLQX tAVQV Figure 2. PROM Read Cycle RADIATION HARDNESS The UT28F256 PROM incorporates special design and layout features which allow operation in high-level radiation environments. UTMC has developed special low-temperature processing techniques designed to enhance the total-dose radiation hardness of both the gate oxide and the field oxide while maintaining the circuit density and reliability. For transient radiation hardness and latchup immunity, UTMC builds all radiation-hardened products on epitaxial wafers using an advanced twin-tub CMOS process. In addition, UTMC pays special attention to power and ground distribution during the design phase, minimizing dose-rate upset caused by rail collapse. RADIATION HARDNESS DESIGN SPECIFICATIONS 1 Total Dose 1E6 rad(Si) Latchup LET Threshold >128 MeV-cm2/mg Memory Cell LET Threshold >128 MeV-cm2/mg 54 MeV-cm2/mg 1E-6 cm2 Transient Upset LET Threshold Transient Upset Device Cross Section @ LET=128 MeV-cm2/mg Note: 1. The PROM will not latchup during radiation exposure under recommended operating conditions. 6 330 ohms VREF=1.73V TTL 90% 90% 3.0V 50pF 10% 0V 10% < 5ns < 5ns Input Pulses Notes: 1. 50pF including scope probe and test socket. 2. Measurement of data output occurs at the low to high or high to low transition mid-point (TTL input = 1.5V). Figure 3. AC Test Loads and Input Waveforms 7 k 0.015 0.008 PIN NO. 1 ID. 6 k 0.015 0.008 26 PLACES 0.050 BSC e -A- -B- D 0.740 MAX S1 (4) PLACES 0.000 MIN. E1 0.550 MAX b 0.022 7 0.015 28 PLACES 0.010 M H 0.036 M H A-B S D S 5 A-B S D S 5 TOP VIEW E 0.520 0.460 A 0.115 0.045 -D7 c 0.009 0.004 0.040 -H- -CQ 0.045 0.026 E2 0.180 MIN L 0.370 0.250 E3 0.030 MIN END VIEW Notes: 1. All exposed metalized areas to be plated per MIL-PRF-38535. 2. The lid is connected to V SS . 3. Lead finishes are in accordance with MIL-PRF-38535. 4. Dimension letters refer to MIL-STD-1835. 5. Lead position and coplanarity are not measured. 6. ID mark symbol is vendor option. 7. With solder, increase maximum by 0.003. 8. Total weight is approximately 2.4 grams. Figure 5. 28-Lead 50-mil Center Flatpack (0.490 x 0.74) 7 ORDERING INFORMATION 256K PROM: SMD 5962 * 96891 * * * * Lead Finish: (A) = Solder (C) = Gold (X) = Optional Case Outline: (Y) = 28-pin DIP (contact factory) (X) = 28-lead Flatpack Class Designator: (Q) = Class Q (V) = Class V Device Type (03) = 45ns Access Time, TTL inputs, CMOS/TTL compatible outputs (04) = 40ns Access Time, TTL inputs, CMOS/TTL compatible outputs Drawing Number: 96891 Total Dose: (F) = 3E5 (G) = 5E5 (H) = 1E6 (R) = 1E5 rads(Si) rads(Si) rads(Si) rads(Si) Federal Stock Class Designator: No options Notes: 1. Lead finish (A, C, or X) must be specified. 2. If an “X” is specified when ordering, part marking will match the lead finish and will be either “A” (solder) or “C” (gold). 3. Total dose radiation must be specified when ordering. QML Q and QML V not available without radiation hardening. 4. Check factory for availability of 45ns part. 5. Lead finish: Factory programming either solder or gold. Field programming gold only. 8 256K PROM UT **** *** - * * * * * * Total Dose: ( ) = Total dose characteristics neither tested nor guaranteed Lead (A) (C) (X) Finish: = Solder = Gold = Optional Screening: (C) = Mil Temp (P) = Prototype Package Type: (P) = 28-lead DIP (contact factory) (U) = 28-lead Flatpack Access Time: (40) = 40ns access time, TTL compatible inputs, CMOS/TTL compatible outputs (45) = 45ns access time, TTL compatible inputs, CMOS/TTL compatible outputs Device Type Modifier: (T) = TTL compatible inputs and CMOS/TTL compatible outputs Device Type: (28F256) = 32Kx8 One Time Programmable PROM Notes: 1. Lead finish (A,C, or X) must be specified. 2. If an “X” is specified when ordering, then the part marking will match the lead finish and will be either “A” (solder) or “C” (g old). 3. Military Temperature Range flow per UTMC Manufacturing Flows Document. Radiation characteristics are neither tested nor guaranteed and may not be specified. 4. Prototype flow per UTMC Manufacturing Flows Document. Devices have prototype assembly and are tested at 25°C only. Radiation characteristics are neither tested nor guaranteed and may not be specified. 5. Check factory for availability of 45ns part. 6. Lead finish: Factory programming either solder or gold. Field programming gold only. 9 Notes 10 Notes 11