UT54ACTQ16245 - Aeroflex Microelectronic Solutions

Standard Products
UT54ACTQ16245
RadHard CMOS 16-bit Bidirectional Transceiver, TTL Inputs, and
Three-State Outputs
Datasheet
May 16, 2012
www.aeroflex.com/radhard
LOGIC SYMBOL
FEATURES
 16 non-inverting bidirectional buffers with three-state outputs
 Guaranteed simultaneously switching noise level and
dynamic threshold performance
 Separate control logic for each byte
OE1 (48)
G1
OE2 (25)
(1)
T/R1
G2
A0
TM
 0.6m Commercial RadHard CMOS
- Total dose: 100K rad(Si)
- Single Event Latchup immune
 High speed, low power consumption
 Output source/sink 24mA
 Standard Microcircuit Drawing 5962-06244
- QML compliant part
 Package:
- 48-lead flatpack, 25 mil pitch (.390 x .640)
A1
(2)
11
12
(46)
(3)
(43)
A3
(41)
A4
(40)
A5
(38)
A6
(37)
A7
(36)
A8
(6)
A10
(8)
B0
B1
B2
B3
B4
(9)
B5
(11)
B6
(12)
B7
(13)
B8
21
22
(35)
(33)
(32)
A11
(30)
A12
(29)
A13
(27)
A14
(26)
A15
Aeroflex’s Commercial RadHardTM epitaxial CMOS technology and is ideal for space applications. This high speed, low
power UT54ACTQ16245 transceiver is designed to perform
asynchronous two-way communication and signal buffering.
Balanced outputs and low "on" output impedance make the
UT54ACTQ16245 well suited for driving high capacitance
loads and low impedance backplanes. The Transmit/Receive
input (T/R) controls the direction of data flow through the device. The output enable input (OEn, active low) overrides the
direction control (T/R) and disables both the A and B ports by
placing them in a high impedance state. These signals can be
driven from either port A or B. The direction and output enable
controls operate these devices as either two independent 8-bit
transceivers or one 16-bit transceiver
T/R2
(5)
A9
The 16-bit wide UT54ACTQ16245 transceiver is built using
(47)
(24)
(44)
A2
DESCRIPTION
2EN1 (BA)
2EN2 (AB)
1EN1 (BA)
1EN2 (AB)
(14)
B9
(16)
B10
(17)
B11
(19)
B12
(20)
B13
(22)
B14
(23)
B15
PIN DESCRIPTION
Pin Names
Description
OEn
Output Enable Input (Active Low)
T/Rn
Direction Control Inputs
A0-A15
Side A Inputs or 3-State Outputs
B0-B15
Side B Inputs or 3-State Outputs
FUNCTION TABLE
1
ENABLE
OEn
DIRECTION
T/Rn
OPERATION
L
L
B Data To A Bus
L
H
A Data To B Bus
H
X
Isolation, High-Z State on
Bus A and Bus B
PINOUTS
48-Lead Flatpack
Top View
T/R1
1
48
OE1
B0
2
47
A0
B1
3
46
VSS
B2
4
5
45
44
A1
VSS
A2
B3
6
43
A3
VDD
7
42
VDD
B4
B5
VSS
8
9
10
41
40
39
A4
A5
VSS
B6
11
38
A6
B7
12
37
A7
B8
13
36
A8
B9
VSS
14
15
35
34
A9
VSS
B10
16
33
A10
B11
17
32
A11
VDD
B12
B13
VSS
18
19
20
21
31
30
29
28
VDD
A12
A13
VSS
B14
B15
T/R2
22
23
24
27
26
25
A14
A15
OE2
2
LOGIC DIAGRAM
T/R1
(1)
A0
(48)
A8
A3
(20)
A14
(22)
A15
(12)
3
B14
(26)
(23)
B7
B13
(27)
B6
(37)
B12
(29)
B5
(38)
(11)
A7
(19)
A13
B11
(30)
B4
(40)
(9)
A6
(17)
A12
B10
(32)
B3
(41)
(8)
A5
(16)
A11
B9
(33)
B2
(43)
(6)
A4
(14)
A10
B8
(35)
B1
(44)
OE2
(36)
(13)
A9
(5)
(25)
B0
(46)
(3)
A2
(24)
OE1
(47)
(2)
A1
T/R2
B15
RADIATION HARDNESS SPECIFICATIONS 1
PARAMETER
LIMIT
UNITS
Total Dose
1.0E5
rad(Si)
SEL Latchup
>108
MeV-cm2/mg
SEU Onset Let
N/A3
MeV-cm2/mg
Neutron Fluence2
1.0E14
n/cm2
Notes:
1. Logic will not latchup during radiation exposure within the limits VDD = 5.5V, T = 125oC.
2. Not tested, inherent of CMOS technology.
3. This device contains no memory storage elements which can be upset.
ABSOLUTE MAXIMUM RATINGS1
SYMBOL
PARAMETER
LIMIT (Mil only)
UNITS
VI/O
Voltage any pin during operation
-.3 to VDD +.3
V
VDD
Supply voltage
-0.3 to 6.0
V
TSTG
Storage Temperature range
-65 to +150
C
TJ
Maximum junction temperature
+175
C
JC
Thermal resistance junction to case
20
C/W
II
DC input current
10
mA
PD
Maximum power dissipation
310
mW
Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at
these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability and performance.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMIT
UNITS
VDD
Supply voltage
4.5 to 5.5
V
VIN
Input voltage any pin
0 to VDD
V
TC
Temperature range
-55 to + 125
C
tINRISE
tINFALL
Maximum input rise or fall time
(VIN transitioning between VIL (max) and VIH (min))
20
ns
4
DC ELECTRICAL CHARACTERISTICS 1
( -55C < TC < +125C)
SYMBOL
PARAMETER
CONDITION
MIN
MAX
UNIT
0.8
V
VIL
Low level input voltage2
VDD from 4.5V to 5.5V
VIH
High level input voltage2
VDD from 4.5 V to 5.5V
2.0
IIN
Input leakage current
VDD from 4.5V to 5.5V
-1
1
A
-10
10
A
-600
600
mA
0.35
0.5
V
V
VIN = VDD or VSS
IOZ
Three-state output leakage current
VDD from 4.5V to 5.5V
VIN = VDD or VSS
IOS
Short-circuit output current 3,4
VO = VDD or VSS
VDD from 4.5V to 5.5V
VOL1
Low-level output voltage5
IOL= 24mA
-55C, 25C
IOL= 24mA
+125C
IOL= 100A
0.2
VIN = 2.0V or 0.8V
VDD = 4.5V to 5.5V
VOL2
Low-level output voltage5,6
IOL= 50 mA
VIN = 2.0V or 0.8V
-55C, 25C
+125C
0.8
1.0
V
VDD = 5.5V
VOH1
High-level output voltage5
IOH= -24 mA
-55C, 25C
IOL= -24mA
+125C
IOH= -100A
VDD - 0.64
VDD - 0.8
V
VDD - 0.2
VIN = 2.0V or 0.8V
VDD = 4.5V to 5.5V
VOH2
High-level output voltage5, 6
IOH= -50 mA
-55C, 25C
VDD - 1.1
+125C
VDD - 1.3
V
VIN = 2.0V or 0.8V
VDD = 5.5V
VIC+
Positive input clamp voltage
For input under test, IIN = 18mA
0.4
1.5
V
-1.5
-0.4
V
1.5
mW/MHz
VDD = 0.0V
VIC-
Negative input clamp voltage
For input under test, IIN = -18mA
VDD = open
Ptotal
Power dissipation 7, 8, 9
CL = 20pF
VDD from 4.5V to 5.5V
5
IDDQ
Standby Supply Current VDD
VIN = VDD or VSS
VDD = 5.5V
IDDQ
Pre-Rad 25oC
OEn = VDD
10
Pre-Rad -55oC to +125oC
OEn = VDD
160
Post-Rad 25oC
OEn = VDD
160
Quiescent Supply Current Delta, TTL input level
For input under test
VIN = VDD - 2.1V
For other inputs
A
mA
1.6
VIN = VDD or VSS
VDD = 5.5V
CIN
Input capacitance10
 = 1MHz @ 0V
15
pF
15
pF
VDD from 4.5V to 5.5V
COUT
Output capacitance10
 = 1MHz @ 0V
VDD from 4.5V to 5.5V
VOLP
Low level VSS bounce noise11
VIN = 3.0V, VIL = 0.0V, TA=+25oC,
VDD = 5.0V
1200
-1500
mV
mV
High level VDD bounce noise11
See figure "Quiet Output Under Test"
VOH
+1500
VOH
-1600
mV
VOLV
VOHP
VOHV
mV
Notes:
1. All specifications valid for radiation dose  1E5 rad(Si) per MIL-STD-883, Method 1019.
2. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%, 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are
guaranteed to VIH(min) and VIL(max).
3. Not more than one output may be shorted at a time for maximum duration of one second.
4. Supplied as a design limit, but not guaranteed or tested.
5. Per MIL-PRF-38535, for current density  5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765
pF-MHz.
6. Transmission driving tests are performed at VDD = 5.5V, only one output loaded at a time with a duration not to exceed 2ms. The test is guaranteed, if not tested,
for VIN=VIH minimum or VIL maximum.
7. Guaranteed by characterization.
8. Power does not include power contribution of any CMOS output sink current.
9. Power dissipation specified per switching output.
10.Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS
at frequency of 1MHz and a signal amplitude of 50mV rms maximum.
11. This test is for qualification only. VSS and VDD bounce tests are performed on a non-switching (quiescent) output and are used to measure the magnitude of induced
noise caused by other simultaneously switching outputs. The test is performed on a low noise bench test fixture.
6
AC ELECTRICAL CHARACTERISTICS1
(VDD = 5V 10%, -55C < TC < +125C)
SYMBOL
PARAMETER
CONDITION
MIN
MAX
UNIT
tPLH
Propagation delay Data to Bus
CL = 40 pF
3
8.5
ns
tPHL
Propagation delay Data to Bus
RL = 50
3
8.5
ns
tPZL1
Output enable time OEn to Bus
See figure "Test
Load"
3
10
ns
tPZH1
Output enable time OEn to Bus
3
10
ns
tPLZ1
Output disable time OEn to Bus high impedance
2.5
9.5
ns
tPHZ1
Output disable time OEn to Bus high impedance
2.5
9.5
ns
tPZL22
Output enable time T/Rn to Bus
2.5
13
ns
tPZH22
Output enable time T/Rn to Bus
2.5
13
ns
tPLZ22
Output disable time T/Rn to Bus high impedance
1.5
15
ns
tPHZ22
Output disable time T/Rn to Bus high impedance
1.5
15
ns
tSKEW3
Skew between outputs
-
1.0
ns
tDSKEW4
Differential skew between outputs
-
1.25
ns
tSKEWPP3,5
Part-to-Part output skew
500
ps
Notes:
1. All specifications valid for radiation dose  1E5 rad(Si) per MIL-STD-883, Method 1019.
2. T/Rn to bus times are guaranteed by design, but not tested. OEx to bus times are tested
3. Output skew is defined as a comparison of any two output transitions high-to-low vs. high-to-low and low-to-high vs low-to-high.
4. Differential skew is defined as a comparison of any two output transitions high-to-low vs. low-to-high and low-to-high vs high-to low.
5. Guaranteed by characterization, but not tested.
7
Propagation Delay
Input
tPLH
3.0V
1.5V
0V
tPHL
VOH
VDD/2
VOL
Output
Enable Disable Times
Control Input
5V Output
Normally Low
5V Output
Normally High
tPZLn
tPLZn
.2VDD + .2V
VDD/2-0.2
tPHZN
tPZHn
VDD/2+0.2
.8VDD - .2V
3.0V
1.5V
0V
VDD/2
.2VDD
.8VDD
VDD/2
Bounce Noise
VOH
Active Outputs
VOL
Quiet Outputs
Under Test
VOHP
VOLP
VOH
VOL
VOLV
VOHV
Test Load or Equivalent1
VDD
VDD
100ohms
40pf
100ohms
VSS
Notes
1. Equivalent test circuit means that DUT performance will be correlated and remain guaranteed to the applicable test circuit, above, whenever a test platform
change necessitates a deviation from the applicable test circuit.
8
PACKAGE
NOTE:
1. Seal ring is connected to VSS.
2. Units are in inches.
3. All exposed metalized areas must be gold plated 100 to 225 microinches thick. Dyer electroplated nickel
undercoating 100 to 350 microinches per MIL-PRF-38535.
Figure 1. 48-Lead Flatpack
9
ORDERING INFORMATION
UT54ACTQ16245: SMD
5962 R 06244 **
*
*
*
Lead Finish: (NOTES 1 & 2)
(A) = Hot solder dip
(C) = Gold
(X) = Factory option (gold or solder)
Case Outline:
(X) = 48 lead BB FP (Gold only)
Class Designator:
(Q) = Class Q
(V) = Class V
Device Type
(01) = 16-bit Bi-Directional Transceiver (4.5V - 5.5V)
Drawing Number: 06244
Total Dose: (NOTE 3)
(R) = 1E5 rad(Si)
Federal Stock Class Designator: No options
Notes:
1. Lead finish (A,C, or X) must be specified.
2. If an “X” is specified when ordering, part marking will match the lead finish and will be either “A” (solder) or “C” (gold).
3.Total dose radiation must be specified when ordering. QML Q not available without radiation hardening.
10
UT54ACTQ16245
UT54 *** ****** -* * *
Lead Finish: (NOTES 1 & 2)
(A)
= Hot Solder Dip
(C)
= Gold
(X)
= Factory Option (Gold or Solder)
Screening: (NOTES 3 & 4)
(C) = Mil Temp
(P)
= Prototype
Package Type:
(U) = 48-lead BB FP
Part Number:
(16245) = 16-bit Bi-Directional Transceiver
I/O Type:
(ACTQ)=
CMOS compatible I/O Level
Aeroflex Core Part Number
Notes:
1. Lead finish (A, C, or X) must be specified.
2. If an “X” is specified when ordering, then the part marking will match the lead finish and will be either “A” (solder) or “C” (gold).
3. Prototype flow per Aeroflex Manufacturing Flows Document. Tested at 25C only. Lead finish is Gold "C" only. Radiation neither tested nor guaranteed.
4. Military Temperature Range flow per Aeroflex Manufacturing Flows Document. Devices are tested at -55C, room temp, and 125C. Radiation neither
tested nor guaranteed.
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Aeroflex Colorado Springs - Datasheet Definition
Advanced Datasheet - Product In Development
Preliminary Datasheet - Shipping Prototype
Datasheet - Shipping QML & Reduced Hi-Rel
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Aeroflex Colorado Springs, Inc., reserves the right to make
changes to any products and services herein at any time
without notice. Consult Aeroflex or an authorized sales
representative to verify that the information in this data sheet
is current before using this product. Aeroflex does not assume
any responsibility or liability arising out of the application or
use of any product or service described herein, except as
expressly agreed to in writing by Aeroflex; nor does the
purchase, lease, or use of a product or service from Aeroflex
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trademark rights, or any other of the intellectual rights of
Aeroflex or of third parties.
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