UT7R2XLR816 Clock Network Manager

Standard Products
UT7R2XLR816 Clock Network Manager
Datasheet
April, 2015
www.aeroflex.com/Clocks
FEATURES:
+3.3V Core Power Supply
Independent power supply for each clock bank
Temperature range:
- Commercial: 0oC to +70oC
- Industrial: -40oC to +85oC
- HiRel: -55oC to +125oC
 Operational environment:
- Power supply range from +2.25V to +3.6V
8 Output clock banks with flexible I/O signaling
- Up to 16 LVCMOS3.3 outputs with
12mA slew-rate limited, break-before-make, buffers, or
- Up to 16 LVCMOS2.5 outputs with
8mA slew-rate limited, break-before-make, buffers, or
- Up to 8 standard drive LVDS outputs
- Total-dose: 100 krad (Si)
- SEL Immune to a LET of 109 MeV-cm2/mg
- SEU Immune to a LET of 109 MeV-cm2/mg
Packaging options (1.27mm pitch, 17mm sq. body):
- 168-CLGA
- 168-CBGA
- 168-CCGA
Input clock multiplication of any integer from 1 - 32
PLL Operation
- Low frequency range: 24MHz to 50MHz
- Mid frequency range: 48MHz to 100MHz
- High frequency range: 96MHz to 200MHz
 Standard Microcircuit Drawing 5962-08243
- QML Q and Q+
Applications
- High altitude avionics
- X-ray Cargo Scanners
- Test and Measurement
- Networking, telecommunications and mass storage
Input reference clock signaling and control:
- LVCMOS3.3/LVTTL (Cold-Spared),
LVDS (Cold-Spared), &
Parallel Resonant Quartz Crystal
- Reference input divide-by-1 or divide-by-2
- Input frequency range from 2MHz to 200MHz
Dedicated feedback Input/Output module
- Independent feedback power supply (+3.0V to +3.6V)
- 1-to-32 divider options with/without inverting
- Phase control -6, -4, -3, -2, -1, 0, 1, 2, 3, 4, 6 tU
- Disabled HIGH-Z when RST/DIV = LOW
- No Synchronous Output Enable (sOE) control in order to maintain PLL lock
INTRODUCTION:
The UT7R2XLR816 is a low voltage, low power, clock network
manager. The device features 16-outputs in 8 banks of 2.
Independent power supplies for each bank (+2.25V to +3.6V)
give the user great flexibility in multi- voltage systems. Outputs
can be configured as LVCMOS (2.5V/8mA or 3.3V/12mA) or
standard LVDS pairs. Independent output bank division and
phase skewing empower the system designer to optimize output
phase and frequency relationships throughout a clock network.
Output clock bank signaling and control:
- Output frequency range from 750KHz to 200MHz
- 1-to-32 divider options with/without inverting
- Odd bank phase control -4, -3, -2, -1, 0, 1, 2, 3, 4 tU
- Even bank phase control -6, -4, -2, -1, 0, 1, 2, 4, 6 tU
- Disable HIGH, LOW, or HIGH-Z
- Synchronous Output Enable (sOE) control
The skew controls enable outputs to lead or lag the reference
clock while the ternary output divider control can divide the
PLL oscillator frequency by any integer from 1to 32 before
driving the clock out of the desired bank. Regardless of output divider
settings, input and output clock edges are synchronized at start-up and
whenever the device is removed from power down mode. Power
down mode is controlled by the RST/DIV ternany input which also
controls input division of the reference clock. Time units for skew
control (tU) are 22.5o of the clock cycle for low and mid frequency
Guaranteed reference input to output edge
synchronization
Low inherent output bank skew (e.g. SKEW = 0*tU)
- < 50ps intrabank skew (typical)
- < 100ps interbank skew without dividing or inverting (typ)
- < 250ps interbank skew across divided or inverted banks (typ)
oscillators and 45o of the clock cycle for the high frequency oscillator.
1
Clock outputs are deterministic in that if either the reference input
clock or feedback clock are absent, the outputs will oscillate at a frequency near the midpoint of the selected PLL operating range.
Test modes are available for user diagnostics. The TEST ternary input
enables the test modes. When TEST is low, normal operation occurs.
Floating the TEST pin to a mid-range value disables the PLL oscillators and drives the clock output banks with the REF clock input. Setting TEST high disables the PLL oscillators and drives the clock
output banks with the FB_IN input.
Slew rate optimization of outputs is determined by the PLL oscillator
range selected and thus is controlled by the FREQ_SEL input. Output
rise times decrease as higher frequency range oscillators are selected.
The input reference clock can be LVCMOS/LVTTL/ LVDS or a
quartz crystal. The LVCMOS/LVTTL and LVDS inputs are coldspared. Input reference frequencies can range from 2MHz to
200MHz. Using the RST/DIV pin and FB_DS[3:0] feedback divider
settings for the reference clock can be multiplied by 0.5x-32x in steps
of 0.5 through a multiplication factor of 16 and integer steps for multiplication factors 17 through 32.
To provide further clock network optimization, the feedback
output bank includes independent skew and division control.
PLL lock is identified by the active high LOCK signal. LOCK will
only become true when the REFERENCE and FB_IN clocks are stable and aligned to within tLOCKRES, which is variable based on the
state of the FREQ_SEL pin. At all other times, LOCK will remain
LOW.
2
M6
M5
L5
M4
0Q_DS3
0Q_DS2
0Q_DS1
0Q_DS0
M2
L3
0Q_PS1
0Q_PS0
K6
L7
K8
L8
1Q_DS3
1Q_DS2
1Q_DS1
1Q_DS0
L6
K5
1Q_PS1
1Q_PS0
K10
L10
L11
M10
2Q_DS3
2Q_DS2
2Q_DS1
2Q_DS0
M9
L9
2Q_PS1
2Q_PS0
H11
F10
F11
G11
3Q_DS3
3Q_DS2
3Q_DS1
3Q_DS0
H12
J11
3Q_PS1
3Q_PS0
E11
C12
D11
F12
4Q_DS3
4Q_DS2
4Q_DS1
4Q_DS0
L12
J10
4Q_PS1
4Q_PS0
D8
C11
C9
B9
5Q_DS3
5Q_DS2
5Q_DS1
5Q_DS0
D10
C10
5Q_PS1
5Q_PS0
B10
C7
B4
D6
6Q_DS3
6Q_DS2
6Q_DS1
6Q_DS0
C8
B8
6Q_PS1
6Q_PS0
C5
C3
D7
B5
7Q_DS3
7Q_DS2
7Q_DS1
7Q_DS0
B6
C6
7Q_PS1
7Q_PS0
2-Lvl
2-Lvl
2-Lvl
2-Lvl
2-Lvl
3-Lvl
(R-Divider)
Reference
Clock
Select
Phase –
Frequency
Detector
CTRL
VCO
PLL
24MHZ – 200MHz
K4
FB_PS2
J4
K3
FB_PS1
FB_PS0
FB_DS3
3-Lvl
3-Lvl
3-Lvl
Divide by 1-to-32
& Invert
3-Lvl
3-Lvl
Bank 1 Clock Control
3-Lvl
Phase Select
3-Lvl
3-Lvl
3-Lvl
Divide by 1-to-32
& Invert
3-Lvl
3-Lvl
Bank 2 Clock Control
3-Lvl
Phase Select
3-Lvl
3-Lvl
3-Lvl
Divide by 1-to-32
& Invert
3-Lvl
3-Lvl
Bank 3 Clock Control
3-Lvl
Phase Select
3-Lvl
3-Lvl
3-Lvl
Divide by 1-to-32
& Invert
3-Lvl
3-Lvl
Bank 4 Clock Control
3-Lvl
Phase Select
3-Lvl
3-Lvl
3-Lvl
Divide by 1-to-32
& Invert
3-Lvl
3-Lvl
Bank 5 Clock Control
3-Lvl
Phase Select
3-Lvl
3-Lvl
3-Lvl
Divide by 1-to-32
& Invert
3-Lvl
3-Lvl
Bank 6 Clock Control
3-Lvl
Phase Select
3-Lvl
3-Lvl
3-Lvl
Divide by 1-to-32
& Invert
3-Lvl
3-Lvl
Bank 7 Clock Control
3-Lvl
Phase Select
3-Lvl
3
J1
J2
H3
FB_DS2
LVCMOS
3-Lvl
3-Lvl
Divide by 1-to-32
& Invert
3-Lvl
3-Lvl
Bank 0 Clock Control
3-Lvl
Phase Select
3-Lvl
Figure 1. UT7R2XLR816 Block Diagram
FB_OUT
L2
3-Lvl
Phase Select
REF
LVDIN+_
LVDIN-_
XTAL_IN
XTAL_OUT
REF_SEL
Feedback
Output
G1
C1
D1
M1
L1
F3
K2
3-Lvl
R-Div
FB_DS1
RST#
FB_DS0
TEST
3-Lvl
H1
3-Lvl
RST#/DIV
(N-divider)
Divide by
1-to-32
& Invert
B2
FREQ_SEL
2-Lvl
K11
FB_IN
F2
3-Lvl
LVCMOS/
LVDS
DRIVERS
3-Lvl
3-Lvl
N8
1Q1
N7
2Q0
N12
2Q1
N11
3Q0
J13
3Q1
K13
4Q0
D13
4Q1
E13
5Q0
A11
5Q1
A12
6Q0
A7
6Q1
A8
7Q0
A3
7Q1
A4
2-Lvl
3-Lvl
LVCMOS/
LVDS
DRIVERS
3-Lvl
3-Lvl
1Q0
2-Lvl
3-Lvl
LVCMOS/
LVDS
DRIVERS
3-Lvl
3-Lvl
N3
2-Lvl
3-Lvl
LVCMOS/
LVDS
DRIVERS
3-Lvl
3-Lvl
0Q1
2-Lvl
3-Lvl
LVCMOS/
LVDS
DRIVERS
3-Lvl
3-Lvl
N4
2-Lvl
3-Lvl
LVCMOS/
LVDS
DRIVERS
3-Lvl
3-Lvl
0Q0
2-Lvl
3-Lvl
LVCMOS/
LVDS
DRIVERS
3-Lvl
3-Lvl
D4
2-Lvl
3-Lvl
LVCMOS/
LVDS
DRIVERS
3-Lvl
3-Lvl
LOCK
2-Lvl
sOE#
D9
CM#/LV
H10
1.0 Functional Description
The UT7R2XLR816, clock network manager, has an array of
special features designed to overcome many of the clock
management and clock distribution challenges common in
today’s high-performance electronic systems. This section of
the datasheet provides an overview of the primary features
within and is intended to acquaint the designer with their basic
capabilities.
The UT7R2XLR816 provides a ternary reference select
pin (REF_SEL) that is used to control which of the three
available clock sources the UT7R2XLR816 will use as its
timing reference. Since REF_SEL ensures that only one
reference source can drive the internal circuitry of the
UT7R2XLR816 the remaining two clock sources may be
driven simultaneously allowing the REF_SEL pin to
select between these reference sources. As mentioned
above, REF_SEL is a ternary, or three level input. Setting
REF_SEL L(ow) selects the XTAL_IN/XTAL_OUT
crystal resonator source. Placing REF_SEL into a M(id)
level (left floating), sets the REF input as the
UT7R2XLR816 reference clock source. Finally, driving
REF_SEL H(igh), enables the LVDS (LVDIN+/LVDIN-)
clock source. These available REF_SEL configurations
are shown in figures 2, 3 and 4.
Although discussed in more detail below, the user should
understand that many features within the UT7R2XLR816 are
selected by ternary control signals. These ternary controls
recognize three separate logic levels on a single pin. The
L(ow) state means that the control input pin is driven below
the VILL level specified in the DC electrical table of this
datasheet. Conversely, a H(igh) means that the control input is
driven above the VIHH voltage described in the DC electrical
table. While a M(id) state requires that the input pin be floated,
allowing the internal resistor divider network to place the pin
into a level compliant with the VIMM voltage listed in the DC
1.2 Feedback Clock
The UT7R2XLR816 contains a dedicated feedback I/O
module that is completely separate from the eight (8)
output clock banks. The FB_IN feedback input can be
driven directly from the FB_OUT pin, or from a digital
circuit having the FB_OUT pin as its source.
electrical table, or externally driven/biased to the VIMM level.
1.1 Reference Clocks
The UT7R2XLR816 is capable of receiving its reference
clock from one of three sources. The REF input allows for
a single ended, LVTTL/LVCMOS clock source. The
LVDIN+ and LVDIN- pins combine to receive an LVDS
reference clock. The LVDIN+ should be driven by the
positive half of the LVDS clock signal while the LVDINshould be driven by the negative half of the LVDS clock
signal. A 100 terminating resistor should be connected
directly between the LVDIN+ and LVDIN- terminals.
Finally, the XTAL_IN and XTAL_OUT terminals
provide for a quartz crystal resonator reference clock
input. The XTAL_IN pin is the input to the on-chip pierce
oscillator and should be connected directly to one side of
an external quartz crystal that is tuned to operate in the
parallel resonance mode. The XTAL_OUT pin drives out
the 180° phase shifted version of the reference clock
received on XTAL_IN. The XTAL_OUT pin should drive
the other end of the external quartz crystal resonator
circuit. Reference figure 3 for an example quartz crystal
oscillator circuit.
The FB_IN signal connects to the internal PhaseFrequency Detector (PFD), which compares the FB_IN
signal with the clock reference source as selected by the
REF_SEL control. Phase shifts associated with board
trace delays from routing, in-line circuitry, or intentional
phase skewing within the feedback path are adjusted by
the PFD to advance or delay the Phase-Locked Loop
(PLL), as necessary, to ensure that the clock arriving at
FB_IN is phase aligned with the selected reference clock
source.
The FB_OUT is an LVCMOS3 output signal driven by
the PLL. As discussed in Tables 1 and 2, the frequency
and phase of the FB_OUT signal may be adjusted by the
FB_DS[3:0] output divider settings and the FB_PS[2:0]
phase selection settings, respectively. Both pin groups,
FB_DS[3:0] and FB_PS[2:0], are ternary inputs. The
FB_DS[3:0] settings are used to multiply the frequency of
the internal PLL by dividing the frequency of the
FB_OUT signal.
The REF, LVDIN+ and LVDIN- inputs are cold-spared.
The cold-sparing capability of these reference pins make
them ideal for receiving an off-board clock source that
may be active while the UT7R2XLR816 is unpowered.
FB_OUT may be divided by any integer from 1 to 32, aswell-as inverted following the division operation.
Inversion provides a 180° phase shift of the PLL from the
4
incoming reference source, effectively synchronizing the
PLL to the opposite edge of the reference clock. To ensure
stable locking of the PLL and to free the output clock
banks to drive the system clock, FB_OUT should always
be used as the originating clock source for the FB_IN pin.
frequency of operation in the event that either one, or
both, of the reference and feedback clocks are removed or
drop to a frequency below fREFDET. The intent of this
feature is to ensure that the PLL demonstrates
deterministic behavior if the device is out of reset and the
PFD does not receive valid, stable, input clocks. By
controlling the active VCO when the PFD does not have a
valid set of input clocks to compare ensures that any
active output clock bank oscillates at a manageable
frequency for downstream electronics. It is also
recommended that the sOE pin be used in conjunction
with the UT7R2XLR816 startup by disabling the output
banks until the device has completed its PLL locktime
(tLOCK) and the LOCK output is stable high.
The FB_PS[2:0] feedback phase selection pins allow the
FB_OUT signal to be phase shifted by -6, -4, -3, -2, -1, 0,
1, 2, 3, 4, or 6 tu (time units). The value of tu is
determined by the FREQ_SEL setting and the PLL’s
operating frequency. Examples of tu calculation are
shown in Equation 1 and Table 5. Phase shifting FB_OUT
has the effect of advancing or delaying the PLL and, by
extension, the nominal phase of all output clock banks. A
positive phase shift (i.e. delay) in FB_OUT advances the
PLL and clock output banks so they lead the reference
clock by the same phase shift amount. Conversely, a
negative shift (i.e. advancement) of FB_OUT causes the
PLL and output clock banks to lag the reference clock
source by the same amount of phase shift.
When valid, stable, reference and feedback clocks are
available to the PFD, it will override the pre-charge
circuitry and begin to control the VCO. Although the PFD
works to maintain frequency and phase alignment
between the reference and FB_IN to an ideal 0ns
difference, it will inform the user that the PLL is locked
onto the incoming clocks when they are phase aligned to
within 2ns (typical) for the low and mid VCO selections,
and within 1.5ns (typical) for the high VCO. When this
condition is met, the UT7R2XLR816 will drive the LOCK
output high, indicating to the system the PLL is locked.
When the LOCK pin is LOW, the PLL is not locked and
the clock outputs may not be stable or synchronized to the
reference clock source. The LOCK will de-assert LOW
when the reference clock and the FB_IN are separated by
greater than the defined alignments, unless the device is
reset.
1.3 Phase-Locked Loop (PLL) and Frequency Generation
The UT7R2XLR816’s PLL circuitry consists of the
previously mentioned reference and feedback input clock
sources, a Phase–Frequency Detector (PFD), and a
Voltage-Controlled Oscillator (VCO). The voltage
controlled oscillator consists of three separate oscillators
that are optimized to run in three specific frequency
bands. The ternary FREQ_SEL input is used to select the
appropriate VCO based upon the nominal PLL frequency
required by the application. The nominal PLL frequency
range selected by FREQ_SEL are 24 – 50MHz
(FREQ_SEL=Low), 48 – 100MHz (FREQ_SEL=Mid)
and 96 – 200MHz (FREQ_SEL=High).
The UT7R2XLR816 includes an internal reset signal to
ensure that the selected VCO starts-up and the PLL
establishes lock with the stable reference clock sources
whenever power is applied to the device, or the device is
dynamically reconfigured to select a different VCO.
However, Aeroflex recommends that dynamic
reconfiguration be performed while the device is held in
RESET (e.g. RST/DIV=Low) to ensure a smooth re-start
and avoid uncontrolled behavior from the device during
the reconfiguration process.
An additional start-up feature provided by the
UT7R2XLR816 is the inclusion of a PLL pre-charge
circuit that places the selected VCO into a mid-band
5
2.0 DEVICE CONFIGURATION:
Table 2: Feedback Bank or Output Bank Phase Select
Setting1
Table 1: Output Divider Settings
FB (N-factor) & Bank 0Q through Bank 7Q (MnQ-factor)
FB_PS
[2:0]
Skew
FB
nQ_PS
[1:0]
Skew
EVEN
Banks
Skew
ODD
Banks
LLL
-6tU
LL
-6tU
-4tU
25+INV
LLM
-4tU
LM
-4tU
-3tU
HLML
26+INV
LLH
-3tU
LH
-2tU
-2tU
32
HLMM
27+INV
LML
-2tU
ML
-1tU
-1tU
MLMH
1+INV
HLMH
28+INV
LMM
-1tU
MM
7
MLHL
2+INV
HLHL
29+INV
LMH
Zero Skew
MH
+1tU
+1tU
LLHM
8
MLHM
3+INV
HLHM
30+INV
LHL
+1tU
HL
+2tU
+2tU
LLHH
9
MLHH
4+INV
HLHH
31+INV
LHM
+2tU
HM
+4tU
+3tU
LMLL
10
MMLL
5+INV
HMLL
32+INV
LHH
11
MMLM
6+INV
HMLM
Note 1
+3tU
HH
LMLM
+6tU
+4tU
LMLH
12
MMLH
7+INV
HMLH
Note 1
MLL
+4tU
LMML
13
MMML
8+INV
HMML
Note 1
MLM
+6tU
LMMM
14
MMMM
9+INV
HMMM
Note 1
MLH
Note 2
LMMH
15
MMMH
10+INV
HMMH
Note 1
MML
Note 2
LMHL
16
MMHL
11+INV
HMHL
Note 1
MMM
Note 2
LMHM
17
MMHM
12+INV
HMHM
Note 1
MMH
Note 2
LMHH
18
MMHH
13+INV
HMHH
Note 1
MHL
Note 2
Note 2
19
MHLL
14+INV
HHLL
DIS_LO
Note 2
MHM
LHLL
MHH
Note 2
LHLM
20
MHLM
15+INV
HHLM
Note 1
HLL
Note 2
LHLH
21
MHLH
16+INV
HHLH
DIS_HI
Note 2
HLM
Note 2
HLH
Note 2
LHML
22
MHML
17+INV
HHML
Note 1
HML
Note 2
LHMM
23
MHMM
18+INV
HHMM
Note 1
HMM
Note 2
LHMH
24
MHMH
19+INV
HHMH
Note 1
HMH
Note 2
LHHL
25
MHHL
20+INV
HHHL
Note 1
HHL
Note 2
LHHM
26
MHHM
21+INV
HHHM
Note 1
HHM
Note 2
HHHH
HI-Z
Note 2
HHH
Note 2
DS[3:0]
Output
Divider
DS[3:0]
Output
Divider
DS[3:0]
Output
Divider
LLLL
1
MLLL
28
HLLL
23+INV
LLLM
2
MLLM
29
HLLM
24+INV
LLLH
3
MLLH
30
HLLH
LLML
4
MLML
31
LLMM
5
MLMM
LLMH
6
LLHL
LHHH
27
MHHH
22+INV
Zero Skew Zero Skew
Notes:
1. Skew accuracy is within +/- 300ps of n*tU where "n" is the selected number
of skew steps.
2. These skew settings are for engineering modes only and will default to the
ZERO SKEW state when selected by a user.
Notes:
1. These DS[3:0] settings are for engineering modes only and will default to the
DS[3:0] = LLLL state when selected by a user.
2. These DS[3:0] settings are not available on the FB_OUT clock. If selected
by the user, the FB_OUT clock will default to the DS[3:0] = LLLL state.
6
2.1 Reference Clock Interface
Table 3: Calculating Output Frequency Settings 1, 2
Output Frequency
PLL Operating
Frequency
(fPLL)
FB_OUT
nQ[1:0]
(N/R) * fREFERENCE
(1/N) * fPLL
(1/MnQ) * fPLL
LVCMOS3.3 /
LVTTL
Clock
N/C
Notes:
1. Reference Table 1 for N-factor and MnQ-factor. Reference RST/DIV pin description for R-factor.
2. The N-factor, R-factor, and Reference frequency should be selected such that
the PLL oscillates within a range defined by the Frequency Selection shown
in Table 4.
REF_SEL
Figure 2. LVCMOS3.3/LVTTL
Reference Clock Interface
Table 4: Frequency Range Select
FREQ_SEL
REF
C2
XTAL_IN
Nominal PLL
Frequency Range (fPLL)
Y1
RDC
C1
L
XTAL_OUT
24 MHz to 50 MHz
M
48 MHz to 100 MHz
H
L1
CDC
96 MHz to 200 MHz
REF_SEL
Optional L-C
Tank Circuit
Selectable output skew is in discrete increments of time unit
(tU). The value of tU is determined by the FREQ_SEL setting
and the PLL’s operating frequency (fPLL). Use the following
equation to calculate the time unit (tU):
Equation 1.
R1
Figure 3. Parallel Resonant Crystal
Reference Interface
LVDIN+
LVDS
Driver
t =
1
u (f
PLL * MF)
100
LVDINVDD_C
REF_SEL
The fPLL term, which is calculated with the help of Table 3,
must be compatible with the nominal frequency range selected
by the FREQ_SEL signal as defined in Table 4. The multiplication factor (MF), also determined by FREQ_SEL, is shown in
Table 5. The UT7R2XLR816 output skew steps have a typical
accuracy of +/- 300ps of the calculated time unit (tU).
Figure 4. LVDS Reference Clock Interface
Table 5: MF Calculation
FREQ_SEL
MF
fPLL examples that result
in a tU of 1.0ns
L
32
31.25 MHz
M
16
62.5 MHz
H
8
125 MHz
7
3.0 OPERATIONAL ENVIRONMENT
Table 6: Operational Environment Design Specifications
Parameter
Limit
Units
min = none
max = 1E5
rads(Si)
Single Event Latchup (SEL) 1, 2
>109
MeV-cm2/mg
Onset Single Event Upset (SEU) LET Threshold 3
>109
MeV-cm2/mg
Onset Single Event Transient (SET) LET Threshold 4
@ 50 MHz; FREQ_SEL = L
@ 24 MHz; FREQ_SEL = L
>60
>50
MeV-cm2/mg
1.0E14
n/cm2
Total Ionizing Dose (TID)
Neutron Fluence
Notes:
1. The UT7R2XLR816 is latchup immune to particle LETs >109 MeV-cm2/mg.
2. Worst case temperature and voltage of TC = +125oC, VDD_A/C = 3.6V, VDD_nQ = 3.6V for SEL.
3. Worst case temperature and voltage of TC = +25oC, VDD_A/C = 3.0V, VDD_nQ = 3.0V for SEU.
4. Worst case temperature and voltage of TC = +25oC, VDD_A/C = 3.0V, VDD_nQ = 2.25V for SET.
8
N
M
L
1
VDD
_C
XTAL
_IN
XTAL
_OUT
2
VSS
_0Q
0Q
_PS1
3
0Q1
4
K
J
H
G
F
E
D
VSS
_C
FB
_OUT
FB
_IN
REF
VSS
_C
VDD
_A
LVD
IN-
LVD
IN+
VDD
_C
FB
_DS0
FB
_DS1
FB
_DS2
VDD
_C
VDD
_C
RST#/
DIV
VDD
_A
VDD
_C
VSS
_C
TEST
VSS
_7Q
VDD
_C
0Q
_PS0
FB
_PS1
VDD
_C
FB
_DS3
VSS
_C
REF
_SEL
VSS
_A
VDD
_C
7Q
_DS2
VDD
_C
7Q0
0Q0
0Q
_DS0
VSS
_C
FB
_PS2
FB
_PS0
VSS
_C
VDD
_C
VDD
_C
VSS
_C
LOCK
VSS
_C
6Q
_DS1
7Q1
5
VDD
_0Q
0Q
_DS2
0Q
_DS1
1Q
_PS0
VDD
_C
VDD
_C
VSS
_C
VDD
_C
VDD
_C
VSS
_C
7Q
_DS3
7Q
_DS0
VDD
_7Q
6
VSS
_1Q
0Q
_DS3
1Q
_PS1
1Q
_DS3
VDD
_C
VSS
_C
VSS
_C
VSS
_C
VDD
_C
6Q
_DS0
7Q
_PS0
7Q
_PS1
VSS
_6Q
7
1Q1
VDD
_C
1Q
_DS2
VDD
_C
VSS
_C
VSS
_C
VSS
_C
VSS
_C
VSS
_C
7Q
_DS1
6Q
_DS2
VDD
_C
6Q0
8
1Q0
VSS
_C
1Q
_DS0
1Q
_DS1
VDD
_C
VSS
_C
VSS
_C
VSS
_C
VSS
_C
5Q
_DS3
6Q
_PS1
6Q
_PS0
6Q1
9
VDD
_1Q
2Q
_PS1
2Q
_PS0
VSS
_C
VDD
_C
VDD
_C
VSS
_C
VDD
_C
VDD
_C
sOE#
5Q
_DS1
5Q
_DS0
VDD
_6Q
10
VDD
_2Q
2Q
_DS0
2Q
_DS2
2Q
_DS3
4Q
_PS0
CM#/
LV
VDD
_C
3Q
_DS2
VDD
_C
5Q
_PS1
5Q
_PS0
6Q
_DS3
VDD
_5Q
11
2Q1
VSS
_C
2Q
_DS1
FREQ
_SEL
3Q
_PS0
3Q
_DS3
3Q
_DS0
3Q
_DS1
4Q
_DS3
4Q
_DS1
5Q
_DS2
VSS
_C
5Q0
12
2Q0
VDD
_C
4Q
_PS1
VDD
_C
VSS
_C
3Q
_PS1
VDD
_C
4Q
_DS0
VSS
_C
VDD
_C
4Q
_DS2
VDD
_C
5Q1
13
VSS
_2Q
VDD
_C
VSS
_3Q
3Q1
3Q0
VDD
_3Q
VSS
_C
VDD
_4Q
4Q1
4Q0
VSS
_4Q
VDD
_C
VSS
_5Q
Figure 5. 168-CLGA Pinout (view looking through top of package)
9
C
B
A
4.0 PIN DESCRIPTION
168 CLGA
Pin No.
Name
I/O
Type
Description
REFERENCE BLOCK
G1
REF
IN
COLD Digital reference clock input.
SPARED This cold spared input should be driven by a single-ended LVTTL/
LVCMOS LVCMOS clock source.
or LVTTL
Because REF_SEL selects which reference clock drives the PLL, this
input may be actively driven when not selected, but it should never be
left floating.
M1
XTAL_IN
IN
CRYSTAL Quartz crystal resonator reference clock input.
This pin is the input to the on-chip pierce oscillator. This input should
be connected to the output of an external quartz crystal that is tuned
to operate in the parallel mode of resonance.
Because REF_SEL selects which reference clock drives the PLL, this
input may be actively driven when not selected, but it should never be
left floating.
L1
XTAL_OUT OUT CRYSTAL Quartz crystal resonator reference clock output.
This pin drives the 180o phase shifted version of the reference signal
received on XTAL_IN. This pin should be connected to the input of
the external quartz crystal resonator circuit.
C1
LVDIN+
IN
COLD Positive LVDS reference clock input terminal.
SPARED This cold spared input should be driven by the positive half of an LVDS
LVDS
clock signal. A 100 terminating resistor should be connected directly
between this terminal and its complement LVDIN-.
Because REF_SEL selects which reference clock drives the PLL, this
input may be actively driven when not selected or left floating in the
fail-safe state.
D1
LVDIN-
IN
COLD Negative LVDS reference clock input terminal.
SPARED This cold spared input should be driven by the negative half of an
LVDS
LVDS clock signal. A 100 terminating resistor should be connected
directly between this terminal and its complement LVDIN+.
Because REF_SEL selects which reference clock drives the PLL, this
input may be actively driven when not selected or left floating in the
fail-safe state.
10
168 CLGA
Pin No.
Name
I/O
F3
REF_SEL
IN
Type
Description
3-LEVEL Reference selection input.
This ternary input selects one of the three user reference sources to
drive the internal PLL.
Note: The input buffers on the reference sources that are NOT selected
by REF_SEL are disabled LOW.
Note: When the device is placed into the reset mode of operation (e.g.
RST/DIV = LOW), the XTAL_IN/XTAL_OUT buffers will remain
enabled if REF_SEL = LOW.
F2
RST/DIV
IN
REF_SEL
Selected Source
LOW
XTAL_IN
MID
REF
HIGH
LVDIN+, LVDIN-
3-LEVEL Reset and reference divider control.
This ternary input operates as a dual function pin that controls the reset
operation and selects the input reference divider. When driven HIGH,
the selected input reference will directly drive the PLL. Allowing this
pin float results in the selected reference source being divided in half
before it drives the PLL.
Holding the pin low during power up and reference clock stabilization
ensures clean UT7R2XLR816 startup that is independent of the
power-up behavior of the reference clock. The pin may also be driven
low at any time to force a reset to the PLL and the output divider
synchronization.
Note: When the device is placed into the reset mode of operation (e.g.
RST/DIV = LOW), the XTAL_IN/XTAL_OUT buffers will remain
enabled if REF_SEL = LOW.
The following table summarizes the operating states controlled by the
RST/DIV pin.
11
RST/DIV
Operating Mode
Input
Reference
Divider
LOW
RESET
N/A
MID
Normal Operation
÷2
HIGH
Normal Operation
÷1
168 CLGA
Pin No.
Name
I/O
Type
Description
FEEDBACK BLOCK
H1
FB_IN
IN
J1
FB_OUT
OUT
COLD
SPARED
LVCMOS
or LVTTL
Feedback input clock source.
This cold spared LVCMOS/LVTTL input can be driven directly from
the FB_OUT pin or from a digital circuit which has the FB_OUT pin
at its source.
LVCMOS Feedback output clock source.
This LVCMOS3.3 output is driven from the PLL. The FB_DS[3:0]
and FB_PS[2:0] inputs determine the divider, inverter, enable/disable,
and phase settings for this output.
The FB_OUT pin should be used as the originating clock source for
the FB_IN pin.
H3
J2
K2
L2
FB_DS3
FB_DS2
FB_DS1
FB_DS0
IN
3-LEVEL Feedback output division selector and controller.
These four ternary inputs are used to control the FB_OUT clock
divider, inverter, and enable control. Table 1 lists the output behavior
resulting from each combination of these pins.
K4
K3
J4
FB_PS2
FB_PS1
FB_PS0
IN
3-LEVEL Feedback output phase selector.
These three ternary inputs are used to control the FB_OUT phase
alignment. Table 2 lists the output phase selections resulting from each
combination of these pins.
12
168 CLGA
Pin No.
Name
I/O
Type
Description
CLOCK BANK 0
N4
0Q0
OUT LVCMOS Bank 0 clock output 0.
This LVCMOS output is driven from the PLL. The 0Q_DS[3:0] and
0Q_PS[1:0] inputs determine the divider, inverter, enable/disable, and
phase settings for this output.
This terminal is enabled as an LVCMOS output when the CM/LV pin
is LOW.
LVDS
Bank 0 positive LVDS output terminal.
This LVDS output is driven from the PLL. The 0Q_DS[3:0] and
0Q_PS[1:0] inputs determine the divider, inverter, enable/disable, and
phase settings for this output. This terminal should drive the positive
LVDS input terminal on the receiving device and is the complement
of the 0Q1 LVDS output terminal.
This terminal is enabled as an LVDS output when the CM/LV pin is
MID or HIGH.
N3
0Q1
OUT LVCMOS Bank 0 clock output 1.
This LVCMOS output is driven from the PLL. The 0Q_DS[3:0] and
0Q_PS[1:0] inputs determine the divider, inverter, enable/disable, and
phase settings for this output.
This terminal is enabled as an LVCMOS output when the CM/LV pin
is LOW.
LVDS
Bank 0 negative LVDS output terminal.
This LVDS output is driven from the PLL. The 0Q_DS[3:0] and
0Q_PS[1:0] inputs determine the divider, inverter, enable/disable, and
phase settings for this output. This terminal should drive the negative
LVDS input terminal on the receiving device and is the complement
of the 0Q0 LVDS output terminal.
This terminal is enabled as an LVDS output when the CM/LV pin is
MID or HIGH.
M6
M5
L5
M4
0Q_DS3
0Q_DS2
0Q_DS1
0Q_DS0
IN
3-LEVEL 0Q bank output division selector and controller.
These four ternary inputs are used to control the 0Q[1:0] output clock
divider, inverter, and enable control. Table 1 lists the output behavior
resulting from each combination of these pins.
M2
L3
0Q_PS1
0Q_PS0
IN
3-LEVEL 0Q bank output phase selector.
These two ternary inputs are used to control the 0Q[1:0] output phase
alignment. Table 2 lists the output phase selections resulting from each
combination of these pins.
N5
VDD_0Q
PWR
POWER
0Q bank power supply.
+2.5V +/-10% or +3.3V +/-0.3V power source.
N2
VSS_0Q
PWR
POWER
0Q bank ground reference supply.
0.0V ground reference source.
13
168 CLGA
Pin No.
Name
I/O
Type
Description
CLOCK BANK 1
N8
1Q0
OUT
LVCMOS Bank 1 clock output 0.
This LVCMOS output is driven from the PLL. The 1Q_DS[3:0] and
1Q_PS[1:0] inputs determine the divider, inverter, enable/disable, and
phase settings for this output.
This terminal is enabled as an LVCMOS output when the CM/LV pin
is LOW or MID.
LVDS
Bank 1 positive LVDS output terminal.
This LVDS output is driven from the PLL. The 1Q_DS[3:0] and
1Q_PS[1:0] inputs determine the divider, inverter, enable/disable, and
phase settings for this output. This terminal should drive the positive
LVDS input terminal on the receiving device and is the complement
of the 1Q1 LVDS output terminal.
This terminal is enabled as an LVDS output when the CM/LV pin is
HIGH.
N7
1Q1
OUT
LVCMOS Bank 1 clock output 1.
This LVCMOS output is driven from the PLL. The 1Q_DS[3:0] and
1Q_PS[1:0] inputs determine the divider, inverter, enable/disable, and
phase settings for this output.
This terminal is enabled as an LVCMOS output when the CM/LV pin
is LOW or MID.
LVDS
Bank 1 negative LVDS output terminal.
This LVDS output is driven from the PLL. The 1Q_DS[3:0] and
1Q_PS[1:0] inputs determine the divider, inverter, enable/disable, and
phase settings for this output. This terminal should drive the negative
LVDS input terminal on the receiving device and is the complement
of the 1Q0 LVDS output terminal.
This terminal is enabled as an LVDS output when the CM/LV pin is
HIGH.
K6
L7
K8
L8
1Q_DS3
1Q_DS2
1Q_DS1
1Q_DS0
IN
3-LEVEL 1Q bank output division selector and controller.
These four ternary inputs are used to control the 1Q[1:0] output clock
divider, inverter, and enable control. Table 1 lists the output behavior
resulting from each combination of these pins.
L6
K5
1Q_PS1
1Q_PS0
IN
3-LEVEL 1Q bank output phase selector.
These two ternary inputs are used to control the 1Q[1:0] output phase
alignment. Table 2 lists the output phase selections resulting from each
combination of these pins.
N9
VDD_1Q
PWR
POWER
1Q bank power supply.
+2.5V +/-10% or +3.3V +/-0.3V power source.
N6
VSS_1Q
PWR
POWER
1Q bank ground reference supply.
0.0V ground reference source.
14
168 CLGA
Pin No.
Name
I/O
Type
Description
CLOCK BANK 2
N12
2Q0
OUT LVCMOS Bank 2 clock output 0.
This LVCMOS output is driven from the PLL. The 2Q_DS[3:0] and
2Q_PS[1:0] inputs determine the divider, inverter, enable/disable, and
phase settings for this output.
This terminal is enabled as an LVCMOS output when the CM/LV pin
is LOW.
LVDS
Bank 2 positive LVDS output terminal.
This LVDS output is driven from the PLL. The 2Q_DS[3:0] and
2Q_PS[1:0] inputs determine the divider, inverter, enable/disable, and
phase settings for this output. This terminal should drive the positive
LVDS input terminal on the receiving device and is the complement
of the 2Q1 LVDS output terminal.
This terminal is enabled as an LVDS output when the CM/LV pin is
MID or HIGH.
N11
2Q1
OUT LVCMOS Bank 2 clock output 1.
This LVCMOS output is driven from the PLL. The 2Q_DS[3:0] and
2Q_PS[1:0] inputs determine the divider, inverter, enable/disable, and
phase settings for this output.
This terminal is enabled as an LVCMOS output when the CM/LV pin
is LOW.
LVDS
Bank 2 negative LVDS output terminal.
This LVDS output is driven from the PLL. The 2Q_DS[3:0] and
2Q_PS[1:0] inputs determine the divider, inverter, enable/disable, and
phase settings for this output. This terminal should drive the negative
LVDS input terminal on the receiving device and is the complement
of the 2Q0 LVDS output terminal.
This terminal is enabled as an LVDS output when the CM/LV pin is
MID or HIGH.
K10
L10
L11
M10
2Q_DS3
2Q_DS2
2Q_DS1
2Q_DS0
IN
3-LEVEL 2Q bank output division selector and controller.
These four ternary inputs are used to control the 2Q[1:0] output clock
divider, inverter, and enable control. Table 1 lists the output behavior
resulting from each combination of these pins.
M9
L9
2Q_PS1
2Q_PS0
IN
3-LEVEL 2Q bank output phase selector.
These two ternary inputs are used to control the 2Q[1:0] output phase
alignment. Table 2 lists the output phase selections resulting from each
combination of these pins.
N10
VDD_2Q
PWR
POWER
2Q bank power supply.
+2.5V +/-10% or +3.3V +/-0.3V power source.
N13
VSS_2Q
PWR
POWER
2Q bank ground reference supply.
0.0V ground reference source.
15
168 CLGA
Pin No.
Name
I/O
Type
Description
CLOCK BANK 3
J13
3Q0
OUT
LVCMOS Bank 3 clock output 0.
This LVCMOS output is driven from the PLL. The 3Q_DS[3:0] and
3Q_PS[1:0] inputs determine the divider, inverter, enable/disable, and
phase settings for this output.
This terminal is enabled as an LVCMOS output when the CM/LV pin
is LOW or MID.
LVDS
Bank 3 positive LVDS output terminal.
This LVDS output is driven from the PLL. The 3Q_DS[3:0] and
3Q_PS[1:0] inputs determine the divider, inverter, enable/disable, and
phase settings for this output. This terminal should drive the positive
LVDS input terminal on the receiving device and is the complement
of the 3Q1 LVDS output terminal.
This terminal is enabled as an LVDS output when the CM/LV pin is
HIGH.
K13
3Q1
OUT
LVCMOS Bank 3 clock output 1.
This LVCMOS output is driven from the PLL. The 3Q_DS[3:0] and
3Q_PS[1:0] inputs determine the divider, inverter, enable/disable, and
phase settings for this output.
This terminal is enabled as an LVCMOS output when the CM/LV pin
is LOW or MID.
LVDS
Bank 3 negative LVDS output terminal.
This LVDS output is driven from the PLL. The 3Q_DS[3:0] and
3Q_PS[1:0] inputs determine the divider, inverter, enable/disable, and
phase settings for this output. This terminal should drive the negative
LVDS input terminal on the receiving device and is the complement
of the 3Q0 LVDS output terminal.
This terminal is enabled as an LVDS output when the CM/LV pin is
HIGH.
H11
F10
F11
G11
3Q_DS3
3Q_DS2
3Q_DS1
3Q_DS0
IN
3-LEVEL 3Q bank output division selector and controller.
These four ternary inputs are used to control the 3Q[1:0] output clock
divider, inverter, and enable control. Table 1 lists the output behavior
resulting from each combination of these pins.
H12
J11
3Q_PS1
3Q_PS0
IN
3-LEVEL 3Q bank output phase selector.
These two ternary inputs are used to control the 3Q[1:0] output phase
alignment. Table 2 lists the output phase selections resulting from each
combination of these pins.
H13
VDD_3Q
PWR
POWER
3Q bank power supply.
+2.5V +/-10% or +3.3V +/-0.3V power source.
L13
VSS_3Q
PWR
POWER
3Q bank ground reference supply.
0.0V ground reference source.
16
168 CLGA
Pin No.
Name
I/O
Type
Description
CLOCK BANK 4
D13
4Q0
OUT LVCMOS Bank 4 clock output 0.
This LVCMOS output is driven from the PLL. The 4Q_DS[3:0] and
4Q_PS[1:0] inputs determine the divider, inverter, enable/disable, and
phase settings for this output.
This terminal is enabled as an LVCMOS output when the CM/LV pin
is LOW.
LVDS
Bank 4 positive LVDS output terminal.
This LVDS output is driven from the PLL. The 4Q_DS[3:0] and
4Q_PS[1:0] inputs determine the divider, inverter, enable/disable, and
phase settings for this output. This terminal should drive the positive
LVDS input terminal on the receiving device and is the complement
of the 4Q1 LVDS output terminal.
This terminal is enabled as an LVDS output when the CM/LV pin is
MID or HIGH.
E13
4Q1
OUT LVCMOS Bank 4 clock output 1.
This LVCMOS output is driven from the PLL. The 4Q_DS[3:0] and
4Q_PS[1:0] inputs determine the divider, inverter, enable/disable, and
phase settings for this output.
This terminal is enabled as an LVCMOS output when the CM/LV pin
is LOW.
LVDS
Bank 4 negative LVDS output terminal.
This LVDS output is driven from the PLL. The 4Q_DS[3:0] and
4Q_PS[1:0] inputs determine the divider, inverter, enable/disable, and
phase settings for this output. This terminal should drive the negative
LVDS input terminal on the receiving device and is the complement
of the 4Q0 LVDS output terminal.
This terminal is enabled as an LVDS output when the CM/LV pin is
MID or HIGH.
E11
C12
D11
F12
4Q_DS3
4Q_DS2
4Q_DS1
4Q_DS0
IN
3-LEVEL 4Q bank output division selector and controller.
These four ternary inputs are used to control the 4Q[1:0] output clock
divider, inverter, and enable control. Table 1 lists the output behavior
resulting from each combination of these pins.
L12
J10
4Q_PS1
4Q_PS0
IN
3-LEVEL 4Q bank output phase selector.
These two ternary inputs are used to control the 4Q[1:0] output phase
alignment. Table 2 lists the output phase selections resulting from each
combination of these pins.
F13
VDD_4Q
PWR
POWER
4Q bank power supply.
+2.5V +/-10% or +3.3V +/-0.3V power source.
C13
VSS_4Q
PWR
POWER
4Q bank ground reference supply.
0.0V ground reference source.
17
168 CLGA
Pin No.
Name
I/O
Type
Description
CLOCK BANK 5
A11
5Q0
OUT
LVCMOS Bank 5 clock output 0.
This LVCMOS output is driven from the PLL. The 5Q_DS[3:0] and
5Q_PS[1:0] inputs determine the divider, inverter, enable/disable, and
phase settings for this output.
This terminal is enabled as an LVCMOS output when the CM/LV pin
is LOW or MID.
LVDS
Bank 5 positive LVDS output terminal.
This LVDS output is driven from the PLL. The 5Q_DS[3:0] and
5Q_PS[1:0] inputs determine the divider, inverter, enable/disable, and
phase settings for this output. This terminal should drive the positive
LVDS input terminal on the receiving device and is the complement
of the 5Q1 LVDS output terminal.
This terminal is enabled as an LVDS output when the CM/LV pin is
HIGH.
A12
5Q1
OUT
LVCMOS Bank 5 clock output 1.
This LVCMOS output is driven from the PLL. The 5Q_DS[3:0] and
5Q_PS[1:0] inputs determine the divider, inverter, enable/disable, and
phase settings for this output.
This terminal is enabled as an LVCMOS output when the CM/LV pin
is LOW or MID.
LVDS
Bank 5 negative LVDS output terminal.
This LVDS output is driven from the PLL. The 5Q_DS[3:0] and
5Q_PS[1:0] inputs determine the divider, inverter, enable/disable, and
phase settings for this output. This terminal should drive the negative
LVDS input terminal on the receiving device and is the complement
of the 5Q0 LVDS output terminal.
This terminal is enabled as an LVDS output when the CM/LV pin is
HIGH.
D8
C11
C9
B9
5Q_DS3
5Q_DS2
5Q_DS1
5Q_DS0
IN
3-LEVEL 5Q bank output division selector and controller.
These four ternary inputs are used to control the 5Q[1:0] output clock
divider, inverter, and enable control. Table 1 lists the output behavior
resulting from each combination of these pins.
D10
C10
5Q_PS1
5Q_PS0
IN
3-LEVEL 5Q bank output phase selector.
These two ternary inputs are used to control the 5Q[1:0] output phase
alignment. Table 2 lists the output phase selections resulting from each
combination of these pins.
A10
VDD_5Q
PWR
POWER
5Q bank power supply.
+2.5V +/-10% or +3.3V +/-0.3V power source.
A13
VSS_5Q
PWR
POWER
5Q bank ground reference supply.
0.0V ground reference source.
18
168 CLGA
Pin No.
Name
I/O
Type
Description
CLOCK BANK 6
A7
6Q0
OUT LVCMOS Bank 6 clock output 0.
This LVCMOS output is driven from the PLL. The 6Q_DS[3:0] and
6Q_PS[1:0] inputs determine the divider, inverter, enable/disable, and
phase settings for this output.
This terminal is enabled as an LVCMOS output when the CM/LV pin
is LOW.
LVDS
Bank 6 positive LVDS output terminal.
This LVDS output is driven from the PLL. The 6Q_DS[3:0] and
6Q_PS[1:0] inputs determine the divider, inverter, enable/disable, and
phase settings for this output. This terminal should drive the positive
LVDS input terminal on the receiving device and is the complement
of the 6Q1 LVDS output terminal.
This terminal is enabled as an LVDS output when the CM/LV pin is
MID or HIGH.
A8
6Q1
OUT LVCMOS Bank 6 clock output 1.
This LVCMOS output is driven from the PLL. The 6Q_DS[3:0] and
6Q_PS[1:0] inputs determine the divider, inverter, enable/disable, and
phase settings for this output.
This terminal is enabled as an LVCMOS output when the CM/LV pin
is LOW.
LVDS
Bank 6 negative LVDS output terminal.
This LVDS output is driven from the PLL. The 6Q_DS[3:0] and
6Q_PS[1:0] inputs determine the divider, inverter, enable/disable, and
phase settings for this output. This terminal should drive the negative
LVDS input terminal on the receiving device and is the complement
of the 6Q0 LVDS output terminal.
This terminal is enabled as an LVDS output when the CM/LV pin is
MID or HIGH.
B10
C7
B4
D6
6Q_DS3
6Q_DS2
6Q_DS1
6Q_DS0
IN
3-LEVEL 6Q bank output division selector and controller.
These four ternary inputs are used to control the 6Q[1:0] output clock
divider, inverter, and enable control. Table 1 lists the output behavior
resulting from each combination of these pins.
C8
B8
6Q_PS1
6Q_PS0
IN
3-LEVEL 6Q bank output phase selector.
These two ternary inputs are used to control the 6Q[1:0] output phase
alignment. Table 2 lists the output phase selections resulting from each
combination of these pins.
A9
VDD_6Q
PWR
POWER
6Q bank power supply.
+2.5V +/-10% or +3.3V +/-0.3V power source.
A6
VSS_6Q
PWR
POWER
6Q bank ground reference supply.
0.0V ground reference source.
19
168 CLGA
Pin No.
Name
I/O
Type
Description
CLOCK BANK 7
A3
7Q0
OUT
LVCMOS Bank 7 clock output 0.
This LVCMOS output is driven from the PLL. The 7Q_DS[3:0] and
7Q_PS[1:0] inputs determine the divider, inverter, enable/disable, and
phase settings for this output.
This terminal is enabled as an LVCMOS output when the CM/LV pin
is LOW or MID.
LVDS
Bank 7 positive LVDS output terminal.
This LVDS output is driven from the PLL. The 7Q_DS[3:0] and
7Q_PS[1:0] inputs determine the divider, inverter, enable/disable, and
phase settings for this output. This terminal should drive the positive
LVDS input terminal on the receiving device and is the complement
of the 7Q1 LVDS output terminal.
This terminal is enabled as an LVDS output when the CM/LV pin is
HIGH.
A4
7Q1
OUT
LVCMOS Bank 7 clock output 1.
This LVCMOS output is driven from the PLL. The 7Q_DS[3:0] and
7Q_PS[1:0] inputs determine the divider, inverter, enable/disable, and
phase settings for this output.
This terminal is enabled as an LVCMOS output when the CM/LV pin
is LOW or MID.
LVDS
Bank 7 negative LVDS output terminal.
This LVDS output is driven from the PLL. The 7Q_DS[3:0] and
7Q_PS[1:0] inputs determine the divider, inverter, enable/disable, and
phase settings for this output. This terminal should drive the negative
LVDS input terminal on the receiving device and is the complement
of the 7Q0 LVDS output terminal.
This terminal is enabled as an LVDS output when the CM/LV pin is
HIGH.
C5
C3
D7
B5
7Q_DS3
7Q_DS2
7Q_DS1
7Q_DS0
IN
3-LEVEL 7Q bank output division selector and controller.
These four ternary inputs are used to control the 7Q[1:0] output clock
divider, inverter, and enable control. Table 1 lists the output behavior
resulting from each combination of these pins.
B6
C6
7Q_PS1
7Q_PS0
IN
3-LEVEL 7Q bank output phase selector.
These two ternary inputs are used to control the 7Q[1:0] output phase
alignment. Table 2 lists the output phase selections resulting from each
combination of these pins.
A5
VDD_7Q
PWR
POWER
7Q bank power supply.
+2.5V +/-10% or +3.3V +/-0.3V power source.
A2
VSS_7Q
PWR
POWER
7Q bank ground reference supply.
0.0V ground reference source.
20
168 CLGA
Pin No.
Name
I/O
Type
Description
MISCELLANEOUS I/O
B2
TEST
IN
3-LEVEL Test controller input.
This ternary input is used to enable the various test modes available
with this device. The following table lists the available test modes:
TEST*
Selected Source
L
Normal Operation
M
REF bypass PLL
H
FB_IN bypass PLL
Note* Whenever TEST does not equal the L state, the internal oscillator will
be held in reset.
K11
FREQ_SEL
IN
3-LEVEL PLL operating frequency range selection.
This ternary input selects the nominal operating frequency range in
which the PLL oscillates.
The following table shows the PLL frequency range selected by this
input.
D9
sOE
IN
FREQ_SEL
Nominal PLL
Frequency Range (fPLL)
L
24 MHz to 50 MHz
M
48 MHz to 100 MHz
H
96 MHz to 200 MHz
LVCMOS Synchronous output enable.
or LVTTL This LVCMOS/LVTTL input synchronously enables/disables the
nQ[1:0] pins. Each clock output that is controlled by the sOE pin is
synchronously enabled/disabled by the individual output clock. When
HIGH, sOE forces all clocks to a LOW level, unless individual clock
banks have been disabled by the nQ_DS [3:0] settings.
21
Name
I/O
H10
CM/LV
IN
Type
Description
3-LEVEL CMOS/LVDS clock bank signaling selector.
This ternary input controls whether nQ[1:0] outputs drive LVCMOS
or LVDS signalling.
The following table shows the output signalling that is selected by this
input.
CM/LV
Banks
168 CLGA
Pin No.
22
HIGH
MID
LOW
0Q
LVDS
LVDS
LVCMOS
1Q
LVDS
LVCMOS
LVCMOS
2Q
LVDS
LVDS
LVCMOS
3Q
LVDS
LVCMOS
LVCMOS
4Q
LVDS
LVDS
LVCMOS
5Q
LVDS
LVCMOS
LVCMOS
6Q
LVDS
LVDS
LVCMOS
7Q
LVDS
LVCMOS
LVCMOS
168 CLGA
Pin No.
Name
I/O
Type
D4
LOCK
OUT
LVCMOS
Description
PLL lock indication signal.
This LVCMOS output informs the system that the PLL is locked onto
the reference and FB_IN clocks. A HIGH state indicates that the PLL
is in a locked condition. A LOW state indicates that the PLL is not
locked and the outputs may not be stable or synchronized to the
reference clock source. As indicated in Table 10.0, AC Electrical
Characteristics for LVCMOS Outputs, the level of phase alignment
between the reference and FB_IN that will cause the LOCK pin to
signal a "LOCKED" condition is dependent upon the frequency range
selected by the FREQ_SEL input.
After the LOCK pin is asserted HIGH, indicating the reference clock
and FB_IN are stable and phase aligned per the above table. The LOCK
pin will de-assert to a LOW state when the Reference and FB_IN clock
separate by more than the above amount. Special conditions apply
when the device is placed in either test or reset mode. When in test
mode, (TEST=MID or HIGH), all ternary inputs are NANDed to drive
the LOCK output. When in reset mode (RST/DIV=LOW, TEST=
LOW), the LOCK output is driven HIGH. These conditions are
summarized in the following table.
RST/DIV
TEST
LOCK
M/H
L
LOCK=HIGH if REF+FB_IN are
aligned. LOCK=LOW otherwise
L
L
HIGH
Don’t Care
M/H
LOCK=HIGH if all ternary inputs
are LOW. LOCK=LOW if any
ternary input is not LOW
23
168 CLGA
Pin No.
Name
I/O
Type
Description
B1, B3, B7, B12, B13,
D2, D3, D12, E5, E6,
E9, E10, F4, F5, F9,
G2, G4, G10, G12, H2,
H5, H9, J3, J5, J6, J8,
J9, K7, K12, M3, M7,
M12, M13, N1
VDD_C
PWR
POWER
Core power supply.
+3.3V +/-0.3V power source. This power supply must be operated at
the same potential as the analog power supply.
B11, C2, C4, D5, E4,
E7, E8, E12, F1, F6,
F7, F8, G3, G5, G6,
G7, G8, G9, G13, H4,
H6, H7, H8, J7, J12,
K1, K9, L4, M8, M11
VSS_C
PWR
POWER
Core ground reference supply.
0.0V ground reference source.
E1, E2
VDD_A
PWR
POWER
Analog power supply.
+3.3V +/-0.3V power source. This power supply must be operated at
the same potential as the core power supply.
E3
VSS_A
PWR
POWER
Analog ground reference supply.
0.0V ground reference source.
24
5.0 ABSOLUTE MAXIMUM RATINGS:1
(Referenced to VSS_A/C/nQ)
Symbol
VDD_C & VDD_A
VDD_0Q through VDD_7Q
Description
Limits
Units
Core Power Supply Voltage
-0.3 to 4.0
V
Output Bank Power Supply Voltage
-0.3 to 4.0
V
VIN_C
Voltage Any Core Input Pin
-0.3 to VDD_C + 0.3
V
VIN_R
Voltage Any Reference Input Pin
-0.3 to VDD_C + 0.3
V
VIN_FB
Voltage FB_IN Input Pin
-0.3 to VDD_C + 0.3
V
VOUT_LVCMOS
Voltage Any Clock Bank Output
-0.3 to VDD_nQ + 0.3
V
VOUT_LVDS
Voltage Any Clock Bank Output
-0.3 to VDD_nQ + 0.3
V
Voltage on XTAL_OUT, FB_OUT, and LOCK Outputs
-0.3 to VDD_C + 0.3
V
+10
mA
5
W
-65 to +150
C
+150
C
5
C/W
750
V
VO
II
DC Input Current
PD 2
Maximum Power Dissipation Permitted @ TC = +125oC
TSTG
Storage Temperature
TJ 3
JC-168CLGA
ESDHBM
Maximum Junction Temperature
Thermal Resistance, Junction to Case (168-CLGA)
ESD Protection (Human Body Model) - Class I
Notes:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device
at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability and performance.
2. Per MIL-STD-883, Method 1012, Section 3.4.1, PD = (TJ(max) - TC(max)) / JC
3. Maximum junction temperature may be increased to +175C during burn-in and steady-static life.
25
6.0 RECOMMENDED OPERATING CONDITIONS
Symbol
Limits
Units
Core and Analog Power Supply Voltage
3.0 to 3.6
V
Output Bank Operating Voltage
2.25 to 3.6
V
Voltage Any Configuration and Control Input
0 to VDD_C
V
VIN_REF
Voltage REF Input
0 to VDD_C
V
VIN_XTAL
Voltage XTAL_IN Input
0 to VDD_C
V
VIN_LVDIN
Voltage LVDS Input
2.4
V
VIN_FB
Voltage FB_IN Input
0 to VDD_C
V
VOUT_LOCK
Voltage LOCK Output
0 to VDD_C
V
VOUT_XTAL
Voltage XTAL_OUT Output
0 to VDD_C
V
Voltage Any LVCMOS Clock Bank Output
0 to VDD_nQ
V
Voltage LVDS Outputs
0.925 to 1.65
V
0 to VDD_C
V
HiRel
-55 to +125
C
Industrial
-40 to +85
C
0 to +70
C
VDD_C & VDD_A
VDD_0Q through VDD_7Q
VIN_CONTROL
VOUT_nQ
VOUT_LVDS
VOUT_FB
TC
Description
Voltage FB_OUT Output
Case Operating Temperature
Commercial
Notes:
1. When configuring an output bank for LVDS drive, the corresponding VDD_NQ range is 3.0 to 3.6V.
26
7.0 DC ELECTRICAL CHARACTERISTICS 3-LEVEL and LVCMOS/LVTTL INPUTS
(VDD_A/C = +3.3V + 0.3V; TC is per the screening level ordered)*
Symbol
Description
Conditions
Min.
Max.
Units
VIH
High-level input voltage
(REF, FB_IN, and sOE)
+2.0
--
V
VIL
Low-level input voltage
(REF, FB_IN, and sOE)
--
+0.8
V
VIHH 1
High-level input voltage
VDD_C - 0.6
--
V
VIMM 1
Mid-level input voltage
(VDD_C/2) - 0.3
(VDD_C/2) + 0.3
V
VILL 1
Low-level input voltage
--
+0.6
V
Ternary Inputs
VIC+
Positive input clamp voltage
(except REF and FB_IN pin)
For input under test: IIN = +18mA;
VDD_A/C = 0.0V
+0.4
+1.5
V
VIC-
Negative input clamp voltage
(all inputs)
For input under test: IIN = -18mA;
VDD_A/C = 0.0V
-1.5
-0.4
V
ICS
Input cold spare leakage
(REF, FB_IN)
For input under test: VIN = +3.6V;
VDD_C = 0.0V +0.3V
-5
+5
A
For input under test:
VIN = +3.6V or 0.0V;
VDD_A/C = +3.6V
Pin: sOE
-1
+1
IIL-2L
Input leakage current on
2-level inputs
Pins: REF, FB_IN
-5
5
HIGH, VIN = VDD_C
--
+200
A
MID, VIN = VDD_C/2
-50
+50
A
LOW, VIN = VSS_C
-200
--
A
I3L 1
3-level input DC current
CIN-2L 2
Input pin capacitance
(2-level inputs)
f = 1MHz @ 0V
CIN-3L 2
Input pin capacitance
(3-level inputs)
f = 1MHz @ 0V

REF, FB_IN
6 (typical)
sOE
9 (typical)
pF
12 (typical)
pF
Notes:
* For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25C per MIL-STD-883 Method 1019, Condition
A up to the maximum TID level procured.
1. These inputs are normally wired to VDD_C, VSS_C, or left unconnected. Internal termination resistors bias unconnected inputs to VDD_C/2 + 0.3V.
2. Capacitance is measured for initial qualification and when design changes may affect the input/output capacitance. Capacitance is measured between the designated
terminal and VSS_C at a frequency of 1MHz and a signal amplitude of 50mV rms maximum.
27
7.1 DC ELECTRICAL CHARACTERISTICS LVDS INPUTS1
(VDD_A/C = +3.3V + 0.3V; TC is per the screening level ordered)*
Symbol
Description
Conditions
ILVDIN
Input leakage current
For input under test VIN = +3.6V or 0.0V; VDD_C = +3.6V
VTH 2
Differential input high threshold
VCM = +1.2V
VTL 2
Differential input low threshold
VCM = +1.2V
Common mode voltage range
VID = 200mV peak-to-peak
ICS
Input cold spare leakage
For input under test VIN = +3.6V; VDD_C = 0.0V
VIC-
Negative input clamp voltage
For Input Under Test: IIN = -18mA
Input pin capacitance
f = 1MHz @ 0V
VCMR 4
CLVDIN 3
Min.
Max.
Units
-15
+15

VCM+0.1
V
VCM-0.1
V
0.1
2.3
V
-5
+5
A
-1.5
-0.4
V
7
pF
Notes:
* For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25C per MIL-STD-883 Method 1019, Condition
A up to the maximum TID level procured.
1. LVDS compatible input pins include: LVDIN+, LVDIN-.
2. Guaranteed by characterization, and functionally tested.
3. Capacitance is measured for initial qualification and when design changes may affect the input/output capacitance. Capacitance is measured between the designated
terminal and VSS_C at a frequency of 1MHz and a signal amplitude of 50mV rms maximum.
4. Guaranteed by characterization, but not tested.
7.2 DC ELECTRICAL CHARACTERISTICS XTAL_IN INPUT
(VDD_A/C = +3.3V + 0.3V; TC is per the screening level ordered)*
Symbol
Description
Conditions
Min.
Max.
Units
VIH
High-level input voltage
0.55 *
VDD_C
--
V
VIL
Low-level input voltage
--
0.35 *
VDD_C
V
-1
+1

Input leakage current
For input under test VIN = +3.6V or 0.0V; VDD_C = +3.6V
VIC+
Positive input clamp voltage
For input under test: IIN = +18mA; VDD_C = 0.0V
+0.4
+1.5
V
VIC-
Negative input clamp voltage
For Input Under test: IIN = -18mA
-1.5
-0.4
V
Input pin capacitance
f = 1MHz @ 0V
IXTAL_IN
CXTAL_IN 1
10
pF
Notes:
* For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25C per MIL-STD-883 Method 1019, Condition
A up to the maximum TID level procured.
1. Capacitance is measured for initial qualification and when design changes may affect the input/output capacitance. Capacitance is measured between the designated
terminal and VSS_C at a frequency of 1MHz and a signal amplitude of 50mV rms maximum.
28
8.0 DC ELECTRICAL CHARACTERISTICS LVCMOS3.3 OUTPUTS1
(VDD_nQ = +3.3V + 0.3V; VDD_A/C = +3.3V + 0.3V; TC is per the screening level ordered)*
Symbol
Description
Conditions
Min.
Max.
TC = Room, Cold
--
0.4
TC = Hot
--
0.6
IOL = 2mA (Pin: LOCK)
--
0.4
V
IOH = -12mA (Pins: nQ[1:0]; FB_OUT)
2.4
--
V
IOH = -2mA (Pin: LOCK)
2.4
--
V
Output three-state
current
nQ1 or nQ0 = 0V or VDD_nQ, VDD_nQ = +3.6V
-10
+10

Output pin capacitance
f = 1MHz @ 0V
IOL = 12mA (Pins: nQ[1:0]; FB_OUT)
VOL
VOH
IOZ
COUT 2
Low-level output voltage
Units
V
High-level output voltage
13
pF
Notes:
* For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25C per MIL-STD-883 Method 1019, Condition
A up to the maximum TID level procured.
1. LVCMOS3.3 compatible output pins include: FB_OUT, LOCK, 0Q[1:0], 1Q[1:0], 2Q[1:0], 3Q[1:0], 4Q[1:0], 5Q[1:0], 6Q[1:0], 7Q[1:0].
2. Capacitance is measured for initial qualification and when design changes may affect the input/output capacitance. Capacitance is measured between the designated
terminal and VSS_nQ at a frequency of 1MHz and a signal amplitude of 50mV rms maximum.
8.1 DC ELECTRICAL CHARACTERISTICS LVCMOS2.5 OUTPUTS1
(VDD_nQ = +2.5V + 10%; VDD_A/C = +3.3V + 0.3V; TC is per the screening level ordered)*
Symbol
Description
VOL
Low-level output voltage
Pins: nQ[1:0]
VOH
High-level output voltage
Pins: nQ[1:0]
Conditions
Min.
Max.
Units
IOL = 6mA; VDD_nQ = +2.25V; VDD_A/C=3.3V
--
0.4
V
IOL = 8mA; VDD_nQ = +2.375V; VDD_A/C=3.3V
--
0.4
V
TC = Room, Cold
2.0
--
TC = Hot
1.9
--
TC = Room, Cold
2.0
--
TC = Hot
1.9
--
IOH = -6mA; VDD_nQ = +2.25V;
VDD_A/C=3.3V
IOH = -8mA; VDD_nQ = +2.375V;
VDD_A/C=3.3V
COUT 2
Output pin capacitance
f = 1MHz @ 0V
V
V
13
pF
Notes:
* For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25C per MIL-STD-883 Method 1019, Condition
A up to the maximum TID level procured.
1. LVCMOS2.5 compatible output pins include: 0Q[1:0], 1Q[1:0], 2Q[1:0], 3Q[1:0], 4Q[1:0], 5Q[1:0], 6Q[1:0], 7Q[1:0].
2. Capacitance is measured for initial qualification and when design changes may affect the input/output capacitance. Capacitance is measured between the designated
terminal and VSS_nQ at a frequency of 1MHz and a signal amplitude of 50mV rms maximum.
29
8.2 DC ELECTRICAL CHARACTERISTICS LVDS OUTPUTS1,2
(VDD_nQ = +3.3V + 0.3V; VDD_A/C = +3.3V + 0.3V; TC is per the screening level ordered)*
Symbol
Description
Conditions
VOL
Low-level output voltage
RL = 100(see figure 9)
VOH
High-level output voltage
RL = 100(see figure 9)
VOD2
Differential output voltage
RL = 100(see figure 9)
VOD2
VOS
Min.
Max.
0.925
V
1.650
V
400
mV
35
mV
1.450
V
25
mV
-10
10
mA
-10
+10

250
Change in magnitude of VOD
RL = 100(see figure 9)
for complementary output states
Offset voltage
Voh + Vol
RL = 100 ,  Vos = ---------------------------
2
Units
1.125
(see figure 9)
VOS
Change in magnitude of VOS for
complementary output states
RL = 100 (see figure 9)
nQ1 or nQ0 = VSS_nQ or VDD_nQ
IOS
Output short circuit current
IOZ
Output three-state current
nQ1 or nQ0 = VSS_nQ or VDD_nQ,
VDD_nQ = +3.6V
Output pin capacitance
f = 1MHz @ 0V
COUT 3
VDD_nQ = +3.6V
13
pF
Notes:
* For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25C per MIL-STD-883 Method 1019, Condition
A up to the maximum TID level procured.
1. LVDS compatible output pins include: 0Q[1:0], 1Q[1:0], 2Q[1:0], 3Q[1:0], 4Q[1:0], 5Q[1:0], 6Q[1:0], 7Q[1:0].
2. All voltages are referenced to VSS except for differential voltages.
3. Capacitance is measured for initial qualification and when design changes may affect the input/output capacitance. Capacitance is measured between the designated
terminal and VSS_nQ at a frequency of 1MHz and a signal amplitude of 50mV rms maximum.
8.3 DC ELECTRICAL CHARACTERISTICS XTAL_OUT OUTPUT
(VDD_A/C = +3.3V + 0.3V; TC is per the screening level ordered)*
Symbol
VOL
VOH
COUT 1
Description
Low-level output voltage
Conditions
Min.
Max.
TC = Room, Cold
--
0.4
TC = Hot
--
0.5
2.4
--
IOL = 16mA
High-level output voltage
IOH = -16mA
Output pin capacitance
f = 1MHz @ 0V
Units
V
15
V
pF
Notes:
* For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25C per MIL-STD-883 Method 1019, Condition
A up to the maximum TID level procured.
1. Capacitance is measured for initial qualification and when design changes may affect the input/output capacitance. Capacitance is measured between the designated
terminal and VSS_C at a frequency of 1MHz and a signal amplitude of 50mV rms maximum.
30
9.0 AC INPUT ELECTRICAL CHARACTERISTICS
(VDD_A/C = +3.3V + 0.3V; TC is per the screening level ordered)*
Symbol
Description
Max.
Unit
Pins: REF, FB_IN
--
20
VTH(min)-VTL(max)
Pins: LVDIN+, LVDIN-
--
20
HIGH or LOW; REF
2
--
ns
Input clock period
1÷fREF
5
500
ns
Ref clock detector
frequency
FREQ_SEL = LOW; RST/DIV = HIGH;
--
100
KHz
FREQ_SEL = LOW; RST/DIV = HIGH
2.0
50
MHz
FREQ_SEL = LOW; RST/DIV = MID
4.0
100
MHz
FREQ_SEL = MID; RST/DIV = HIGH
2.0
100
MHz
FREQ_SEL = MID; RST/DIV = MID
4.0
200
MHz
FREQ_SEL = HIGH; RST/DIV = HIGH
3
200
MHz
FREQ_SEL = HIGH; RST/DIV = MID
6
200
MHz
400
--
ns
Input rise/fall time
tPWC 3,4
Input clock pulse width
tPER 3,5,6,7
fREFDET 8
tRESET
Min.
VIH(min)-VIL(max)
tR, tF 2
fREF 3,5,6
Condition
ns
Reference clock frequency
Reset duration
Reference clock and all control inputs are stable and valid while
RST/DIV is low
Notes:
* For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25C per MIL-STD-883 Method 1019, Condition
A up to the maximum TID level procured.
1. Reference Figure 8 for clock output loading circuit that is equivalent to the load circuit used for all AC testing. The input waveform used to test these parameters
is shown in Figure 7.
2. Characterized in lab through functional testing.
3. Guaranteed by functional testing except where characterized.
4. For REF_SEL = HIGH, this parameter is guaranteed by characterization, but not tested. For REF_SEL=LOW, this parameter is not applicable.
5. Although the input reference frequencies are defined as-low-as 2MHz, the N and R dividers must be selected to ensure the PLL operates from 24MHz-50MHz
when FREQ_SEL = LOW, 48MHz-100MHz when FREQ_SEL = MID, and 96MHz-200MHz when FREQ_SEL = HIGH.
6. XTAL_IN is characterized for crystal operation over VDD_C and temperature corners using 2MHz, 24MHz, 48MHz, and 66.667MHz crystals which were configured
in accordance with figure 3.
7. For REF_SEL = LOW, this parameter is guaranteed by laboratory characterization through functional testing of the XTAL_IN pin with a digital input clock signal
at 2MHz and 62.5MHz in accordance with the test waveform in figure 7C.
8. Maximum REF frequency in which the UT7R2XLR816 will ignore the REF input and place the PLL into a pre-charge oscillator state.
31
10.0 AC ELECTRICAL CHARACTERISTICS FOR LVCMOS OUTPUTS
(VDD_nQ = +2.5V +10% or +3.3V + 0.3V; VDD_A/C = +3.3V + 0.3V; TC is per the screening level ordered)*
Symbol
fOR 6
Description
Condition
Min.
Max.
Unit
0.75
200
MHz
24
200
MHz
-150
+150
ps
(n*tU-300)
(n*tU+300)
ps
--
250
ps
Figure 8B
45
55
Figure 8C (Note 5)
45
55
Figure 8A (Note 5)
45
55
Figure 8B
40
60
Figure 8C (Note 5)
40
60
Figure 8A (Note 5)
40
60
VDD_nQ= 3.3V
Outputs loaded per Fig. 8A
1.5
--
Measured at 0.5* VDD_nQ + 0.5V
VDD_nQ= 2.5V
Outputs loaded per Fig. 8A
1.5
--
fREF=200MHz
VDD_nQ= 3.3V
Outputs loaded per Fig. 8B
1.5
--
VDD_nQ= 2.5V
Outputs loaded per Fig. 8B
1.5
--
VDD_nQ= 3.3V
Outputs loaded per Fig. 8A
2
--
Measured at 0.5* VDD_nQ - 0.5V
VDD_nQ= 2.5V
Outputs loaded per Fig. 8A
2
--
fREF=200MHz
VDD_nQ= 3.3V
Outputs loaded per Fig. 8B
2
--
VDD_nQ= 2.5V
Outputs loaded per Fig. 8B
2
--
--
1.0
ms
Output frequency range
VCOLR 6
VCO lock range
tPD0 2, 5
Reference to FB_IN
propagation delay
VDD_C = +3.3V; TC = Room Temperature
tn*tu7
Accuracy of phase
selection time units
Skew accuracy from any output bank to any output bank
configured to a valid number of skew steps, without division or
inversion.
Part-part skew
Skew between the outputs of any two devices under identical
settings and conditions (VDD_nQ, VDD_A/C, temp, air flow,
frequency, etc).
tPART 5
fout < 100 MHz, measured at
(VDD_nQ)/2
tODCVLVCMOS
5
Output duty cycle
LVCMOS Outputs
fout > 100 MHz, measured at
(VDD_nQ)/2
tPWH 5
tPWL
5
tLOCK 3
tLOCKRES 4,5
Output high time
pulse width
Output low time
pulse width
%
%
ns
ns
PLL lock time
RST/DIV = MID or HIGH to LOCK = STABLE HIGH
LOCK Pin Resolution
Maximum phase
difference between
reference and FB_IN to
maintain LOCK
FREQ_SEL = LOW and MID
0.9
ns
FREQ_SEL = HIGH
0.5
ns
32
Symbol
tORISELVCMOS
5
tOFALLLVCMOS
5
Description
LVCMOS
output rise time
Figure 8A
LVCMOS
output fall time
Figure 8A
Condition
Min.
Max.
Unit
Measured as transition time from
VOL(max) to VOH(min)
for VDD_A/C = 3.3V;
VDD_nQ = 2.25V; CM/LV= LOW
fREF=1MHz
FREQ_SEL=LOW or MID
3.0
ns
FREQ_SEL=HIGH
2.75
ns
Measured as transition time from
VOL(max) to VOH(min)
for VDD_A/C = 3.3V;
VDD_nQ = 3.6V; CM/LV= LOW
fREF=1MHz
FREQ_SEL=LOW or MID
1.25
ns
FREQ_SEL=HIGH
1.0
ns
Measured as transition time from
VOH(min) to VOL(max)
for VDD_A/C = 3.3V;
VDD_nQ = 2.25V; CM/LV= LOW
fREF=1MHz
FREQ_SEL=LOW or MID
2.25
ns
FREQ_SEL=HIGH
2.0
ns
Measured as transition time from
VOH(min) to VOL(max)
for VDD_A/C = 3.3V;
VDD_nQ = 3.6V; CM/LV= LOW
fREF=1MHz
FREQ_SEL=LOW or MID
2.0
ns
FREQ_SEL=HIGH
1.75
ns
Notes:
* For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25C per MIL-STD-883 Method 1019, Condition
A up to the maximum TID level procured.
1. All outputs are equally loaded. See figure 8B.
2. tPD0 is measured at 1.5V for VDD_C = +3.3V with REF rise/fall times of 1ns between 0.8V-2.0V.
3. tLOCK is the time that is required before outputs synchronize to the reference input as determined by the phase alignment between the selected reference and FB_IN.
This specification is valid with stable input reference clock and power supplies that are within normal operating limits.
4. The lock detector circuit will monitor the phase alignment between the selected reference input and FB_IN. When the phase separation between these two inputs
is greater than the amount listed, the LOCK pin will drop low signaling that the PLL is out of lock.
5. Guaranteed by characterization, but not tested.
6. Guaranteed by functional testing.
7. The time unit tU is calculated by equation 1 using the PLL operating frequency (see Table 3) and the multiplication factor determined by the state of the FREQ_SEL
pin (see Table 5). Valid phase selection steps for each output clock bank are identified in Table 2.
33
10.1 AC ELECTRICAL CHARACTERISTICS FOR LVDS OUTPUTS
(VDD_nQ = +3.3V + 0.3V; VDD_A/C = +3.3V + 0.3V; TC is per screening level ordered)*
Symbol
Description
Condition
Min.
Max.
Unit
tn*tu3,4
Accuracy of phase
selection time units
Skew accuracy from FB_OUT to any output bank configured
to a valid number of skew step, without division or inversion.
(n*tU-300)
(n*tU+300)
ps
tPART 2
Part-part skew
Skew between the outputs of any two devices under identical
settings and conditions (VDD_nQ, VDD_A/C, temp, air flow,
frequency, etc).
--
250
ps
fout < 100 MHz, measured at VOS (Figure 10)
48
52
%
fout > 100 MHz, measured at VOS (Figure 10)
45
55
%
tODCV-LVDS2
tORISELVDS
2
tOFALLLVDS
2
Output duty cycle
LVDS Outputs
LVDS
output rise time
Measured as transition time between
20% VDIFF and 80% VDIFF (Figure 10)
CM/LV=HIGH; fREF=1MHz
1.25
ns
LVDS
output fall time
Measured as transition time between
80% VDIFF and 20% VDIFF (Figure 10)
CM/LV=HIGH; fREF=1MHz
1.25
ns
Notes:
* For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25C per MIL-STD-883 Method 1019, Condition
A up to the maximum TID level procured.
1. All outputs are equally loaded. See figure 9.
2. Guaranteed by characterization, but not tested.
3. The time unit tU is calculated by equation 1 using the PLL operating frequency (see Table 3) and the multiplication factor determined by the state of the FREQ_SEL
pin (see Table 5). Valid phase selection steps for each output clock bank are identified in Table 2.
4. Guaranteed by characterization and testing with LVCMOS buffers.
34
11.0 RECOMMENDED QUARTZ CRYSTAL SPECIFICATIONS
(Parallel Resonant Mode; Fundamental and Third Overtone)
Description
Conditions
Fundamental
Min.
Max.
Units
2.0
Frequency range
MHz
Third Overtone
50
Frequency tolerance
User Defined
Frequency to temperature stability
Aging
ppm
-100
+100
ppm
-5
+5
ppm/
year
Load capacitance
Parallel load
10
30
pF
Shunt capacitance
Frequency dependant
--
7
pF
Equivalent series resistance (ESR)
Frequency dependant
25
3000

--
1.0
mW
Drive level
35
12.0 POWER DISSIPATION CHARACTERISTICS
(Unless otherwise noted, VDD_nQ = +2.5V +10% or +3.3V + 0.3V; VDD_A/C = +3.3V + 0.3V; TC is per the screening level ordered)*
Symbol
Description
Conditions
Min.
Max.
Units
IDDRSTC
RESET Core Power
Supply Current
VDD_A/C = +3.6V;
sOE = HIGH; FB_IN = FB_OUT;
REF, LVDIN+, LVDIN-, XTAL_IN,
RST/DIV, FREQ_SEL, & TEST =
LOW;
All other inputs are floated;
Outputs are not loaded
TC = Room, Cold
--
+1.40
mA
TC = Hot
--
+1.40
mA
--
+170
mA
--
+40
VDD_A/C = +3.6V;
SIDD_C
Standby Core Power
Supply Current
sOE, RST/DIV, FREQ_SEL = HIGH;
FB_IN = FB_OUT;
REF, LVDIN+, LVDIN-, XTAL_IN, CM/LV, and
TEST = LOW;
All other inputs are floated; Outputs are not loaded
VDD_A/C = +3.6V;
AIDD_C
AIDD_nQ33
(Notes 1,2)
AIDD_nQ25
(Notes 1,2)
AIDD_CLVDS
(Notes 2,3)
AIDD_nQLVDS
(Notes 2,3)
AIDD_XTAL
(Note 4)
RST/DIV = HIGH;
FB_IN = FB_OUT;
sOE, LVDIN+, LVDIN-, XTAL_IN,
FREQ_SEL,
and TEST = LOW;
All other inputs are floated; Outputs
are not loaded
REF = 2MHz
PLL = 24MHz
REF = 200MHz
PLL = 200MHz
--
290
nQ[1:0] = 24MHz
--
12
Dynamic output bank supply
current
LVCMOS3.3 Outputs
REF = 2MHz and 200MHz;
sOE = LOW; VDD_nQ = +3.6V;
CL = 40pF/output;
nQ[1:0] = 200MHz
--
23
nQ[1:0] = 24MHz
--
8.75
Dynamic output bank supply
current
LVCMOS2.5 Outputs
REF = 2MHz and 200MHz;
sOE = LOW; VDD_nQ = +2.75V; CL
= 40pF/output;
nQ[1:0] = 200MHz
--
17
VDD_A/C = VDD_nQ = +3.6V;
REF = 2MHz
PLL = 24MHz
nQ[1:0] = 24MHz
--
75
Active core power supply
current
Core power supply current
when LVDS output banks
are running
RST/DIV = CM/LV = HIGH;
FB_IN = FB_OUT; sOE,
FREQ_SEL, and TEST = LOW;
All other ternary inputs are floated;
CL = 40pF/output;
RL = 100 Differential
mA
mA/
Bank
mA
REF = 200MHz
PLL = 200MHz
nQ[1:0] = 200MHz
--
340
nQ[1:0] = 24MHz
--
0.5
Dynamic output bank supply
current
LVDS Outputs; CM/LV = HIGH;
VDD_nQ = +3.6V;
CL = 40pF/output; RL = 100
Differential
nQ[1:0] = 200MHz
--
3.5
REF = 2MHz
PLL = 24MHz
--
1.5
Dynamic supply current
from XTAL interface
XTAL_OUT Output
VDD_C = +3.6V; XTAL_IN =
VDD_C to VSS_R; REF_SEL = LOW;
RST/DIV = HIGH
CL = 40pF
36
mA/
Bank
mA/
Bank
mA
REF = 50MHz
PLL = 50MHz
--
2.0
Notes:
* For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25C per MIL-STD-883 Method 1019, Condition
A up to the maximum TID level procured.
1. When measuring the dynamic supply current, all outputs are disconnected from the equivalent test load defined in figure 8B.
2. To reduce power consumption for the device, the user may tie the unused VDD_nQ pins to VSS_nQ.
3. When measuring, use Figure 9.
4. Guaranteed by characterization, but not tested.
37
tPER
tPWC
REF
XTAL_IN
LVDIN+
tPD0
FB_IN &
FB_OUT
Figure 6a. Reference and Feedback Timing Diagrams
38
(tPER - tPWC)
REF
FB_PS
[2:0]
nQ_PS
[1:0]
n=0,2,4,6
nQ_PS
[1:0]
n=1,3,5,7
FB_IN
LLL
LL
N/A
-6tU
LLM
LM
LL
-4tU
LLH
N/A
LM
-3tU
LML
LH
LH
-2tU
LMM
ML
ML
-1tU
LMH
MM
MM
0tU
LHL
MH
MH
1tU
LHM
HL
HL
2tU
LHH
N/A
HM
3tU
MLL
HM
HH
4tU
MLM
HH
N/A
6tU
Figure 6b. Phase Select Time Unit Step Relationships
39
tODCV-LVCMOS 3.3
tORISE
VDD_nQ
VOH
VTH+0.5V
tOFALL
tPWH
VTH=0.5*(VDD_nQ)
tPWL
VTH-0.5V
VOL
0V
Figure 7A. +3.3V LVCMOS3.3/LVTTL Output Waveform
tODCV-LVCMOS 2.5
tORISE
VDD_nQ
VOH
VTH+0.5V
tOFALL
tPWH
VTH = 0.5*(VDD_nQ)
tPWL
VTH-0.5V
VOL
0V
Figure 7B. +2.5V LVCMOS2.5/LVTTL Output Waveform
< 1ns
< 1ns
VDD_C
VIH
VTH = 0.5*(VDD_C)
VIL
0V
Figure 7C. LVCMOS3.3/LVTTL and XTAL_IN Input Test Waveform
40
VDD_nQ
RTERM = 33-ohms
Test
Point
Zo = 50-ohms
DUT
CL
Figure 8A. Series Terminated LVCMOS/LVTTL Test Circuit
VDD_nQ
VDD_nQ
RTERM =
100-ohms
DUT
CL
Zo = 50-ohms
Test
Point
RTERM =
100-ohms
Figure 8B. Thevenin Terminated LVCMOS/LVTTL Test Circuit
VDD_nQ
DUT
CL
Zo = 50-ohms
Test
Point
RTERM =
50-ohms
CTERM =
3.5*tr/Zo
Figure 8C. AC Terminated LVCMOS/LVTTL Test Circuit
Note: For ATE test load, CL=40pF. For lab characterization, CL=15pF
41
nQ0
CL
TEST IN
Generator
nQ[1:0]
RL = 100
VOD
50
Driver Enabled
nQ1
CL
Figure 9. LVDS Driver VOD and VOS Test Circuit or Equivalent
Note: For ATE test load, CL=40pF. For lab characterization, CL=15pF
tODCV-LVDS
VOH
80%
80%
VDIFF = nQ0 - nQ1
VOS
VOS
20%
20%
VOL
tOFALL
tORISE
Figure 10. LVDS Driver Transition Time Waveform
42
Figure 11. 168-CLGA Package
43
Figure 12. 168-CCGA Package
44
Figure 13. 168-CBGA Package
45
UT7R2XLR8**: Datasheet
UT7R2XLR8 * * *
*
*
Lead Finish: (Notes: 1)
(A) = Hot Solder Dipped or Tinned
(C) = Gold
Screening Level: (Notes: 2,3,4,5)
(P) = Prototype Flow
(C) = HiRel Flow
(G) = Commercial Flow
(I) = Industrial Flow
(Temperature Range: 25°C only)
(Temperature Range: -55°C to +125°C)
(Temperature Range: 0°C to +70°C)
(Temperature Range: -40°C to +85°C)
Case Outline:
(Z) = 168-Ceramic Land Grid Array
(S) = 168-Ceramic Column Grid Array
(C) = 168-Ceramic Ball Grid Array (High Temp Solder Ball)
TID Tolerance:
(-) = None
(R) = 100 krad (Si)
Device Type
(16) = Clock Network Manager II with 16 clock outputs driven by eight clock banks
Generic UT7R2XLR8 part number
Notes:
1. Lead finish (A or C) must be specified.
2. Prototype Flow per Aeroflex Manufacturing Flows Document. Devices are tested at 25oC only. Radiation is neither tested nor guaranteed.
3.Commercial Flow per Aeroflex Manufacturing Flows Document. Radiation TID tolerance may be ordered.
4. Industrial Flow per Aeroflex Manufacturing Flows Document. Radiation TID tolerance may be ordered.
5. HiRel Flow per Aeroflex Manufacturing Flows Document. Radiation TID tolerance may be ordered.
Package Option
Associated Lead Finish
(Z) 168 CLGA
(C) Gold
(S) 168 CCGA
(A) Hot Solder Dipped
(C) 168 CBGA
(A) Hot Solder Dipped
46
UT7R2XLR816: SMD
5962
*
08243
**
*
*
*
Lead Finish: (Note 1)
(C) = Gold
(A) = Solder
Case Outline:
(X) = 168-pin Ceramic Land Grid Array
(Y) = 168-pin Ceramic Column Grid Array
Class Designator:
(Q) = QML Class Q
(V) = QML Class V (Pending, contact Factory for availability)
Device Type: (Note 2)
01 = UT7R2XLR816 (Temperature Range: -55oC to +125oC)
02 = UT7R2XLR816 assembled to Aeroflex’s Q+ flow (Temperature Range: -55oC to +125oC)
Drawing Number: 08243
Total Dose:
(-) = none
(R) = 1E5 (100 krad (Si))
Federal Stock Class Designator: No options
Notes:
1. Lead finish is "C" (gold) only for case outline "X" and "A" (solder) only for cast outline "Y".
2. Aeroflex’s Q+ assembly flow, as defined in section 4.2.2.d of the SMD, provides QML-Q product through the SMD that is manufactured with Aeroflex’s standard QML-V flow, and has completed QML-V qualification per MIL-PRF-38535.
47
48
Aeroflex Colorado Springs - Datasheet Definition
Advanced Datasheet - Product In Development
Preliminary Datasheet - Shipping Prototype
Datasheet - Shipping QML & Reduced HiRel
COLORADO
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Aeroflex Colorado Springs, Inc., reserves the right to make
changes to any products and services herein at any time
without notice. Consult Aeroflex or an authorized sales
representative to verify that the information in this data sheet
is current before using this product. Aeroflex does not assume
any responsibility or liability arising out of the application or
use of any product or service described herein, except as
expressly agreed to in writing by Aeroflex; nor does the
purchase, lease, or use of a product or service from Aeroflex
convey a license under any patent rights, copyrights,
trademark rights, or any other of the intellectual rights of
Aeroflex or of third parties.
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49