Standard Products Datasheet RDC5028C 16-Bit Monolithic Tracking Rad Tolerant Resolver-To-Digital Converter www.aeroflex.com/RDC May 7, 2014 FEATURES Enhanced version of the ACT5028B Radiation performance - Total dose: 1 Mrad(Si), Dose rate = 50 - 300 rads(Si)/s - SEL:Immune up to 100 MeV-cm2/mg +5VDC power only Programmable: By using a few non critical external resistors and capacitors - Resolution: 10, 12, 14 or 16 bit resolution - Bandwidth - Tracking rate Low power: +5V @ 20 mA typ 45 to 30,000 Hz carrier frequency range Accuracy: - 10.0 Arc Minutes if not compensated by INL correction factors. - 5.3 Arc Minutes using INL correction factors. Differential instrument amplifiers resolver input -55° to +125°C operating temperature Digital interface logic voltage of 3.3V to 5V Designed for aerospace and high reliability space applications Packaging – Hermetic - 52 Pin Ceramic QUAD flat package (CQFP), .956" SQ x .100"Ht - Weight: 5.0g max Evaluation board available for test and evaluation. See Aeroflex Application note AN5028-1 Aeroflex Plainview’s Radiation Hardness Assurance Plan is DLA Certified to MIL-PRF-38534, Appendix G. APPLICATIONS This single chip Resolver-to-Digital Converter (RDC) is used in shaft angle control systems, and is suitable for space or other radiation environments that require > 1 Mrad(Si) total dose tolerance. The part is latchup free in heavy ion environments (e.g., geosynchronous orbits) and is estimated to experience SEU induced errors of less than 15 minutes of arc at a rate of 1 per device per 2 years when operating dynamically. THEORY OF OPERATION The RDC5028 converter is a single CMOS Type II tracking resolver to digital converter monolithic chip. It is implemented using precision analog circuitry and digital logic. For flexibility, the converter bandwidth, dynamics and velocity scaling are externally set with passive components. Refer to Figure 1, RDC5028 Block Diagram. The converter is powered from +5VDC. Analog signals are referenced to signal ground, which is nominally VCC /2. The converter consists of three main sections; the Analog Control Transformer (CT), the Analog Error Processor (EP) and the Digital Logic Interface. The CT has two analog resolver inputs (Sin and Cos) that are buffered by high impedance input instrumentation type amplifiers and the 16 bit digital word which represents the output digital angle. The CT performs the ratiometric trigonometric computation of: SIN(A) sin(wt) COS(B) – COS(A) sin(wt) SIN(B) = SIN(A-B) sin(wt) Utilizing amplifiers, switches, logic and resistors in precision ratios. “A” represents the resolver angle, “B“ represents the digital angle and sin(wt) represents the resolver reference carrier frequency. The Error Processor is configured as a critically damped Type II loop. The AC error, SIN (A-B) sin (wt) is full wave demodulated using the reference squared off as its drive. This DC error is integrated in an analog integrator yielding a velocity voltage which in turn drives a Voltage Controlled Oscillator (VCO). Note in the block diagram, hysterisis is added to prevent dithering and disables counting when the error is less than 1 LSB. This VCO is an incremental integrator (constant voltage input to position rate output) which, together with the velocity integrator, forms a Type II loop. A lead is inserted to stabilize the loop and a lag is inserted at a higher frequency to attenuate the carrier frequency ripple. The error processor drives the 16 bit digital output until it nulls out. Then angle “A” = “B”. The digital output equals angle input to the accuracy of the precision control transformer. The various error processor settings are done with external resistors and capacitors so that the converter loop dynamics can be easily controlled by the user.The digital logic interface has a separate power line, VL I/O that sets the interface logic 1 level. It can be set anywhere from +3V to the +5V power supply. SCD5028-2 Rev G RIPPLE -COS +COS -SIN +SIN 52 24 25 21 22 2 BIT 1 MSB DATA LOAD 28 VL I/O A 1 G=2 G=2 2 - + - + RDC5028 ENABLE 45 R6 INH 47 + - ERROR AMP SC1 49 48 SC2 DEMOD COMP 12 -REF 3,19,23 A GND GND 26 +5VA +5V 4 INTERNAL ANALOG GROUND 27 +5VD BUSY 50 VCO & TIMING HYSTERESIS + 5 10 9 R3 8 R2 6 - C2 18 R1 -VEL 17 D GND SIGNAL GND +2.25V 16 11 15 13 +REF 14 C1 C3 DEMOD1 C1 DEMOD2 R4 R2 INTIN2 R4 C2 INTIN1 C4 AC1 R1 INT1 +2.5V AC2 +VEL INT2 R5 BPF2 FIGURE 1 – RDC5028 BLOCK DIAGRAM LSB BIT 16 44 OUTPUT DATA LATCH 16 BIT UP/DOWN COUNTER B DIFFERENTIAL CONTROL TRANSFORMER +5V BPF1 C3 VCOIN SCD5028-2 Rev G 5/7/2014 Aeroflex Plainview 51 CW/CCW PIN DESCRIPTIONS SIGNAL DIRECTION PIN +SIN -SIN INPUT 22 21 Analog Sine input from Synchro or Resolver. 1.3Vrms nominal +COS -COS INPUT 25 24 Analog Cosine input from Synchro or Resolver. 1.3Vrms nominal +REF -REF INPUT 11 12 Analog Reference input is typically a sine wave @ 1.3Vrms Digital angle data. Parallel format. Natural binary positive logic. Bit 1, most significant bit = 180°, Bit 2 = 90°, Bit 3 = 45° and so on. BIDIR 28 29 30 31 32 34 35 36 37 38 39 40 41 42 43 44 BIT 1 (MSB) BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 BIT 9 BIT 10 BIT 11 BIT 12 BIT 13 BIT 14 BIT 15 BIT 16 (LSB) SC1 SC2 SIGNAL DESCRIPTION In the 10 bit mode, Bit 10 is the LSB. Bits 11-16 are 0s. In the 12 bit mode, Bit 12 is the LSB. Bits 13-16 are 0s. In the 14 bit mode, Bit 14 is the LSB. Bits 15-16 are 0s. In the 16 bit mode, Bit 16 is the LSB. INPUT 49 48 Digital input. Sets the resolution. SC1 SC2 Resolution 0 0 10 bit 0 1 12 bit 1 0 14 bit 1 1 16 bit ENABLE* INPUT 45 Logic 0 enables digital angle output. Otherwise it is high impedance. INH* INPUT 47 Logic 0 freezes the digital angle output so that it can be safely read. INPUT 1 Logic 0 enables the digital angle lines to be inputs to preset the angle. Logic 1 is for normal digital angle output. OUTPUT 50 A logic 1 pulse when the digital angle changes by 1 LSB. OUTPUT 51 For turns counting. Logic 1 = counting up (CW), logic 0 = counting down (CCW). OUTPUT 52 Ripple clock for turns counting. A logic 0 pulse = a 0° transition in either direction. AC1 AC2 OUTPUT 14 13 Differential AC error output BPF1 BPF2 INPUT 16 15 Differential AC error input to demodulator OUTPUT 17 18 Differential DC error output INPUT 8 6 Differential DC input to differential velocity integrator OUTPUT 9 10 Differential velocity output VCOIN INPUT 5 Input to Voltage Controlled Oscillator VCC VDD POWER 4 27 Analog Power In Digital Power In A GND D GND POWER 3, 19, 23 26 VL I/O POWER 2 DATALOAD* BUSY CW/CCW RIPPLE* DEMOD1 DEMOD2 INTIN1 INTIN2 INT1 INT 2 Analog Power ground Digital Power ground Digital input/output DC power supply. Sets logic 1 level. +3V to +5V * Indicates Active Low Signal SCD5028-2 Rev G 5/7/2014 3 Aeroflex Plainview ABSOLUTE MAXIMUM RATINGS * PARAMETER VALUE Operating Temperature -55°C to +125°C Storage Temperature -65°C to +150°C Positive Power Supply Voltage (VCC = VDD) -0.5 V to +7.0 V Analog Output Current (Output Shorted to GND) 32 mA Max Digital Output Current (Output Shorted to GND) 18.6 mA Max Analog Input Voltage Range -0.5 V to + (VCC + 0.5 V) Digital Input Voltage Range -0.5 V to + (VDD + 0.5 V) Thermal Resistance ØJC Specification 1.25°C/W Maximum Junction Temperature 135°C Lead Temperature (soldering, 10 seconds) 300°C ESD Class 2 MIL-STD-883 Method 3015, 8 2000 V to 3999 V * Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. These are stress ratings only; functional operation beyond these operating conditions is not recommended and extended exposure beyond these operating conditions may effect device reliability. OPERATING CONDITIONS (TA = -55°C to +125°C) POWER SUPPLY PARAMETER MIN TYP MAX UNIT VDD = VCC Operating Voltage 4.5 5 5.5 VDC IDD + ICC 9/ Operating Current - 20 35 mA VL I/O Interface Voltage 3 3.3, 5 5.5 VDC ELECTRICAL CHARACTERISTICS 2/, 5/, 6/ (TA = -55°C to +125°C) PARAMETER Accuracy 4/ 8/ 9/ CONDITIONS MIN TYP MAX Add 1 LSB for total Error, Using INL correction factors. - +/-2 +/-5.0 Add 1 LSB for total Error, Not compensated by INL correction factors - +/-4 +/-10.0 - - 1 LSB 0.35 - - Degrees 21.1 - - Minutes 0.09 - - Degrees 5.27 - - Minutes 0.022 - - Degrees 1.32 - - Minutes 0.0055 - - Degrees 0.33 - - Minutes Repeatability Resolution per LSB 10 Bit Mode 12 Bit Mode 14 Bit Mode 16 Bit Mode Max Tracking Rate SC1 SC2 UNITS Minutes Bits Used 10 Bit Mode 3/ 0 0 B1 - B10 1024 - - RPS 12 Bit Mode 3/ 0 1 B1 - B12 256 - - RPS 14 Bit Mode 3/ 1 0 B1 - B14 64 - - RPS SCD5028-2 Rev G 5/7/2014 4 Aeroflex Plainview ELECTRICAL CHARACTERISTICS 2/, 5/, 6/ (TA = -55°C to +125°C) PARAMETER 16 Bit Mode 3/ CONDITIONS 1 1 MIN TYP MAX UNITS 16 - - RPS 1.05 - - MHz B1 - B16 VCO Frequency 3/ ELECTRICAL SPECIFICATIONS 2/, 5/, 6/ (TA = -55°C to +125°C) ANALOG SIGNAL INPUTS SIN, COS, REF, VCOIN, INTIN1, INTIN2, BPF1, BPF2 SYM PARAMETER MIN TYP MAX UNITS VSIN, VCOS, VREF Voltage measurement made between ± inputs 9/ 1.0 1.3 1.5 VRMS FREF Frequency 1/ 45 - 30K Hz DC Resistance 3/ 2.5 - - M - 5 15 pF - VCC /2 - VDC +25°C -100 - +100 nA +125°C -1000 - +1000 nA VIL Logic Low - - 0.8 VDC VIH Logic High 2 - - VDC IIN Leakage Current +25°C -200 - +200 nA +125°C -2000 - +2000 nA 2.5 - - M Capacitance - 5 15 pF VOL Logic Low @ 1.6mA - - 0.3 VDC VOH Logic High @ -1.6mA VL I/O - 0.8 - - VDC VIL Logic Low - - 0.8 VDC VIH Logic High 2 - - VDC VOL Logic Low @ 1.6mA - - 0.3 VDC VOH Logic High @ -1.6mA VL I/O - 0.8 - - VDC IIN Leakage Current +25°C -200 - +200 nA +125°C -2000 - +2000 nA +25°C -200 - +200 nA +125°C -2000 - +2000 nA Capacitance 3/ DC Bias on -Sin, -Cos 3/ Bias Current 3/ DIGITAL INPUTS ENABLE, DATALOAD SC2, SC1, INH 3/ DC Resistance DIGITAL OUTPUTS BUSY, RIPPLE CW/CCW 3/ DIGITAL I/O B1 - B16 7/ 3/ IZ SCD5028-2 Rev G 5/7/2014 High-Z Leakage Current 5 Aeroflex Plainview TIMING SPECIFICATIONS DIGITAL OUTPUT SYM Busy CW/CCW, Ripple, B1- B16 COMMENTS Busy to Data Stable Ripple Pulse Width 3/ READ DATA TYP 2/ MAX UNITS Rise Time - 20 85 ns tHL Fall Time - 20 85 ns tLH Rise Time - 45 120 ns tHL Fall Time - 45 100 ns 300 400 600 ns - - 350 ns tRPW 140 200 300 ns tBR - 100 150 ns tBDS 3/ MIN tLH tBPW Busy Pulse Width Busy to Ripple 6/ Enable = Low 3/ (Enable & INH would normally be tied together, Data Load = Logic Hi) Enable Low to Data Stable tELDS - - 70 ns Enable High to Data Hi-Z tEHZ - - 70 ns INH Low to Data Stable tILDS - - 400 ns INH High to Data Change tIHZ - - 150 ns 200 - - ns WRITING DATA 3/ (Enable & INH = Logic Hi) Transparent Trailing Edge Latch Data Load Pulse Width tDLPW Data Setup to Data Load tWDS 60 - - ns Data Hold tWDH 10 - - ns Notes 1/ @ 10 Bits, FREF > 4 x BWCL @ 12 Bits, FREF > 8 x BWCL @ 14 Bits, FREF > 12 x BWCL @ 16 Bits, FREF > 16 x BWCL 2/ All typical values are measured at +25°C. 3/ Characteristics are guaranteed by design, not production tested. 4/ Accuracy applies over the full operating Power Supply voltage range, Full operating Temperature range, Reference Frequency range, 10% Signal Amplitude variation and 10% Reference Harmonic distortion. 5/ For ESD protection the RDC5028 features limiting resistors in series with diodes. Proper ESD precautions are strongly recommended to avoid functional damage or performance degradation. 6/ All testing at nominal voltage. 7/ All unused inputs shall be tied to Ground. Bit 1 is always the MSB. 8/ See Application Note 1, page 16 and Table II, page 19 "Using INL Error Correction Factors to Improve Accuracy" 9/ Specification de-rated to reflect Total Dose Rate (1019 condition A) to 1 Mrad(Si) @ 25°C. SCD5028-2 Rev G 5/7/2014 6 Aeroflex Plainview READ CYCLE HI DATALOAD INH ENABLE tEHZ / tIHZ tELDS / tILDS DATA DATA WRITE CYCLE HI ENABLE HI INH tDLPW DATA LOAD tWDS tWDH DATA DATA BUSY TIMING CW/CCW tBPW BUSY tBR tRPW RIPPLE DATA DATA DATA + 1 tBDS EN FIGURE 2 – RDC5028 TIMING DIAGRAMS SCD5028-2 Rev G 5/7/2014 7 Aeroflex Plainview INPUT RESOLVER 8 INPUT HYSTERESIS = 75nA + 10 9 8 R2 6 - C2 18 R1 17 16 BIT UP/DOWN COUNTER G=0.9 DEMOD COMP 12 -REF C3 +2.25V R3 - CT 0.9(EG) H=1 2 S [(S/10T)+1] Vco (G2/S) EP G1 [(S/T)+1] DIGITAL Vco 20.5p Cvco Threshold = 1.95V 5 OUTPUT FIGURE 3 – RDC5028 TRANSFER FUNCTION DIAGRAM + VELOCITY FIGURE 2 – RDC5028 FUNCTIONAL BLOCK DIAGRAM H=1 ERROR AMP + - G=14 16 11 15 +REF 13 C1 C1 14 .1µf .1µf R4 100K AC1 R2 DEMOD1 R4 100K AC2 C2 + RESOLVER CT G=2 R6 BPF2 R1 DEMOD2 C4 INTIN2 +2.5V INTIN1 R5 INT1 +5V INT2 SCD5028-2 Rev G 5/7/2014 BPF1 C3 - Aeroflex Plainview OUTPUT DIGITAL Vco & TIMING -12dB/oct 2G Closed Loop Bandwidth (BWcl) (Hz) = ------------- Gain = 4 -6dB/oct BWcl BW T G 10T rad/sec 2G (T = G/2) Gain = 0.4 -12dB/oct FIGURE 4 – RDC5028 OPEN LOOP BODE PLOT TRANSFER FUNCTION AND BODE PLOT The dynamic performance of the converter can be determined from its Functional Block Diagram, Transfer Function Diagram and Bode plots, as shown in Figures 2, 3 and 4. PROCEDURE FOR SELECTING RDC BANDWIDTH COMPONENTS * Input: Carrier Frequency (Fc) in Hz [47 to 30,000 Hz] Input: Nominal Resolver Input Level in Vrms [1Vrms min. to 1.5Vrms max.] Input: Resolution in bits; 10, 12, 14 or 16 bits Input: Closed Loop Bandwidth (BWcl) in Hz [10 bit; BWcl = Fc/4 max.] [12 bit; BWcl = Fc/8 max.] [14 bit; BWcl = Fc/12 max.] [16 bit; BWcl = Fc/16 max. ] Input: Maximum Tracking Rate in RPS (RPS = rotations per second) [16 bit; 16 RPS max.] [14 bit, 64 RPS max.] [12 bit; 256 RPS max.] [10 bit, 1024 RPS max.] Input: Hysteresis in LSBs. Recommended is 1 LSB for 16 & 14 bits and 0.7 LSBs for 12 & 10 bits. EG = Nominal Resolver Input Level EG = Nominal Resolver Input Level EG = Nominal Resolver Input Level EG = Nominal Resolver Input Level G = 2.22 BWcl .0027 .011 .043 .17 [16 bit] or [14 bit] or [12 bit] or [10 bit] G2 = EG 0.45 G1 G2 SCD5028-2 Rev G 5/7/2014 9 Aeroflex Plainview PROCEDURE FOR SELECTING RDC BANDWIDTH COMPONENTS * (Cont) Hysteresis recommended values HYS = 0.7 [10 & 12 bit] or HYS = 1 [14 & 16 bit] or R1(ohms) = 6 106 EG HYS G2 = Maximum Tracking Rate 215 G2 = Maximum Tracking Rate 213 G2 = Maximum Tracking Rate 211 G2 = Maximum Tracking Rate 29 R3(ohms) = (25 109)/G2 [16 bit] or [14 bit] or [12 bit] or [10 bit] G1 = G2/(EG .45 G2) C2(farads) = 1/(G1 R1) C3(farads) = C2/10 R2(ohms) = 2/(G C2) * Software Program SW5028-2 available at Aeroflex WEB site. RDC5028 EXAMPLE CALCULATIONS Carrier Frequency = 800 Hz Nominal Resolver Input Level = 1.3Vrms Resolution = 14 bits Closed Loop Bandwidth (BWcl) = 20 Hz Maximum Tracking Rate in RPS = 1 Hysteresis = 1 LSB EG = Nominal Resolver Input Level .011 [14 bit] = 1.3 .011 = .014 G = 2.22 BWcl = 2.22 20 = 44.4 HYS = 1 [14 bit] R1(ohms) = 6 106 EG HYS = 6 106 .014 1 = 84K. Use closest standard resistor = 84.5K 1% G2 = Maximum Tracking Rate 213 = 8192 [213 for 14 bits] R3(ohms) = (25 109)/G2 = (25 109)/8192 = 3,050K. Use closest standard resistor = 3.01M 1% or 3M 5% G2 = EG 0.45 G1 G2 G1 = G2/(EG .45 G2) = 44.42/(.014 .45 8192) = 38.2 C2(farads) = 1/(G1 R1) = 1/(38.2 84.5K) = .31µF. Use closest standard capacitor = .33µF 10% C3 = C2/10(farads) = C2/10 = .33µ/10 = .033µF R2(ohms) = 2/(G C2) = 2/(44.4 .33µ) = 136.5K. Use closest standard resistor = 137K 1% SIGNAL AND REFERENCE INPUT CONDITIONING Inputs to the converter should be 1.3 Vrms nominal, resolver format referenced to VCC /2 nominal Figure 5 shows various input configurations. SCD5028-2 Rev G 5/7/2014 10 Aeroflex Plainview REFERENCE CONDITIONING Most resolvers have a LEADING input to output phase shift. A simple C-R leading phase shift network (Figure 5 – Reference Conditioning) from the resolver reference to the RDC’s reference input will provide the compensating phase shift required to bring the signals in phase. If the resolver has a LAGGING input to output phase shift an R-C lagging phase shift network (low pass network) would be required. Note the C-R phase lead circuit on the input to the Demodulator (BPF1 and BPF2) in Figure 1 should be considered when calculating the total system phase compensation. The formula for calculating the phase shift network is as follows: Phase angle = ArcTan 1 6.28 x (R7 + R8) x C FREF Select a convenient capacitor value and perform the following calculation to determine the proper resistor value. R= 1 (Tan (Phase Angle)) x FREF x 6.28 x C POWER UP INITIALIZATION The RDC5028 RDC converter can provide incorrect data output if a unit step of 180° (starting at any angle) is introduced to the Sin / Cos input. This is difficult to reproduce since a Resolver will never provide a unit step function to the RDC chip. The only time this would be a concern is during power up, if the Resolver is set to 180°. The RDC will initialize its internal counter to 0000h which simulates the unit step function mentioned above. In practice this error condition during power up is difficult to produce because of the dynamics associated with all the variables when power is first applied. If the system designer does nothing to accommodate this potential problem the system could see an error at power on, however, this error will be self corrected once the Resolver begins to rotate. If the Resolver does not rotate, the error can be corrected by writing to the RDC5028 any angle except 180°. VELOCITY CONTROL The RDC5028 RDC exhibits nonlinearity below 4 degrees/sec due to an anti-dither circuit that was added to reduce the effects of any noise condition that may exist. This result can be seen in the least significant bit or on the velocity output pins 9 & 10 on this device. SCD5028-2 Rev G 5/7/2014 11 Aeroflex Plainview SCD5028-2 Rev G 5/7/2014 12 Aeroflex Plainview +5V x x VCC /2 10K 10K 2.5VDC + 4.7µF y y VCC /2 -COS +COS -SIN R7 VCC /2 R8 -REF +REF SINGLE ENDED REFERENCE CONDITIONING +REF +REF C5 x x x y y y y VCC /2 VCC /2 -COS +COS -SIN C5 C5 R7 R7 x x x/2 x x VCC /2 VCC /2 z = x (sq rt 3) z z y y -COS +COS -SIN +SIN R8 R8 VCC /2 -REF +REF SYNCHRO CONDITIONING S2 S1 S3 DIFFERENTIAL REFERENCE CONDITIONING (FLOATING REFERENCE) -REF +REF DIFFERENTIAL RESOLVER CONDITIONING -COS +COS -SIN x +SIN FIGURE 5 – RDC5028 RESOLVER, SYNCHRO AND REFERENCE INPUT CONFIGURATIONS .1µF VCC /2 x x +SIN SINGLE ENDED RESOLVER CONDITIONING -COS +COS +COS -COS -SIN +SIN -SIN +SIN DIRECT RESOLVER -COS +COS -SIN +SIN +SIN READING THE ACT 5028B The Busy signal is asynchronous to the Read signal created by the interface circuit that reads it. Because of the asynchronous nature of the system (inherent with other Resolver to Digital Converters) the designer must be careful when reading the digital interface. The implementation of reading the RDC is accomplished in one of two ways, using a CPU/MPU or using an FPGA. The best method for reading the counter may also depend on the rep rate of the counter clock that can vary from 0 to 1µS. The Busy pulse is instrumental in reading stable data from the RDC5028. The Busy pulse will be present for the following two situations: 1) When ever data is incremented or decremented in the RDC counter. 2) Directly after the trailing positive going edge of /INH (see A within example 5 timing diagram). Based on 1 above there are many methods that can be implemented to synchronize the reading of data from the RDC5028, below are a few examples: Example 1: If the only time a read will occur is after the RDC has stopped (0 rps) there will be no Busy signal to contend with. Example 2: Knowing the Busy rep rate an Interrupt to a CPU or Logic can be developed from the Busy pulse for the system to Read the RDC chip as long as the read is guaranteed to occur prior to the next Busy pulse. Example 3: As long as the resolver is rotating the Busy Pulse can be used to indicate stable data to be sampled on leading or trailing edge. Example 4: Ignore Busy and perform two reads back to back and compare, if they are equal you have good data. The designer should be aware of the rep rate of Busy which is equal to the clock rate of the counter. In most cases the angular velocity is < 3 rps in which case with a 16 bit counter rep rate would be (1 / 216 * 3) 5µS. In this situation the reads would like to be within 5µs of each other and the LSB would be ignored. Although this method would be easier to implement with a CPU it could also be done in an FPGA. Example 5: The circuit below ignores the Busy signal but insures sampling of stable data. The clock should be a least 10MHz, the /RD pulse should be a minimum of 1.2µs (to insure minimum /INH pulse width of 400ns), the sampling of data should be taken on the rising edge of the signal /RD. The /RD signal is synced up with the CLK such that the sampling on the D latch occurs on the opposite edge of the /RD transition. /RD D Busy D CLK SCD5028-2 Rev G 5/7/2014 CK S CK Q S Q /INH & /EN /Q /Q 13 Aeroflex Plainview FIGURE 6 – CIRCUIT TIMING WAVEFORMS SCD5028-2 Rev G 5/7/2014 14 Aeroflex Plainview TABLE I – RDC5028 PIN OUT DESCRIPTIONS (CQFP PACKAGE) PIN # FUNCTION PIN # 1 DATA LOAD 19 A GND 37 BIT 9 2 VL I/O 20 N/C 38 BIT 10 3 A GND 21 -SIN 39 BIT 11 4 A +5V 22 +SIN 40 BIT 12 5 VCOIN 23 A GND 41 BIT 13 6 INTIN2 24 -COS 42 BIT 14 7 N/C 25 +COS 43 BIT 15 8 INTIN1 26 D GND 44 BIT 16 (LSB) 9 INT1 27 D +5V 45 ENABLE 10 INT2 28 BIT 1 (MSB) 46 N/C 11 +REF 29 BIT 2 47 INH 12 -REF 30 BIT 3 48 SC2 13 AC2 31 BIT 4 49 SC1 14 AC1 32 BIT 5 50 BUSY 15 BPF2 33 N/C 51 CW/CCW 16 BPF1 34 BIT 6 52 RIPPLE 17 DEMOD1 35 BIT 7 18 DEMOD2 36 BIT 8 SCD5028-2 Rev G 5/7/2014 FUNCTION 15 PIN # FUNCTION Aeroflex Plainview FIGURE 7 – 52 PIN CERAMIC QUAD FLAT PACKAGE (CQFP) OUTLINE SCD5028-2 Rev G 5/7/2014 16 Aeroflex Plainview APPLICATION NOTE 1 USING INL ERROR CORRECTION FACTORS TO IMPROVE ACCURACY: The information provided in this section is to address the constant Integral Nonlinearity (INL) that exists at each angle of the RDC5028 Resolver to Digital Converter (RDC). This error is repeatable from chip to chip and provides a look up Table of offsets that can be added to the output of the Resolver to Digital Converter to obtain the 5.3 minute accuracy. Figure 8 shows the error in Minutes that exists at 2o increments for the full 360o. Note that the INL error from 0o to 180o is basically the same as the error between 180o and 360o. Table II has the angle and correction factor (in Minutes) that must be added to zero out the INL error. A simple calculation can be performed to derive a correction factor for angles that fall between the angles listed in Table II herein. AL = Larger Angle AS = Smaller Angle CL = Correction Factor associated with larger Angle CS = Correction Factor associated with smaller Angle NA = New Angle NCF = New Correction Factor Formula: NCF = CS + (((NA - AS) / (AL - AS)) * (CL - CS)) Example: Require the correction factor @ 15o for 5028-3-1 NCF = 5.10687 + (((15 – 14) / (16 – 14)) * (5.61783 - 5.10687)) NCF = 5.10687 + (((1) / (2)) * .51096) NCF = 5.10687 + (.5 * .51096) NCF = 5.10687 + .25548 NCF = 5.36235 minutes SCD5028-2 Rev G 5/7/2014 17 Aeroflex Plainview SCD5028-2 Rev G 5/7/2014 18 Aeroflex Plainview Minutes -8 -6 -4 -2 0 2 4 6 8 0 20 40 60 80 Angle FIGURE 8 – ANGLE ERROR CHART 100 120 140 160 180 200 220 240 260 280 300 320 340 TABLE II – CORRECTION FACTORS (MINUTES) Angle 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 Correction Factor 0.020387 2.013632 3.864167 5.646746 5.951268 6.097790 6.327559 5.617827 5.106868 4.917005 5.080516 5.374844 5.856053 5.761329 6.313892 5.408785 4.777203 4.060675 3.463072 2.811103 2.339220 2.458559 2.467469 2.354057 2.300107 2.332801 1.849025 1.188562 0.523002 -0.33114 -1.21076 -1.92219 -1.89799 -1.87039 -1.94813 -2.01057 -2.05603 -2.50413 -3.23255 -3.90830 -4.26466 -4.31011 -4.22645 -2.72929 -1.10131 SCD5028-2 Rev G 5/7/2014 Angle 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 Correction Factor Angle 0.557245 2.253179 3.867565 5.342640 5.370238 5.311191 4.961630 4.284177 3.543865 3.066884 3.004440 2.936898 2.821787 2.789923 2.758059 2.010951 1.092252 0.222822 -0.47841 -1.18305 -1.69741 -1.73267 -1.81210 -1.95779 -1.98626 -1.87711 -2.40166 -3.07912 -4.01311 -4.43062 -5.13696 -5.72437 -5.51329 -5.30390 -5.13530 -4.91062 -4.76070 -4.99474 -5.51759 -5.92152 -6.03663 -5.87312 -5.57369 -3.78432 -1.88282 180 182 184 186 188 190 192 194 196 198 200 202 204 206 208 210 212 214 216 218 220 222 224 226 228 230 232 234 236 238 240 242 244 246 248 250 252 254 256 258 260 262 264 266 268 19 Correction Factor 0.018688 2.047610 3.923629 5.679026 5.963160 6.140263 6.050635 5.641612 5.111965 4.923800 5.094107 5.368048 5.533258 5.751135 5.989399 5.400290 4.768708 4.062374 3.471566 2.821297 2.346015 2.480645 2.479361 2.381239 2.305203 2.326006 1.837133 1.171573 0.497518 -0.34473 -1.22435 -1.94088 -1.92687 -1.89418 -1.97361 -2.02926 -2.07132 -2.52961 -3.26992 -3.94058 -4.29014 -4.32540 -4.25703 -2.75308 -1.11321 Angle 270 272 274 276 278 280 282 284 286 288 290 292 294 296 298 300 302 304 306 308 310 312 314 316 318 320 322 324 326 328 330 332 334 336 338 340 342 344 346 348 350 352 354 356 358 Correction Factor 0.535159 2.242985 3.864167 5.356231 5.411012 5.360460 4.982017 4.331747 3.572746 3.095766 3.026526 2.981070 2.864260 2.840891 2.836209 2.075510 1.180596 0.317962 -0.38497 -1.06413 -1.58528 -1.58996 -1.67959 -1.83547 -1.86054 -1.75479 -2.29293 -2.97718 -3.61556 -4.32699 -5.04352 -5.62413 -5.40795 -5.20707 -5.06734 -4.86136 -4.70974 -4.92339 -5.45983 -5.90113 -6.02644 -5.86972 -5.57199 -3.78602 -1.89811 Aeroflex Plainview ORDERING INFORMATION MODEL DLA SMD # SCREENING RDC5028-3-1-7 1/ RDC5028-3-1-S PACKAGE Commercial Flow, +25°C testing only - 1/ Military Temperature, -55°C to +125°C Screened in accordance with the individual Test Methods of MIL-STD-883 for Space Applications RDC5028-301-1S RDC5028-301-2S 5962-0423503KXC 5962-0423503KXA In accordance with DLA SMD RDC5028-931-1S RDC5028-931-2S 5962H0423503KXC 5962H0423503KXA In accordance with DLA Certified RHA Program Plan to RHA Level "H", 1 Mrad(Si) - - RDC5028, Evaluation board 2/ CQFP - Notes 1/ Dash #’s: The first dash number indicates the revision of silicon: -3 = Rev. C The second dash number indicates the wafer lot run. -1 = First diffusion lot 2/ See Application note AN5028-1 EXPORT CONTROL: This product is controlled for export under the International Traffic in Arms Regulations (ITAR). A license from the U.S. Government is required prior to the export of this product from the United States. www.aeroflex.com/HiRel [email protected] Datasheet Definitions: Advanced Preliminary Datasheet Product in Development Shipping Non-Flight Prototypes Shipping QML and Reduced HiRel Aeroflex Plainview, Inc. reserves the right to make changes to any products and services described herein at any time without notice. Consult Aeroflex or an authorized sales representative to verify that the information in this data sheet is current before using this product. Aeroflex does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by Aeroflex; nor does the purchase, lease, or use of a product or service from Aeroflex convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual rights of Aeroflex or of third parties. SCD5028-2 Rev G 5/7/2014 20 Our passion for performance is defined by three attributes. Solution-Minded Performance-Driven Customer-Focused