UT54ACS162245SLV Schmitt CMOS 16-bit Bidirectional MultiPurpose Low Voltage Transceiver Datasheet September, 2014 LOGIC SYMBOL FEATURES • Voltage translation - 3.3V bus to 2.5V bus - 2.5V bus to 3.3V bus • Cold sparing all pins • 0.25μ CMOS • Operational environment - Total dose: 300Krad(Si) and 1Mrad(Si) - Single Event Latchup immune • High speed, low power consumption • Schmitt trigger inputs to filter noisy signals • Cold and Warm Spare - all outputs • Available QML Q or V processes • Standard Microcircuit Drawing 5962-02543 • Package: - 48-lead flatpack, 25 mil pitch (.390 x .640), wgt 1.4 Grams OE1 (48) G1 OE2 (25) (1) DIR1 G2 1A1 1A2 (47) (2) 11 12 (46) (3) (43) 1A4 (41) 1A5 (40) 1A6 (38) 1A7 (37) 1A8 (36) 2A1 (6) 2A3 (8) 1B1 1B2 1B3 1B4 1B5 (9) 1B6 (11) 1B7 (12) 1B8 (13) 2B1 21 22 (35) (33) (32) 2A4 (30) 2A5 (29) 2A6 (27) 2A7 (26) 2A8 age transceiver is built using Aeroflex’s epitaxial CMOS technology and is ideal for space applications. This high speed, low power UT54ACS162245SLV low voltage transceiver is designed to perform multiple functions including: asynchronous two-way communication, Schmitt input buffering, voltage translation, warm and cold sparing. With VDD equal to zero volts, the UT54ACS162245SLV outputs and inputs present a minimum impedance of 1MΩ making it ideal for "cold spare" applications. Balanced outputs and low "on" output impedance make the UT54ACS162245SLV well suited for driving high capacitance loads and low impedance backplanes. The UT54ACS162245SLV enables system designers to interface 2.5 volt CMOS compatible components with 3.3 volt CMOS components. For voltage translation, the A port interfaces with the 2.5 volt bus; the B port interfaces with the 3.3 volt bus. The direction control (DIRx) controls the direction of data flow. The output enable (OEx) overrides the direction control and disables both ports. These signals can be driven from either port A or B. The direction and output enable controls operate these devices as either two independent 8-bit transceivers or one 16-bit transceiver. DIR2 (5) 2A2 The 16-bit wide UT54ACS162245SLV MultiPurpose low volt- (24) (44) 1A3 DESCRIPTION 2EN1 (BA) 2EN2 (AB) 1EN1 (BA) 1EN2 (AB) (14) 2B2 (16) 2B3 (17) 2B4 (19) 2B5 (20) 2B6 (22) 2B7 (23) 2B8 PIN DESCRIPTION Pin Names 1 Description OEx Output Enable Input (Active Low) DIRx Direction Control Inputs xAx Side A Inputs or 3-State Outputs (2.5V Port) xBx Side B Inputs or 3-State Outputs (3.3V Port) powered up first to ensure proper control of output enable (/OEx) and direction control (DIRx). Control of the outputs / OEx and DIRx pins is not guaranteed until VDD2 reaches 1.5 +/ -5%. During normal operation of the device, after power up, insure VDD1≥VDD2. PINOUTS 48-Lead Flatpack Top View DIR1 1 48 OE1 1B1 2 47 1A1 1B2 3 46 VSS 1B3 4 5 45 44 1A2 VSS 1A3 1B4 6 43 1A4 VDD1 7 42 VDD2 1B5 1B6 VSS 8 9 10 41 40 39 1A5 1A6 VSS 1B7 11 38 1A7 1B8 12 37 1A8 2B1 13 36 2A1 2B2 VSS 14 15 35 34 2A2 VSS 2B3 16 33 2A3 2B4 17 32 2A4 VDD1 2B5 2B6 VSS 18 19 20 21 31 30 29 28 VDD2 2A5 2A6 VSS 2B7 2B8 DIR2 22 23 24 27 26 25 2A7 2A8 OE2 Power Up Sequence Users should power up VDD2 before VDD1 because the DIRx and /OEx pins on the UT54ACS162245SLV are powered by VDD2. If VDD1 is powered on first, VDD2 must be powered on within 1 second of VDD1 reaching 1.5V +/-5%. An elevated VDD1 supply current up to 150mA may occur when VDD1 > 1.5V+/5% and VDD2 < 1.5V +/-5%. VDD1 VDD2 DIR1 Enable/ Direction Control Logic OE1 DIR2 Enable/ Direction Control Logic PORTB CORE OE2 PORTA POWER TABLE Port B Port A OPERATION 3.3 Volts 2.5 Volts Voltage Translator 3.3 Volts 3.3 Volts Non Translating 2.5 Volts 2.5 Volts Non Translating Warm Spare Once the UT54ACS162245SLV is powered up with VDD1 ≥ VDD2, the application may place the device into “Warm Spare” mode by driving EITHER supply to VSS +/- 0.25V with a maximum 1kΩ impedance between VDDx and VSS. While in Warm Spare, the device places all outputs into a high impedeance state (see DC electrical parameters, Iws). FUNCTION TABLE ENABLE OEx DIRECTION DIRx OPERATION L L B Data To A Bus L H A Data To B Bus H X Isolation Cold Spare The UT54ACS162245SLV places the device into “Cold Spare” mode when BOTH supplies are set to VSS +/- 0.25V with a maximum 1KΩ impedance between VDDx and VSS. While in Cold Spare, the device places all outputs into a high impedeance state (see DC electrical parameters, Ics). Power Application Guidelines For proper operation, connect power to all VDD pins and ground all VSS pins (i.e., no floating VDD or VSS supply pins). If VDD1 and VDD2 are not powered up together, then VDD2 should be 2 LOGIC DIAGRAM 2A1 2.5V PORT 1A4 1A6 (20) 2A7 (22) 2A8 (12) 3 2B7 (26) (23) 1B8 2B6 (27) 1B7 (37) 2B5 (29) 1B6 (38) 2B4 (30) (19) 2A6 (11) 1A8 (17) 2A5 2B3 (32) 1B5 (40) (9) 1A7 1B4 (41) (8) (16) 2A4 2B2 (33) 1B3 (43) (6) 1A5 (14) 2A3 2B1 (35) 1B2 (44) OE2 (36) (13) 2A2 (5) (25) 1B1 (46) (3) 1A3 (24) OE1 (47) (2) 1A2 DIR2 2.5V PORT 1A1 (48) 2B8 3.3 V PORT (1) 3.3 V PORT DIR1 OPERATIONAL ENVIRONMENT 1 PARAMETER LIMIT UNITS Total Dose 1.0E5 rad(Si) SEL Latchup >113 MeV-cm2/mg Neutron Fluence (Note 2) 1.0E14 n/cm2 Notes: 1. Logic will not latchup during radiation exposure within the limits defined in the table. 2. Not tested, inherent to CMOS technology. ABSOLUTE MAXIMUM RATINGS1 SYMBOL PARAMETER LIMIT (Mil only) UNITS VI/O (Note 2) Voltage any pin -.3 to VDD1 +.3 V VDD1 Supply voltage -0.3 to 4.0 V VDD2 Supply voltage -0.3 to 4.0 V TSTG Storage Temperature range -65 to +150 °C Maximum junction temperature +150 °C ΘJC Thermal resistance junction to case 20 °C/W II DC input current ±10 mA PD Maximum power dissipation 1 W TJ (Note 3) Note: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability and performance. 2. For Cold Spare mode (VDD1=VSS, VDD2=VSS), VI/O may be -0.3V to the maximum recommended operating level of VDD1 +0.3V. 3. Maximum junction temperature may be increased to +175oC during burn-in and life test. DUAL SUPPLY OPERATING CONDITIONS SYMBOL PARAMETER LIMIT UNITS VDD1 Supply voltage 2.3 to 3.6 V VDD2 Supply voltage 2.3 to 3.6 V VIN Input voltage any pin 0 to VDD1 V TC Temperature range -55 to + 125 °C 4 DC ELECTRICAL CHARACTERISTICS 1 ( -55°C < TC < +125°C) SYMBOL PARAMETER CONDITION VT+ Schmitt Trigger, positive going threshold2 VT- Schmitt Trigger, negative going threshold2 VDD from 2.3 to 3.6 VH1 Schmitt Trigger range of hysteresis9 VH2 IIN MIN VDD from 2.3 to 3.6 MAX UNIT .7VDD V .3VDD V VDD from 3.0 to 3.6 0.5 V Schmitt Trigger range of hysteresis9 VDD from 2.3 to 2.7 0.4 V Input leakage current9 VDD from 2.7 to 3.6 -1 3 μA -1 3 μA -5 5 μA -5 5 μA -200 200 mA -100 100 mA 0.4 V VIN = VDD or VSS IOZ Three-state output leakage current9 VDD from 2.7 to 3.6 VIN = VDD or VSS ICS Cold sparing input leakage current3,11 VIN = 3.6 VDD = VSS IWS Warm sparing input leakage current3,11 VIN = VSS or VDD, VDD1 = 0, VDD2 = VDD or VDD1 = VDD, VDD2 = 0 IOS1 Short-circuit output current 5, 10 VO = VDD or VSS VDD from 3.0 to 3.6 IOS2 Short-circuit output current 5, 10 VO = VDD or VSS VDD from 2.3 to 2.7 VOL1 Low-level output voltage9 IOL= 8mA IOL= 100μA 0.2 VDD = 3.0 VOL2 Low-level output voltage9 IOL= 8mA 0.4 IOL= 100μA 0.2 VDD = 2.3 VOH1 High-level output voltage9 IOH= -8mA IOH= -100μA VDD = 3.0 VOH2 High-level output voltage9 IOH= -8mA IOH= -100μA VDD = 2.3 5 V VDD - 0.7 V VDD - 0.2 VDD - 0.7 VDD - 0.2 V DC ELECTRICAL CHARACTERISTICS 1 ( -55°C < TC < +125°C) SYMBOL Ptotal1 PARAMETER Power dissipation4,6,7 CONDITION CL = 40pF MIN MAX UNIT 6.2 mW/ MHz 3 MHz VDD from 3.0V to 3.6V Ptotal2 Power dissipation4,6,7 CL = 40pF VDD from 2.3V to 2.7V IDD CIN Standby Supply Current VDD1 or VDD2 VIN = VDD or VSS Pre-Rad 25oC OE = VDD 10 μA Pre-Rad -55oC to +125oC OE = VDD 475 μA Post-Rad 25oC OE = VDD 15 mA Input Capacitance8 f = 1MHz @ 0V 15 pF 15 pF VDD1 or VDD2 Zero Volt Offset 250 mV VDD1 and VDD2 Rise-Time12 500 mS VDD = 3.6V VDD from 2.3V to 3.6V Cout Output Capacitance8 f = 1MHz @ 0V VDD from 2.3V to 3.6V POR VDD1 & VDD2 Power-On4,13 Notes: 1. All specifications valid for radiation dose ≤ 1E5 rad(Si) per MIL-STD-883, Method 1019. 2. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%, 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed to VIH(min) and VIL(max). 3. All combinations of OEx and DIRx 4. Guaranteed by characterization. 5. Not more than one output may be shorted at a time for maximum duration of one second. 6. Power does not include power contribution of any CMOS output sink current. 7. Power dissipation specified per switching output. 8.Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at frequency of 1MHz and a signal amplitude of 50mV rms maximum. 9.Guaranteed; tested on a sample of pins per device. 10. Supplied as a design limit, but not guaranteed or tested. 11. Zero Volts is defined as 0.0 Volts +/- 0.25Volts. 12. VDD1 and VDD2 Voltage rise is monotonic. 13. Rise time measured from VDD @ Zero Volts to VDD @ greater than 2.3 V. 6 AC ELECTRICAL CHARACTERISTICS1 (Port B = 3.3 Volt, Port A = 2.5 Volt) (VDD1 = 3.0V to 3.6V; VDD2 = 2.3V to 2.7V, -55°C < TC < +125°C) SYMBOL PARAMETER MINIMUM MAXIMUM UNIT tPLH Propagation delay Data to Bus 2 10 ns tPHL Propagation delay Data to Bus 2 10 ns tPZL Output enable time OEx to Bus 2 12 ns tPZH Output enable time OEx to Bus 2 12 ns tPLZ Output disable time OEx to Bus high impedance 2 15 ns tPHZ Output disable time OEx to Bus high impedance 2 15 ns tPZL2 Output enable time DIRx to Bus 2 12 ns tPZH2 Output enable time DIRx to Bus 2 12 ns tPLZ2 Output disable time DIRx to Bus high impedance 2 15 ns tPHZ2 Output disable time DIRx to Bus high impedance 2 15 ns tSLH3 Skew between outputs (40pF +/- 10 pF on each output) 0 900 ps tSHL3 Skew between outputs (40pF +/- 10 pF on each output) 0 900 ps Notes: 1. All specifications valid for radiation dose ≤ 1E5 rad(Si) per MIL-STD-883, Method 1019. 2. DIRx to bus times are guaranteed by design, but not tested. OEx to bus times are tested 3. Output skew is defined as a comparison of any two output transitions high-to-low vs. high-to-low and low-to-high vs. low-to-high Propagation Delay Input tPLH VDD VDD/2 0V tPHL VOH VDD/2 VOL Output Enable Disable Times Control Input 3.3V Output Normally Low 3.3V Output Normally High tPZL tPLZ VDD/2-0.2 tPZH tPHZ VDD/2+0.2 VDD/2-0.2 tPZH .8VDD - .2V tPLZ tPZL 2.5V Output Normally Low 2.5V Output Normally High .2VDD + .2V .2VDD + .2V tPHZ VDD/2+0.2 7 .7VDD - .2V VDD VDD/2 0V VDD/2 .2VDD .8VDD VDD/2 VDD/2 .2VDD .7VDD VDD/2 AC ELECTRICAL CHARACTERISTICS1 (Port A = Port B, 3.3 Volt Operation) (VDD1 = 3.0 to 3.6V; VDD2 = 3.0V to 3.6V, -55°C < TC < +125°C) SYMBOL PARAMETER MINIMUM MAXIMUM UNIT tPLH Propagation delay Data to Bus 2 7.5 ns tPHL Propagation delay Data to Bus 2 7.5 ns tPZL Output enable time OEx to Bus 2 10 ns tPZH Output enable time OEx to Bus 2 10 ns tPLZ Output disable time OEx to Bus high impedance 2 12 ns tPHZ Output disable time OEx to Bus high impedance 2 12 ns tPZL2 Output enable time DIRx to Bus 2 10 ns tPZH2 Output enable time DIRx to Bus 2 10 ns tPLZ2 Output disable time DIRx to Bus high impedance 2 12 ns tPHZ2 Output disable time DIRx to Bus high impedance 2 12 ns tSLH3 Skew between outputs (40pF +/- 10 pF on each output) 0 900 ps tSHL3 Skew between outputs (40pF +/- 10 pF on each output) 0 900 ps Notes: 1. All specifications valid for radiation dose ≤ 1E5 rad(Si) per MIL-STD-883, Method 1019. 2. DIRx to bus times are guaranteed by design, but not tested. OEx to bus times are tested 3. Output skew is defined as a comparison of any two output transitions high-to-low vs. high-to-low and low-to-high vs. low-to-high Propagation Delay Input tPLH VDD VDD/2 0V tPHL VOH VDD/2 VOL Output Enable Disable Times Control Input 3.3V Output Normally Low 3.3V Output Normally High tPZL tPLZ VDD/2-0.2 .2VDD + .2V tPHZ tPZH VDD/2+0.2 8 .8VDD - .2V VDD VDD/2 0V VDD/2 .2VDD .8VDD VDD/2 AC ELECTRICAL CHARACTERISTICS1 (Port A = Port B, 2.5 Volt Operation) (VDD1 = 2.3V TO 2.7V; VDD2 = 2.3V to 2.7V, -55°C < TC < +125°C) SYMBOL PARAMETER MINIMUM MAXIMUM UNIT tPLH Propagation delay Data to Bus 2 10 ns tPHL Propagation delay Data to Bus 2 10 ns tPZL Output enable time OEx to Bus 2 12 ns tPZH Output enable time OEx to Bus 2 12 ns tPLZ Output disable time OEx to Bus high impedance 2 15 ns tPHZ Output disable time OEx to Bus high impedance 2 15 ns tPZL2 Output enable time DIRx to Bus 2 12 ns tPZH2 Output enable time DIRx to Bus 2 12 ns tPLZ2 Output disable time DIRx to Bus high impedance 2 15 ns tPHZ2 Output disable time DIRx to Bus high impedance 2 15 ns tSLH3 Skew between outputs (40pF +/- 10 pF on each output) 0 900 ps tSHL3 Skew between outputs (40pF +/- 10 pF on each output) 0 900 ps Notes: 1. All specifications valid for radiation dose ≤ 1E5 rad(Si) per MIL-STD-883, Method 1019. 2. DIRx to bus times are guaranteed by design, but not tested. OEx to bus times are tested 3. Output skew is defined as a comparison of any two output transitions high-to-low vs. high-to-low and low-to-high vs. low-to-high Propagation Delay Input tPLH VDD VDD/2 0V tPHL VOH VDD/2 VOL Output Enable Disable Times Control Input 2.5V Output Normally Low 2.5V Output Normally High tPZL tPLZ VDD/2-0.2 tPZH .2VDD + .2V tPHZ VDD/2+0.2 9 .7VDD - .2V VDD VDD/2 0V VDD/2 .2VDD .7VDD VDD/2 PACKAGE 5 6 4 6 1. All exposed metalized areas are gold plated over electroplated nickel per MIL-PRF-38535. 2. The lid is electrically connected to VSS. 3. Lead finishes are in accordance with MIL-PRF-38535. 4. Lead position and colanarity are not measured. 5. ID mark symbol is vendor option. 6. With solder, increase maximum by 0.003. Figure 1. 48-Lead Flatpack 10 ORDERING INFORMATION UT54ACS162245SLV: SMD 5962 R 02543 01 * * * Lead Finish: (C) = Gold (A) = Solder Case Outline: (X) = 48 lead FP Class Designator: (Q) = Class Q (V) = Class V Device Type (01) = 16-bit MultiPurpose Low Voltage Transceiver Drawing Number: 02543 Total Dose: (R) = 1E5 rad(Si) (F) = 3E5 rad(Si) (G) = 5E5 rad(Si) (H) = 1E6 rad(Si) Federal Stock Class Designator Notes: 1. Total dose radiation must be specified when ordering. QML Q and QML V not available without radiation hardening. 11 UT54ACS162245SLV UT54 *** ****** * * * Lead Finish: (C) = Gold (A) = Solder Screening: (C) = HiRel Temp (P) = Prototype Package Type: (U) = 48-lead FP Part Number: (162245SLV) = 16-bit MultiPurpose Low Voltage Transceiver I/O Type: (ACS)= CMOS compatible I/O Level Aeroflex Core Part Number Notes: 1. HiRel Temperature Range flow per Aeroflex Colorado Springs Manufacturing Flows Document. Devices are tested -55C, room temp, and 125C. Radiation neither tested nor guaranteed. 2. Prototype flow per Aeroflex Colorado Springs Manufacturing Flows Document Tested at 25C only. Lead finish is gold only. Radiation neither tested nor guaranteed. 12 Aeroflex Colorado Springs - Datasheet Definition Advanced Datasheet - Product In Development Preliminary Datasheet - Shipping Prototype Datasheet - Shipping QML & Reduced Hi-Rel This product is controlled for export under the Export Administration Regulations (EAR). A license from the U.S. Government is required prior to the export of this product from the United States. www.aeroflex.com/HiRel [email protected] Aeroflex Colorado Springs, Inc. (Aeroflex) reserves the right to make changes to any products and services herein at any time without notice. Consult Aeroflex or an authorized sales representative to verify that the information in this data sheet is current before using this product. Aeroflex does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by Aeroflex; nor does the purchase, lease, or use of a product or service from Aeroflex convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual rights of Aeroflex or of third parties. Our passion for performance is defined by three attributes represented by these three icons: solution-minded, performance-driven and customer-focused 13