UT54ACS164646S MultiPurpose Registered Transceiver

Standard Products
UT54ACS164646S
Schmitt CMOS 16-bit Bidirectional MultiPurpose Registered Transceiver
Datasheet
May 17, 2012
www.aeroflex.com/16bitLogic
FEATURES
DESCRIPTION
 Flexible voltage operation
- 5V bus to 3.3V bus
- 3.3V bus to 5V bus
- 5V bus to 5V bus
- 3.3V bus to 3.3V bus
 Independent registers for A and B buses
 Multiplexed real-time and stored data
 Flow-through architecture optimizes PCB layout
 Cold- and Warm-sparing
- 750k minimum input impedance power-off
- Guranteed output tri-state while one power supply is "off"
and the other is "on"
 Schmitt trigger inputs to filter noisy signals
 All inputs are 5V tolerant regardless of power supply voltage
 m CRH CMOS Technology
 Operational Environment:
- Total dose: 100K rad(Si)
- Single Event Latchup immune>110 MeV-cm2/mg
The UT54ACS164646S is a 16-bit, MultiPurpose, registered,
level shifting, bus transceiver consisting of D-type flip-flops,
control circuitry, and 3-state outputs arranged for multiplexed
transmission of data directly from the data bus or from the
internal storage registers. The high-speed, low power
UT54ACS164646S transceiver is designed to perform multiple functions including: asynchronous two-way communication, signal buffering, voltage translation, cold- and warmsparing. The device can be used as two independant 8-bit
transceivers or one 16-bit transceiver. Data on the A or B bus
is clocked into the registers on the rising edge of the appropriate clock (xCLKAB or xCLKBA) input. With either VDD supply equal to zero volts, the UT54ACS164646S outputs and
inputs present a minimum impedance of 750k making it
ideal for “cold-spare” and "warm-spare" applications. By virtue of its flexible power supply interface, the
UT54ACS164646S may operate as a 3.3-volt only, 5-volt only,
or mixed 3.3V/5V bus transceiver.
- SEU Onset LET >75 MeV-cm2/mg
 High speed, low power consumption
 Available QML Q or V processes
 Standard Microcircuit Drawing: 5962-06234
 Package:
- 56-pin ceramic flatpack
The Output-enable (xOE) and direction-control (xDIR) inputs
are provided to control the tri-state function and input/output
direction of the transceiver respectively. The select controls
(xSAB and xSBA) select whether stored register data or realtime data is driven to the outputs as determined by the xDIR
inputs. The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the
transition between stored and real-time data. Regardless of the
selected operating mode ("real-time" or "recall"), a rising edge
on the port input clocks (xCLKAB and xCLKBA) will latch
the corresponding I/O states into their respective registers.
Furthermore, when a data port is isolated (xOE = high), A-port
data may be stored into its corresponding register while B-port
data may be independantly stored into its corresponding registers. Therefore, when an output function is disabled, the input
function is still enabled and may be used to store and transmit
data. Lastly, only one of the two buses, xA-port or xB-port,
may be driven at a time.
PIN DESCRIPTION
Pin Names
Description
xOE
Output Enable Input (Active Low)
xDIR
Direction Control Inputs
xAx
Side A Inputs or 3-State Outputs (3.3V Port)
xBx
Side B Inputs or 3-State Outputs (5V Port)
xSAB
Select real-time or stored A bus data to B bus
xSBA
Select real-time or stored B bus data to A bus
xCLKAB
Store A bus data
xCLKBA
Store B bus data
1
56-Lead Flatpack
Pinout
LOGIC SYMBOL
1DIR
1
56
1OE
1CLKBA
2
55
1CLKAB
1SBA
3
54
1SAB
VSS
4
53
VSS
1B1
5
52
1A1
1B2
6
51
1A2
VDDB
7
50
VDDA
1B3
8
49
1A3
1CLKAB 55
54
1SAB
2
1CLKBA
3
1SBA
29
2OE
1B4
9
48
1A4
2DIR
28
1B5
10
47
1A5
11
46
VSS
1B6
12
45
1A6
1B7
13
44
1A7
2CLKAB
2SAB
2CLKBA
2SBA
30
VSS
1B8
14
43
1A8
2B1
15
42
2A1
2B2
16
41
2A2
2B3
17
40
2A3
VSS
18
39
1OE
1DIR
1B1
56
1
31
27
26
5
G3
3 EN1 (BA)
3 EN2 (AB)
C4
G5
C6
G7
G10
10 EN8 (BA)
10 EN9 (AB)
C11
G12
C13
G14
5
6D
7
1
VSS
1B2
2B4
19
38
2A4
1B3
2B5
20
37
2A5
2B6
21
36
2A6
1B4
1B5
VDDB
22
35
VDDA
2B7
23
34
2A7
2B8
24
33
2A8
VSS
25
32
VSS
2SBA
26
31
2SAB
2CLKBA
27
30
2CLKAB
2DIR
28
29
2OE
1B6
1B7
1B8
2B1
2B3
2B4
2B5
2B6
2B7
2B8
2
4D
52
2
7
51
8
49
9
10
12
13
14
15
8
16
17
19
20
21
23
24
12
12
>1
14
1 14
1A1
1
>1
6
13D
2B2
5
>1
1
11D
1A2
1A3
48
1A4
47
1A5
45
1A6
44
1A7
43
1A8
42
2A1
1
>1
9
41
2A2
40
2A3
38
2A4
37
2A5
36
2A6
34
2A7
33
2A8
POWER APPLICATION GUIDELINES
For proper operation connect power to all VDDx pins and
ground all VSS pins (i.e., no floating VDDx or VSS input pins).
By virtue of the UT54ACS164646S warm-spare feature, power
supplies VDDB and VDDA may be applied to the device in any
order. To ensure the device is in cold-spare mode, both supplies, VDDB and VDDA , must be equal to VSS +/- 0.3V. Warmspare operation is in effect when one power supply is >1V and
the other power supply is equal to VSS +/- 0.3V. If VDDB has a
power-on ramp rate longer than 1 second, then VDDA should be
powered-on first to ensure proper control of xDIR and xOE.
During normal operation of the part, after power-up, ensure
VDDB > VDDA.
POWER TABLE
Port B
Port A
OPERATION
5 Volts
3.3 Volts
Voltage Translator
5 Volts
5 Volts
Non Translating
3.3 Volts
3.3 Volts
Non Translating
VSS
VSS
Cold Spare
VSS
3.3V or 5V
Port A Warm Spare
3.3V or 5V
VSS
Port B Warm Spare
I/O GUIDELINES
Control signals xDIR, xOE, xSAB, xSBA, xCLKAB, and
xCLKBA are powered by VDDA. All inputs are 5-volt tolerant.
When VDD2 is at 3.3 volts, either 3.3 or 5-volt CMOS logic
levels can be applied to all control inputs. Control signals
DIRx, /OEx, xSAB, xSBA, xCLKAB, and xCLKBA are powered by VDDA. All inputs are 5-volt tolerant. Additionally, it
is recommended that all unused inputs be tied to VSS through
a 1K to 10K resistor. It's good design practice to tie the unused input to VSS via a resistor to reduce noise susceptibility.
The resistor protects the input pin by limiting the current from
high going variations in VSS. The number of inputs that can be
tied to the resistor pull-down can vary. It is up to the system designer to choose how many inputs are tied together by figuring
out the max load the part can drive while still meeting system
performance specs. Input signal transitions should be driven to
the device with a rise and fall time that is <100ms.
By definition, warm sparing occurs when half of the chip receives its normal VDD supply value while the VDD supplying
the other half of the chip is set to 0.0V. When the chip is ’warm
spared’, the side that has its VDD set to a normal operational
value is ’actively’ tristated because the chip’s internal OE signal is forced low. The side of the chip that has VDD set to 0.0V
is ’passively’ tristated by the cold spare circuitry.
In order to minimize transients and current consumption, the
user is encouraged to first apply a high level to the xOE pins
and then power down the appropriate supply.
FUNCTION TABLE
Data I/O+
Inputs
xA1-xA8
Operation or Function
xOE
xDIR
xCLKAB
xCLKBA
xSAB
xSBA
xB1-xB8
X
X

X
X
X
Input
Unspecified
Store A, B unspecified+
X
X
X

X
X
Unspecified
Input
Store B, A unspecified+
H
X


X
X
Input
Input
Store A and B data+
H
X
H or L
H or L
X
X
Input
Input
Isolation, hold storage
L
L
X
X
X
L
Output
Input
Real-time B data to A bus
L
L
X
H or L
X
H
Output
Input
Recall stored B data to A bus
L
H
X
X
L
X
Input
Output
Real-time A data to B Bus
L
H
H or L
X
H
X
Input
Output
Recall stored A data to B bus
+ The data-output functions may be enabled or disabled by various signals xOE or xDIR. Data-input functions are always enabled, i.e. data at the bus terminals is
stored on every low-to-high transition of the clock inputs.
3
LOGIC DIAGRAM
OE1
56
DIR1 1
1CLKAB 55
1SAB 54
1CLKBA 2
1SBA 3
SEL
ENB
Y
1B1 5
B
A
D Q
CLK
CLK
SEL
Q D
A
Y
B
1B2
1B3
1B4
1B5
1B6
1B7
1B8
OE2
6
8
9
10
12
13
14
52 1A1
ENB
51
49
48
47
45
44
43
Seven Channels Identical
To Channel One Above
1A2
1A3
1A4
1A5
1A6
1A7
1A8
29
DIR2 28
2CLKAB 30
2SAB 31
2CLKBA 27
2SBA 26
SEL
ENB
Y
2B1 15
B
A
D Q
CLK
CLK
SEL
Q D
A
Y
B
2B2
2B3
2B4
2B5
2B6
2B7
2B8
16
17
19
20
21
23
24
42 2A1
ENB
Seven Channels Identical
To Channel One Above
4
41
40
38
37
36
34
33
2A2
2A3
2A4
2A5
2A6
2A7
2A8
OPERATIONAL ENVIRONMENT 1
PARAMETER
LIMIT
UNITS
Total Dose
1.0E5
rad(Si)
SEL LET Threshold
>110
MeV-cm2/mg
SEU Onset LET Threshold4
>97 @4.5V, >74@ 3.0V
MeV-cm2/mg
SEU Error Rate2
Immune @4.5V, 6.3E-10 @3.0V
errors/bit-day
Neutron Fluence3
1.0E14
n/cm2
Notes:
1. Logic will not latchup during radiation exposure within the limits defined in the table.
2. Adams 90% worst case particle environment, geosynchronous orbit, 100mils of Aluminum shielding
3. Not tested, inherent of CMOS technology.
4. Core logic is driven by VDDB.
ABSOLUTE MAXIMUM RATINGS1
SYMBOL
PARAMETER
LIMIT (Mil only)
UNITS
VI/OB (Port B)2
Voltage any pin
-0.3 to 6.0
V
VI/OA (Port A)2
Voltage any pin
-0.3 to 6.0
V
VDDB
Supply voltage
-0.3 to 6.0
V
VDDA
Supply voltage
-0.3 to 6.0
V
TSTG
Storage Temperature range
-65 to +150
C
TJ
Maximum junction temperature
+175
C
JC
Thermal resistance junction to case
20
C/W
II
DC input current
10
mA
PD
Maximum power dissipation
250
mW
Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at
these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability and performance.
2. For cold spare mode (VDDx = VSS +/- 0.3V), VI/Ox may be -0.3V to the maximum recommended operating VDDx + 0.3V.
5
DUAL SUPPLY OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMIT
UNITS
VDDB1
Supply voltage
3.0 to 3.6 or 4.5 to 5.5
V
VDDA1
Supply voltage
3.0 to 3.6 or 4.5 to 5.5
V
VINB (Port B)2
Input voltage any pin
0 to VDDB
V
VINA (Port A)2
Input voltage any pin
0 to VDDA
V
TC
Temperature range
-55 to +125
C
Note:
1. During normal operation, VDDB > VDDA.
2. All input pins are 5-volt tolerant inputs powered by VDDA. Therefore, when VDDA is at 3.3 volts, either 3.3 or 5-volt CMOS logic levels can be applied to all control
inputs.
6
DC ELECTRICAL CHARACTERISTICS 1
(TC = -55C to +125C); Unless otherwise noted, Tc is per the temperature ordered.
SYMBOL
PARAMETER
CONDITION
VT +
Schmitt Trigger, positive going threshold2
VT-
Schmitt Trigger, negative going threshold2 VDDx from 3.0V to 5.5V
VH1
Schmitt Trigger range of hysteresis
VH2
IIN
MIN
VDDx from 3.0V to 5.5V
MAX
UNIT
.7VDDx
V
.3VDDx
V
VDDx from 4.5V to 5.5V
0.7
V
Schmitt Trigger range of hysteresis
VDDx from 3.0V to 3.6V
0.5
V
Input leakage current
VDDx from 3.6V to 5.5V
-1
1
A
-1
1
A
-5
7
A
-3
3
A
-200
200
mA
-100
100
mA
VDDx = 4.5V; IOL= 8mA
0.4
V
VDDx = 4.5V; IOL= 100A
0.2
VDDx = 4.5V
-55C, 25C
V
IOL= 12mA
+125C
0.4
0.55
VDDx = 3.0V; IOL= 8mA
0.5
V
VDDx = 3.0V; IOL= 100A
0.2
V
VDDx = 3.0V
-55C, 25C
IOL= 12mA
+125C
0.5
0.6
V
V
VIN = VDDx or VSS
IOZ
Three-state output leakage current
VDDx from 3.6 to 5.5
VIN = VDDx or VSS
ICS
IWS
Cold sparing input leakage current3
VIN = 5.5V
(any pin)
VDDB = VDDA = VSS
Warm sparing input leakage current3
VIN = 5.5; VDDA = 3V to 5.5V
(any pin)
& VDDB = VSS or
VDDB = 3V to 5.5V &
VDDA = VSS
IOS1
Short-circuit output current 6, 10
VO = VDDx or VSS
VDDx from 4.5 to 5.5
IOS2
Short-circuit output current 6, 10
VO = VDDx or VSS
VDDx from 3.0 to 3.6
VOL1
VOL2
VOL3
VOL4
Low-level output voltage4
Low-level output voltage4
Low-level output voltage4
Low-level output voltage4
7
SYMBOL
VOH1
VOH2
VOH3
VOH4
Ptotal1
PARAMETER
High-level output voltage4
High-level output voltage4
High-level output voltage4
High-level output voltage4
Power dissipation 5,7, 8
CONDITION
MIN
MAX
VDDx = 4.5V; IOH= -8mA
VDDx - 0.5
VDDx = 4.5V; IOH= -100A
VDDx - 0.2
VDDx = 4.5V
-55C, 25C
IOL= -12mA
+125C
VDDx - 0.6
VDDx - 0.7
V
V
VDDx = 3.0V; IOH= -8mA
VDDx - 0.6
V
VDDx = 3.0V; IOH= -100A
VDDx - 0.2
VDDx = 3.0V
-55C, 25C
VDDx - 0.8
IOL= -12mA
+125C
VDDx - 0.95
CL = 20pF
V
V
V
2.0
mW/
MHz
1.5
mW/
MHz
10
A
VDDB = VDDA = 4.5V to 5.5V
Ptotal2
Power dissipation 5, 7, 8
CL = 20pF
VDDB = VDDA = 3.0V to 3.6V
IDDQ
Standby Supply Current VDDB or VDDA
VIN = VDDx or VSS
Pre-Rad 25oC
VDDB = VDDA = 5.5V
Standby Supply Current VDDB or VDDA
UNIT
xOE = VDDA
100
Pre-Rad -55oC, +125oC
Standby Supply Current VDDB or VDDA
100
Post-Rad 25oC
CIN
Input capacitance 9
 = 1MHz
15
pF
15
pF
VDDx from 3.0V to 5.5V
COUT
Output capacitance9
 = 1MHz
VDDx from 3.0V to 5.5V
Notes:
* For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25×C per MIL-STD-883 Method 1019, Condition
A up to the maximum TID level procured.
1. All specifications valid for radiation dose  1E5 rad(Si) per MIL-STD-883, Method 1019.
2. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%, 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are
guaranteed to VIH(min) and VIL(max).
3. This parameter is uneffected by the state of xOE or xDIR.
4. Per MIL-PRF-38535, for current density  5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765
pF-MHz.
5. Guaranteed by characterization.
6. Not more than one output may be shorted at a time for maximum duration of one second.
7. Power does not include power contribution of any CMOS output sink current.
8. Power dissipation specified per switching output.
9.Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at
frequency of 1MHz and a signal amplitude of 50mV rms maximum.
10. Supplied as a design limit, but not guaranteed or tested.
8
AC ELECTRICAL CHARACTERISTICS*1 (Port B = 5 Volt, Port A = 3.3 Volt)
(VDDB = 5V 10%; VDDA = 3.3V 0.3V); Unless otherwise noted, Tc is per the temperature ordered.
SYMBOL
PARAMETER
MINIMUM
MAXIMUM
UNIT
tPLH1
Propagation delay Data to Bus
3.5
9
ns
tPHL1
Propagation delay Data to Bus
3.5
9
ns
tPLH2
xCLKABor xCLKBAto Bus
4.5
10.5
ns
tPHL2
xCLKABor xCLKB to Bus
4.5
10.5
ns
tPLH32
xSABor xSBA to Bus
4
10.5
ns
tPHL32
xSABor xSBA to Bus
4
10.5
ns
tPLH42
xSBA or xSAB  to Bus
4
10.5
ns
tPHL42
xSBA or xSAB  to Bus
4
10.5
ns
tPZH1
Output enable time xOE to Bus
4
10
ns
tPZL1
Output enable time xOE to Bus
4
10
ns
tPLZ1
Output disable time xOE to Bus high impedance
3
10
ns
tPHZ1
Output disable time xOE to Bus high impedance
3
10
ns
tPZH23
Output enable time xDIR to Bus
3
12
ns
tPZL23
Output enable time xDIR to Bus
3
12
ns
tPLZ23
Output disable time xDIR to Bus high impedance
3
12
ns
tPHZ23
Output disable time xDIR to Bus high impedance
3
12
ns
tSKEW4
Skew between outputs
800
ps
tOST5
Dfiferential skew between outputs
1500
ps
tPART6
Part to part skew
500
ps




Notes:
* For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25oC per MIL-STD-883 Method 1019, Condition
A up to the maximum TID level procured.
1. All specifications valid for radiation dose  1E5 rads(Si) per MIL-STD-883, Method 1019.
2. These parameters are measured with the internal output state of the storage register opposite to that of the bus input.
3. xDIR to bus times are guaranteed by design, but not tested. xOE to bus times are tested.
4. Output skew is defined as a comparison of any two output transitions of the same type at the saame temperature and voltage for the same port within the same byte:
1A1 through 1A8 are compared high-to-low versus high-to-low and low-to-high versus low-to-high; similarly 1B1 through 1B8 are compared, 2A1 through 2A8
are compared, and 2B1 through 2B8 are compared.
5. Differential output skew is defined as a comparison of any two output transitions of opposite types on the same type at the same temperature and voltage for the
same port within the same byte: 1A1 through 1A8 are compared high-to-low versus low-to-high; similarly 1B1 through 1B8 are compared, 2A1 through 2A8 are
compared, and 2B1 through 2B8 are compared.
6. Guaranteed by characterization, but not tested.
9
Propagation Delay
Input
VDDx
VDDx/2
0V
tPLHn
tPHLn
VOH
0.5VDDX + 0.2
Output
0.5VDDX - 0.2
VOL
Enable Disable Times
Control Input
VDDA
VDDA/2
0V
tPLZn
tPZLn
5V Output
Normally Low
5V Output
Normally High
3.3V Output
Normally Low
VDDx/2-0.2
.2VDDx + .2V
VDDB/2
.2VDDB
tPHZn
tPZHn
.8VDDB
.8VDDx - .2V
VDDx/2+0.2
VDDB/2
tPLZn
tPZLn
VDDx/2-0.2
.2VDDx + .2V
VDDA/2
.2VDDA
tPHZn
3.3V Output
Normally High
tPZHn
.7VDDA
VDDx/2+0.2
.7VDDx - .2V
AC Timing Waveforms for Level Translation
(e.g. VDDA = 3.3V +/- 0.3V and VDDB = 5V +/- 10%)
10
VDDA/2
AC ELECTRICAL CHARACTERISTICS*1 (Port A = Port B, 5 Volt Operation)
(VDDB = 5V 10%; VDDA = 5V +10%) (TC = -55C to +125C); Unless otherwise noted, Tc is per the temperature ordered
SYMBOL
PARAMETER
MINIMUM
MAXIMUM
UNIT
tPLH1
Propagation delay Data to Bus
3.5
7.5
ns
tPHL1
Propagation delay Data to Bus
3.5
7.5
ns
tPLH2
xCLKAB or xCLKBA to Bus
4
9
ns
tPHL2
xCLKAB or xCLKBA to Bus
4
9
ns
tPLH32
xSAB or xSBA  to Bus
3
8
ns
tPHL32
xSAB or xSBA to Bus
3
8
ns
tPLH42
xSBA
to Bus
3
8
ns
tPHL42
xSBA
to Bus
3
8
ns
tPZH1
Output enable time xOE to Bus
3.5
9
ns
tPZL1
Output enable time xOE to Bus
3.5
9
ns
tPLZ1
Output disable time xOE to Bus high impedance
3
8
ns
tPHZ1
Output disable time xOE to Bus high impedance
3
8
ns
tPZH23
Output enable time xDIR to Bus
3
11
ns
tPZL23
Output enable time xDIR to Bus
3
11
ns
tPLZ23
Output disable time xDIR to Bus high impedance
3
11
ns
tPHZ23
Output disable time xDIR to Bus high impedance
3
11
ns
tSKEW4
Skew between outputs
600
ps
tOST5
Differential output skew
1500
ps
tPART6
Part to part skew
500
ps

or xSAB


or xSAB

Notes:
* For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25oC per MIL-STD-883 Method 1019, Condition
A up to the maximum TID level procured.
1. All specifications valid for radiation dose  1E5 rads(Si) per MIL-STD-883, Method 1019.
2. These parameters are measured with the internal output state of the storage register opposite to that of the bus input.
3. xDIR to bus times are guaranteed by design, but not tested. xOE to bus times are tested.
4. Output skew is defined as a comparison of any two output transitions of the same type at the saame temperature and voltage for the same port within the same byte:
1A1 through 1A8 are compared high-to-low versus high-to-low and low-to-high versus low-to-high; similarly 1B1 through 1B8 are compared, 2A1 through 2A8
are compared, and 2B1 through 2B8 are compared.
5. Differential output skew is defined as a comparison of any two output transitions of opposite types on the same type at the same temperature and voltage for the
same port within the same byte: 1A1 through 1A8 are compared high-to-low versus low-to-high; similarly 1B1 through 1B8 are compared, 2A1 through 2A8 are
compared, and 2B1 through 2B8 are compared.
6. Guaranteed by characterization, but not tested.
11
Propagation Delay
VDDx
VDDx/2
0V
Input
tPLHn
Output
tPHLn
VOH
0.5VDDX + 0.2
0.5VDDX - 0.2
VOL
Enable Disable Times
Control Input
tPZLn
5V Output
Normally Low
5V Output
Normally High
tPLZn
VDDx/2-0.2
.2VDDx + .2V
tPHZn
tPZHn
VDDx/2+0.2
.8VDDx - .2V
AC Timing Waveforms for 5-Volt only operation
(e.g. VDDA = VDDB = 5V +/- 10%)
12
VDDx
VDDx/2
0V
VDDx/2
.2VDDx
.8VDDx
VDDx/2
AC ELECTRICAL CHARACTERISTICS*1 (Port A = Port B, 3.3 Volt Operation)
(VDDB = VDDA = 3.3V 0.3V) (TC = -55C to +125C); Unless otherwise noted, Tc is per the temperature ordered
SYMBOL
PARAMETER
MINIMUM
MAXIMUM
UNIT
tPLH1
Propagation delay Data to Bus
4
10
ns
tPHL1
Propagation delay Data to Bus
4
10
ns
tPLH2
xCLKAB or xCLKBA to Bus
4.5
12.5
ns
tPH2
xCLKAB or xCLKBA to Bus
4.5
12.5
ns
tPLH32
xSAB or xSBA to Bus
4.5
11
ns
tPHL32
xSAB or xSBA to Bus
4.5
11
ns
tPLH42
xSBA

to Bus
4.5
11
ns
tPHL42
xSBA

to Bus
4.5
11
ns
tPZH1
Output enable time xOE to Bus
4
11
ns
tPZL1
Output enable time xOE to Bus
4
11
ns
tPLZ1
Output disable time xOE to Bus high impedance
4
10
ns
tPHZ1
Output disable time xOE to Bus high impedance
4
10
ns
tPZH23
Output enable time xDIR to Bus
3
13
ns
tPZL23
Output enable time xDIR to Bus
3
13
ns
tPLZ23
Output disable time xDIR to Bus high impedance
3
13
ns
tPHZ23
Output disable time xDIR to Bus high impedance
3
13
ns
tSKEW4
Skew between outputs
700
ps
tOST5
Differential output skew
1500
ps
tPART6
Part to part skew
500
ps

or xSAB

or xSAB
Notes:
* For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25oC per MIL-STD-883 Method 1019, Condition
A up to the maximum TID level procured.
1. All specifications valid for radiation dose  1E5 rads(Si) per MIL-STD-883, Method 1019.
2. These parameters are measured with the internal output state of the storage register opposite to that of the bus input.
3. xDIR to bus times are guaranteed by design, but not tested. xOE to bus times are tested.
4. Output skew is defined as a comparison of any two output transitions of the same type at the saame temperature and voltage for the same port within the same byte:
1A1 through 1A8 are compared high-to-low versus high-to-low and low-to-high versus low-to-high; similarly 1B1 through 1B8 are compared, 2A1 through 2A8
are compared, and 2B1 through 2B8 are compared.
5. Differential output skew is defined as a comparison of any two output transitions of opposite types on the same type at the same temperature and voltage for the
same port within the same byte: 1A1 through 1A8 are compared high-to-low versus low-to-high; similarly 1B1 through 1B8 are compared, 2A1 through 2A8 are
compared, and 2B1 through 2B8 are compared.
6. Guaranteed by characterization, but not tested.
13
Propagation Delay
Input
Output
tPLHn
VDDx
VDDx/2
0V
tPHLn
VOH
0.5VDDX + 0.2
0.5VDDX - 0.2
VOL
Enable Disable Times
Control Input
3.3V Output
Normally Low
3.3V Output
Normally High
tPZLn
tPLZn
.2VDDx + .2V
VDDx/2-0.2
tPHZn
tPZHn
.2VDDx
.7VDDx
.7VDDx - .2V
VDDx/2+0.2
VDDx
VDDx/2
0V
VDDx/2
VDDx/2
AC Timing Waveforms for 3-Volt only operation
(e.g. VDDA = VDDB = 3.3V +/- 0.3V)
AC ELECTRICAL CHARACTERISTICS (Clock Input Timing Relationships)
SYMBOL
VDDA
VDDB
Clock Frequency
4.5
3.0
3.0
4.5
4.5
3.0
tP1
Clock Period
4.5
3.0
3.0
4.5
4.5
3.0
10
11.1
12.5
ns
tW1
Pulse duration. CLKAB or CLKBA high or low
4.5
3.0
3.0
4.5
4.5
3.0
3.5
5
5
ns
tSU
Setup time. A before CLKAB
rising edge or B before CLKBA
rising edge
Data High
4.5
3.0
3.0
4.5
4.5
3.0
2
3
3
ns
Data Low
4.5
3.0
3.0
4.5
4.5
3.0
1
2
2
4.5
3.0
3.0
4.5
4.5
3.0
1.5
1.5
1.5
fCLOCK1
tH
PARAMETER
Hold time. Bus A after CLKAB rising edge or Bus B after CLKBA
rising edge
1. Guaranteed by functional test.
14
MIN
MAX
UNIT
100
90
80
MHz
ns
Setup and Hold Timing
VDDx
VDDx/2
0V
CLOCK Input
tSU
tH
VOH
VDDx/2
VOL
Data Input
fCLOCK
Clock Pulse Width
VDDx
VDDx/2
0V
CLOCK Input
tW
AC ELECTRICAL CHARACTERISTICS (Input Rise and Fall Requirements)
(All Power Supply Ranges, -55C < TC < +125C)
SYMBOL
PARAMETER
MINIMUM
MAXIMUM
UNIT
trise1
Input rise time
--
100
ms
tfall1
Input fall time
--
100
ms
1. The input rise and fall parameter is guaranteed by characterization and is not tested.
INPUT RISE AND FALL TIMING:
0.9 * VDDx
Any
Input
0.9 * VDDx
0.1 * VDDx
0.1 * VDDx
tfall
trise
AC Test Load or Equivalent
VDDx
VDDx
100ohms
Dut
40pf
100ohms
VSS
Notes:
1. Equivalent test circuit means that DUT performance will be correlated and remain guaranteed to the applicable test circuit, above, whenever a test platform
15
change necessitates a deviation from the applicable test circuit.
PACKAGE
NOTE:
1. All exposed metalized areas must be gold plated 100 over electroplated nickel
underplating 100 microinches thick per MIL-PRF-38535.
2. Lead finish is in accordance with MIL-PRF-38535.
3. Seal ring is electrically connected to VSS.
4. Ceramic is dark alumina.
5. Letter designations are to cross-referenced to MIl-STD-1835.
6. Lead true position tolerance and coplanarity are not measured.
16
ORDERING INFORMATION
UT54ACS164646S
UT54
***
*******
-
*
*
*
Lead Finish: (Notes 1 & 2)
(A) = Solder
(C) = Gold
(X) = Factory Option (Gold or Solder)
Screening: (Notes 3 & 4)
(C) = HiRel Temperature (-55oC to +125oC)
(P) = Prototype
Package Type:
(U) = 56-Lead Bottom Brazed Flatpack
Part Number:
(164646S)= 16-Bit Bidirectional MultiPurpose Registered Transceiver
I/O Type:
(ACS)= CMOS Compatible I/O Level
Aeroflex High Reliability Logic Root Part Number
Notes:
1. Lead finish (A, C, or X) must be specified.
2. If an "X" is specified when ordering, then the part marking will match the lead finish and will be either "A" (solder) or "C" (gold).
3. Prototype flow per Aeroflex Colorado Springs Manufacturing Flows Document. Tested at 25oC only. Lead finish is GOLD ONLY. Radiation
neither tested nor guaranteed.
4. HiRel Temperature Range flow per Aeroflex Colorado Springs Manufacturing Flows Document. Devices are tested at -55oC, 25oC
and 125oC. Radiation neither tested nor guaranteed.
17
UT54ACS164646S: SMD
5962
*
06234
**
*
*
*
Lead Finish: (Notes 1 & 2)
(A) = Solder
(C) = Gold
(X) = Factory Option (Gold or Solder)
Case Outline:
(X) = 56-Lead Ceramic Bottom Brazed Flatpack
Class Designator:
(Q) = QML Class Q
(V) = QML Class V
Device Types:
(01) = 16-Bit Bidirectional MultiPurpose Registered Transceiver
Drawing Number: 5962-06234
Total Dose: (Note 3)
(R) = 1E5 rads(Si)
Federal Stock Class Designator: No Options
Notes:
1. Lead finish (A, C, or X) must be specified.
2. If an "X" is specified when ordering, then the part marking will match the lead finish and will be either "A" (solder) or "C" (gold).
3. Total dose radiation must be specified when ordering. QML-Q and QML-V are not available without radiation hardening.
18
Aeroflex Colorado Springs - Datasheet Definition
Advanced Datasheet - Product In Development
Preliminary Datasheet - Shipping Prototype
Datasheet - Shipping QML & Reduced Hi-Rel
COLORADO
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Tel: 719-594-8017
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www.aeroflex.com
[email protected]
Aeroflex Colorado Springs, Inc., reserves the right to make
changes to any products and services herein at any time
without notice. Consult Aeroflex or an authorized sales
representative to verify that the information in this data sheet
is current before using this product. Aeroflex does not assume
any responsibility or liability arising out of the application or
use of any product or service described herein, except as
expressly agreed to in writing by Aeroflex; nor does the
purchase, lease, or use of a product or service from Aeroflex
convey a license under any patent rights, copyrights,
trademark rights, or any other of the intellectual rights of
Aeroflex or of third parties.
Our passion for performance is defined by three
attributes represented by these three icons:
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