UT1553 BCRTMP - Aeroflex Microelectronic Solutions

UT1553 BCRTMP
FEATURES
p Register-oriented architecture to enhance
p Comprehensive MIL-STD-1553 dual-redundant Bus
p DMA memory interface with 64K addressability
p Eight mode select inputs configure the device for a
programmability
Controller (BC) and Remote Terminal (RT) functions
p Multiple message processing capability in BC and
p
p
p
p
wide variety of 1553 protocols: MIL-STD-1553A,
MIL-STD-1553B, McDonnell Douglas A3818,
A5232, A5690, Grumman Aerospace SP-G-151A
p Comprehensive Built-In-Test (BIT) includes:
Continuous on-line wrap-around test, off-line BIT,
special system wrap-around test
p Available in 144-pin pingrid array or 132-lead flatpack
packages
p Standard Microcircuit Drawing 5962-89501 available
- QML Q compliant
RT modes
Time tagging and message logging in RT mode
Automatic polling and intermessage delay in
BC mode
Programmable interrupt scheme and internally
generated interrupt history list
Remote terminal operations in ASD/ENASD-certified
(SEAFAC)
REGISTERS
HIGH-PRIORITY
STD PRIORITY LEVEL
STD PRIORITY PULSE
MASTER
RESET
12MHz
TIMRONA
TIMRONB
WRAP-AROUNDTEST
MULTIPLEXER
1553
DATA
CHANNEL
B
DUAL
CHANNEL
ENCODER/
DECODER
MODULE
TIMEOUT
STATUS
CURRENT BC BLOCK/
RT DESCRIPTOR SPACE
INTERRUPT
HANDLER
CLOCK &
RESET
LOGIC
1553
DATA
CHANNEL
A
CONTROL
POLLING COMPARE
BUILT-IN-TEST WORD
PARALLELTO-SERIAL
CONVERSION
BC PROTOCOL
&
MESSAGE
HANDLER
16
SERIAL-TOPARALLEL
CONVERSION
ADDRESS
GENERATOR
CURRENT COMMAND
INTERRUPT LOG
LIST POINTER
BUS
TRANSFER
LOGIC
HIGH-PRIORITY
INTERRUPT ENABLE
16
HIGH-PRIORITY
INTERRUPT STATUS
16
RT PROTOCOL
&
MESSAGE
HANDLER
16
DMA/CPU
CONTROL
DMA ARBITRATION
REGISTER CONTROL
16
STANDARD INTERRUPT
ENABLE
16
RT ADDRESS
BUILT-IN-TEST
START COMMAND
BUILTINTEST
RESET COMMAND
RT TIMER
RESET COMMAND
ACTIVITY STATUS/
OPERATIONAL MODE
ADDRESS
DUAL-PORT MEMORY CONTROL
PROGRAMMABLE STATUS
16
Figure 1. BCRTMP BlockDiagram
16
DATA
BCRTMP-1
Table of Contents
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
11.0
12.0
13.0
BCRTMP-2
INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1
Features - Remote Terminal (RT) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2
Features - Bus Controller (BC) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3
Features - Multiple Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
PIN IDENTIFICATION AND DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
INTERNAL REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
SYSTEM OVERVIEW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
SYSTEM INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.1
DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.2
Hardware Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.3
CPU Interconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.4
RAM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.5
Legalization Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.6
Transmitter/Receiver Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
REMOTE TERMINAL ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.1
RT Functional Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.1.1 RT Subaddress Descriptor Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.1.2 Message Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.1.3 Mode Code Descriptor Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.2
RT Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.3
RT Operational Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
BUS CONTROLLER ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.1
BC Functional Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.2
Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.3
BC Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.4
BC Operational Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7.5
BC Operational Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
MULTIPLE PROTOCOL OPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8.1
Operational Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8.1.1 Legalization Select (RT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8.1.2 Broadcast Option Select (BC, RT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8.1.3 RT Response Time Select (RT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8.1.4 Mode Code Option Select (BC, RT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.1.5 Status Word Option Select (RT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.1.6 Message Error Technique Select (RT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.1.7 Mode code with Data Select (BC, RT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.1.8 Remote Terminal Time Out Option Select (BC, RT) . . . . . . . . . . . . . . . . . . 43
8.2
Additional UT1553 BCRTMP Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.2.1 DOMC Do Mode Code Control Signal (RT) . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.2.2 Continuous Wrap-Around Circuitry (BC, RT) . . . . . . . . . . . . . . . . . . . . . . . 44
8.2.3 Stop Enable (BC, RT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8.2.4 Forced Busy (RT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8.2.5 ACTIVE Signal (RT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8.2.6 Transmitter Inhibit Signals (BC, RT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8.2.7 Immediate Clear Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8.2.8 Status Word Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
EXCEPTION HANDLING AND INTERRUPT LOGGING . . . . . . . . . . . . . . . . . . . . 46
MAXIMUM AND RECOMMENDED OPERATING CONDITIONS . . . . . . . . . . . . 50
DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
AC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
PACKAGE OUTLINE DRAWINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
1.0 INTRODUCTION
The monolithic CMOS UT1553 BCRTMP provides the
system designer with an intelligent solution to
MIL-STD-1553 multiplexed serial data bus design
problems. The UT1553 BCRTMP is a single-chip device
that implements two of the three defined MIL-STD-1553
functions - Bus Controller and Remote Terminal - and is
flexible enough to conform to many of the MIL-STD-1553
“industry standards” created between and including releases
of MIL-STD-1553A and MIL-STD-1553B. Designed to
reduce host CPU overhead, the BCRTMP’s powerful state
machines automatically execute message transfers, provide
interrupts, and generate status information. The BCRTMP’s
register-based architecture allows it to conform to the many
protocol options regarding status words, mode codes, use
of Broadcast, Message Error, and RT Response Time as
specified in the various “1553 standards.” Multiple registers
offer many programmable functions as well as extensive
information for host use. In the BC mode, the BCRTMP
uses a linked-list message scheme to provide the host with
message chaining capability. The BCRTMP enhances
memory use by supporting variable-size, relocatable data
blocks. In the RT mode, the BCRTMP implements timetagging and message history functions. It also supports
multiple (up to 128) message buffering and variable length
messages to any subaddress.
The UT1553 BCRTMP is an intelligent, versatile, and easy
to implement device -- a powerful asset to system designers.
1.1 Features - Remote Terminal (RT) Mode
Indexing
The BCRTMP is programmable to index or buffer messages
on a subaddress-by-subaddress basis. The BCRTMP, which
can index as many as 128 messages, can also assert an
interrupt when either the selected number of messages is
reached or every time a specified subaddress is accessed.
Variable Space Allocation
The BCRTMP can use as little or as much memory (up to
64K) as needed.
Selectable Data Storage
Address programmability within the BCRTMP provides
flexible data placement and convenient access.
Sequential Data Storage
The BCRTMP stores/retrieves, by subaddress, all messages
in the order in which they are transacted.
Sequential Message Status Information
The BCRTMP provides message validity, time-tag, and
word-count information, and stores it sequentially in a
separate, cross-referenced list.
Illegalizing Mode Codes and Subaddresses
The host can declare mode codes and subaddresses illegal
by setting the appropriate bit(s) in memory.
Programmable Interrupt Selection
The host CPU can select various events to cause an interrupt
with provision for high and standard priority interrupts.
Interrupt History List
The BCRTMP provides an Interrupt History List that
records, in the order of occurrence, the events that caused
the interrupts. The list length is programmable.
1.2 Features - Bus Controller (BC) Mode
Multiple Message Processing
The BCRTMP autonomously processes any number of
messages or lists of messages that may be stored in a 64K
memory space.
Automatic Intermessage Delay
When programmed by the host, the BCRTMP can delay a
host-specified time before executing the next message in
sequence.
Automatic Polling
When polling, the BCRTMP interrogates the remote
terminals and then compares their status word responses to
the contents of the Polling Compare Register. The BCRTMP
can interrupt the host CPU if an erroneous remote terminal
status word response occurs.
Automatic Retry
The BCRTMP can automatically retry a message on busy,
message error, and/or response time-out conditions. The
BCRTMP can retry up to four times on the same or on the
alternate bus.
Programmable Interrupt Selection
The host CPU can select various events to cause an interrupt
with provision for high and standard priority interrupts.
Interrupt History List
The BCRTMP provides an Interrupt History List that
records, in the order of occurrence, the events that caused
the interrupts. The list length is programmable.
Variable Space Allocation
The BCRTMP uses as little or as much memory (up to 64K)
as needed.
Selectable Data Storage
Address programmability within the BCRTMP provides
flexible data placement and convenient access.
BCRTMP-3
1.3 Features - Multiple Protocol
Since the inception of the loosely defined MIL-STD-1553A
in 1973, various “1553 standards” have developed, all with
their own peculiarities. The UT1553 BCRTMP addresses
MIL-STD-1553A, MIL-STD-1553B, McDonnell Douglas
A3818, McDonnell Douglas A5232, McDonnell Douglas
A5690, and Grumman Aerospace SP-G-151A. While the
part was designed with these “standards” specifically in
mind, the BCRTMP’s flexibility permits conformance to
nearly any conceivable “1553-like standard.” The basic
differences among the various “standards” fall into five
categories:
1) Status Word Definition
2) Mode Code Definition
3) Use of Broadcast
4) Message Error Handling
5) Remote Terminal (RT) Response Time
Status Word Definition
The BCRTMP can operate in a mode where the status word
is defined in strict conformance with MIL-STD-1553B, or
it can operate in a more flexible mode. In this flexible status
word mode, the user can program the individual status word
bits using internal registers.
BCRTMP-4
Mode Code Definition
The designer can place the BCRTMP in an operational mode
so that the device performs in strict conformance with the
mode code definitions for MIL-STD-1553B. The designer
may also opt not to automatically execute mode codes,
providing flexibility in mode code definition and
illegalization.
Use of Broadcast
The BCRTMP has a programmable mode option that allows
the user to determine whether to allow broadcast commands
in a system.
Message Error Handling
Some 1553 protocols (e. g., MIL-STD-1553B) consider any
message error reason to discard the entire message and
suppress status word transmission, while others
(e. g., McDonnell Douglas A3818) define the required
activity according to message error severity. The BCRTMP
can be programmed to conform to either requirement.
Remote Terminal (RT) Response Time
The BCRTMP offers two methods of legalization (Bus
Legalization and DMA Legalization), which the designer
selects depending on the required RT response time.
2.0 P IN IDENTIFICATION AND DESCRIPTION
BIPHASE OUT
TAZ
TAO
TBZ
TBO
53
52
57
56
(L13)
(M14)
(K13)
(M15)
BIPHASE IN
RAZ
RAO
RBZ
RBO
51
50
55
54
(N14)
(P14)
(L14)
(N15)
TERMINAL
ADDRESS**
RTA0
RTA1
RTA2
RTA3
RTA4
RTPTY
44
45
46
47
48
49
(P12)
(N11)
(P13)
(R14)
(N12)
(N13)
STDINTL
STDINTP
HPINT
TIMRONA
TIMRONB
ACTIVE
COMSTR
SSYSF
BCRTF
CHA/B
TEST
82
83
84
85
86
81
90
128
129
89
59
RD
WR
CS
AEN
BCRTSEL
LOCK
EXTOVR
MRST
MEMCSO
MEMCSI
RRD
RWR
62
63
61
60
87
15
88
7
69
64
70
71
(J15)
(H14)
(K15)
(J13)
(A13)
(M3)
(B11)
(K3)
(G15)
(H15)
(F15)
(G14)
BRDCAST
MC
LGLEN
LGLCMD
ERR
DOMC
122
123
127
124
125
126
(D1)
(F3)
(F1)
(F2)
(G2)
(G3)
LGL0
LGL1
LGL2
LGL3
LGL4
LGL5
LGL6
LGL7
LGL8
LGL9
LGL10
111
112
113
114
115
116
117
118
119
120
121
(C5)
(B3)
(A2)
(C4)
(C3)
(B2)
(C2)
(D2)
(E3)
(C1)
(E2)
DMAR
DMAG
DMAGO
DMACK
BURST
TSCTL
72
73
78
75
77
76
(F14)
(F13)
(E13)
(D15)
(D14)
(C15)
FBUSY
BUSYACK
79
80
(C14)
(B15)
STATUS
SIGNALS
CONTROL
SIGNALS
LEGALIZATION
SIGNALS
LEGALIZATION
BUS*
DMA
SIGNALS
FORCED BUSY
SIGNALS
*
**
+
++
***
Pin at high impedance when MRST is low.
Pin internally pulled up.
Pin at high impedance when not asserted.
Bidirectional pin.
Formerly MEMWIN.
(C13) +
(B14)
(B13) +
(B12)
(C11)
(D13)
(C10)
(G1)
(H2)
(A12)
(J14)***
**
**
**
**
+
+
(N6)
(P6)
(P7)
(N7)
(R6)
(R7)
(P8)
(R8)
(R9)
(R10)
(P9)
(P10)
(N10)
(R11)
(R12)
(R13)
24
25
26
27
28
29
30
31
36
37
38
39
40
41
42
43
A0 ++
A1 ++
A2 ++
A3 ++
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
(B10)
(B9)
(C9)
(A10)
(A9)
(B8)
(A8)
(A7)
(A6)
(B7)
(B6)
(C6)
(A5)
(A4)
(A3)
(B4)
91
92
93
94
95
96
97
102
103
104
105
106
107
108
109
110
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
DATA
LINES ++
(R4)23
(P5)22
(R3)21
(N5)20
(P4)19
(P3)18
(P2)17
(N3)16
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0
MODE
SELECT
INPUTS**
(P1)14
(N2)13
(L3)12
(M2)11
(N1)10
(M1)9
(L1)8
MDO6
MDO5
MDO4
MDO3
MDO2
MDO1
MDO0
MODE
OUTPUTS*
(K14)58
(E15)74
(J1)3
MCLK
MCLKD2
CLK
CLOCK
SIGNALS
(H3)132
(N9)34
(G13)67
(C7)100
VDD
VDD
VDD
VDD
POWER
(J3)1
(N8)33
(H13)66
(C8)99
VSS
VSS
VSS
VSS
GROUND
WRAPEN
WRAPF
ALTWRAP
WRAP-AROUND
TEST SIGNALS
(K2)6
(J2)5
(K1)4
( )
ADDRESS
LINES +
Pingrid array pin identification in parentheses.
Flatpack pin numbers not in parentheses.
Figure 2. BCRTMP Functional Pin Description
BCRTMP-5
Legend for TYPE and ACTIVE fields:
TUI = TTL input (pull-up)
AL = Active low
AH = Active high
ZL = Active low - inactive state is high impedance
TI = TTL input
TO = TTL output
TTO = Three-state TTL output
TTB = Bidirectional
Notes:
1. Address and data buses are in the high-impedance state when idle.
2. Flatpack pin numbers are same as LCC.
ADDRESS BUS
NAME
PIN NUMBER
F/P
PGA
A0
24
A1
TYPE
ACTIVE
N6
TTB
--
Bit 0 (LSB) of the Address bus
25
P6
TTB
--
Bit 1 of the Address bus
A2
26
P7
TTB
--
Bit 2 of the Address bus
A3
27
N7
TTB
--
Bit 3 of the Address bus
A4
28
R6
TTO
--
Bit 4 of the Address bus
A5
29
R7
TTO
--
Bit 5 of the Address bus
A6
30
P8
TTO
--
Bit 6 of the Address bus
A7
31
R8
TTO
--
Bit 7 of the Address bus
A8
36
R9
TTO
--
Bit 8 of the Address bus
A9
37
R10
TTO
--
Bit 9 of the Address bus
A10
38
P9
TTO
--
Bit 10 of the Address bus
A11
39
P10
TTO
--
Bit 11 of the Address bus
A12
40
N10
TTO
--
Bit 12 of the Address bus
A13
41
R11
TTO
--
Bit 13 of the Address bus
A14
42
R12
TTO
--
Bit 14 of the Address bus
A15
43
R13
TTO
--
Bit 15 (MSB) of the Address bus
BCRTMP-6
DESCRIPTION
DATA BUS
NAME
PIN NUMBER
F/P
PGA
D0
91
D1
D2
TYPE
ACTIVE
DESCRIPTION
B10
TTB
--
Bit 0 (LSB) of the Data bus
92
B9
TTB
--
Bit 1 of the Data bus
93
C9
TTB
--
Bit 2 of the Data bus
D3
94
A10
TTB
--
Bit 3 of the Data bus
D4
95
A9
TTB
--
Bit 4 of the Data bus
D5
96
B8
TTB
--
Bit 5 of the Data bus
D6
97
A8
TTB
--
Bit 6 of the Data bus
D7
102
A7
TTB
--
Bit 7 of the Data bus
D8
103
A6
TTB
--
Bit 8 of the Data bus
D9
104
B7
TTB
--
Bit 9 of the Data bus
D10
105
B6
TTB
--
Bit 10 of the Data bus
D11
106
C6
TTB
--
Bit 11 of the Data bus
D12
107
A5
TTB
--
Bit 12 of the Data bus
D13
108
A4
TTB
--
Bit 13 of the Data bus
D14
109
A3
TTB
--
Bit 14 of the Data bus
D15
110
B4
TTB
--
Bit 15 (MSB) of the Data bus
TYPE
ACTIVE
TERMINAL ADDRESS INPUTS
NAME
PIN NUMBER
F/P
PGA
RTA0
44
P12
TUI
--
Remote Terminal Address Bit 0 (LSB). The entire
RT address is strobed in at Master Reset. Verify it
by reading the Remote Terminal Address Register.
All the Remote Terminal Address bits are internally
pulled up.
RTA1
45
N11
TUI
--
Remote Terminal Address Bit 1. This is bit 1 of
the Remote Terminal Address.
RTA2
46
P13
TUI
--
Remote Terminal Address Bit 2. This is bit 2 of
the Remote Terminal Address.
RTA3
47
R14
TUI
--
Remote Terminal Address Bit 3. This is bit 3 of
the Remote Terminal Address.
RTA4
48
N12
TUI
--
Remote Terminal Address Bit 4. This is bit 4
(MSB) of the Remote Terminal Address.
RTPTY
49
N13
TUI
--
Remote Terminal (Address) Parity. This is an odd
parity input for the Remote Terminal Address.
DESCRIPTION
BCRTMP-7
CONTROL SIGNALS
NAME
PIN NUMBER
F/P
PGA
TYPE
ACTIVE
DESCRIPTION
RD
62
J15
TI
AL
Read. The host uses this in conjunction with CS to read an
internal BCRT register.
WR
63
H14
TI
AL
Write. The host uses this in conjunction with CS to write an
internal BCRTMP register.
CS
61
K15
TI
AL
Chip Select. This selects the BCRTMP when accessing
the BCRTMP’s internal register.
AEN
60
J13
TI
AH
Address Enable. The host CPU uses AEN to indicate to the
BCRTMP that the BCRTMP’s address lines can be asserted;
this is a precautionary signal provided to avoid address bus
crash. If not used, it must be tied high.
BCRTSEL
87
A13
TUI
--
LOCK
15
M3
TUI
AH
EXTOVR
88
B11
TUI
AL
MRST
7
K3
TI
AL
MEMCSO
69
G15
TO
AL
MEMCSI
64
H15
TUI
AL
Memory Chip Select In. Used in the pseudo-dual-port
RAM mode only, MEMCSI is received from the host and
is propagated through to the MEMCSO. This pin is
internally pulled high.
RRD
70
F15
TO
AL
RAM Read. In the pseudo-dual-port RAM mode, the host
uses this signal in conjunction with MEMCSO to read
from external RAM through the BCRTMP. It is also the
signal the BCRTMP uses to read from memory. It is
asserted following receipt of DMAG. When the BCRTMP
performs multiple reads, this signal is pulsed.
RWR
71
G14
TO
AL
RAM Write. In the pseudo-dual-port RAM mode, the
CPU and BCRTMP use this to write to external RAM.
This signal is asserted following receipt of DMAG. For
multiple writes, this signal is pulsed.
BCRTMP-8
BC/RT Select. This selects between either the Bus
Controller or Remote Terminal mode. The BC/RT Mode
Select bit in the Control Register overrides this input if
the LOCK pin is not high. This pin is internally
pulled high.
Lock. When set, this pin prevents internal changes
to the RT address and BC/RT mode select functions as
well as the Operation Mode select (MD7-MD0) functions.
This pin is internally pulled high.
External Override. Use this in multi-redundant
applications. Upon receipt, the BCRTMP aborts all
current activity. EXTOVR should be connected to
COMSTR output of the adjacent BCRTMP when used.
This pin is internally pulled high.
Master Reset. This resets all internal state machines,
encoders, decoders, and registers. The minimum pulse
width for a successful Master Reset is 500ns.
Memory Chip Select Out. This is the regenerated
MEMCSI input for external RAM during the pseudodual-port RAM mode. The BCRTMP also uses it to select
external memory during memory accesses.
STATUS SIGNALS
NAME
PIN NUMBER
F/P
PGA
TYPE
ACTIVE
DESCRIPTION
STDINTL
82
C13
TTO
ZL
Standard Interrupt Level. This is a level interrupt. It is
asserted when one or more events enabled in either the
Standard Interrupt Enable Register, RT Descriptor, or BC
Command Block occur. Resetting the Standard Interrupt
bit in the High-Priority Interrupt Status/Reset Register
clears the interrupt.
STDINTP
83
B14
TO
AL
Standard Interrupt Pulse. STDINTP pulses when an
interrupt is logged.
HPINT
84
B13
TTO
ZL
High Priority Interrupt. The High-Priority Interrupt level
is asserted upon occurance of events enabled in the High
Priority Interrupt Enable Register. The corresponding
bit(s) in the High-Priority Interrupt Status/Reset Register
reset HPINT.
TIMRONA
85
B12
TO
AL
Timer On - Channel A. When low, this pin indicates that
the BCRTMP is transmitting data. This output remains
active until the data transmission is complete or until the
internal fail-safe timer times out (at 660µs), indicating that
the transceiver should be disabled.
TIMRONB
86
C11
TO
AL
Timer On - Channel B. See TIMRONA description.
ACTIVE
81
D13
TO
AH
Activity on 1553 Bus. When high, this pin indicates
that the BCRTMP has detected a valid command to any
remote terminal address on the bus.
COMSTR
90
C10
TO
AL
SSYSF
128
G1
TI
AH
Subsystem Fail. Upon receipt, this signal propagates
directly to the RT 1553 status word and the BCRTMP
Status Register.
BCRTF
129
H2
TO
AH
BCRT Fail. this indicates a Built-In-Test (BIT) failure.
In the RT mode, the Terminal Flag bit in 1553 status word
is also set.
CHA/B
89
A12
TO
--
TEST
59
J14
TO
AL
(RT) Command Strobe. The BCRTMP asserts this
signal after receiving a valid command. The BCRTMP
deactivates it after servicing the command.
ChannelA/B. This indicates the active or last active
channel.
TEST. This pin is used as a factory test pin. (Formerly
MEMWIN.)
BCRTMP-9
BIPHASE INPUTS
NAME
PIN NUMBER
F/P
PGA
TYPE
ACTIVE
RAO
50
P14
TI
--
Receive Channel A One. This is the Manchester-encoded
true signal input from Channel A of the bus receiver.
DESCRIPTION
RAZ
51
N14
TI
--
Receive Channel A Zero. This is the Manchester-encoded
complementary signal input from Channel A of the bus
receiver.
RBO
54
N15
TI
--
Receive Channel B One. This is the Manchester-encoded
true signal input from Channel B of the bus receiver.
RBZ
55
L14
TI
--
Receive Channel B Zero. This is the Manchester-encoded
complementary signal input from Channel B of the bus
receiver.
BIPHASE OUTPUTS
NAME
PIN NUMBER
F/P
PGA
TYPE
ACTIVE
DESCRIPTION
TAO
52
M14
TO
--
Transmit Channel A One. This is the Manchesterencoded true output to be connected to the Channel A bus
transmitter input. This signal is idle low.
TAZ
53
L13
TO
--
Transmit Channel A Zero. This is the Manchesterencoded complementary output to be connected to the
Channel A bus transmitter input. This signal is idle low.
TBO
56
M15
TO
--
Transmit Channel B One. This is the Manchesterencoded true output to be connected to the Channel B bus
transmitter input. This signal is idle low.
K13
TO
--
Transmit Channel B Zero. This is the Manchesterencoded complementary output to be connected to the
Channel B bus transmitter input. This signal is idle low.
TBZ
BCRTMP-10
57
DMA SIGNALS
NAME
PIN NUMBER
F/P
PGA
TYPE
ACTIVE
DESCRIPTION
DMAR
72
F14
TTO
ZL
DMA Request. The BCRTMP issues this signal when access
to RAM is required. It goes inactive after receiving a DMAG
signal.
DMAG
73
F13
TI
AL
DMA Grant. This input to the BCRTMP allows the
BCRMTP to access RAM. It is recognized 45ns before
the rising edge of MCLKD2.
DMAGO
78
E13
TTO
AL
DMA Grant Out. If DMAG is received but not needed, it
passes through to this output.
DMACK
75
D15
TO
ZL
DMA Acknowledge. The BCRTMP asserts this signal to
confirm receipt of DMAG, it stays low until memory access
is complete.
BURST
77
D14
TO
AH
Burst (DMA Cycle). This indicates that the current
DMA cycle transfers at least two words; worst-case is five
words plus a “dummy” word.
TSCTL
76
C15
TO
AL
Three-State Control. This signal indicates when the
BCRTMP is actually accessing memory. The host
subsystem’s address and data lines must be in the highimpedance state when the signalis active. This signal assists
in placing the external data and address buffers into the highimpedance state.
BCRTMP-11
MODE SELECT INPUTS
MD7
PIN NUMBER
F/P
PGA
23
R4
MD6
22
P5
TUI
--
Mode 6. This input selects whether mode codes with
data are allowed in the selected 1553 protocol. When
this signal is high, the protocol does allow mode codes
with data. When this signal is low, the protocol does not
allow mode codes with data.
MD5
21
R3
TUI
--
Mode 5. This input selects the message error handling
technique. When this signal is high, the message error
handling technique is as defined in MIL-STD-1553B.
When the signal is low, the message error handling
technique is as defined in MACAIR A3818.
MD4
20
N5
TUI
--
Mode 4. This input selects between MIL-STD-1553A
and MIL-STD-1553B status word protocol. When this
signal is high, the selected status word protocol is the
“B” option. When this signal is low, the selected status
word protocol is the “A” option.
MD3
19
P4
TUI
--
Mode 3. This input selects between MIL-STD-1553A
and MIL-STD-1553B mode code protocol. When this
signal is high, the selected mode code protocol is the
“B” option. When this signal is low, the selected mode
code protocol is the “A” option.
MD2
18
P3
TUI
--
Mode 2. This input selects between MIL-STD-1553A
and MIL-STD-1553B RT Response Time protocol.
When this signal is high, the selected response time
protocol is the “B” option. This signal is low, the
selected response time protocol is the “A” option.
MD1
17
P2
TUI
--
Mode 1. This input selects whether broadcast is allowed.
When this signal is high, broadcast is allowed. When
this signal is low, broadcast is not allowed. When MD1
is low, RT address 11111 is treated like RT addresses
00000-11110.
MD0
16
N3
TUI
--
Mode 0. This input selects the legalization method.
When this signal is high, the DMA method of
legalization is used. When this signal is low, the
legalization bus is used.
NAME
BCRTMP-12
TYPE
ACTIVE
DESCRIPTION
TUI
--
Mode 7. This input selects between two Remote
Terminal Time Out (RTO) options. When this signal is
high, the selected RTO is 16µs. When this signal is low,
the selected RTO is 32µs.
MODE OUTPUTS
NAME
MD06
PIN NUMBER
F/P
PGA
14
P1
TYPE
ACTIVE
DESCRIPTION
TTO
--
Mode 6 Out. This output signal reflects the internal
state of Mode 6 (MD6).
MDO5
13
N2
TTO
--
Mode 5 Out. This output signal reflects the internal
state of Mode 5 (MD5).
MDO4
12
L3
TTO
--
Mode 4 Out. This output signal reflects the internal
state of Mode 4 (MD4).
MDO3
11
M2
TTO
--
Mode 3 Out. This output signal reflects the internal
state of Mode 3 (MD3).
MDO2
10
N1
TTO
--
Mode 2 Out. This output signal reflects the internal
state of Mode 2 (MD2).
MDO1
9
M1
TTO
--
Mode 1 Out. This output signal reflects the internal
state of Mode 1 (MD1).
MD00
8
L1
TTO
--
Mode 0 Out. This output signal reflects the internal
state of Mode 0 (MD0).
TYPE
ACTIVE
DESCRIPTION
TUI
AL
Forced Busy. This signal places the RT in a mode
where it will automatically respond to a command
with the Busy bit set in the RT status word. No DMA
memory bus accesses are necessary, and the memory
buses remain in the high-impedance state until the
busy mode is exited. If the RT is involved in a 1553
message transaction then entry into the busy state is
held off until completion of the last DMS associated
with that message. Upon entry into the busy state, the
BCRTMP asserts the BUSYACK signal.
TTO
--
FORCED BUSY SIGNAL
NAME
FBUSY
BUSYACK
PIN NUMBER
F/P
PGA
79
C14
80
N2
Busy Acknowledge. This signal indicates that the
BCRTMP has entered the Forced Busy state.
BCRTMP-13
WRAP-AROUND TEST SIGNALS
NAME
WRAPEN
PIN NUMBER
F/P
PGA
6
K2
TYPE
ACTIVE
DESCRIPTION
TUI
AL
Wrap-Around Enable. When this signal is low, thE
continuous wrap-around feature is enabled.
WRAPF
5
J2
TO
AH
Wrap Fail. When high, this pin indicates that the
continuous wrap-around circuitry has detected a
failure.
ALTWRAP
4
K1
TUI
AL
Alternate Wrap-Around. This signal, when used in
conjunction with WRAPEN, places the BCRTMP in
a special system diagnostic mode, where the two 1553
buses are connected by a stub, and commands
transmitted over one bus are received through the
continuous wrap circuitry on the other bus. This
permits off-line testing of both channels and the
associated 1553 interface components.
TYPE
ACTIVE
DESCRIPTION
TTO
--
Legalization bus bit 10. The Legalization bus bits 010 reflect bit times 19-9 of the current command (i.e.,
LGL10 = Current Command bit time 9 and LGL0 =
Current Command bit time19. This bus is used to
determine whether or not the command is legal. This
bus can also be used to selectively determine if autoexecution of a particular mode code is allowed.
LEGALIZATION BUS
LGL10
PIN NUMBER
F/P
PGA
121
E2
LGL9
120
C1
TTO
--
Legalization bus bit 9
LGL8
119
E3
TTO
--
Legalization bus bit 8
LGL7
118
D2
TTO
--
Legalization bus bit 7
LGL6
117
C2
TTO
--
Legalization bus bit 6
LGL5
116
B2
TTO
--
Legalization bus bit 5
LGL4
115
C3
TTO
--
Legalization bus bit 4. When the MACAIR A3818
method of error logging is selected, Legalization bus
bits 4-0 reflect the word count for the defective
data word.
LGL3
114
C4
TTO
--
Legalization bus bit 3
LGL2
113
A2
TTO
--
Legalization bus bit 2
LGL1
112
B3
TTO
--
Legalization bus bit 1
LG10
111
C5
TTO
--
Legalization bus bit 0
NAME
BCRTMP-14
LEGALIZATION SIGNALS
BRDCAST
PIN NUMBER
F/P
PGA
122
D‘
MC
123
F3
TTO
AH
Mode Code. When high, this pin indicates that the
current command is a mode command.
LGLEN
127
F1
TTO
AL
Legalization Bus Enable. When low, this pin enables
the user-supplied legalization logic (if the
Legalization bus is used).
LGLCMD
124
F2
TUI
AH
Legal Command. A high on this input signal indicates
to the BCRTMP that the current command is legal.
ERR
125
G2
TO
AL
Error. When low, this pin indicates that a data word
parity error or a Manchester error occurred in the
current command. When this signal is asserted, the
Legalization bus bits 4-0 contain the word count for
the defective data word.
DOMC
126
G3
TUI
AH
Do Mode Code. When high, this signal enables the
automatic execution of mode codes. When low, this
signal disables auto-execution.
NAME
TYPE
ACTIVE
DESCRIPTION
TTO
AH
Broadcast. When high, this pin indicates that the
current command is a broadcast command.
CLOCK SIGNALS
NAME
PIN NUMBER
F/P
PGA
TYPE
ACTIVE
DESCRIPTION
3
J1
TI
--
Clock. The 12MHz input clock requires a 50%
± 10% duty cycle with an accuracy of ± 0.01%. The
accuracy is required in order to meet the Manchester
encoding/decoding requirements of MIL-STD-1553.
MCLK
58
K14
TI
--
Memory Clock. This is the input clock frequency the
BCRTMP uses for memory accesses. The memory cycle
time is equal to two MCLK cycles. Therefore, RAM
access time is dependent upon the chosen MCLK
frequency (6MHz minimum, 12MHz maximum). Please
see the BCRTMP DMA timing diagrams in this data sheet.
MCLKD2
74
E15
TO
--
Memory Clock Divided by Two. This signal is the
Memory Clock input divided by two. It assists the
host subsystem in synchronizing DMA events.
CLK
BCRTMP-15
POWER AND
NAME
PIN NUMBER
F/P
PGA
VDD
132
H3
PWR
--
+5V
VDD
34
N9
PWR
--
+5V
VDD
67
G13
PWR
--
+5V
VDD
100
C7
PWR
--
+5V
VSS
1
J3
GND
--
Ground
VSS
33
N8
GND
--
Ground
VSS
66
H13
GND
--
Ground
VSS
99
C8
GND
--
Ground
BCRTMP-16
TYPE
ACTIVE
DESCRIPTION
3.0 INTERNAL REGISTERS
The BCRTMP’s internal registers (see table 1 on pages 2425) enable the CPU to control the actions of the BCRTMP
while maintaining low DMA overhead by the BCRTMP. All
functions are active high and ignored when low unless stated
otherwise. Functions and parameters are used in both RT
and BC modes except where indicated. Registers are
addressed by the binary equivalent of their decimal number.
For example, Register 1 is addressed as 0001B. Register
usage is defined as follows:
#0 Control Register
Bit
Number
Description
BITs 15-13
Reserved.
BIT 12
(BC,RT) MD7 (Mode 7). Remote Terminal Time-Out Option Select. When high, this bit selects a Remote
Terminal Time-Out that is nominally 32µs. When low, this bit selects a Remote Terminal Time-Out that is
nominally 16µs.
BIT 11
Enable External Override. For use in multi-redundant systems. This bit enables the EXTOVR pin.
BIT 10
BC/RT Select. This function selects between the Bus Controller and Remote Terminal operation modes. It
overrides the external BCRTSEL input setting if the Change Lock-Out function is not used. A reset operation
must be performed when changing between BC and RT modes. This bit is write-only.
BIT 9
(BC) Retry on Alternate Bus. This bit enables an automatic retry to operate on alternate buses. For example, if
on bus A, with two automatic retries programmed, the automatic retries occur on bus B.
BIT 8
(RT) Channel B Enable. When set, this bit enables Channel B operation.
(BC) No significance.
BIT 7
(RT) Channel A Enable. When set, this bit enables Channel A operation.
(BC) Channel Select A/B. When set, this bit selects Channel A.
BITs 6-5
(BC) Retry Count. These bits program the number (1-4) of retries to attempt. (00 = 1 retry, 11 = 4 retries)
BIT 4
(BC) Retry on Bus Controller Message Error. This bit enables automatic retries on an error the bus controller
detects (see the Bus Controller Architecture section, page 36).
BIT 3
(BC) Retry on Time-Out. This bit enables an automatic retry on a response time-Out condition.
BIT 2
(BC) Retry on Message Error. This bit enables an automatic retry when the Message Error bit is set in the RT’s
status word response.
BIT 1
(BC) Retry on Busy. This bit enables automatic retry on a received Busy bit in an RT status word response.
BIT 0
Start Enable. In the BC mode, this bit starts/restarts Command Block execution. In the RT mode, it enables the
BCRTMP to receive a valid command. RT operation does not start until a valid command is received. When
using this function:
•
•
Restart the BCRTMP after each Master Reset or programmed reset.
This bit is not readable; verify operation by reading bit 0 of the BCRTMP’s Status Register.
BCRTMP-17
#1 Status Register (Read Only)
These bits indicate the BCRTMP’s current status.
Bit
Number
Description
BIT 15
BIT 14
TEST. This bit reflects the inverse of the TEST output. It changes state simultaneously with theTEST output.
(RT) Remote Terminal Active. Indicates that the BCRTMP, in the Remote Terminal mode, is presently servicing
a command. This bit reflects the inverse of the COMSTR pin.
BIT 13
(RT) Dynamic Bus Control Acceptance. This bit reflects the state of the Dynamic Bus Control Acceptancebit
in the RT status word (see Register 10 on page 20).
BIT 12
(RT) Terminal Flag bit is set in RT status word. See also section 8.2.8.10.
BIT 11
(RT) Service Request bit is set in RT status word. See also section 8.2.8.4.
BIT 10
(RT) Busy bit is set in RT status word. See also section 8.2.8.7.
BIT 9
BIT is in progress.
BIT 8
Reset is in progress. This bit indicates that either a write to Register 12 has just occurred or the BCRTMP has
just received a Reset Remote Terminal (#01000) Mode Code. This bit remains set less than 1ms.
BIT 7
BC/(RT) Mode. Indicates the current mode of operation. A reset operation must be performed when changing
between BC and RT modes.
BIT 6
Channel A/B. Indicates either the channel presently in use or the last channel used.
BIT 5
Subsystem Fail Indicator. Indicates receiving a subsystem fail signal from the host subsystem on the
SSYSF input.
BITs 4-1
Reserved.
BIT 0
(BC) Command Block Execution is in progress. (RT) Remote Terminal is in operation. This bit reflects bit 0 of
Register 0.
#2 Current Command Block Register (BC)/Remote Terminal Descriptor Space Address Register (RT)
(BC) This register contains the address of the head pointer of the Command Block being executed. Accessing a new Command
Block updates it.
(RT) The host CPU initializes this register to indicate the starting location of the RT Descriptor Space. The host must allocate
320 sequential locations following this starting address. For proper operation, this location must start on an I x 512 decimal
address boundary, where I is an integer multiple.
#3 Polling Compare Register
In the polling mode, the CPU sets the Polling Compare Register to indicate the RT response word on which the BCRTMP
should interrupt. This register is 11 bits wide, corresponding to bit times 9 through 19 of the RT’s 1553 status word response.
The sync, Remote Terminal Address, and parity bits are not included (see the section on Polling, page 38).
#4 BIT (Built-In-Test) Word Register
The BCRTMP uses the contents of this register when it responds to the Transmit BIT Word Mode Code (#10011). In addition,
the BCRTMP writes to the two most significant bits of the BIT Word Register in response to either an Initiate Self-Test Mode
Code (RT mode) or a write to Register 11 (BIT Start Command) to indicate a BIT failure. If the BIT Word needs to be modified,
it can be read out, modified, then rewritten to this register. Note that if the processor writes a “1” to either bit 14 or 15 of this
register, it effectively induces a BIT failure. Also note that during normal RT operation, bits 10 through 13 of this register
indicate specific types of message errors, as shown below.
Bit
Number
BIT 15
BIT 14
BIT 13
BIT 12
BIT 11
BIT 10
BITs 9-0
BCRTMP-18
Description
Channel B failure.
Channel A failure.
Word Count Error.
Parity Error.
Manchester Error.
Remote Terminal Time-Out.
BIT Word. The least significant ten bits of the BIT Word are user programmable.
#5 Current Command Register (Read Only)
In the RT, this register contains the command currently being processed. When not processing a command, the BCRTMP stores
the last command/status word transmitted on the 1553 bus in this register. This register is updated only when bit 0 of Register 0
is set. In the BC mode, this register contains the most current command sent out on the 1553 bus.
#6 Interrupt Log List Pointer Register
Initialized by the CPU, the Interrupt Log List Pointer Register indicates the start of the Interrupt Log List. After each list entry,
the BCRTMP updates this register with the address of the next entry in the list. (See page 46-47.)
#7 High-Priority Interrupt Enable Register (Read/Write)
Setting the bits in this register causes a High-Priority Interrupt when the enabled event occurs. If enabled in Register 14, setting
these bits also determines which events trigger the Stop Enable feature. To service the High-Priority Interrupt, the user reads
Register 8 to determine the cause of the interrupt, then writes to Register 8 to clear the appropriate bits. The BCRTMP also
provides a Standard Priority Interrupt Scheme that does not require host intervention. If High-Priority Interrupt service is not
possible in a given application, it is advisable to use the Standard Priority features.
Bit
Number
Description
BITs 15-9
Reserved.
BIT 8
Data Overrun Enable. When set, this bit enables an interrupt when DMAG was not received by the BCRTMP
within the allotted time needed for a successful data transfer to memory.
BIT 7
(BC) Illogical Command Error Enable. This bit enables a High-Priority Interrupt to be asserted upon the
occurrence of an Illogical Command. Illogical commands include incorrectly formatted RT-RT Command
Blocks.
BIT 6
(RT) Dynamic Bus Control Mode Code Interrupt Enable. When set, an interrupt is asserted when the Dynamic
Bus Control Mode Code is received, provided the T/R bit is “1,” the command is legal, and DOMC is active.
BIT 5
Subsystem Fail Enable. When set, a High-Priority Interrupt is asserted after receiving a Subsystem Fail
(SSYSF) input pin.
BIT 4
End of BIT Enable. This bit indicates the end of the internal BIT routine.
BIT 3
BIT Word Fail Enable. This bit enables an interrupt indicating that the BCRTMP detected a BIT failure.
BIT 2
(BC) End of Command Block List Enable (see Command Block Control Word, page 38.) This interrupt can be
superseded by other high-priority interrupts.
BIT 1
Message Error Enable. If enabled, a High-Priority Interrupt is asserted at the occurrence of a message error. If a
High-Priority Interrupt condition occurs, as the result of an enabled message error, the device will halt operation
until the user clears the interrupt by writing a “1” to bit 1 of the High-Priority Interrupt Status/Reset Register
(Reg. #8). If this interrupt is not cleared, the BCRTMP remains in the HALTED state (appearing to be “locked
up”), even if it receives a valid message. This High-Priority Interrupt scheme is necessary in order to maintain the
BCRT MP’s state of operation so that the host CPU has this information available at the time of interrupt service.
BIT 0
Standard Interrupt Enable. Setting this bit enables the STDINTL pin, but does not cause a high-priority
interrupt. If the user wants the Stop Enable feature activated for Standard Interrupts, this bit must be set. If low,
only the STDINTL pin is asserted when a Standard Interrupt occurs.
BCRTMP-19
#8 High-Priority Interrupt Status/Reset Register
When a High-Priority Interrupt is asserted, this register indicates the event that caused it. To clear the interrupt signal and reset
the bit, write a “1” to the appropriate bit. See the corresponding bit definitions of Register 7, High-Priority Interrupt Enable Register.
Bit
Number
Description
BITs 15-9
Reserved.
BIT 8
Data Overrun.
BIT 7
Illogical Command.
BIT 6
Dynamic Bus Control Accepted.
BIT 5
Subsystem Fail.
BIT 4
End of BIT.
BIT 3
BIT Word Fail.
BIT 2
End of Command Block.
BIT 1
Message Error.
BIT 0
Standard Interrupt. The BCRTMP sets this bit when any Standard Interrupt occurs, providing bit 0 of Register 7
is enabled.
#9 Standard Interrupt Enable Register
This register enables Standard Interrupt logging for any of the following enabled events (Standard Interrupt logging can also
occur for events enabled in the BC Command Block or RT Subaddress/Mode Code Descriptor):
Bit
Number
Description
BITs 15-6
Reserved.
BIT 5
(RT) Illegal Broadcast Command. When set, this bit enables an interrupt indicating that an Illegal Broadcast
Command has been received.
BIT 4
(RT) Illegal Command. When set, this bit enables an interrupt indicating that an illegal command has been
received.
BIT 3
(BC) Polling Comparison Match. This enables an interrupt indicating that a polling event has occurred. The user
must also set bit 12 in the BC Command Block Control Word for this interrupt to occur.
BIT 2
(BC) Retry Fail. This bit enables an interrupt indicating that all the programmed number of retries have failed.
BIT 1
(BC, RT) Message Error Event. This bit enables a standard interrupt for message errors.
BIT 0
(BC) Command Block Interrupt and Continue. This bit enables an interrupt indicating that a Command Block,
with the Interrupt and Continue Function enabled, has been executed.
BCRTMP-20
#10 Remote Terminal Address Register
This register sets the Remote Terminal Address via software. The Change Lock-Out Enable feature, when set, prevents the Remote
Terminal Address or the BCRTMP Mode Selection from changing. Note that MD4 also controls the effect of BITs 9-15 on status
word generation. See section 8.2.8.
Bit
Number
Description
BIT 15
(RT) Instrumentation. Setting this bit sets the RT status word Instrumentation bit.
BIT 14
(RT) Busy. Setting this bit sets the RT status word Busy bit. It does not inhibit data transfers to the subsystem.
BIT 13
(RT) Subsystem Fail. Setting this bit sets the RT status word Subsystem Flag bit. In the RT mode, the Subsystem
Fail is also logged into the Message Status Word.
BIT 12
(RT) Dynamic Bus Control Acceptance. Setting this bit sets the RT status word Dynamic Bus Control
Acceptance bit when the BCRTMP receives the Dynamic Bus Control Mode Code from the currently active Bus
Controller. Host intervention is required for the BCRTMP to take over as the active Bus Controller.
BIT 11
(RT) Terminal Flag. Setting this bit sets the RT status word Terminal Flag bit; the Terminal Flag bit in the RT
status word is also internally set if the BIT fails.
BIT 10
(RT) Service Request. Setting this bit sets the RT status word Service Request bit.
BIT 9
(RT) Busy Mode Enable. Setting this bit sets the RT status word Busy bit and inhibits all data transfers to the
subsystem. (See Forced Busy Mode, section 8.2.4.)
BIT 8
BC/RT Mode Select. This bit’s state reflects the external pin BCRTSEL. It does not necessarily reflect the state
of the chip, since the BC/RT Mode Select is software-programmable via bit 10 of Register 0. This bit is
read-only.
BIT 7
Change Lock-Out. This bit’s state reflects the external pin LOCK. When set, this bit indicates that changestothe
RT address or the BC/RT Mode Select are not allowed using internal registers. This bit is read-only.
BIT 6
Remote Terminal Address Parity Error. This bit indicates a Remote Terminal Address Parity error. It appears
after the Remote Terminal Address is latched if a parity error exists.
BIT 5
Remote Terminal Address Parity. This is an odd parity input bit used with the Remote Terminal Address. It
ensures accurate recognition of the Remote Terminal Address.
BITs 4-0
Remote Terminal Address (Bit 0 is the LSB). This reflects the RTA4-0 inputs at Master Reset. Modify the
Remote Terminal Address by writing to these bits.
#11 BIT Start Register (Write Only)
Any write (i.e., data = don’t care) to this register’s address location initiates the internal BIT routine, which lasts
100µs. Verify using the BIT-in-Progress bit in the Status Register. If the BCRTMP is online (Bit 0 of Register 1 is high), a
programmed reset (write to Register 12) must precede a write to this register to initiate the internal BIT.
The BCRTMP’s self-test performs an internal wrap-around test between its Manchester encoder and its two Manchester decoders.
If the BCRTMP detects a failure on either the primary or the secondary channel, it flags this failure by setting bit 14 of Register
4 (BIT Word Register) for Channel A and/or bit 15 for Channel B. When in the Remote Terminal mode, while the BCRTMP is
performing its self-test, it ignores any commands on the 1553 bus until it has completed the self-test.
#12 Programmed Reset Register (Write Only)
Any write (i.e., data = don’t care) to this register’s address location initiates a reset sequence of the encoder/decoder and protocol
sections of the BCRTMP which lasts less than 1µs. This is identical to the reset used for the Reset Remote Terminal Mode Code
except that command processing halts. For a total reset (i.e., including registers), see the MRST signal description.
#13 RT Timer Reset Register (Write Only)
Any write (i.e., data = don’t care) to this register’s address location resets the RT Time Tag timer to zero. The BCRTMP’s Remote
Terminal Timer time-tags message transactions. The time tag is generated from a free-running eight-bit timer of 64µs resolution.
This timer can be reset to zero simply by writing to Register 13. When the timer is reset, it immediately starts running.
BCRTMP-21
#14 Activity Status/Operational Mode Register
Bit
Number
Description
BITs 15-14
Reserved.
BIT 13
Ignore T/R bit in Mode Command. When high, this bit causes the BCRTMP to ignore the value of the T/R bit in
1553 Mode Commands 0-15 (mode codes without data) and prevents automatic execution of modes 18-19. This
feature is used in conjunction with Operational Mode 6 (input pin MD6).
BIT 12
Stop Enable. When the BCRTMP is in the RT mode, this bit enables a feature that places the BCRTMP into the
Forced Busy Mode when an interrupt (either Standard or High-Priority) occurs. When the BCRTMP enters the
Forced Busy Mode, the device responds with the Busy bitset in the 1553 status word any time a valid 1553
command is received. When the interrupt iscleared, the BCRTMP exits the Forced Busy Mode.
For BC operation, setting the Stop Enable bit causes the BCRTMP to halt Command Block execution when an
enabled interrupt (either Standard or High-Priority) occurs. Command Block execution resumes when the user
clears the interrupt by writing a “1” to the appropriate bit in Register 8.
BIT 11
Bus B Active. This bit goes high when the BCRTMP, acting as a Remote Terminal, receives a valid 1553 command
on the secondary bus.
BIT 10
Bus A Active. This bit goes high when the BCRTMP, acting as a Remote Terminal, receives a valid 1553 command
on the primary bus.
BIT 9
WRAPF Wrap-Around Test Fail. This bit reflects the state of the WRAPF output signal.
BIT 8
ALTWRAP Alternate Channel Wrap-Around Test Enable. After Master Reset, this bit reflects the complement of
the state of the ALTWRAP input signal. This bit can be software-modified if the LOCK pin is low. Thus, to enable
the ALTWRAP feature, write a one to this bit location.
BIT 7
WRAPEN Wrap-Around Test Enable. After Master Reset, this bit reflects the complement of the state of the
WRAPEN input signal. This bit can be software-modified if the LOCK pin is low. Thus, to enable the WRAPEN
feature, write a one to this bit location.
BIT 6
MD6 Operational Mode 6. After Master Reset, this bit reflects the state of the corresponding input pin (MD6).
See section 8.1.7 for a summary of Operational Mode 6. This bit can be software-modified if the LOCK pin is low.
BIT 5
MD5 Operational Mode 5. After Master Reset, this bit reflects the state of the corresponding input pin (MD5).
See section 8.1.6 for a summary of Operational Mode 5. This bit canbe software-modified if the LOCK pin
is low.
BIT 4
MD4 Operational Mode 4. After Master Reset, this bit reflects the state of the corresponding input pin (MD4).
See section 8.1.5 for a summary of Operational Mode 4. This bit canbe software-modified if the LOCK pin
is low.
BIT 3
MD3 Operational Mode 3. After Master Reset, this bit reflects the state of the corresponding input pin (MD3).
See section 8.1.4 for a summary of Operational Mode 3. This bit canbe software-modified if the LOCK pin
is low.
BIT 2
MD2 Operational Mode 2. After Master Reset, this bit reflects the state of the corresponding input pin (MD2).
See section 8.1.3 for a summary of Operational Mode 2. This bit can be software-modified if the LOCK pin is low.
BIT 1
MD1 Operational Mode 1. After Master Reset, this bit reflects the state of the corresponding input pin (MD1).
See section 8.1.2 for a summary of Operational Mode . This bit can be software-modified if the LOCK pin is low.
BIT 0
MD0 Operational Mode 0. After Master Reset, this bit reflects the state of the corresponding input pin (MD0).
See section 8.1.1 for a summary of Operational Mode 0. This bit canbe software-modified if the LOCK pin
is low.
BCRTMP-22
#15 Programmable Status/Last Status Word Register (RT)
This register provides control of and access to the RT Status Word. Bits 15-12 (read/write) allow for special operations on some
or all of the Status Word bits. Writing to bit 11 places the BCRTMP into the Forced Busy mode. Reading this bit will verify that
the BCRTMP has entered the Forced Busy mode (see section 8.2.4). Writing to the remaining bits (bits 10-0) of this register allows
control of the RT Status Word (see section 8.2.8). When reading from this register, bits 10-0 indicate the last Status Word sent by
the BCRTMP.
Bit
Number
Description
BIT 15
Immediate Clear Mode Enable. When set, this bit will cause the BCRTMP to automatically clear all programmable
status bits (bits 10-0 of this register and bits 15-9 of Register 10) after the BCRTMP transmits the RT Status Word.
When this bit is set, the first Status Word sent outcontains the Status Word created from the programmable status
bits in this register, Register 10, and from internally generated conditions (see section 8.2.8). After Status Word
transmission, the BCRTMP clears bits 10-0 of this register and bits 15-9 of Register 10. There is one exception to
this automatic status bit clearing. When the next command received is the Transmit Status Word or Transmit Last
Command mode code, the BCRTMP will respond with the appropriate Status Word from the previous valid
command. This feature applies to all operational modes. Note that inhibition of the Terminal Flag bit (receipt of
Mode Code 6) is also cleared by this bit.
BIT 14
Automatic Terminal Flag Bit Enable, Option 1. When set, this bit will cause the Terminal Flag to be automatically
set when any of the Status Word field bits are set (Status Word bit times 9 through 18).
BIT 13
Automatic Terminal Flag Bit Enable, Option 2. When set, this bit will cause the Terminal Flag to be automatically
set when the Busy or Subsystem Flag Status Word bits are set. If both bits 14 and 13 of this register are set,
neither option is selected, and the Busy bit will not be set by the Forced Busy mode. These automatic Terminal
Flag bit options apply for all operational modes.
BIT 12
Automatic Data Ready. This bit, when set, causes the BCRTMP to place the complement of the Busy Bit in the
Data Ready Bit (bit 8). Therefore, when the BCRTMP transmits the Status Word, bit 8 = NOT bit 3.
BIT 11
Forced Busy.
BIT 10
ME Message Error (Bit Time 9)/Last Status Word Message Error Bit.
BIT 9
PSBT10 Programmable Status Bit Time 10/Last Status Word Bit Time 10.
BIT 8
PSBT11 Programmable Status Bit Time 11/Last Status Word Bit Time 11.
BIT 7
PSBT12 Programmable Status Bit Time 12/Last Status Word Bit Time 12.
BIT 6
PSBT13 Programmable Status Bit Time 13/Last Status Word Bit Time 13.
BIT 5
PSBT14 Programmable Status Bit Time 14/Last Status Word Bit Time 14.
BIT 4
PSBT15 Programmable Status Bit Time 15/Last Status Word Bit Time 15.
BIT 3
PSBT16 Programmable Status Bit Time 16/Last Status Word Bit Time 16.
BIT 2
PSBT17 Programmable Status Bit Time 17/Last Status Word Bit Time 17.
BIT 1
PSBT18 Programmable Status Bit Time 18/Last Status Word Bit Time 18.
BIT 0
TF Terminal Flag (Bit Time 19)/Last Status Word Terminal Flag Bit.
BCRTMP-23
#0
BC/RT CONTROL REGISTER
15
14
UNUSED
7
CHNSEL
BUSAEN
#1
8
BUSBEN
4
3
2
1
0
RTYBCME
RTYTO
RTYME
RTYBSY
STEN
13
12
11
DYNBUS
RT FLAG
SRQ
10
BUSY
8
RESET
5
4
3
2
1
0
UNUSED
UNUSED
UNUSED
UNUSED
CMBKPG
(BC) CURRENT COMMAND BLOCK REGISTER
(RT) REMOTE TERMINAL DESCRIPTOR SPACE ADDRESS REGISTER
15
14
13
12
11
10
A14
A13
A12
A11
A10
9
8
A9
A8
7
6
5
4
3
2
1
0
A7
A6
A5
A4
A3
A2
A1
A0
POLLING COMPARE REGISTER
15
14
13
12
11
X
X
X
X
7
6
5
4
3
SWBT12
SWBT13
SWBT14
SWBT15
SWBT16
BIT WORD REGISTER
15
14
CHAFAIL
13
12
WCERR
PARERR
10
MSGERR
2
SWBT17
11
10
MANERR
RTTO
9
SWBT10
8
SWBT11
1
0
SWBT18
TF
9
8
D9
D8
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
CURRENT COMMAND REGISTER
15
14
13
12
11
10
D12
D11
D10
D14
D13
9
8
D9
D8
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
INTERRUPT LOG LIST POINTER REGISTER
15
14
13
12
A14
A13
A12
11
10
A11
A10
9
8
A9
A8
7
6
5
4
3
2
1
0
A7
A6
A5
A4
A3
A2
A1
A0
BCRTMP HIGH-PRIORITYINTERRUPT ENABLE REGISTER
15
14
13
12
11
UNUSED
UNUSED
7
6
ILLCMD
DYNBUS
UNUSED
5
SSFAIL
UNUSED
UNUSED
10
9
8
UNUSED
UNUSED
DATOVR
4
3
2
1
0
ENDBIT
BITFAIL
EOL
MSGERR
STDINT
Table 1. BCRTMP Registers
BCRTMP-24
9
BIT
SSFAIL
A15
#7
9
RTYALTB
6
D15
#6
10
BC/RT
BUSA/B
CHBFAIL
#5
RTACT
11
EXTOVR
7
X
#4
5
RTYCNT
12
RTO
BC/RT
A15
#3
13
UNUSED
6
BC/RT STATUS REGISTER
15
14
TEST
#2
UNUSED
#8
BCRTMP HIGH-PRIORITYINTERRUPT STATUS/RESET REGISTER
15
14
13
12
11
UNUSED
#9
7
6
ILLCMD
DYNBUS
#12
#13
#14
4
ENDBIT
UNUSED
UNUSED
UNUSED
UNUSED
3
BITFAIL
1
0
MSGERR
STDINT
9
8
UNUSED
UNUSED
5
4
3
ILLCMD
POLMTCH
DBC
2
EOL
10
ILLBCMD
SS FLAG
8
DATOVR
UNUSED
6
BUSY2
9
UNUSED
11
UNUSED
REMOTE TERMINAL ADDRESS REGISTER
15
14
13
12
10
UNUSED
UNUSED
7
2
RTYFAIL
1
0
MSGERR
CMDBLK
11
10
9
8
RT FLAG
SRQ
BUSY1
BC/RT
7
6
5
4
3
2
1
0
LOCK
PARERR
RTAPAR
RTA4
RTA3
RTA2
RTA1
RTA0
BUILT-IN-TEST START REGISTER
15
14
13
12
11
10
9
8
X
X
X
X
X
X
X
X
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
PROGRAMMED RESET REGISTER
15
14
13
12
11
10
9
8
X
X
X
X
X
X
X
X
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
REMOTE TERMINAL TIMER RESET REGISTER
15
14
13
12
11
10
9
8
X
X
X
X
X
X
X
X
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
ACTIVITY STATUS/OPERATIONAL MODE REGISTER
15
14
13
12
UNUSED
#15
5
SSFAIL
UNUSED
UNUSED
INSTR
#11
UNUSED
STANDARD INTERRUPT ENABLE REGISTER
15
14
13
12
UNUSED
#10
UNUSED
UNUSED
IGNORTR
STPEN
11
10
9
8
B ACT
A ACT
WRAPF
ALTWRAP
7
6
5
4
3
2
1
0
WRPEN
MD6
MD5
MD4
MD3
MD2
MD1
MD0
PROGRAMMABLE STATUS REGISTER
15
14
13
IMM CLR
TF OPT1
TF OPT2
12
11
10
9
8
PS8=NB
FBUSY
ME
PSBT10
PSBT11
7
6
5
4
3
2
1
0
PSBT12
PSBT13
PSBT14
PSBT15
PSBT16
PSBT17
PSBT18
TF
X = DON’T CARE
Table 1. BCRTMP Registers (continued from page 24)
BCRTMP-25
4.0 SYSTEM OVERVIEW
The BCRTMP can be configured for a variety of processor
and memory environments. The host processor and the
BCRTMP communicate via a flexible, programmable
interrupt structure, internal registers, and a user-definable
shared memory area. The shared memory area (up to 64K)
is completely user-programmable and communicates
BCRTMP control information -- message data, and status/
error information.
Built-in memory management functions designed
specifically for MIL-STD-1553 applications aid processor
off-loading. The host needs only to establish the parameters
within memory so the BCRTMP can access this information
as required. For example, in the RT mode, the BCRTMP can
store data associated with individual subaddresses
anywhere within its 64K address space. The BCRTMP then
can automatically buffer up to 128 incoming messages of
the same subaddress, thus preventing the previous messages
from being overwritten by subsequent messages. This
buffering also extends the intervals required by the host
processor to service the data. Selecting an appropriate
MCLK frequency to meet system memory access time
requirements controls the memory access rate. The
completion of a user-defined task or the occurrence of a
user-selected event is indicated by using the extensive set
of interrupts provided.
In the BC mode, the BCRTMP can process multiple
messages, assist in scheduling message lists, and provide
host-programmable functions such as auto retry. The
BCRTMP is incorporated in systems with a variety of
interrupt latencies by using the Interrupt History List feature
(see Exception Handling and Interrupt Logging, page 46).
RAM
CPU MEMORY
CONTROL SIGNALS
RRD
RWR
MEMCSO
BCRTMP
RD
WR
MEMCSI
Figure 3a. Pseudo-Dual-Port RAM
Control Signals
BCRTMP-26
The Interrupt History List sequentially stores the events that
caused the interrupt in memory without losing information
if a host processor does not respond immediately to
an interrupt.
5.0 SYSTEM INTERFACE
5.1 DMA Transfers
The BCRTMP initiates DMA transfers whenever it executes
command blocks (BC mode) or services commands (RT
mode). DMAR initiates the transfer and is terminated by the
inactive edge of DMACK. The Address Enable (AEN)
input enables the BCRTMP to output an address onto the
Address bus.
The BCRTMP requests transfer cycles by asserting the
DMAR output, and initiates them when a DMAG input is
received. A DMACK output indicates that the BCRTMP
has control of the Data and Address buses. The TSCTL
output is asserted when the BCRTMP is actually asserting
the Address and Data buses.
To support using multiple bus masters in a system, the
BCRTMP outputs the DMAGO signal that results from the
DMAG signal passing through the chip when a BCRTMP
bus request was not generated (DMAR inactive). You can
use DMAGO in daisy-chained multimaster systems.
5.2 Hardware Interface
The BCRTMP provides a simple subsystem interface and
facilitates DMA arbitration. The user can configure the
BCRTMP to operate in a variety of memory-processor
environments including pseudo-dual-port RAM and
standard DMA configurations.
For complete circuit description, such as arbitration logic
and I/O, please refer to the appropriate application note.
5.3 CPU Interconnection
Pseudo-Dual-Port RAM Configuration
The BCRTMP’s Address and Data buses connect directly
to RAM, with buffers isolating the BCRTMP’s buses from
those of the host CPU (figures 3a and 3b). The CPU’s
memory control signals (RD, WR, and MEMCSI) pass
through the BCRTMP and connect to memory as RRD,
RWR, and MEMCSO.
Standard DMA Configuration
The BCRTMP’s and CPU’s data, address, and control
signals are connected to each other as shown in figures 3c
and 3d. The RWR, RRD, and MEMCSO are activated after
DMAG is asserted.
In either case, the BCRTMP’s Address and Data buses
remain in a high-impedance state unless the CS and RD
signals are active, indicating a host register access; or
TSCTL is asserted, indicating a memory access by the
BCRTMP. CPU attempts to access BCRTMP registers are
ignored during BCRTMP memory access. Inhibit DMA
transfers by using the Busy function in the Remote Terminal
Address Register while operating in the Remote
Terminal mode.
The designer can use TSCTL to indicate when the BCRTMP
is accessing memory. AEN is also available (use is optional),
giving the CPU control over the BCRTMP’s Address bus.
A DMA Burst (BURST) signal indicates multiple
DMA accesses.
BUFFERS
16 DATA
RAM
HOST
CPU
16 ADDRESS
CONTROL
CONTROL/ARBITRATION
BCRTMP
(DUAL REDUNDANT)
TRANSMITTER
TIMEOUT
DUAL
TRANSCEIVER
XFMR
XFMR
BUS A
1553 BUS
BUS B
Figure 3b. CPU/BCRTMP Interface -- Pseudo-Dual-Port RAM Configuration
ADDRESS BUS
DMA
CPU
DMA
DMAC
BCRTMP
DATA BUS
RRD RWR
SHARED
MEMORY
AREA
OE
•
WE
•
CS
•
MEMCSO
Figure 3c. DMA Signals
BCRTMP-27
RAM
DATA
ADDRESS
BCRTMP
MEMORY
BUFFER
CONTROL
CPU
ARBITRATION
DUAL
TRANSCEIVER
XFMR
XFMR
BUS A
1553 BUS
BUS B
Figure 3d. CPU/BCRTMP Interface -- DMA Configuration
Register Access
Registers 0 through 15 are accessed with the decode of the
four LSBs of the Address bus (A0-A3) and asserting CS.
Pulse either RD or WR for multiple register accesses.
5.4 RAM Interface
The BCRTMP’s RRD, RWR, and MEMCSO signals serve
as read and write controls during BCRTMP memory
accesses. The host subsystem signals RD, WR, and
MEMCSI propagate through the BCRTMP to becomeRRD,
RWR, and MEMCSO outputs to support a pseudo-dualport. During BCRTMP-RAM data transfers, the host
subsystem’s memory signals are ignored until the BCRTMP
access is complete.
BCRTMP-28
5.5 Legalization Bus
In the RT mode, when the UT1553 BCRTMP receives a
command on the 1553 bus, it must determine whether that
command is legal. The BCRTMP provides two methods for
the designer to accomplish this task. With the first method,
called DMA Legalization, the BCRTMP automatically
accesses a specific Descriptor Block when it receives a
command to a given subaddress (or mode code). This
Descriptor Block (see figure 4a) contains information that
the BCRTMP uses to determine if the command is legal or
illegal. With the second method, called Bus Legalization,
the 1553 Command Word, minus the RT Address, is routed
to the Legalization bus outputs of the BCRTMP (see figure
4b). The BCRTMP uses this information, for example, as a
PROM address. The single-bit output from the PROM then
feeds the LGLCMD input signal of the BCRTMP (see figure
4c). If the command is legal, the PROM output is high; if
the command is illegal, the PROM output is low. Figure 31
shows the required timing for the BCRTMP
Legalization bus.
BCRTMP
The Descriptor Pointer Register (Register
2) combined with the Command Word
generates the address of the Control
Word for the Descriptor Block fetch. The
Control Word contains Legalization
information.
DMA fetch of three words
when command is received.
RAM
Control Word
Message Status Pointer
First Receive Subaddress
Descriptor Block
Data List Pointer
Unused
Control Word
Message Status Pointer
Second Receive Subaddress
Descriptor Block
Data List Pointer
Unused
Control Word
Message Status Pointer
Last Mode Code
Descriptor Block
Data List Pointer
Unused
Figure 4a. BCRTMP Descriptor Block Legalization
BIT TIME
1553 Command Word
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
COMMAND
SYNC
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
P
RT ADDRESS
T/R
SUBADDRESS/
MODE
WORD COUNT
OR MODE CODE
LGL0
LGL1
LGL2
LGL3
COMBINATIONAL
LOGIC
LGL4
LGL5
LGL6
LGL7
LGL8
LGL9
LGL10
COMBINATIONAL
LOGIC
MC
BRDCAST
Figure 4b. BCRTMP Legalization Bus
BCRTMP-29
OPTIONAL FOR A3818 MESSAGE
ERROR LOGGING
FIFO
BCRTMP
DATA
OUT
SHIFT
OUT
SHIFT
IN
DATA
IN
ERR
LGL0 - LGL4
5
LEGALIZATION
BUS
LEGALIZATION
PROM
LGLEN
LGLCMD
5
MICROPROCESSOR
ADDRESS
DECODER
ADDRESS BUS
DATA BUS
RAM
Figure 4c. BCRTMP Bus Legalization Example
To facilitate on-board programming of the 5-volt
EEPROMs on the host board, the BCRTMP places the
Legalization bus into the high-impedance state when the
user asserts the MRST signal.
5.6 Transmitter/Receiver Interface
The BCRTMP’s Manchester II encoder/decoder interfaces
directly with the 1553 bus transceiver, using the TAO-TAZ
and RAZ-RAO signals for Channel A, and TBO-TBZ and
RBZ-RBO signals for Channel B.
The BCRTMP also provides TIMRONA and TIMRONB
signal outputs and an active channel output indicator
(CHA/B) to assist in meeting the MIL-STD-1553B fail-safe
timer requirements (see figure 5).
BCRTMP
TIMRONB
TIMRONA
CHANNEL A
CHANNEL A
TXINHA
CHANNEL B CHA/B
CHANNEL B
DUAL
TRANSCEIVER
TXINHB
Figure 5. Dual-Channel Transceiver
BCRTMP-30
6.0 REMOTE TERMINAL ARCHITECTURE
The Remote Terminal architecture is a descriptorbased configuration of relevant parameters. It is composed
of an RT Descriptor Space (see figure 6) and internal, hostprogrammable registers. The Descriptor Space contains
only descriptors. Descriptors contain programmable
subaddress parameters relating to handling message
transfers. Each descriptor consists of four words: (1) a
Control Word, (2) a Message Status List Pointer, (3) a Data
List Pointer, and (4) an unused fourth word (see figure 7.)
These words indicate how to perform the data transfers
associated with the designated subaddress.
- STARTING ADDRESS
INITIALIZED BY CPU
IN THE RT DESCRIPTOR
SPACE REGISTER
RECEIVE
SUBADDRESS
#1
RECEIVE
SUBADDRESS
#2
RECEIVE
SUBADDRESS
#31
TRANSMIT
SUBADDRESS
#1
TRANSMIT
SUBADDRESS
#2
Message Status information -- including word count, an
internally generated time tag, and broadcast and message
validity information -- is provided for each message. The
Message Status Words are stored in a separate Message
Status Word list according to subaddress. The list’s starting
locations are programmable within the descriptor.
Message data, received or transmitted, is also stored in lists.
The message capacity of the lists and the lists’ locations are
user selectable within the descriptor.
6.1 RT Functional Operation
The RT off-loads the host computer of all routine data
transfers involved with message transfers over the 1553 bus
by providing a wide range of user-programmable functions.
These functions make the BCRTMP’s operation flexible for
a variety of applications. The following paragraphs give
each function’s operational descriptions.
6.1.1 RT Subaddress Descriptor Definition
The host sets words within the descriptor. The BCRTMP
then reads the descriptor words when servicing a command
corresponding to the specified descriptor. All bit-selectable
functions are active high and inhibited when low.
UNUSED
ILLEGAL BROADCAST
SUBADDRESS
TRANSMIT
SUBADDRESS #31
ILLEGAL
SUBADDRESS
UNUSED
INTERRUPT WHEN
ADDRESSED
MODE CODE
#’S 0 & 16
MODE CODE
#’S 1 & 17
INTERRUPT WHEN
INDEX = 0
15
MODE CODE
#’S 15 & 31
Figure 6. Descriptor Space
UNUSED
10
9
8
7
I
I
I
I
6
0
INDEX
MESSAGE STATUS LIST POINTER
DATA LIST POINTER
A receive descriptor and a transmit descriptor are associated
with each subaddress. The descriptors reside in memory and
are listed sequentially by subaddress. By using the index
within the descriptor, the BCRTMP can buffer incoming and
outgoing messages, which reduces host CPU overhead. This
message buffering also reduces the risk of incoming
messages being overwritten by subsequent incoming
messages.
Each descriptor contains a programmable interrupt structure
for subsystem notification of user-selected message
transfers and indicates when the message buffers are full.
Illegalizing subaddresses, in normal and broadcast modes,
is accomplished by using programmable bits within the
descriptor (see the RT Functional Operation section below).
FOR FUTURE EXPANSION
Figure 7. Remote Terminal Subaddress Descriptor
BCRTMP-31
A. Control Word. The first word in the descriptor, the Control Word, selects or disables message transfers and selects
an index.
Bit
Number
Description
BITs 15-11
BIT 10
Reserved.
Illegal Broadcast Subaddress. Indicates to the BCRTMP not to access this subaddress using broadcast
commands. The Message Error bit in the status word is set if the illegal broadcast subaddress is addressed.
Since transmit commands do not apply to broadcast, this bit applies only to receive commands.
BIT 9
Illegal Subaddress. Set by the host CPU, it indicates to the BCRTMP that a command with this subaddress is
illegal. If a command uses an illegal subaddress the Message Error bit in the 1553 status word is set. The Illegal
Command Interrupt is also asserted if enabled.
BIT 8
Interrupt Upon Valid Command Received. Indicates that the BCRTMP is to assert an interrupt every time a
command addresses this descriptor. The interrupt occurs just prior to post-command descriptor updating.
BIT 7
Interrupt When Index = 0. Indicates that the BCRTMP initiates an interrupt when the index is decremented
to zero.
BITs 6-0
Index. These bits are for indexed message buffering. Indexing means transacting a pre-specified number of
messages before notifying the host CPU. After each message transaction, the BCRTMP decrements the index by
one until index = 0. Note that the index is decremented for messages that contain message errors.
B. Message Status List Pointer. The host sets the Message Status List Pointer, the second word within the descriptor, and the
BCRTMP uses it as a starting address for the Message Status List. It is incremented by one with each Message Status Word
write. If the Control Word Index is already equal to zero, the Message Status List Pointer is not incremented and the previous
Message Status Word is overwritten.
Note: A Message Status Word is written and the pointer is incremented when the BCRTMP detects a message error.
C. Data List Pointer. The Data List Pointer is the third word within the descriptor. The BCRTMP stores data in RAM beginning
at the address indicated by the Data List Pointer. The Data List Pointer is updated at the end of each successful message with
the next message’s starting address with the following exceptions:
• If the message is erroneous, the Data List Pointer is not updated. The next message overwrites any data
corresponding to the erroneous message.
•
Upon receiving a message, if the index is already equal to zero, the Data List Pointer is not
incremented and data from the previous message is overwritten.
D. Reserved. The fourth descriptor word is reserved for future use.
BCRTMP-32
6.1.2 Message Status Word
Each message the BCRTMP transacts has a corresponding
Message Status Word, which is pointed to by the Message
Status List Pointer of the Descriptor. This word allows the
host CPU to evaluate the message’s validity, determine the
word count, and calculate the approximate time frame in
which the message was transacted (figures 8 and 9).
15
14
13
12
8
7
WORD COUNT
0
TIME TAG
MESSAGE ERROR
MESSAGE WAS BROADCASTED
SUBSYSTEM FAIL INPUT WAS
ASSERTED DURING THIS MESSAGE
Figure 8. Message Status Word
MESSAGE STATUS WORD
LIST
DATA LIST
MESSAGE
#1
#1
#2
MESSAGE
#3
#2
#4
MESSAGE STATUS
LIST POINTER
MESSAGE
#5
#3
DATA LIST
POINTER
MESSAGE
#4
(FROM RT DESCRIPTOR)
MESSAGE
#5
Figure 9. Remote Terminal Data and Message Status List
Message Status Word Definition
Bit
Number
Description
BIT 15
BIT 14
BIT 13
BITs 12-8
BITs 7-0
Subsystem Failed. Indicates SSYSF was asserted before the Message Status Word transfer to memory. This
bit is also set when the user sets bit 13 of Register 10.
Broadcast Message. Indicates that the corresponding message was received in the broadcast mode.
Message Error. Indicates a message is invalid due to improper synchronization, bit count, word count, or
Manchester error.
Word Count. Indicates the number of words in the message and reflects the Word Count field in thecommand
word. Should the message contain a different number of words than the Word Count field, the Message Error
flag is triggered. If there are too many words, they are withheld from RAM. If the actual word count is less than
it should be, the Message Error bit in the 1553 status word is set.
Time Tag. The BCRTMP writes the internally generated Time Tag to this location after message completion.
The resolution is 64µs. (See Register 13). If the timer reads 2, it indicates the message was completed 128 to
191µs after the timer started.
BCRTMP-33
6.1.3 Mode Code Descriptor Definition
Mode codes are handled similarly to subaddress
transactions. Both use the four-word descriptors residing in
the RT descriptor space to allow the host to program their
operational mode. Corresponding to each mode code is a
descriptor (see figure 10a). Of the 32 address combinations
for mode codes in MIL-STD-1553, some are clearly defined
functions while others are reserved for future use. Sixteen
descriptors are used for mode code operations with each
descriptor handling two mode codes: one mode code with
an associated data word and one mode code without an
associated data word. All mode codes can be handled in
accordance with MIL-STD-1553B. The function of the first
word of the Mode Code Descriptor is similar to that of the
Subaddress Descriptor and is defined below. The remaining
three words serve the same purpose as in the
Subaddress Descriptor.
REMOTE TERMINAL
DESCRIPTOR SPACE
STARTING ADDRESS
(RTDSSA) + 256
MODE CODE
#’S 0 & 16
MODE CODE
#’S 1 & 17
MODE CODE
#’S 2 & 18
MODE CODE
#’S 15 & 31
RTDSSA + 320
Note:
Mode code descriptor blocks are also provided for reserved mode
codes but have no associated predefined BCRTMP operation.
Figure 10a. (RT) Mode CodeDescriptor Space
INTERRUPT ON RECEPTION OF MODE CODE
(WITHOUT DATA WORD)
ILLEGALIZE BROADCAST MODECODE
(WITHOUT DATA WORD)
ILLEGALIZE MODE CODE
(WITHOUT DATA WORD)
RESERVED
ILLEGALIZE BROADCAST MODECODE
(WITH DATA WORD)
ILLEGALIZE TRANSMIT MODE CODE
(WITH DATA WORD)
ILLEGALIZE RECEIVE MODE CODE
(WITH DATA WORD)
INTERRUPT ON RECEPTION OF MODE CODE
(WITH DATA WORD)
INTERRUPT IF INDEX = 0
15
14
13
12
11
10
9
8
7
6
0
INDEX
MESSAGE STATUS LIST POINTER
DATA LIST POINTER
RESERVED
Figure 10b. (RT) Mode CodeDescriptor
Control Word
Bit
Number Description
BIT 15
BIT 14
BIT 13
BIT 12
BIT 11
BIT 10
BIT 9
BIT 8
BIT 7
BITs 6-0
Interrupt on Reception of Mode Code (without Data Word).
Illegalize Broadcast Mode Code (without Data Word).
Illegalize Mode Code (without Data Word).
Reserved.
Illegalize Broadcast Mode Code (with Data Word).
Illegalize Transmit Mode Code (with Data Word).
Illegalize Receive Mode Code (with Data Word).
Interrupt on Reception of Mode Code (with Data Word).
Interrupt if Index = 0.
Index. Functionally equivalent to the index described in the Subaddress Descriptor. It applies to mode codes with
data words only.
BCRTMP-34
The descriptors, numbered sequentially from 0 to 15,
correspond to mode codes 0 to 15 without data words and
mode codes 16 to 31 with data words. For example, mode
codes 0 and 16 correspond to descriptor 0 and mode codes
1 and 17 correspond to descriptor 1. The Mode Code
Descriptor Space is appended to the Subaddress Descriptor
Space starting at 0100H (256D) of the 320-word RT
Descriptor Space (see figure 6).
The BCRTMP can autonomously support all mode codes
without data words by executing the specific function and
transmitting the 1553 status word. The subsystem provides
the data word for mode codes with data words (see the Data
List Pointer section). For all mode codes, an interrupt can
be asserted by setting the appropriate bit in the control word
upon successful completion of the mode command (see
figure 10b).
Dynamic Bus Control #00000
This mode code is accepted automatically if the Dynamic
Bus Control Enable bit in the Remote Terminal Address
Register is set. Setting the Dynamic Bus Control
Acceptance bit in the 1553 status word and BCRTMP Status
Register confirms the mode code acceptance. A HighPriority Interrupt is also asserted if enabled. If the Dynamic
Bus Control Enable bit is not set, the BCRTMP does not
accept Dynamic Bus Control.
Synchronize (Without Data Word) #00001
If enabled in the Mode Code #00001 Descriptor Control
Word, the BCRTMP asserts an interrupt when this mode
code is received.
Transmit Status Word #00010
The BCRTMP automatically transmits the 1553 status word
corresponding to the last message transacted.
Initiate Self-Test #00011
The BCRTMP automatically starts its BIT routine. An
interrupt, if enabled, is asserted when the test is completed.
The BIT Word Register and external pin BCRTF are updated
when the test is completed. A failure in BIT will also set the
TF status word bit.
Transmitter Shutdown #00100
The BCRTMP disables the channel opposite the channel on
which the command was received.
Override Transmitter Shutdown #00101
The BCRTMP enables the channel previously disabled.
Reset Remote Terminal #01000
The BCRTMP automatically resets the encoder, decoders,
and protocol logic.
Transmit Vector Word #10000
The BCRTMP transmits the vector word from the location
addressed by the Data List Pointer in the Mode Code
Descriptor Block.
Synchronize (with Data Word) #10001
On receiving this mode code, the BCRTMP simply stores
the associated data word.
Transmit Last Command #10010
The BCRTMP transmits the last command executed and the
corresponding 1553 status word.
Transmit BIT Word #10011
The BCRTMP transmits BIT information from the
BIT Register.
Selected Transmitter Shutdown #10100
On receiving this mode code, the BCRTMP simply stores
the associated data word.
Override Selected Transmitter Shutdown #10101
On receiving this mode code, the BCRTMP simply stores
the associated data word.
Mode codes 9-15 and 22-31 are reserved for future
expansion of MIL-STD-1553.
6.2 RT Error Detection
In accordance with MIL-STD-1553, the remote terminal
handles superseding commands on the same or opposite bus.
When receiving, the Remote Terminal performs a response
time-out function of 56ms for RT-RT transfers. If the
response time-out condition occurs, a Message Error bit can
be set in the 1553 status word and in the Message Status
Word. Error checking occurs on both of the Manchester
logic and the word formats. Detectable errors include word
count errors, long words, short words, Manchester errors
(including zero crossing deviation), parity errors, and data
discontiguity.
6.3 RT Operational Sequence
The following is a general description of the typical
behavior of the BCRTMP as it processes a message in the
RT mode. It is assumed that the user has already written a
“1” to Register 0, bit 0, enabling RT operation.
Inhibit Terminal Flag Bit #00110
The BCRTMP inhibits the Terminal Flag from being set in
the status word.
Override Inhibit Terminal Flag Bit #00111
The BCRTMP disables the Terminal Flag inhibit.
BCRTMP-35
Valid Command Received.
COMSTR goes active
Bus Legalization occurs (if selected)
DMA Descriptor Read. (If Bus Legalization is used,
the BCRTMP ignores the legalization information in
the Control Word). After receiving a valid command,
the BCRTMP initiates a burst DMA:
DMA arbitration (BURST)
Control Word read
Message Status List Pointer read
Data List Pointer read
Data Transmitted/Received.
•
Data Word DMA.
If the BCRTMP needs to transmit data from
memory, it initiates a DMA cycle for each Data
Word shortly before the Data Word is needed on
the 1553B bus:
DMA arbitration
Data Word read (starting at Data List
Pointer address, incremented for each
successive word)
If the BCRTMP receives data, it writes each Data
Word to memory after the Data Word is received:
DMA arbitration
Data Word write (starting at Data List
Pointer address, incremented for each
successive word)
Status Word Transmission.
The BCRTMP automatically transmits the Status
Word as described in section 8.2.8. For illegalized
commands, the BCRTMP also sets the Message
Error Bit in the 1553 Status Word.
Exception Handling.
If an interrupting condition occurs during the
message, the following occurs:
For High-Priority Interrupts:
HPINT is asserted (if enabled in Register 7).
For message errors, the BCRTMP is put in
a hold state until the interrupt is
acknowledged (by writing a “1” to the
appropriate bit in Register 8).
For Standard Interrupts:
DMA arbitration (BURST)
Interrupt Status Word write
RT Descriptor Block Pointer write
Tail Pointer read (into Register 6)
STDINTP pulses low
STDINTL asserted (if enabled)
Processing continues
•
Descriptor Write.
After the BCRTMP processes the message, a final
DMA burst occurs to update the descriptor block,
if necessary:
DMA arbitration (BURST)
Message Status Word write
Data List Pointer write (incremented by
word count)
Message Status List Pointer write
(incremented by 1)
Control Word write (index decremented)
Note the following exceptions:
Mode codes without data require no
descriptor update.
Illegalized commands require no
description updates (or data word accesses).
Predefined mode codes (18 and 19) which
do not require access to memory for the data
word, do not involve updating the Data
List Pointer.
Messages with errors prevent updates to the
Data List Pointer.
If the message index was zero, neither the
Message Status List Pointer nor the Data
List Pointer is updated.
7.0 BUS CONTROLLER ARCHITECTURE
The BCRTMP’s bus controller architecture is based on a
Command Block structure and internal, hostprogrammable registers. Each message transacted over the
MIL-STD-1553 bus has an associated Command Block,
which the CPU sets up (see figures 11 and 12). The
Command Block contains all the relevant message and RT
status information as well as programmable function bits
that allow the user to select functions and interrupts. This
memory interface system is flexible due to a doubly-linked
list data structure
HEAD POINTER
CONTROL WORD
COMMAND WORD 1
COMMAND WORD 2 (RT-RT ONLY)
DATA LIST POINTER
STATUS WORD 1
STATUS WORD 2 (RT-RT ONLY)
TAIL POINTER
Figure 11. Command Block
BCRTMP-36
In a doubly-linked Command Block structure, pointers
delimit each Command Block to the previous and
successive blocks (see figure 13). The linking feature eases
multiple message processing tasks and supports message
scheduling because of its ability to loop through a series of
transfers at a predetermined cycle time. A data pointer in
the command allows efficient space allocation because data
blocks only have to be configured to the exact word count
used in the message. Data pointers also provide flexibility
in data-bank switching.
Continue function facilitates the host subsystem’s
synchronization by generating an interrupt when the
specified Command Block’s message is executed.
COMMAND BLOCK #1
HP
TP
#2
COMMAND BLOCK
DATA LIST POINTER
HP
DATA WORD #1
DATA WORD #2
X
TP
#3
LAST DATA WORD
HP
X IS BETWEEN 1 & 32
Figure 12. Data Placement
TP
#4
A control word with bit-programmable functions and a
Message Error bit are in each Command Block. This allows
selecting individual functions for each message and
provides message validity information. The BCRTMP’s
register set provides additional global parameters and
address pointers.
A programmable auto retry function is selectable from the
control word and Control Register.
The auto retry can be activated when any of the following
occurs:
• Busy bit set in the status word
•
Message Error (indicated by the RT status response)
•
Response Time-Out
•
Message Error detected by the Bus Controller
One to four retries are programmable on the same or
opposite bus.
The Bus Controller also has a programmable intermessage
delay timer that facilitates message transfer scheduling (see
figures 14 and 15). This timer, programmed in the control
word, automatically delays between the start of two
successive commands.
A polling function is also provided. The Bus Controller,
when programmed, compares incoming status words to a
host-specified status word and generates an interrupt if the
comparison indicates any matching bits. An Interrupt and
HP
TP
Figure 13. Command Block Chaining
7.1 BC Functional Operation
The Bus Controller off-loads the host computer of many
functions needed to coordinate 1553 bus data transfers.
Special architectural features provide message- by-message
flexibility. In addition, a programmable interrupt scheme,
programmable intermessage timing delays, and internal
registers enhance the BCRTMP’s operation.
The host determines the first Command Block by setting the
initial starting address in the current Command Block
Register. Once set, the BCRTMP updates the current
Command Block register with the next Command Block
Address. The BCRTMP then executes the sequential
Command Blocks and counts out message delays (where
programmed) until it encounters the last Command Block
listed (indicated by the End of List bit in the control word).
Interrupts are asserted when enabled events occur (see
section 9.0, Exception Handling and Interrupt Logging).
The functions and their programming instructions are
described below. The registers also contain many
programmable functions and function parameters.
BCRTMP-37
15
14
MESSAGE
ERROR
13
SKIP
INTERRUPT
AND
CONTINUE
12
11
10
POLLING
ENABLE
AUTO
RETRY
ENABLE
END
OF
LIST
9
8
RT-RT
TRANSFER
MONITOR
RT-RT
TRANSFER
7
0
‘TIME DELAY’
Figure 14. Command Word
MESSAGE #1
MESSAGE #2
T DELAY1
MESSAGE #3
TDELAY2
Figure 15. BC Timing Delays
BC Command Block Definition
Each Command Block contains (see figure 11):
A. Head Pointer. Host-written, this location can contain the address of the previous Command Block’s Head Pointer. The
BCRTMP does not access this location.
B. Control Word. Host-written, the Control Word contains bit-selectable options and a Message Error bit the BCRTMP
provides (see figure 14). The bit definitions follow.
Bit
Number
Description
BIT 15
Message Error. The BCRTMP sets this bit when it detects an invalid RT response as defined in
MIL-STD 1553B.
Skip. When set, this bit instructs the BCRTMP to skip this Command Block and execute the next.
Interrupt and Continue. If set, a Standard Interrupt is asserted when this block is addressed; operation,
however, continues. Note that this interrupt must also be enabled by setting bit 0 of Register 9.
Polling Enable. Enables the BCRTMP’s polling operation.
Auto Retry Enable. When set, the Auto Retry function, governed by the global parameters in the Control
Register, is enabled for this message.
End of List. Set by the CPU, this bit indicates that the BCRTMP, upon completion of the current message,
will halt (Register 1, bit 0 goes inactive) and assert a High-Priority Interrupt. The interrupt must also be
enabled in theHigh-Priority Interrupt Enable Register.
RT-RT. Set by the CPU, this indicates that this Command Block transacts an RT-RT transfer.
Monitor RT-RT Transfer. Set by the CPU, this function indicates that the BCRTMP should receive and store
the message beginning at the location indicated by the data pointer.
Time Delay. The CPU sets this field, which causes the BCRTMP to delay the specified time between sequential
message starts (see figures 14 and 15). Regardless of the value in the Time Delay field (including zero), The
BCRTMP will at least meet the minimum 4µs intermessage gap time as specified in MIL-STD-1553B. The
timer is enabled by having a non-zero value in this bit field. When using this function, please note:
BIT 14
BIT 13
BIT 12
BIT 11
BIT 10
BIT 9
BIT 8
BITs 7-0
•
Timer resolution is 16µs. As an example, if a given message requires 116µs to complete (including the
minimum 4ms intermessage gap time) the value in the Time Delay field must be at least 00001000 (8 x
16µs = 128 µs) to provide an intermessage gap greater than the 4ms minimum requirement.
•
If the timer is enabled and the Skip bit is set, the timer provides the programmed delay before proceeding.
•
If the message duration exceeds the timer delay, the message is completed just as if the time were
not enabled.
BCRTMP-38
C. Command Word One. Initialized by the CPU, this location contains the first command word corresponding to the
Command Block’s message transfer.
D. Command Word Two. Initialized by the CPU, this location is for the second (transmit) command word in RT-RT
transfers. In messages involving only one RT, the location is unused.
E. Data Pointer. Initialized by the CPU, this location contains the starting location in RAM for the Command Block’s
message (see figure 16).
F. Status Word One. Stored by the BCRTMP, this location contains the entire Remote Terminal status response.
G. Status Word Two. Stored by the BCRTMP, this location contains the receiving Remote Terminal status word. For
transfers involving one Remote Terminal, the location is unused.
H. Tail Pointer. Initialized by the host CPU, the Tail Pointer contains the next Command Block’s starting address.
COMMAND BLOCK #1
RAM
DATA WORD #1
DATA POINTER
MESSAGE #1
DATA WORD #2
DATA WORD #3
DATA WORD #1
COMMAND BLOCK #2
MESSAGE #2
DATA POINTER
Example 1. No bit match is present
PCR
0000000001
RT’s 1553 Status Word response
0000010000
Result
No Polling Comparison Interrupt
Example 2. Bit match is present
PCR
0010010000
RT’s 1553 Status Word response
00000100000
Result
Polling Comparison Interrupt
DATA WORD #2
DATA WORD #3
DATA WORD #4
RT
RT
RT
RESPONSE
Figure 16. Contiguous Data Storage
7.2 Polling
During a typical polling scenario (see figure 17) the Bus
Controller interrogates remote terminals by requesting them
to transmit their status words. This feature can also alert the
host if a bit is set in any RT status word response during
normal message transactions. The BCRTMP enables the
host to initialize a chain of Command Blocks with the
command word’s Polling Enable bit. A programmable
Polling Compare Register (PCR) is provided. In the polling
mode, the Remote Terminal response is compared to the
Polling Compare Register contents. Program the PCR by
setting the PCR bits corresponding to the RT’s 1553 status
word bits to be compared. If they match (i.e., two 1’s in the
same bit position) then, if enabled in both the BC Command
Block Control Word and in the Standard Interrupt Enable
Register (Register 9), a polling comparison interrupt
is generated.
Q?
BC
POLLING RESPONSE REGISTER
(RT STATUS WORD)
POLLING COMPARE WORD
(SET BY CPU)
Figure 17. Polling Operation
7.3 BC Error Detection
The Bus Controller checks for errors on each message
transaction. In addition, the BC compares the RT command
word addresses to the incoming status word addresses. The
BC monitors for response time-out and checks data and
control words for proper format according to MIL-STD1553. Illogical commands include incorrectly formatted
RT-RT Command Blocks.
BCRTMP-39
7.4 Bus Controller Operational Sequence
The following is a general description of the typical
behavior of the BCRTMP as it processes a message in the
BC mode.
The user starts BC operation by writing a “1” to Register 0,
Bit 0.
• Command Block DMA - the following occurs
immediately after Bus Controller startup:
DMA arbitration (BURST)
Control Word read
Command Word 1 read (from third location
of Command Block)
Data List Pointer read
A. For BC-to-RT Command Blocks:
C. For RT(A)-to-RT(B) Command Blocks:
The BCRTMP transmits Command Word 1 to RT(B).
• Command Word 2 DMA
DMA arbitration
Command Word 2 read (from fourth
location of Command Block)
The BCRTMP transmits Command Word 2 to RT(A).
The BCRTMP receives the RT Status Word from RT(A).
• Status Word DMA for RT(A) Status Word
DMA arbitration
Status Word write (to sixth location of
Command Block)
The BCRTMP transmits the Command Word.
The BCRTMP receives the first Data Word
• Data Word DMA
• Data Word DMA (only if the BCRTMP is enabled
to monitor the RT-to-RT message).
DMA arbitration
Data Word read (starting at Data List Pointer
address, incremented for each successive
word)
DMA arbitration
Data Word write (starting at Data List
Pointer address, incremented for each
successive word)
The BCRTMP transmits the Data Word. Data Word
DMAs and transmissions continue until all Data Words
are transmitted.
Data Word receptions and DMAs continue until all Data
Words are received.
• Status Word DMA
The BCRTMP receives the RT Status Word from RT(B).
The BCRTMP receives the RT Status Word.
• Status Word DMA for RT(B) Status Word
DMA arbitration
Status Word write (to sixth location of
Command Block)
B. For RT-to-BC Command Blocks:
The BCRTMP transmits the Command Word.
• Status Word DMA
The BCRTMP receives the RT Status Word.
DMA arbitration
Status Word write (to sixth location of
Command Block)
DMA arbitration
Status Word write (to seventh location of
Command Block)
Exception Handling.
If an interrupting condition occurs during the message,
the following occurs:
For High-Priority Interrupts:
HPINT is asserted (if enabled in Register 7). For
message errors, the BCRTMP is put in a hold state until
the interrupt is acknowledged (by writing a “1” to the
appropriate bit in Register 8).
The BCRTMP receives the first Data Word.
• Data Word DMA
DMA arbitration
Data Word write (starting at Data List
Pointer address, incremented for each
successive word)
Data Word receptions and DMAs continue until all Data
Words are received.
BCRTMP-40
For Standard Interrupts:
DMA arbitration (BURST)
Interrupt Status Word write
Command Block Pointer write
Tail Pointer read (into Register 6) STDINTP
pulses low
STDINTL asserted (if enabled)
Processing continues
If Retries are enabled and a Retry condition occurs, the
following DMA occurs:
DMA arbitration (BURST)
Control Word read
Command Word 1 read (from third location
of Command Block)
Data List Pointer read
The BCRTMP proceeds from the current Command Block
to the next successive Command Block.
• If no Message Error has occurred during the
current Command Block, the following occurs:
DMA arbitration (BURST)
Command Block Tail Pointer read (to
determine location of next Command
Block. Note that this occurs only if no
Retry).
DMA hold cycle
Control Word read (next Command Block)
Command Word 1 read (next Command
Block)
Data List Pointer read
• If the BCRTMP detects a Message Error while
processing the current Command Block, the
following occurs:
DMA arbitration (BURST)
Control Word write
Command Block Tail Pointer read (to
determine location of next Command
Block. Note that this occurs only if no
Retry.)
DMA hold cycle
Control Word read (next Command Block)
Command Word 1 read (next Command
Block)
Data List Pointer read
The BCRTMP proceeds again from point A, B, or C as
shown above.
The second Command Block is for a BC-RT transfer of
two words.
• The End of List bit is set in its Control Word.
•
The Data List Pointer contains the address 0404H.
•
The Polling Enable bit is set and the Polling Compare
Register contains 0004H (check for Subsystem Fail bit.
Then:
A. The CPU initializes all the appropriate registers and
Command Blocks, and issues a Start Enable by writing a
“1” to Register 0, bit 0.
B. The BCRTMP, through executing a DMA cycle, reads
the Control Word, Command Words, and the Data List
Pointer. The delay timer starts and message execution
begins by transmitting the receive and transmit
commands stored in the Command Blocks. The
BCRTMP then waits to receive the Status Word back
from the transmitting RT.
C. The BCRTMP receives the RT Status Word with all
status bits low from the transmitting RT and stores the
Status Word in Command Block 1. The incoming data
words from the transmitting RT follow. The BCRTMP
stores them in memory locations 0400H - 0403H.
If the Status Word indicates that the message cannot be
transmitted (Message Error), the response time-out
clock counts to zero and the allotted message time runs
out. An auto-retry can be initiated if programmed to do
so. Nevertheless, the ME bit in the Control Word is set.
D. The BCRTMP receives the Status Word response from
the receiving RT. The ME bit in the Status Word is set,
indicating the message is invalid. The BCRTMP
initiates the auto retry function, (as programmed) on the
alternate bus, re-transmits the Command Words, receives
the correct Status Word, and stores the data again in
locations 0400H - 0403H. This time the Status Word
response from the receiving RT indicates the message
transfer is successful.
7.5 BC Operational Example (figure 19 on page 49)
The BCRTMP is programmed initially to accomplish the
following:
The first Command Block is for a four-word RT-RT transfer
with the BCRTMP monitoring the transfer and storing
the data.
• Auto-retry is enabled on the opposite bus using onlyone
retry attempt, if the incoming Status Word is received
with the Message Error bit set.
•
Wait for a time delay of 400ms before proceeding to the
next Command Block.
•
The Data List Pointer contains the address 0400H.
E. The timer delay between the two successive
transactions counts down another 135µs before
proceeding. This is determined as follows:
The message transaction time is approximately130µs
(the only approximation is due to the range in status
response and intermessage gap times specified by
BCRTMP-41
MIL-STD-1553B). Approximating that with the retry,
the total duration for the two attempts is 265ms.
F. The BCRTMP reads the Tail Pointer of Command
Block 1 and places it in the Current Command Register.
It also reads the Control Word, Command Word, and
Data List Pointer, and the first data word in the second
Command Block.
G. Since this is a BC-RT transfer, the BCRTMP transmits
the receive command followed by two data words from
locations 0404H - 0405H in memory. The BCRTMP
reads the second data word from memory while
transmitting the first.
H. The BCRTMP receives the status response from the RT.
In this case, the Status Word indicates, by the ME bit
being low, that the message is valid. The Status Word
also has the Subsystem Fail bit set.
I.
The Status Word is stored in the Command Block. The
BCRTMP, having encountered the end of the list, halts
message transactions and waits for another start signal.
J.
The BCRTMP asserts a High-Priority Interrupt
indicating the end of the command list. Due to the
polling comparison failure, the BCRTMP also asserts a
Standard Priority Interrupt and logs the event in the
Interrupt Log List.
8.0 MULTIPLE PROTOCOL OPTIONS
The UT1553 BCRTMP was developed from the industry’s
first monolithic MIL-STD-1553B Bus Controller and
Remote Terminal chip, the UT1553B BCRT. Many
additional features were added to the BCRT to create the
UT1553 BCRTMP, which conforms to the requirements of
the many different “1553 standards” which developed
between releases of MIL-STD-1553A and
MIL-STD-1553B.
User-configurable Operational Mode selections allow the
BCRTMP to interface to a wide variety of 1553 protocols.
Protocols for which the user can configure the UT1553
BCRTMP include: MIL-STD-1553A, MIL-STD-1553B,
McDonnell Douglas A3818, A5232, and A5690, and
Grumman Aerospace SP-G-151A. The user need only to
determine which Operational Mode settings are necessary
to conform to the application’s needs.
8.1 Operational Modes
The user can program the BCRTMP to conform to many of
the currently used MIL-STD-1553 variations in protocol by
BCRTMP-42
simply selecting different operating modes. The BCRTMP
provides seven Mode Select input pins and/or register bits t
to select the different operating modes. If all mode bits are
high, the BCRTMP operates in accordance with
MIL-STD-1553B.
8.1.1 MD0 (Mode 0)
Legalization Select (RT)
The MD0 input pin or bit 0 of Register 14 selects the method
of command legalization the BCRTMP uses. Before issuing
the appropriate RT response to a command, the BCRTMP
must determine whether the command is legal. The
BCRTMP accomplishes command legalization by one of
two methods -- DMA, by fetching the appropriate
Descriptor Block (MD0=1); or by using the Legalization
bus (MD0=0). The Legalization bus is the faster of the two
methods and must be selected in order to meet the RT
Response Time requirements of MIL-STD-1553A. Since
the BCRTMP cannot meet the “A” response time unless it
uses the Legalization bus for command legalization, it
forces Mode 0 low internally if the “A” response time is
selected (MD2=0). See also section 5.5, Legalization bus.
8.1.2 MD1 (Mode 1)
Broadcast Option Select (BC, RT)
The MD1 input pin or bit 1 of Register 14 selects the
Broadcast option the BCRTMP uses. The use of Broadcast
varies with differences in the 1553 protocols. For protocols
that support the Broadcast option (MD1=1), the RT address
11111 is reserved to indicate a Broadcast command. When
the Bus Controller transmits a Broadcast command, all RTs
must receive the message, but no RT is to respond with a
status word. For protocols that do not support the Broadcast
option (MD1=0), RT address 11111 is treated as a normal
RT address.
8.1.3 MD2 (Mode 2)
RT Response Time Select (RT)
The MD2 input pin or bit 2 of Register 14 selects the RT
Response Time the BCRTMP uses in the RT mode to
respond to 1553 commands. Before an RT can respond to a
command, it must determine whether that command is legal.
As stated is section 8.1.1 above, the BCRTMP accomplishes
Command Legalization by using either DMA Descriptor
Block fetching or by using the Legalization bus.
The RT Response Time differs among the 1553 protocols.
The RT Response Time is measured from the zero crossing
of the parity bit of the receive command’s last data word (or
the zero crossing of the parity bit of the transmit command
word) to the status word sync’s zero crossing. The maximum
response time allowed for an RT is either 7.0µs (“A”
response time, MD2=0) or 12.0µs (“B” response time,
MD2=1), depending on the specification.
8.1.4 MD3 (Mode 3)
Mode Code Option Select (BC,RT)
The MD3 input pin or bit 3 of Register 14 selects the mode
code option the BCRTMP uses. Differences in mode code
definitions among the 1553 protocols concern the number
of defined mode codes and whether mode codes with data
are defined. MIL-STD-1553B’s definition is formal, but the
other specifications define the possible mode codes to
varying degrees, and may not use mode codes with data.
The BCRTMP uses this selection to determine which bit
patterns in the subaddress field of the command word
indicate that the word count field contains a mode code.
When MD3 is high, either 00000 or 11111 in the subaddress
field indicates a mode code. When MD3 is low, only 00000
indicates a mode code. The BCRTMP provides additional
control over mode code definition with the MD6 selection
(see section 8.1.7). Also, the user can program bit 13 of
Register 14 to provide additional mode code control.
8.1.5 MD4 (Mode 4)
Status Word Option Select (RT)
The MD4 input pin or bit 4 of Register 14 selects the method
the BCRTMP uses to generate the RT status word. Most, if
not all, 1553 protocols define the Terminal Address,
Message Error (ME), and Terminal Flag (TF) status word
bits in the same manner. The remaining bits are defined in
a variety of ways, not only dependent on the 1553 protocol,
but also on the individual procurement specification. MILSTD-1553B is quite formal in defining the status word bits,
while the other specifications either define or leave
undefined the other bits to varying degrees for procurementspecific options. When MD4 is high, the BCRTMP
generates the status word in accordance with MIL-STD1553B, using the contents of Register 10 for many of the
status bits. When MD4 is low, the BCRTMP generates the
status word using the Programmable status register
(Register 15). See section 8.2.8 for more information
regarding status word generation.
8.1.6 MD5 (Mode 5)
Message Error Technique Select (RT)
The MD5 input pin or bit 5 of Register 14 selects the method
the BCRTMP uses for handling message errors. Some 1553
protocols (e. g., MIL-STD-1553B) consider any message
error reason to discard the entire message and suppress
status word transmission, while others
(e. g., McDonnell Douglas A3818) define the required
activity according to message error severity.
When MD5 is high, message error handling is as described
in MIL-STD-1553B. The MIL-STD-1553B definition
states that on the occurrence of any Message Error
condition, the RT sets the message error bit in the status
word and suppresses status word transmission. Message
error conditions are defined as any of the following: parity
errors, word count errors, or Manchester errors.
When MD5 is low, message error handling is as described
in McDonnell Douglas A3818. In this method, a less severe
error (either a Manchester error or a parity error in a data
word, for example) requires special attention. The RT must
mark the individual defective data word and respond with
the message error bit set in the status word. When the
BCRTMP detects this type of Message Error, the BCRTMP
asserts the ERR output and places the word count for the
defective data word on the least significant five bits of the
Legalization bus. Due to the BCRTMP’s internal detection
circuitry, errors in the first two data bits will force the
BCRTMP to ignore the word and cause a word count error.
Word count errors cause the RT to suppress the status word
and set the Message Error bit.
8.1.7 MD6 (Mode 6)
Mode Code with Data Select (BC,RT)
The MD6 input pin or bit 6 of Register 14 selects whether
mode codes with data are allowed. When MD6 is high, the
mode codes defined in MIL-STD-1553B as mode codes
with data have an associated data word. When MD6 is low,
the BCRTMP treats all mode codes as mode codes
without data.
8.1.8 MD7 (Mode 7)
Remote Terminal Time Out Option Select (BC,RT)
The MD7 input pin or bit 12 of Register 0 selects the Remote
Terminal Time-Out option. When MD7 is high, the Remote
Terminal Time-Out (RTO) is nominally16 µs. When MD7
is low, the Remote Terminal Time-Out (RTO) is
nominally 32µs.
8.2 Additional UT1553 BCRTMP Features
8.2.1 DOMC Do Mode Code Control Signal (RT)
The BCRTMP provides additional mode code flexibility
through use of the DOMC input. This input (internally
pulled high) can be pulled low when the BCRTMP receives
a mode code to prevent the BCRTMP from automatically
executing the mode code. This input can be used to disable
automatic execution of mode codes at any time; however,
the individual selection of mode code execution applies only
when using the Legalization bus for command legalization
(i.e., MD0 is low), since the timing for mode code execution
decision-making corresponds with mode code legalization
using the Legalization bus method only. If the user desires
automatic execution of the mode code as defined in MILSTD-1553B, then the user asserts the DOMC signal high
after the BCRTMP receives the mode code. If the user
desires to suppress automatic execution of the Mode Code,
then the user asserts the DOMC signal low after the
BCRTMP receives the mode code. The timing for the
DOMC input follows, identically, the timing for the
LGLCMD of the Legalization bus. See Table 2 for the
actions the BCRTMP takes when receiving specific
mode codes.
BCRTMP-43
8.2.2 Continuous Wrap-Around Circuitry (BC,RT)
The Continuous Wrap-Around Test feature is available for
both Bus Controller and Remote Terminal operation. This
feature permits continuous monitoring of the correct
operation of the BCRTMP.
The user either asserts the WRAPEN input low or writes a
“one” to bit 7 of Register 14 to enable the Continuous WrapAround feature. This feature permits the BCRTMP to
compare everything it transmits with a “reflected-back”
version of the transmitted data. The data is reflected back
by the 1553 transceiver and serially received into the
BCRTMP’s decoder circuitry. If a mismatch is found
between the transmitted data and the reflected data, then the
BCRTMP asserts the WRAPF output.
Asserting the WRAPEN and the ALTWRAP inputs places
the BCRTMP in a special off-line system diagnostics mode
to allow the system to test both 1553 buses and the
associated transceivers, transformers, connectors, etc.
Typical use of this feature would involve connecting a bus
stub between the Channel A and B connectors. The user
could then place the BCRTMP in a Bus Controller mode of
operation and execute a list of commands. With the
ALTWRAP and WRAPEN signals asserted, each
transmission on the selected bus would be received through
the wrap-around circuitry on the opposite bus. Any assertion
of the WRAPF output would indicate that either the
BCRTMP or some part of the bus or interface network has
failed. Note that if no RT is present in the system, then the
BCRTMP will naturally detect a no-response error. This can
be avoided by using Broadcast commands, in which case no
RT is expected to respond on the bus.
8.2.3 Stop Enable (BC,RT)
The user implements this feature by setting bit 12 of Register
14 high. In the Bus Controller mode, when this bit is high,
the occurrence of any enabled interrupt (either Standard or
High-Priority) causes the BCRTMP to automatically halt
Bus Controller message processing. The BCRTMP resumes
message processing when the user clears the interrupt by
writing a “one” to the appropriate bit in Register 8.
In the Remote Terminal mode, when this bit is high, the
occurrence of any enabled interrupt (either Standard or
High-Priority) causes the BCRTMP to automatically enter
the Forced Busy mode of operation (see section 8.2.4). The
BCRTMP exits the Forced Busy mode when the user clears
the interrupt.
8.2.4 Forced Busy (RT)
The user places the BCRTMP into the Forced Busy mode
(RT only) by either pulling the FBUSY input low or by
writing a “one” to bit 11 of Register 15 or bit 9 of Register
10. As discussed in Section 8.2.3, the BCRTMP can also
automatically enter the Forced Busy mode with the
occurrence of enabled interrupts. While in the Forced Busy
BCRTMP-44
mode, all interrupts are disabled, the Busy bit is set in the
status word response, and no DMA transactions will occur.
The BUSYACK output acknowledges that the BCRTMP is
in the Forced Busy mode.
8.2.5 ACTIVE Signal (RT)
The ACTIVE output provides a means for the user to place
the BCRTMP on the 1553 bus, enabled as an RT, and
determines if it should assume bus mastership. The
BCRTMP asserts the ACTIVE signal when it detects a valid
command on the bus to any RT address. The host determines
which bus is active by examining bits 10 and 11 of Register
14. To disable bus activity detection, the host writes a “one”
to bit 10 of Register 14 to disable Channel A (or bit 11 of
Register 14 for Channel B). The ACTIVE output remains
deasserted until one or both of the channels is enabled. The
user writes a “zero” to the appropriate bit location(s) to
enable the desired channel(s). Performing a programmed or
hardware reset also enables both activity monitors.
8.2.6 Transmitter Inhibit Signals (BC,RT)
The UT1553 BCRTMP contains two transmitter inhibit
signals (one for Channel A and one for Channel B) that
provide fail-safe timing for the 1553 buses. The signals are
active (TIMRONA for Channel A or TIMRONB for
Channel B) when the BCRTMP begins transmitting and
time out, or go inactive, 660 µs later, if the BCRTMP has not
completed its transmission.
8.2.7 Immediate Clear Mode
The user sets bit 15 of Register 15 to enter the Immediate
Clear Mode. When set, this bit will cause the BCRTMP to
automatically clear all programmable status bits after the
BCRTMP transmits the RT status word. When this bit is set,
the first status word sent out contains the programmable
status bits as programmed by either the Programmable
Status Register (“A” protocol, MD4 = 0) or the RT Address
Register (“B” protocol, MD4 = 1). After status word
transmission, all programmable status bits are cleared
automatically. The exception to this occurs when the next
command received is the Transmit Status Word or Transmit
Last Command mode code. When either of these mode
codes is received, the BCRTMP will respond with the
appropriate status word from the previous valid command.
This feature applies to all operational modes.
8.2.8 Status Word Generation
As a result of the differing requirements for status words in
the various 1553 protocols, the BCRTMP must be capable
of generating the RT status word in a variety of ways. It is
appropriate to discuss the separate status word bits
individually in order to understand how the BCRTMP
generates these bits. The three status word bits defined as
“reserved” in MIL-STD-1553B are handled identically by
the BCRTMP, as shown below. The action taken to generate
all other status word bits varies, depending on the mode in
which the BCRTMP is operating. In most cases, the
BCRTMP generates the status word bits in different ways
depending on the internal state of Operational Mode 4.
8.2.8.1 The Terminal Address Field
The Terminal Address field in the status word is always
provided in the same manner. The BCRTMP uses pins
RTA4 to RTA0 (or bits 4-0 of the Remote Terminal Address
Register) to generate the Remote Terminal Address bits of
the status word.
8.2.8.2 The Message Error Bit
If MD4 = 1, then the Message Error bit in the status word
is set if any 1553 Message Error condition (or Illegal
Command) occurs.
If MD4 = 0, then the Message Error bit in the status word
is set when any 1553 Message Error condition (or Illegal
Command) occurs or if bit 10 of Register 15 is set.
8.2.8.3 The Instrumentation Bit
If MD4 = 1, then the BCRTMP uses bit 15 of Register 10
to set the Instrumentation bit in the status word.
If MD4 = 0, then the BCRTMP uses bit 9 of Register 15 (the
Programmable Status Register) to set the Instrumentation
bit in the status word.
8.2.8.4 The Service Request Bit
If MD4 = 1, then the BCRTMP uses bit 10 of Register 10
to set the Service Request bit in the status word.
If MD4 = 0, then the BCRTMP uses bit 8 of Register 15 (the
Programmable Status Register) to set the Service Request
bit in the status word.
Also, the Service Request bit can be forced to reflect the
complement of the status word Busy bit (independent of the
internal state of MD4) if the user sets bit 12 of Register
15 high.
8.2.8.5 The MIL-STD-1553B “Reserved” Status
Word Bits
The BCRTMP always provides the MIL-STD-1553B
“Reserved” status word bit field (bit Times 12-14) in the
status word in the same manner. The BCRTMP uses bits
5-7 of the Register 15 to generate these bits (independent of
the internal state of MD4).
8.2.8.6 The Broadcast Command Received Bit
If MD4 = 1, then the Broadcast Command Received bit in
the status word is set when a Broadcast command is
received, if Broadcast is enabled.
If MD4 = 0, then the Broadcast Command Received bit in
the status word is set if bit 4 of the Programmable Status
Register is set high.
8.2.8.7 The Busy Bit
If MD4 = 1, then the Busy bit in the status word is set if
either bit 14 of Register 10 is set high or if the BCRTMP is
in the Forced Busy mode (see section 8.2.4 for a discussion
on entry to the Forced Busy mode). The assertion of the
Busy bit while in the Forced Busy mode can be disabled if
both bits 13 and 14 of Register 15 are set high. Note that the
Forced Busy mode is independent of the internal state
of MD4.
If MD4 = 0, then the Busy bit in the Status Word is set if
either bit 14 of Register 10 or bit 3 of the Programmable
Status Register is set high, or if the BCRTMP is in the Forced
Busy mode.
8.2.8.8 The Subsystem Flag Bit
If MD4 = 1, then the Subsystem Flag bit in the status word
is set either if the user sets bit 13 of Register 10 or asserts
the SSYSF input of the BCRTMP, or if a BIT failure
has occurred.
If MD4 = 0, then the Subsystem Flag bit in the status
word is set if the user sets bit 2 of the Programmable
Status Register.
8.2.8.9 The Dynamic Bus Control Acceptance Bit
If MD4 = 1, the Dynamic Bus Control Acceptance bit in the
status word will be set when the BCRTMP receives a
Dynamic Bus Control Mode Code that is not a Broadcast
command, if the user has not illegalized that command and
has set bit 12 of Register 10 high.
8.2.8.10 The Terminal Flag Bit
If MD4 = 1, setting bit 11 of Register 10 or the occurrence
of a BIT failure will always set the Terminal Flag bit in the
status word.
If MD4 = 0, setting bit 0 of the Programmable Status
Register will always set the Terminal Flag bit in the
status word.
Independent of the internal state of MD4, the following
conditions will also set the Terminal Flag bit in the
status word.
1) If bit 13 of Register 15 is “1”, and bit 14 of
Register 15 is “0”, then the Terminal Flag bit in the
status word is also set if the Busy bit or the
Subsystem Flag bit is set in the status word.
2) If bit 13 of Register 15 is “0” and bit 14 of Register
15 is “1”, then the Terminal Flag bit in the status
word is also set if any of the status word bits are set.
Note that if the Terminal Flag bit has been inhibited by Mode
Code 6, this bit will not be set by any of the above methods.
BCRTMP-45
9.0 E XCEPTION HANDLING AND
INTERRUPT LOGGING
INTERRUPT LOG LIST
POINTER REGISTER
The exception handling scheme the BCRTMP uses is based
on an interrupt structure and provides a high degree of
flexibility in:
• defining the events that cause an interrupt,
ENTRY #1
INTERRUPT STATUS
WORD
COMMAND BLOCK
POINTER
SUBADDRESS/MODE
CODE DESCRIPTOR
POINTER
TAIL POINTER
•
selecting between High-Priority and Standard
interrupts, and
•
selecting the amount of interrupt history retained.
The interrupt structure consists of internal registers that
enable interrupt generation, control bits in the RT and BC
data structures (see the Remote Terminal Descriptor
Definition section, page 30, and the Bus Controller
Command Block definition, page 35), and an Interrupt Log
List that sequentially stores an interrupt events record in
system memory.
The BCRTMP generates the Interrupt Log List (see figure
18) to allow the host CPU to view the Standard Interrupt
occurrences in chronological order. Each Interrupt Log List
entry contains three words. The first, the Interrupt Status
Word, indicates the type of interrupt (entries are only for
interrupts enabled). In the BC mode, the second word is a
Command Block Pointer that refers to the corresponding
Command Block. In the RT mode, the second word is a
Descriptor Pointer that refers to the corresponding
subaddress descriptor. The CPU-initialized third word, a
Tail Pointer, is read by the BCRTMP to determine the next
Interrupt Log List address. The list length can be as long or
as short as required. The configuration of the Tail Pointers
determines the list length.
The host CPU initializes the list by setting the tail pointers.
This gives flexibility in the list capacity and the ability to link
the list around noncontiguous blocks of memory. The host
CPU sets the list’s starting address using the Interrupt Log
List Register. The BCRTMP then updates this register with
the address of the next list entry.The internal High-Priority
Interrupt Status/Reset Register indicates the cause of a HighPriority Interrupt. The High-Priority Interrupt signal is reset
by writing a “1” to the set bits in this register.
BCRTMP-46
ENTRY #2
ENTRY #3
Figure 18. Interrupt Log List
The interrupt structure also uses three BCRTMP- driven
output signals to indicate when an interrupt event occurs:
STDINTL
Standard Interrupt Level. This signal is
asserted when one or more of the events
enabled in the Standard Interrupt Enable
Register occurs. Clear the signal by resetting
the Standard Interrupt bit in the High-Priority
Interrupt Status/Reset Register.
STDINTP
Standard Interrupt Pulse. This signal is
pulsed for each occurrence of an event
enabled in the Standard Interrupt
Enable Register.
HPINT
High-Priority Interrupt. This signal is
asserted for each occurrence of an event
enabled in the High-Priority Interrupt/Enable
Register. Writing to the corresponding bit in
the High-Priority Status/Reset Register
resets it.
Interrupt Status Word Definition
All bits in the Interrupt Status Word are active high and have the following functions:
Bit
Number
Description
BIT 15
Interrupt Status Word Accessed. The BCRT always sets this bit during the DMA Write of the Interrupt Status Word.
If the CPU resets this bit after reading the Interrupt Status Word, the bit can help the CPU determine which entries
have been acknowledged.
BIT 14
No Response Time-Out (Message Error condition). Further defines the Message Error condition to indicate that a
Response Time-Out condition has occurred.
BIT 13
(RT) Message Error (ME). Indicates the ME bit was set in the 1553 status word response.
BITs 12-8 Reserved.
BIT 7
(RT) Subaddress Event or Mode Code with Data Word Interrupt. Indicates a descriptor control word has been
accessed with either an Interrupt Upon Valid Command Received bit set or an Interrupt when Index=0 bit set (and
the Index is decremented to 0).
BIT 6
(RT) Mode Code without Data Word Interrupt. Indicates a mode code has occurred with an Interrupt When
Addressed interrupt enabled.
BIT 5
(RT) Illegal Broadcast Command. Applies to receive commands only. This bit indicates that a received command,
due to an illegal mode code or subaddress field, has been received in the broadcast mode. This does not include
invalid commands.
BIT 4
(RT) Illegal Command. This indicates that an illegal command has occurred due to an illegal mode code or
subaddress and T/R field. This does not include invalid commands.
BIT 3
(BC) Polling Comparison Match. Indicates a polling comparison interrupt.
BIT 2
(BC) Retry Fail. Indicates all the programmed retries have failed.
BIT 1
(BC, RT) Message Error. Indicates a Message Error has occurred.
BIT 0
(BC) Interrupt and Continue. This corresponds to the interrupt and continue function described in the Command Block.
BCRTMP-47
Table 2. BCRTMP Automatic Mode Code Execution
T/R
Bit
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
0
0
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
Mode
Code
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
Function
Dynamic Bus Control
Synchronize (without Data Word)
Transmit Status Word
Initiate Self-Test
Transmitter Shutdown
Override Transmitter Shutdown
Inhibit Terminal Flag Bit
Override Inhibit Terminal Flag Bit
Reset Remote Terminal
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Transmit Vector Word
Synchronize (with Data Word)
Transmit Last Command
Transmit BIT Word
Selected Transmitter Shutdown
Override Selected Transmitter Shutdown
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Automatic
Execution
No 1
No 2
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
Yes 5
No 2
Yes
Yes
No 4
No 4
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
Notes:
1. If the Dynamic Bus Control Enable bit in the RT Address Register (bit 12 of Register 10) is set, then a high priority interrupt can
occur (if enabled in Register 7) and the Dynamic Bus Control Acceptance bit is set in the status word.
2. As with any subaddress or mode code, an interrupt can be caused and used for synchronization purposes.
3. These mode codes can be used, but the BCRTMP will not automatically execute them. The designer can enable an interrupt to
occur on the reception of the mode code.
4. The host CPU is responsible for shutting down a bus in a more than dual-redundant system.
5. For the Transmit Vector Word Mode Code, the BCRTMP must access memory for the Vector Word, as with other mode codes with
data (except mode codes 18 and 19).
BCRTMP-48
READ LOG LIST TAIL PTR
STORE CMD BLOCKPTR
STORE INTERRUPT STATUS WORD
RECOGNIZE ME BIT
STORE STATUS WORD #2
BCRTMP
ACTIVITY
DESCRIPTION
FETCH CONTROL WORD
DATA 4
DATA 3
RTI 2 RTI 2
DATA 2
RTI 2
DATA 1
RTI 2 RTI 2
* STATUS
Figure 19. Bus Controller Scenario
RTI 1
400µs
344 to
392µs
* STATUS
Notes :
1. Times for DMA Arbitration and BCRTMP DMA Activities are not shown to
scale relative to the 1553B message word lengths. This is done to illustrate the
operation of these signals.
2. * = response time of 4 to 12µs.
3. DMA Arbitration represents the DMAR↓ to DMACK↑ sequence.
4. The scenario assumes that all DMA grants (DMAG) are received in the required
period of time.
FETCH DATA POINTER
FETCH COMMAND WORD #1
BCRTMP DMA
ACTIVITY
STATUS
FETCH COMMAND WORD #2
INTERRUPT
FETCH DATA POINTER
FETCH COMMAND WORD #1
FETCH CONTROL WORD
START BCRTMP
INITIALIZE REGISTERS
RTI
BC
CMD #1 CMD #2
BC
AUTO RETRY
STORE DATA WORD#4
BCRTMP DMA
ARBITRATION3
FETCH COMMAND WORD #2
MANCHESTER
DATA BUS B
*
STORE STATUS WORD #1
DATA 2
BC
STORE DATA WORD#1
DATA1
BC
STORE DATA WORD #2
CMD
RTI 1
* STATUS
DATA 4
STORE DATA WORD#3
DATA 3
RTI 2
STORE DATA WORD#4
DATA 2
RTI 2 RTI 2
STORE STATUS WORD #1
484 to
492µs
STATUS DATA1
RTI 2 RTI 2
STORE DATA WORD#1
BC
*
175 to
STORE DATA WORD#2
400µs
BC
CMD #1 CMD #2
BC
168 to
STORE DATA WORD #3
MANCHESTER
DATA BUS A
BCRTMP
ACTIVITY
DESCRIPTION
BCRTMP DMA
ACTIVITY
INTERRUPT
BCRTMP DMA
ARBITRATION3
MANCHESTER
DATA BUS B
MANCHESTER
DATA BUS A
0µs
TIME OUT TO 400 µS
FETCH TAIL POINTER
STORE STATUS WORD #2
EOL IN CONTROL WORD
SO STOP BCRTMP
STORE INTERRUPT STATUS WORD
FETCH DATA WORD #2
FETCH DATA WORD#1
FETCH DATA POINTER
FETCH COMMAND WORD
FETCH CONTROL WORD
TIME OUT TO 400 m
s
BCRTMP-49
BIT TIMES
1
2
COMMAND WORD
3
4
5
6
7
5
SYNC
REMOTE TERMINAL
ADDRESS
8
9
10
11
1
12
13
14
15
16
5
SUBADDRESS/
MODE
T/R
17
18
19
5
20
1
DATA WORD
COUNT/MODE CODE
P
DATA WORD
SYNC
DATA
P
Figure 20. MIL-STD-1553B Word Formats
BCRTMP-50
PARITY
TERMINAL FLAG
DYNAMIC BUS CONTROL ACCEPTANCE
SUBSYSTEM FLAG
BUSY
RESERVED
BROADCAST COMMANDRECEIVED
SERVICE REQUEST
Note:
T/R - transmit/receive
P - parity
REMOTE TERMINAL
ADDRESS
INSTRUMENTATION
SYNC
MESSAGE ERROR
STATUS WORD
10.0 OPERATING CONDITIONS*
(REFERENCED TO VSS) 11.0 DC ELECTRICAL
SYMBOL
PARAMETER
LIMITS
UNIT
VDD
DC supply voltage
-0.3 to + 7.0
V
VI/O
Voltage on any pin
-0.3 to V DD + 0.3
V
VI
DC input current
± 10
mA
TSTG
Storage temperature
-65 to + 150
°C
TJMAX
Maximum junction temperature
+ 175
°C
PD
Average power dissipation
ΘJC
1
Thermal resistance, junctionX0106to-case
300
mW
12
°C/Watt
Notes:
1. Does not reflect the added PD due to an output short-circuited.
* Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of thisspecification
is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
UNIT
VDD
DC supply voltage
4.5 to 5.5
V
TC
Temperature range
-55 to +125
°C
FO
Operating frequency
12 ± .01%
MHz
BCRTMP-51
11.0 DC ELECTRICAL CHARACTERISTICS
(VDD = 5.0V ± 10%; -55°C < TC < + 125°C)
SYMBOL
PARAMETER
CONDITION
MINIMUM
MAXIMUM
UNIT
VIL
Rad and
Non-Rad
Low-level input voltage
TTL inputs
CMOS inputs
VIH
Non-Rad
High-level input voltage
TTL inputs
CMOS inputs
VIH
Rad-Hard
High-level input voltage
TTL inputs 7
CMOS inputs
IIN
Non-Rad
Input leakage current
TTL inputs
Inputs with pull-up resistors
Inputs with pull-up resistors
VIN = VDD or VSS
VIN = VDD
VIN = VSS
-1
-1
-550
-1
-1
-80
mA
mA
mA
IIN
Rad-Hard
Input leakage current
TTL 7 , CMOS inputs
Inputs with pull-up resistors
Inputs with pull-up resistors
VIN = VDD or VSS
VIN = VDD
VIN = VSS
-10
150
-900
10
900
-150
mA
mA
mA
VOL
Low-level output voltage
TTL outputs
CMOS outputs
I OL = 3.2mA
I OL = 50mA
0.4
VSS + .1
V
V
VOH
High-level output voltage
TTL outputs
CMOS outputs
I OH = -400mA
I OH = -50mA
IOZ
Three-state output leakage current
TTL outputs
0.8
.3 VDD
Short-circuit output current
CIN
Input capacitance
CIO
IDD
QIDD
3
Bidirect I/O capacitance
3
Average operating current
Quiescent current
1, 2
3
Output capacitance
2.0
.7 V DD
V
V
2.2
.7 V DD
V
V
6
IOS
COUT
V
V
1, 4
2.4
VDD - .1
VO = VDD or VSS
-10
VDD = 5.5V, VO = VDD
VDD = 5.5V, VO = 0V
-100
V
V
10
mA
100
mA
mA
ƒ = 1MHz @ 0V
10
pF
ƒ = 1MHz @ 0V
15
pF
ƒ = 1MHz @ 0V
20
pF
ƒ = 12MHz, CL = 50pF
50
mA
See Note 5
3
mA
Notes:
1. Supplied as a design limit, but not guaranteed or tested.
2. Not more than one output may be shorted at a time for a maximum duration of one second.
3. Measured only for initial qualification, and after process or design changes which may affect input/output capacitance.
4. Includes current through input pull-up. Instantaneous surge currents on the order of 1 ampere can occur during output switching.
Voltage supply should be adequately sized and decoupled to handle a large current surge.
5. All inputs with internal pull-ups should be left floating. All other inputs should be tied high or low.
6. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions
VIH = VIH(min) +20%, -0%; VIL = VIL(max) +0%, -50%, as specified herein, for TTL-compatible inputs.
Devices may be tested using input voltage within the above specified range, but are guaranteed to VIH(min) and VIL(max).
7. To 1.0E6 total dose; above this level, CMOS I/Os required.
BCRTMP-52
12.0 AC ELECTRICAL CHARACTERISTICS
(OVER RECOMMENDED OPERATING CONDITIONS)
VIH
1
INPUT VIL MAX
tb
ta
IN-PHASE
OUTPUT
OUT-OF-PHASE
OUTPUT
VIH MIN
VIL MAX
1
tc
2
2
VOH MIN
VOL MAX
2
td
2
VOH MIN
VOL MAX
te
VOH MIN
BUS
VOL MAX
tf
tg
th
SYMBOL
ta
PARAMETER
INPUT↑ to response↑
INPUT↓ to response↓
tb
tc
td
INPUT↑ to response↓
INPUT↓ to response↑
INPUT↓ to data valid
INPUT↓ to high Z
INPUT↑ to high Z
INPUT↑ to data valid
te
tf
tg
th
Notes:
1. Timing measurements made at (VIH MIN + VIL MAX)/2.
2. Timing measurements made at (VOL MAX + VOH MIN)/2.
3. Based on 50pF load.
4. Unless otherwise noted, all AC electrical characteristics are guaranteed by design or characterization.
Figure 21. Typical Timing Measurements
5V
IREF (source)
90%
3V
90%
VREF
•
50pF
10%
10%
0V
IREF (sink)
Output Loading
< 2ns
< 2ns
Input Pulses
Note:
Figure 22. AC Test Loads and Input Waveforms
BCRTMP-53
DMA GRANT RECOGNIZED ON THIS EDGE
MCLKD2
tSHL1
DMAR
DMAG
tPW2
DMACK
TSCTL
MEMCSO
ADDRESS
DATA
RWR/RRD2
AEN
BURST
tPZL1
tPHL1
tOOZL1
tPHL2
tPHL4
SYMBOL
tSHL1
PARAMETER
DMACK↓ to DMAR High Impedance
tPHL1 1
tPHL2
tPZL1
tHLH2
tPHL3
tPW2
tOOZL1
DMAG↓ to DMACK↓ 3
DMAG↓ to TSCTL↓
TSCTL↓ to ADDRESS valid
RWR/RRD↑ to DMACK High Impedance
TSCTL↓ to RWR/RRD↓
DMAG↓ to DMAG↑
DMAR↓ to Burst↑
tPHL4
tPHL4
DMAR↓ to DMAG↓
DMAR↓ to DMAG↓
4,6
5,6
tHLH2
tPHL3
MIN
0
0
2xMCLK
MAX
10
45
4xMCLK
0
40
UNITS
ns
ns
ns
ns
THMC1-10
MCLK-20
MCLK
THMC1+10
MCLK+20
6xMCLK
ns
ns
ns
0
0
0
10
3.5 (1.9)
1.9 (0.8)
ns
µs
µs
Notes:
1. Guaranteed by test.
2. See figures 24 and 25 for detailed DMA read and write timing.
3 DMAG must be asserted at least 45ns prior to the rising edge of MCLKD2 in order to be recognized for the next MCLKD2 cycle.
If DMAG is not asserted at least 45ns prior to the rising edge of MCLKD2, DMAG is not recognized until the following MCLKD2
cycle.
4. Provided MCLK = 12MHz. Number in parentheses indicates the longest DMAR↓ to DMAG↓ allowed during worst-case bus switching
conditions in order to meet MIL-STD-1553B RT Response Time. The number not in parentheses applies to all other circumstances.
5 Provided MCLK = 6MHz. Number in parentheses indicates the longest DMAR↓ to DMAG↓ allowed during worst-case bus switching
conditions in order to meet MIL-STD-1553B RT Response Time. The number not in parentheses applies to all other circumstances.
6. The maximum limit for this specification applies only when using DMA Legalization (MD0=1)
MCLK = period of the memory clock cycle.
BURST signal is for multiple-word DMA accesses.
THMC1isequivalenttothepositivephaseofMCLK(seefigure24).
Figure 23. BURST DMA Timing
BCRTMP-54
tIOHL1
tPLH1
THMC1
THMC2
MCLK
MCLKD2
TSCTL
MEMCSO
tPLH2
tHLZ2
ADDRESS
DATA
RRD
tSHL1
SYMBOL
tSHL1
PARAMETER
ADDRESS valid to RRD↓
tSLH1
tPW1
tHLZ1
MIN
(ADDRESS setup) THMC2-20
MAX
UNITS
THMC2
ns
MCLK+5
ns
THMC1
ns
tPW1
RRD↓ to RRD↑
tHLZ2
RRD↑ to ADDRESS High Impedance (ADDRESS hold) THMC1-10
tHLZ1
RRD↑ to DATA High Impedance
(Data hold)
5
-
ns
tSLH1
Data valid to RRD↑
(Data setup)
40
-
ns
0
40
ns
tPLH1
tPLH2
tIOHL1
1
1
MCLK↑ to MCLKD2↑
MCLK-5
MCLK↑ to TSCTL/MEMCSO↓
0
40
ns
MCLK↑ to RRD↓
0
60
ns
Note:
1. Guaranteed by test.
Figure 24. BCRTMP DMA Read Timing (One-Word Read)
BCRTMP-55
tPLH1
tIOHL1
THMC1
THMC2
MCLK
MCLKD2
TSCTL
MEMCSO
tPLH2
tHLZ2
ADDRESS
DATA
RWR
tSHL1
SYMBOL
tSHL1
tOOZL1 1
tHLZ1
tHLZ2
tPW1
tPLH1
tPLH2
tIOHL1
1
1
PARAMETER
tOOZL1
tHLZ1
tPW1
MIN
(ADDRESS setup) THMC2-20
ADDRESS valid to RWR↓
RWR↓ to DATA valid
0
RWR↑ to DATA High Impedance
(DATA hold)
THMC1-20
RWR↑ to ADDRESS High Impedance (ADDRESS hold) THMC1-20
RWR↓ to RWR↑
MCLK-5
MCLK↑ to MCLKD2↑
0
MCLK↑ to TSCTL/MEMCSO↓
0
MCLK↑ to RWR↓
0
Note:
1. Guaranteed by test.
Figure 25. BCRTMP DMA Write Timing (One-Word Write)
BCRTMP-56
MAX
UNITS
THMC2
30
THMC1
THMC1
MCLK+5
40
40
60
ns
ns
ns
ns
ns
ns
ns
ns
tOOZH2
tOOZH1
tHLH1
ADDRESS
DATA
RD+CS
tHLH2
tPW1
tPW2
SYMBOL
PARAMETER
tOOZH2
ADDRESS valid to DATA valid
tHLH2
RD+CS↑ to DATA High Impedance
(DATA hold)
tOOZH1 1 RD+CS↓ to DATA Valid
(DATA access)
tHLH1
RD+CS↑ to ADDRESS High Impedance (ADDRESS hold)
tPW1
RD+CS↓ to RD+CS↑
tPW2
RD+CS↑ to RD+CS↓
Notes:
1. Guaranteed by test.
2. User must adhere to both tOOZH1 and tOOZH2 timing constraints to ensure valid data.
MIN
5
5
60
80
MAX
80
50
60
-
UNITS
ns
ns
ns
ns
ns
ns
Figure 26. BCRTMP Register Read Timing
tSHL1
tPW1
tHLH2
ADDRESS
DATA
WR+CS
tHLH1
tSLH1
SYMBOL
tSHL1
tSLH1
tPW1
tHLH1
tHLH2
tPW2
PARAMETER
ADDRESS valid to WR+CS↓
DATA valid to WR+CS↑
WR+CS↓ to WR+CS↑
tPW2
MIN
(ADDRESS setup)
(DATA setup)
(DATA hold)
WR+CS↑ to DATA High Impedance
WR+CS↑ to ADDRESS High Impedance (ADDRESS hold)
WR+CS↑ to WR+CS↓
60
60
60
10
10
80
MAX
-
UNITS
ns
ns
ns
ns
ns
ns
Figure 27. BCRTMP Register Write Timing
BCRTMP-57
tPLH1
RD
RRD
tPLH2
WR
RWR
tPLH3
MEMCSI
MEMCSO
SYMBOL
tPLH1 1
tPLH2 1
tPLH3 1
PARAMETER
RD↓ to RRD↓
WR↓ to RWR↓
MEMCSI↓ to MEMCSO↓
MIN
MAX
UNITS
0
30
ns
0
0
30
30
ns
ns
Note:
1. Guaranteed by test.
Figure 28. BCRTMP Dual-Port Interface Timing Delays
t PZ
MANCHESTER C
D
D
DMA
ACTIVITY
SYMBOL
tPZL1
PARAMETER
Data word to DMA activity
MIN
0
MAX
4
UNITS
µs
This diagram indicates the relationship between the incoming Manchester code and DMA activity (i.e., DMAR↓ to DMACK↑).
Note:
The pulsewidth = (11ms -tDMA -tPZL1) where tDMA is the time to complete DMA activity (i.e., DMAR↓ to DMACK↑).
Figure 29. DMA Activity(RT Mode)
BCRTMP-58
tPLH2
MCLK
MCLKD2
DMAR
DMAG
DMAGO
DMACK
tSHL1
t PHL1
SYMBOL
PARAMETER
MIN
MAX
UNITS
tPHL1
DMAG↓ to DMAGO↓
0
30
ns
tSHL1
DMACK↓ to DMAR High Impedance
0
10
ns
tPLH2 1
MCLK↑ to MCLKD2↑
0
40
ns
Notes:
1. Guaranteed by test.
2. When DMAG is asserted before DMAR, the DMAG signal passes through the BCRTMP as DMAGO.
Figure 30. BCRTMP Arbitration when DMAG is Asserted before Arbitration
Figure 27. BCRTMP Register WriteTiming
BCRTMP-59
tPW1
LGLEN
tHLH2
t HLZ1
LGLCMD
tHLH1
tSLH1
LGL0-10
SYMBOL
PARAMETER
MIN
tPW1
LGLEN↓ to LGLEN↑
tHLH1
LGLEN↓ to Legalization Bus Valid
tSLH1
LGLCMD↑ to LGLEN↑
(Setup Time)
tHLZ1
LGLEN↑ to LGLCMD Invalid
(Hold Time)
tHLH2
Legalization Bus Valid to LGLCMD¦
(Pulse width)
(Setup Time)
Figure 31. BCRTMP Legalization Bus Timing
BCRTMP-60
MAX
UNITS
ns
750
200
ns
100
ns
ns
0
450
ns
DMAR
DMAG
DMACK
RWR
RRD
TSCTL
BURST
STDINTL
STDINTP
tOOHL1
tOOLH1
t OOHL2
SYMBOL
tOOLH1
PARAMETER
TSCTL↑ to STDINTP/STDINTL↓
MIN
-
MAX
1
UNITS
µs
340
ns
tPW1
STDINTP↓ to STDINTP↑
tOOHL1
DMACK↓ to RWR↓
3xMCLK-10
tOOHL2
DMAG↓ to STDINTL↓
8xMCLK+0.5 10xMCLK+1
320
tPW1
5xMCLK
ns
ns
Note:
Address and data bus relationships (not shown) are identical to figure 23.
Figure 32. BCRTMP Interrupt Log List Entry Operation Timing
BCRTMP-61
MD1
MD0
LOCK
MDO6
MDO5
MDO4
MDO3
MDO2
MDO1
MDO0
MRST
WRAPEN
WRAPF
ALTWRAP
CLK
NC
V SS
V DD
NC
NC
BCRTF
SSYSF
LGLEN
DOMC
LGLCMD
ERR
MC
BRDCAST
LGL10
LGL9
LGL8
LGL7
LGL6
13.0 PACKAGE OUTLINE DRAWINGS
MD2
MD3
18
116
1
132
33
100
34
99
66
50
67
84
RAZ
TAO
TAZ
RBO
RBZ
TBO
TBZ
MCLK
TEST
AEN
CS
RD
WR
MEMCSI
NC
V SS
V DD
NC
MEMCSO
RRD
RWR
DMAR
DMAG
MCLKD2
DMACK
TSCTL
BURST
DMAGO
FBUSY
BUSYACK
ACTIVE
STDINTL
STDINTP
MD4
MD5
MD6
MD7
A0
A1
A2
A3
A4
A5
A6
A7
NC
VSS
VDD
NC
A8
A9
A10
A11
A12
A13
A14
A15
RTA0
RTA1
RTA2
RTA3
RTA4
RTPT
RAO
Figure 33a. BCRTMP Flatpack Identification (Top View)
BCRTMP-62
LGL5
LGL4
LGL3
LGL2
LGL1
LGL0
D15
D14
D13
D12
D11
D10
D9
D8
D7
NC
VDD
VSS
NC
D6
D5
D4
D3
D2
D1
D0
COMSTR
CHA/B
EXTOVR
BCRTSEL
TIMRONB
TIMRONA
HPINT
R
P
N
M
L
K
J
H
G
F
E
REGISTRATION
D
C
B
A
1 2
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
-
B1
NC
B2
LGL2
B3
D14
B4
D13
B5
D12
B6
D8
B7
D7
B8
D6
B9
D4
B10
D3
B11
NC
B12
CHA/B
BCRTSEL B13
B14
NC
B15
NC
-
NC
LGL5
LGL1
D15
NC
D10
D9
D5
D1
D0
EXTOVR
TIMRONA
HPINT
STDINTP
BUSYACK
F1
F2
F3
F13
F14
F15
-
LGLEN
LGLCMD
MC
DMAG
DMAR
RRD
G1
G2
G3
G13
G14
G15
-
SSYSF
ERR
DOMC
VDD
RWR
MEMCSO
3
4
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
H1
H2
H3
H13
H14
H15
-
-
5
6
LGL9
LGL6
LGL4
LGL3
LGL0
D11
VDD
VSS
D2
COMSTR
TIMRONB
NC
STDINTL
FBUSY
TSCTL
NC
BCRTF
VDD
VSS
WR
MEMCSI
7
8
9 10 11 12 13 14 15
N1
N2
N3
N4
N5
N6
N7
N8
N9
N10
N11
N12
N13
N14
N15
-
MDO2
MDO5
MD0
NC
MD4
A0
A3
VSS
VDD
A12
RTA1
RTA4
RTPTY
RAZ
RBO
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15
-
MDO6
MD1
MD2
MD3
MD6
A1
A2
A6
A10
A11
NC
RTA0
RTA2
RAO
NC
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
-
NC
NC
MD5
MD7
NC
A4
A5
A7
A8
A9
A13
A14
A15
RTA3
NC
D1
D2
D3
D4
D13
D14
D15
E1
E2
E3
E13
E14
E15
-
BRDCAST
LGL7
NC
NC
ACTIVE
BURST
DMACK
NC
LGL10
LGL8
DMAGO
NC
MCLKD2
J1
J2
J3
J13
J14
J15
-
CLK
WRAPF
VSS
AEN
TEST
RD
K1
K2
K3
K13
K14
K15
-
ALTWRAP
WRAPEN
MRST
TBZ
MCLK
CS
L1
L2
L3
L13
L14
L15
-
MDO0
NC
MDO4
TAZ
RBZ
NC
M1
M2
M3
M13
M14
M15
-
MDO1
MDO3
LOCK
NC
TAO
TBO
Figure 33b. BCRTMP Pingrid Array Pin Identification (Bottom View)
BCRTMP-63
Package Selection Guide
RTI
24-pin DIP
(single cavity)
36-pin DIP
(dual cavity)
68-pin PGA
84-pin PGA
144-pin PGA
84-lead LCC
36-lead FP
(dual cavity)
(50-mil ctr)
84-lead FP
132-lead FP
RTMP
RTR
Product
BCRT BCRTM BCRTMP
RTS
XCVR
X
X
X
X
X
X
X
X1
X
X1
X
X
X
X
X
X
X
NOTE:
1. 84LCC package is not available radiation-hardened.
Packaging-1
D
1.565 ± 0.025
A
0.130 MAX.
-A-
Q
0.050 ± 0.010
0.040 REF.
0.080 REF.
(2 Places)
A
L
0.130 ±0.010
0.100 REF.
(4 Places)
E
1.565 ± 0.025
-B-
PIN 1 I.D.
(Geometry Optional)
e
0.100
TYP.
TOP VIEW
-CA
(Base Plane)
b
0.018 ± 0.002
0.030 C A B
0.010 C 2
R
SIDE VIEW
P
N
M
L
K
J
D1/E1
1.400
H
G
F
E
D
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
PIN 1 I.D.
(Geometry Optional)
BOTTOM VIEW
0.003 MIN. TYP.
Notes:
1. True position applies to pins at base plane (datum C).
2. True position applies at pin tips.
3. All package finishes are per MIL-M-38510.
4. Letter designations are for cross-reference to MIL-M-38510.
144-Pin Pingrid Array
Packaging-2
1
D/E
1.525 ± 0.015 SQ.
D1/E1
0.950 ± 0.015 SQ.
A
0.110
0.006
A
PIN 1 I.D.
(Geometry
Optional)
e
0.025
SEE DETAIL A
A
LEAD KOVAR
TOP VIEW
C
0.005 + 0.002
- 0.001
L
0.250
MIN.
REF.
S1
0.005 MIN. TYP.
SIDE VIEW
0.018 MAX. REF.
0.014 MAX. REF.
(At Braze Pads)
DETAIL A
BOTTOM VIEW A-A
Notes:
1. All package finishes are per MIL-M-38510.
2. Letter designations are for cross-reference to MIL-M-38510.
132-Lead Flatpack (25-MIL Lead Spacing)
Packaging-3
A
0.115 MAX.
D/E
1.150 ± 0.015 SQ.
A1
0.080 ± 0.008
A
PIN 1 I.D.
(Geometry Optional)
TOP VIEW
SIDE VIEW
L/L1
0.050 ± 0.005 TYP.
h
0.040 x 45_
REF. (3 Places)
B1
0.025 ± 0.003
e
0.050
J
0.020 X 455 REF.
e1
0.015 MIN.
PIN 1 I.D.
(Geometry Optional)
BOTTOM VIEW A-A
Notes:
1. All package finishes are per MIL-M-38510.
2. Letter designations are for cross-reference to MIL-M-38510.
84-LCC
Packaging-4
A
D/E
1.810 ± 0.015 SQ.
D1/E1
1.150 ± 0.012 SQ.
A
0.110
0.060
PIN 1 I.D.
(Geometry
Optional)
A
e
0.050
b
0.016 ± 0.002
SEE DETAIL A
A
LEAD KOVAR
C
0.007 ± 0.001
TOP VIEW
L
0.260
MIN.
REF.
S1
0.005 MIN. TYP.
SIDE VIEW
0.018 MAX. REF.
0.014 MAX.
REF.
(At Braze Pads)
BOTTOM VIEW A-A
DETAIL A
Notes:
1. All package finishes are per MIL-M-38510.
2. Letter designations are for cross-reference to MIL-M-38510.
84-Lead Flatpack (50-MIL Lead Spacing)
Packaging-5
D
1.100 ± 0.020
A
0.130 MAX.
-A-
Q
0.050 ± 0.010
A
L
0.130 ± 0.010
E
1.100 ± 0.020
PIN 1 I.D.
(Geometry Optional)
-B-
-C(Base Plane)
TOP VIEW
e
0.100
TYP.
0.030 C A B
0.010 C 2
SIDE VIEW
L
K
J
H
G
D1/
1.000
F
E
D
1
A
b
0.018 ± 0.002
2
3
4
5
6
7
8 9 10 11
PIN 1 I.D.
(Geometry Optional)
BOTTOM VIEW A-A
0.003 MIN.
Notes:
1. True position applies to pins at base plane (datum C).
2. True position applies at pin tips.
3. All packages finishes are per MIL-M-38510.
4. Letter designations are for cross-reference to MIL-M-38510.
84-Pin Pingrid Array
Packaging-6
1
D
1.100 ± 0.020
A
0.130 MAX.
Q
0.050 ± 0.010
-A-
A
L
0.130 ± 0.010
E
1.100 ± 0.020
-B-
PIN 1 I.D.
(Geometry Optional)
A
-C(Base Plane)
TOP
b
0.010 ± 0.002
∅ 0.030 C A B
∅ 0.010 C 2
e
0.100
TYP.
1
SIDE VIEW
L
K
J
H
G
F
E
D
C
B
A
D1/E1
1.00
1 2 3 4 5 6
PIN 1 I.D.
(Geometry Optional)
7
8
9
10 11
0.003 MIN. TYP.
BOTTOM VIEW A-A
Notes:
1 True position applies to pins at base plane (datum C).
2 True position applies at pin tips.
3. All packages finishes are per MIL-M-38510.
4. Letter designations are for cross-reference to MIL-M-38510.
68-Pin Pingrid Array
Packaging-7
E
0.750 ± 0.015
L
0.490
MIN.
b
0.015 ± 0.002
D
1.800 ± 0.025
e
0.10
PIN 1 I.D.
(Geometry Optional)
TOP VIEW
c
0.008
+ 0.002
- 0.001
A
0.130 MAX.
END VIEW
Notes:
1 All package finishes are per MIL-M-38510.
2. It is recommended that package ceramic be mounted to
a heat removal rail located on the printed circuit board.
A thermally conductive material such as MERECO XLN-589 or
equivalent should be used.
3. Letter designations are for cross-reference to MIL-M-38510.
36-Lead Flatpack, Dual Cavity (100-MIL Lead Spacing)
Packaging-8
Q
0.080 ± 0.010
(At Ceramic Body)
E
0.700 + 0.015
L
0.330
MIN.
b
0.016 + 0.002
D
1.000 ± 0.025
e
0.050
PIN 1 I.D
(Geometry Optional)
TOP
+ 0.002
c
0.007 - 0.001
A
0.100 MAX.
END
Q
0.070 + 0.010
(At Ceramic Body)
Notes:
1. All package finishes are per MIL-M-38510.
2. It is recommended that package ceramic be mounted to
a heat removal rail located on the printed circuit board.
A thermally conductive material such as MERECO XLN-589
or equivalent should be used.
3. Letter designations are for cross-reference to MIL-M-38510.
36-Lead Flatpack, Dual Cavity (50-MIL Lead Spacing)
Packaging-9
E
0.590 ± 0.012
S1
0.005 MIN.
S2
0.005 MAX.
e
0.100
D
1.800 ± 0.025
b
0.018 ± 0.002
PIN 1 I.D.
(Geometry Optional)
TOP VIEW
C
0.010 +- 0.002
0.001
E1
0.600 + 0.010
(At Seating Plane)
A
0.155 MAX.
L/L1
0.150 MIN.
SIDE VIEW
Notes:
1. All package finishes are per MIL-M-38510.
2. It is recommended that package ceramic be mounted to
a heat removal rail located on the printed circuit board.
A thermally conductive material such as MERECO XLN-589
or equivalent should be used.
3. Letter designations are for cross-reference to MIL-M-38510.
END VIEW
36-Lead Side-Brazed DIP, Dual Cavity
Packaging-10
ORDERING INFORMATION
UT1553B BCRTMP Bus Controller Remote Terminal Multi-Protocol: S
5962
*
*
*
*
*
Lead Finish:
(A) = Solder
(C) = Gold
(X) = Optional
Case Outline:
(X) = 144 pin PGA
(Y) = 132 pin FP
Class Designator:
(-) = Blank or No field is QML Q
Drawing Number: 8950101
Total Dose:
(-) = None
Federal Stock Class Designator: No options
Notes:
1. Lead finish (A, C, or X) must be specified.
2. If an "X" is specified when ordering, part marking will match the lead finish and will be either "A" (solder) or "C" (gold).
3. 132 FP available with gold lead finish only.
4. For QML Q product, the Q designator is intentionally left blank in the SMD number (e.g. 5962-8950101YC).
UT1553B BCRTMP Bus Controller Remote Terminal Multi-Protocol
UT1553B
BCRTMP - *
*
*
Lead Finish:
(A) = Solder
(C) = Gold
(X) = Optional
Screening:
(C) = Military Temperature
(P) = Prototype
Package Type:
(G) = 144 pin PGA
(W) = 132 pin FPv (Gold only)
UTMC Core Part Number
Notes:
1. Lead finish (A, C, or X) must be specified.
2. If an "X" is specified when ordering, part marking will match the lead finish and will be either "A" (solder) or "C" (gold).
3. Mil Temp range flow per UTMC’s manufacturing flows document. Devices are tested at -55°C, room temperature, and 125°C. Radiation neither tested
nor guaranteed.
4. Prototpe flow per UTMC’s document manufacturing flows and are tested at 25°C only. Radiation characteristics neither tested nor guaranteed. Lead
finish is GOLD except for LCC
5. 132 FP available with gold lead only.
E
0.590 ± 0.015
S1
0.005 MIN.
S2
0.005 MAX.
e
0.100
D
1.200 ± 0.025
b
0.018 ± 0.002
PIN 1 I.D.
(Geometry Optional)
TOP VIEW
+ 0.002
C
0.010 - 0.001
E1
0.600 + 0.010
(At Seating Plane)
L/L1
0.150 MIN.
A
0.140 MAX.
SIDE VIEW
Notes:
1. All package finishes are per MIL-M-38510.
2. It is recommended that package ceramic be mounted to
a heat removal rail located on the printed circuit board.
A thermally conductive material such as MERECO XLN-589 or
equivalent should be used.
3. Letter designations are for cross-reference to MIL-M-38510.
END VIEW
24-Lead Side-Brazed DIP, Single Cavity
Packaging-11
ORDERING INFORMATION
UT1553B BCRTMP Bus Controller Remote Terminal Multi-Protocol: S
5962
*
*
*
*
*
Lead Finish:
(A) = Solder
(C) = Gold
(X) = Optional
Case Outline:
(X) = 144 pin PGA
(Y) = 132 pin FP
Class Designator:
(-) = Blank or No field is QML Q
Drawing Number: 8950101
Total Dose:
(-) = None
Federal Stock Class Designator: No options
Notes:
1. Lead finish (A, C, or X) must be specified.
2. If an "X" is specified when ordering, part marking will match the lead finish and will be either "A" (solder) or "C" (gold).
3. 132 FP available with gold lead finish only.
4. For QML Q product, the Q designator is intentionally left blank in the SMD number (e.g. 5962-8950101YC).
UT1553B BCRTMP Bus Controller Remote Terminal Multi-Protocol
UT1553B
BCRTMP - *
*
*
Lead Finish:
(A) = Solder
(C) = Gold
(X) = Optional
Screening:
(C) = Military Temperature
(P) = Prototype
Package Type:
(G) = 144 pin PGA
(W) = 132 pin FPv (Gold only)
UTMC Core Part Number
Notes:
1. Lead finish (A, C, or X) must be specified.
2. If an "X" is specified when ordering, part marking will match the lead finish and will be either "A" (solder) or "C" (gold).
3. Mil Temp range flow per UTMC’s manufacturing flows document. Devices are tested at -55°C, room temperature, and 125°C. Radiation neither tested
nor guaranteed.
4. Prototpe flow per UTMC’s document manufacturing flows and are tested at 25°C only. Radiation characteristics neither tested nor guaranteed. Lead
finish is GOLD except for LCC
5. 132 FP available with gold lead only.