Standard Products UT54ACS280/UT54ACTS280 9-Bit Parity Generators/Checkers Datasheet November 2010 www.aeroflex.com/logic FEATURES Generates either odd or even parity for nine data lines Cascadable for n-bits parity 1.2μ CMOS - Latchup immune High speed Low power consumption Single 5 volt supply Available QML Q or V processes Flexible package - 14-pin DIP - 14-lead flatpack UT54ACS280 - SMD 5962-96582 UT54ACTS280 - SMD 5962-96583 PINOUTS 14-Pin DIP Top View G 1 14 VDD H 2 13 F NC 3 12 E I ∑ EVEN 4 5 11 10 D C ∑ ODD VSS 6 7 9 8 B A 14-Lead Flatpack Top View DESCRIPTION The UT54ACS280 and the UT54ACTS280 are 9-bit parity generators/checkers that use high-performance circuitry and features odd and even outputs to facilitate operation of either odd or even parity application. The word-length capability is easily expanded by cascading. OUTPUT Σ ODD 0,2,4,6,8 H L 1,3,5,7,9 L H LOGIC SYMBOL A B C D E F G H I (8) 2k (9) (10) (11) (12) (5) ∑ EVEN (6) ∑ ODD (13) (1) (2) (4) Note: 1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and IEC Publication 617-12. 14 VDD H 2 13 F NC 3 12 E I 4 5 11 10 D C 6 9 B 7 8 A ∑ ODD VSS FUNCTION TABLE Σ EVEN 1 ∑ EVEN The devices are characterized over full military temperature range of -55°C to +125°C. NUMBER OF INPUTS A THRU I THAT ARE HIGH G 1 LOGIC DIAGRAM A (8) ( B (9) C (10) (5) D E F Σ EVEN (11) (12) (13) (6) (1) G (2) H (4) I 2 Σ ODD OPERATIONAL ENVIRONMENT1 PARAMETER LIMIT UNITS Total Dose 1.0E6 rads(Si) SEU Threshold 2 80 MeV-cm2/mg SEL Threshold 120 MeV-cm2/mg Neutron Fluence 1.0E14 n/cm2 Notes: 1. Logic will not latchup during radiation exposure within the limits defined in the table. 2. Device storage elements are immune to SEU affects. ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage -0.3 to 7.0 V VI/O Input voltage any pin -.3 to VDD +.3 V TSTG Storage Temperature range -65 to +150 °C TJ Maximum junction temperature +175 °C TLS Lead temperature (soldering 5 seconds) +300 °C ΘJC Thermal resistance junction to case 20 °C/W II DC input current ±10 mA PD Maximum power dissipation 1 W Note: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage 4.5 to 5.5 V VIN Input voltage any pin 0 to VDD V TC Temperature range -55 to + 125 °C 3 DC ELECTRICAL CHARACTERISTICS 7 (VDD = 5.0V ±10%; VSS = 0V 6, -55°C < TC < +125°C); Unless otherwise noted, Tc is per the temperature range ordered. SYMBOL VIL VIH IIN PARAMETER CONDITION MIN Low-level input voltage 1 ACTS ACS High-level input voltage 1 ACTS ACS MAX UNIT 0.8 .3VDD V .5VDD .7VDD V Input leakage current ACTS/ACS VIN = VDD or VSS Low-level output voltage 3 ACTS ACS IOL = 8.0mA IOL = 100μA High-level output voltage 3 ACTS ACS IOH = -8.0mA IOH = -100μA Short-circuit output current 2 ,4 ACTS/ACS VO = VDD and VSS -200 Output current10 VIN = VDD or VSS 8 mA (Sink) VOL = 0.4V Output current10 VIN = VDD or VSS -8 mA (Source) VOH = VDD - 0.4V Ptotal Power dissipation 2, 8, 9 CL = 50pF 2.2 mW/ MHz IDDQ Quiescent Supply Current VDD = 5.5V 10 μA Quiescent Supply Current Delta For input under test 1.6 mA VOL VOH IOS IOL IOH ΔIDDQ ACTS -1 1 μA 0.40 0.25 V .7VDD VDD - 0.25 V 200 mA VIN = VDD - 2.1V For all other inputs VIN = VDD or VSS VDD = 5.5V CIN COUT Input capacitance 5 ƒ = 1MHz @ 0V 15 pF Output capacitance 5 ƒ = 1MHz @ 0V 15 pF 4 Notes: 1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%, 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed to VIH(min) and VIL(max). 2. Supplied as a design limit but not guaranteed or tested. 3. Per MIL-PRF-38535, for current density ≤ 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pF/MHz. 4. Not more than one output may be shorted at a time for maximum duration of one second. 5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at frequency of 1MHz and a signal amplitude of 50mV rms maximum. 6. Maximum allowable relative shift equals 50mV. 7. All specifications valid for radiation dose ≤ 1E6 rads(Si). 8. Power does not include power contribution of any TTL output sink current. 9. Power dissipation specified per switching output. 10. This value is guaranteed based on characterization data, but not tested. 5 AC ELECTRICAL CHARACTERISTICS 2 (VDD = 5.0V ±10%; VSS = 0V 1, -55°C < TC < +125°C); Unless otherwise noted, Tc is per the temperature range ordered. SYMBOL PARAMETER MINIMUM MAXIMUM UNIT tPLH Any input to ∑ even 1 20 ns tPHL Any input to ∑ even 1 20 ns tPHL Any input to ∑ odd 1 22 ns tPLH Any input to ∑ odd 1 20 ns Notes: 1. Maximum allowable relative shift equals 50mV. 2. All specifications valid for radiation dose ≤ 1E6 rads(Si). 6 PACKAGING Side-Brazed Packages 7 FLATPACK PACKAGES 8 UT54ACS280/UT54ACTS280: SMD 5962 * ***** ** * * * Lead Finish: (Notes 1 & 2) A = Solder C = Gold X = Optional Package Type: X = 14-lead ceramic bottom-brazed dual-in-line Flatpack C = 14-lead ceramic side-brazed dip Class Designator: Q = QML Class Q V = QML Class V Device Type: 01 Drawing Number: 96582 = UT54ACS280 96583 = UT54ACTS280 Total Dose: (Notes 3 & 4) R = 1E5 rads(Si) F = 3E5 rads(Si) G = 5E5 rads(Si) H = 1E6 rads(Si) Notes: 1. Lead finish (A,C, or X) must be specified. 2. If an “X” is specified when ordering, part marking will match the lead finish and will be either “A” (solder) or “C” (gold). 3. Total dose radiation must be specified when ordering. QML Q and QML V not available without radiation hardening. For prototype inquiries, contact factory. 4. Device type 02 is only offered with a TID tolerance guarantee of 3E5 rads(Si) or 1E6 rads(Si) and is tested in accordance with MIL-STD-883 Test Method 1019 Condition A and section 3.11.2. Device type 03 is only offered with a TID tolerance guarantee of 1E5 rads(Si), 3E5 rads(Si), and 5E5 rads(Si), and is tested in accordance with MIL-STD-883 Test Method 1019 Condition A. 9 Aeroflex Colorado Springs - Datasheet Definition Advanced Datasheet - Product In Development Preliminary Datasheet - Shipping Prototype Datasheet - Shipping QML & Reduced Hi-Rel COLORADO Toll Free: 800-645-8862 Fax: 719-594-8468 INTERNATIONAL Tel: 805-778-9229 Fax: 805-778-1980 NORTHEAST Tel: 603-888-3975 Fax: 603-888-4585 SE AND MID-ATLANTIC Tel: 321-951-4164 Fax: 321-951-4254 WEST COAST Tel: 949-362-2260 Fax: 949-362-2266 CENTRAL Tel: 719-594-8017 Fax: 719-594-8468 www.aeroflex.com [email protected] Aeroflex UTMC Microelectronic Systems Inc. (Aeroflex) reserves the right to make changes to any products and services herein at any time without notice. Consult Aeroflex or an authorized sales representative to verify that the information in this data sheet is current before using this product. Aeroflex does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by Aeroflex; nor does the purchase, lease, or use of a product or service from Aeroflex convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual rights of Aeroflex or of third parties. Our passion for performance is defined by three attributes represented by these three icons: solution-minded, performance-driven and customer-focused 10