UT8SF2M48 - Aeroflex Microelectronic Solutions

Standard Products
UT8SF2M48 96Megabit
Flow-thru SSRAM
Preliminary Datasheet
July 2015
The most important thing we build is trust
FEATURES
 Synchronous SRAM organized as 2Meg words x 48bit
 Continuous Data Transfer (CDT) architecture eliminates
wait states between read and write operations
 Supports 40MHz to 80MHz bus operations
 Internally self-timed output buffer control eliminates the
need for synchronous output enable
 Registered inputs and outputs for flow-thru operation
 Single 2.5V to 3.3V supply
 Clock-to-output time
- Clk to Q = 12ns
 Clock Enable (CEN) pin to enable clock and suspend
operation
 Synchronous self-timed writes
 Three Chip Enables (CS0, CS1, CS2) for simple depth
expansion
 "ZZ" Sleep Mode option for partial power-down
 "SHUTDOWN" Mode option for deep power-down
 Four Word Burst Capability--linear or interleaved
 Operational Environment
- Total Dose: 100 krad(Si)
INTRODUCTION
The UT8SF2M48 is a high performance 100,663,296-bit
synchronous static random access memory (SSRAM) device
that is organized as 2M words of 48 bits. This device is
equipped with three chip selects (CS0, CS1, and CS2), a write
enable (WE), and an output enable (OE) pin, allowing for
significant design flexibility without bus contention. The
device supports a four word burst function using (ADV_LD).
All synchronous inputs are registered on the rising edge of the
clock provided the Clock Enable (CEN) input is enabled LOW.
Operations are suspended when CEN is disabled HIGH and the
previous operation is extended. Write operation control signals
are WE and six byte write enables BWE[5:0]. All write
operations are performed by internal self-timed circuitry.
For easy bank selection, three synchronous Chip Enables
(CS0, CS1, CS2) and an asynchronous Output Enable (OE)
provide for output tri-state control. The output drivers are
synchronously tri-stated during the data portion of a write
sequence to avoid bus contention.
- SEL Immune: ≤ 100MeV-cm2/mg
- SEU error rate: 1.7x10-6 errors/bit-day
 Package options:
- 288-lead CLGA, CCGA, and CBGA
 Standard Microelectronics Drawing (SMD) 5962-15225
- QMLQ and Q+ pending
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ADDR
CMD
User Command Interface Logic
Housekeeping,
and Fault Logic
Main Memory Array 2Meg x 48
CLK
Write
Address and
Command
Queue
Write Data
Coherency Logic
Pipeline
Register
Write Data
Steering Logic
Stall Cycle
Registers
Write Data
Queue
Read Data
Steering and
Fault Logic
DIN
QOUT
Figure 1. UT8SF2M48 Block Diagram
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Table 1: Pin Definitions
NAME
CS0
DESCRIPTION
TYPE
Chip Enable 0, Input, Active LOW: Sampled on the rising edge of CLK.
Used in conjunction with CS1 and CS2 to select or deselect the device.
Chip Enable 1 Input, Active HIGH: Sampled on the rising edge of CLK.
Used in conjunction with CS0 and CS2 to select or deselect the device.
Chip Enable 2 Input, Active LOW: Sampled on the rising edge of CLK.
Used in conjunction with CS0 and CS1 to select or deselect the device.
Input-Synchronous
Address Inputs: Sampled at the rising edge of the CLK. A[1:0] is fed to the
two-bit burst counter.
Byte Write Enable, Active LOW: Qualified with WE, allows writes to each
of six bytes of memory when active, and masks input data when disabled.
Input-Synchronous
Write Enable Input, Active LOW: Sampled on the rising edge of CLK if
CEN is active LOW. This signal must be enabled LOW to initiate a write
sequence.
Advance/Load Input: Advances the on-chip address counter or loads a new
address. When HIGH (and CEN is enabled LOW) the internal burst counter
is advanced. When LOW, a new address can be loaded into the device for an
access. After deselection, drive ADV_LD LOW to load a new address.
Input-Synchronous
CLK
Clock Input: Used to capture all synchronous inputs to the device. CLK is
qualified with CEN. CLK is only recognized if CEN is active LOW.
Input-Clock
OE
Output Enable, Asynchronous Input, Active LOW: Combined with the
synchronous logic block inside the device to control the direction of the I/O
pins. When LOW, the I/O pins are enabled to behave as outputs. When
disabled HIGH, I/O pins are tri-stated, and act as input data pins. OE is
masked during the data portion of a write sequence, during the first clock
when emerging from a deselected state and when the device is deselected.
Clock Enable Input, Active LOW: When enabled LOW, the clock signal is
recognized by the SSRAM. When deasserted HIGH, the clock signal is
masked. Because deasserting CEN does not deselect the device, CEN can be
used to extend the previous cycle when required.
Input-Asynchronous
Bidirectional Data I/Os: As inputs, DQ[47:0] feed into an on-chip data
register that is triggered by the rising edge of CLK. As outputs, DQ[47:0]
delivers the data contained in the memory location specified by the addresses
presented during the previous clock rise of the read cycle. The direction of
the pins is controlled by OE. When OE is enabled LOW, the pins behave as
outputs. When HIGH, DQs are placed in a tri-state condition. The outputs
are automatically tri-stated during the data portion of a write sequence,
during the first clock when emerging from a deselected state, and when the
device is deselected, regardless of the state of OE. Aeroflex recommends
connecting all DQ pins to either VDDQ or VSS through a >10kΩ resistor.
Reset Input, Active Low: Resets device to known configuration. Reset is
required at initial power-up, after exiting shutdown mode, or after any power
interruption.
I/O-Synchronous
CS1
CS2
A[20:0]
BWE[5:0]
WE
ADV_LD
CEN
DQ[47:0]
RESET
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Input-Synchronous
Input-Synchronous
Input-Synchronous
Input-Synchronous
Input-Synchronous
Input-ASynchronous
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Table 1: Pin Definitions
NAME
DESCRIPTION
TYPE
ZZ
ZZ “Sleep” Input, Active HIGH: When HIGH, places the device in a nontime critical “sleep” condition with data integrity preserved. During normal
operation, this pin must be LOW.
Input-Synchronous
Shutdown Input, Active HIGH: When HIGH, places device in shutdown
mode. System clock can be stopped. Memory contents are not retained.
Device Ready Output: READY outputs a HIGH when device is available
for normal operations. READY outputs a LOW when requesting an idle
cycle or during power up initialization.
Input-Asynchronous
SHUTDOWN
READY1
VDD
Mode Input: Established at power up. Selects the burst order of the device.
When tied to VSS selects linear burst sequence. When tied to VDDQ selects
interleaved burst sequence.
Input Current Reference: Provided for external precision current reference
resistor connection.
Power supply inputs to the core of the device.
VDDQ
Power supply for the I/O circuitry.
MODE2
EXTRES2
Output-Synchronous
Input-DC
Input-DC
Power Supply
I/O Power Supply
VSS
Ground inputs to the core of the device.
VSSQ
Ground for I/O circuitry.
NUIL
Not used Input Low: Pins designated as NUIL need to be externally
connected by user to VSSQ through a >10kΩ±10% resistor.
--
NUIH
Not used Input High: Pins designated as NUIH need to be externally
connected by user to VDDQ through a >10kΩ±10% resistor.
--
No Connects. Not internally connected to the die.
---
NC
Ground
I/O Ground
TDO3
JTAG Circuit Serial Data Output: Package pin requires a pull-up through
>10kΩ±10% resistor to VDDQ.
JTAG Serial Output
Synchronous
TDI3
JTAG Circuit Serial Data Input: Device pin internally connected through
a 75kΩ±10% resistor to VDDQ.
JTAG Serial Input
Synchronous
TMS3
JTAG Controller Test Mode Select: Device pin internally connected
through a 75kΩ±10% resistor to VDDQ.
Test Mode Select
Synchronous
TCK3
JTAG Circuit Clock Input: Package pin requires a pull-up through
>10kΩ±10% resistor to VDDQ.
JTAG Clock
Note:
1. Reference application note AN-MEM-004 for additional READY signal information.
2. DC inputs are established at power up and cannot be switched while power is applied to the device.
3. Reference application note AN-MEM-005 for JTAG operations. JTAG operations are intended for terrestrial use and not guaranteed in radiation environment.
DEVICE OPERATION
The UT8SF2M48 is synchronous flow-thru SSRAM designed specifically to eliminate wait states during Write/Read or Read/Write
transitions. All synchronous inputs and outputs are registered on the rising edge of clock. The clock signal is enabled by the Clock
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Enable input (CEN). When CEN is HIGH, the clock signal is
disregarded and all internal states are maintained. All
synchronous operations are qualified by CEN. Once power-up
requirements have been satisfied, the input clock may only be
stopped during sleep (ZZ is HIGH) or shutdown mode
(SHUTDOWN is HIGH). Maximum access delay from the
rising edge of clock (tCQV) is 12ns (80 MHz device).
at power up. When MODE pin is LOW, the burst sequence is
linear. The burst sequence is interleaved when MODE is
HIGH. A0 and A1 are controlled by the burst counter. The
burst counter will wrap around when needed. The burst
counter increments anytime ADV_LD is HIGH and CEN is
low. The operation selected by the state of WE is latched at the
beginning of the sequence and maintained throughout.
Access is initiated by asserting all three Chip Enables
(CS0, CS1, CS2) active at the rising edge of the clock with
Clock Enable (CEN) and ADV_LD asserted LOW. The
address presented to the device will be registered. Access can
be either a Read or Write operation, depending on the status of
the Write Enable (WE).
Single Write Accesses
A write access is initiated when the following device inputs are
present at rising clock edge: CEN is enabled LOW, CS0, CS1,
and CS2 are all enabled, the Write Enable input signal WE is
enabled LOW and ADV_LD is asserted LOW. The addresses
present at the address inputs A[20:0] are registered and
presented to the memory core. Data I/Os are tri-stated at the
next rising edge of clock regardless of state of OE. The write is
completed after the next rising clock edge using data present
on DQ pins. Each byte of data is individually qualified by its
applicable byte write enable input (see Table 2). When the
input low, the applicable DQ inputs are registered to memory.
When the input is high, the applicable DQ pins are ignored.
Write operations are initiated by the Write Enable (WE) input.
All write commands are controlled by built in synchronous
self-timed circuitry.
Three synchronous Chip Enables (CS0, CS1, CS2) and an
asynchronous Output Enable (OE) simplify memory depth
expansion. All operations (Reads, Writes, and Deselects) are
pipelined. ADV_LD must be driven LOW once the device has
been deselected in order to load a new address and command
for the next operation.
To avoid bus contention data should not be driven to DQs
when outputs are active. The Output Enable (OE) may be
disabled HIGH before applying data to the DQ lines. This will
tri-state the DQ output drivers. As an additional feature DQ
lines are automatically tri-stated during the data portion of a
Write cycle, regardless of the state of OE.
Single Read Accesses
A read access is initiated when the following device inputs are
present at rising clock edge: CEN is enabled LOW, CS0, CS1,
and CS2 are all enabled, the Write Enable input signal WE is
disabled HIGH and ADV_LD is asserted LOW. The addresses
present at the address inputs A[20:0] are registered and
presented to the memory. Data propagates to the input of the
output register. Data will be available to the bus 12ns after the
next rising clock edge provided OE is enabled LOW. After the
first clock of the read access, the output buffers are controlled
by OE and the internal control logic. OE must be enabled
LOW to drive requested data. During the next rising clock, any
operation (Read/Write/Deselect) may be initiated.
Burst Write Accesses
The UT8SF2M48 has an internal burst counter allowing up to
four writes to be performed from a single address input. A new
address can only be loaded when ADV_LD is driven LOW.
New addresses are loaded into the SSRAM, as described in the
Single Write Access section. When ADV_LD is driven HIGH
on the subsequent clock rise, where CEN is LOW, the Chip
Enables (CS0, CS1, CS2) and WE inputs are ignored and the
burst counter is incremented. The BWE[5:0] inputs must be
LOW in each cycle of the burst write in order to qualify each
respective byte of data.
READY Status
The UT8SF2M48 device operates as a Synchronous SRAM
device. Data integrity housekeeping activities are performed in
the background during normal user activity. These
housekeeping activities are performed on a regular basis.
However, when a housekeeping activity sequence cannot be
completed due to user conflict for memory space, the READY
Burst Read Accesses
The UT8SF2M48 has an internal burst counter allowing up to
four reads to be performed from a single address input. A new
address can only be loaded when ADV_LD is driven LOW.
New addresses are loaded into the SSRAM, as described by
the Single Read Access section. The burst counter operates in
either linear or interleave and is controlled by the MODE input
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pin asserts signifying to the user that an idle cycle is required.
Please reference applications note AN-MEM-004 for more
information.
Table 3. Linear Burst Address Table
(MODE=VSS)
Byte Write Enables BWE[5:0]
The UT8SF2M48 device employs six byte write enable inputs
to be used in conjunction with WE to qualify each associated
byte of data into the memory. When WE is HIGH, the device
is in read mode where all BWE[5:0] are don’t cares. When
WE is LOW, each BWE[5:0] must also be low to write the
associated data input pins into memory. Data input pins whose
associated byte write enable pin is HIGH, will be masked.
Starting
Address
Second
Address
Third
Address
Fourth
Address
A1, A0
A1, A0
A1, A0
A1, A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
Table 2. Byte Write Enable to Data Input Pins
Byte Write
Enable Input
Data Input Pins
BWE0
DQ[7:0]
BWE1
DQ[15:8]
Starting
Address
Second
Address
Third
Address
Fourth
Address
BWE2
DQ[23:16]
A1, A0
A1, A0
A1, A0
A1, A0
BWE3
DQ[31:24]
00
01
10
11
BWE4
DQ[39:32]
01
00
11
10
BWE5
DQ[47:40]
10
11
00
01
11
10
01
00
Table 4. Interleaved Burst Address Table
(MODE=VDDQ)
Sleep Mode
The ZZ input lead is a synchronous input. Asserting the ZZ pin
HIGH places the SSRAM into a power conservative "sleep"
mode. To assure the completion of previous commands and
through the pipeline prior to entering sleep mode, a minimum
of two full clock cycles (tZZS) are required between the last
Power Up/ Down Requirements
The SSRAM requires that VDD < VDDQ at all times. The
SSRAM does require the user to provide an external reset after
initial power application, exiting shutdown mode, or any
power interruption to the device input voltage outside the
specified limit. Performing a reset requires the assertion of the
RESET device input lead (LOW) for a minimum of 1us
(tRLRH). After the RESET input is returned HIGH, the device
requires 50us (tSHTDWNREC) to complete the reset operation.
Once the reset operation is complete, the device requires an
additional 20us (tCR) to synchronize the clock input, providing
a stable input clock is present. The device READY output lead
asserts HIGH once tCR is satisfied at the next rising clock. The
READY out lead HIGH indicates the device is available for
normal operations. For power down it is required that VDD and
VDDQ be powered down to <0.5V for a minimum of 100ms.
operation command and asserting the ZZ input. While in sleep
mode, data integrity is guaranteed. Changing the input clock
frequency or halting the input clock may be executed during
sleep mode. The device must be deselected prior to entering
sleep mode and remain deselected for the duration of tZZREC
after the ZZ input returns LOW.
Shutdown Mode
The SHUTDOWN input pin is an asynchronous input.
Asserting SHUTDOWN places the device in a power saving
shutdown mode. The system clock can be stopped. Memory
contents are not maintained in shutdown mode. The SSRAM
requires a reset cycle upon exiting shutdown mode.
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Clock Conditioning Requirements
The CLK signal input requirements are given in the Clock
section of the AC Characterizations. AC Characterization
performances listed herein are based on providing a clock
input signal meeting these requirements.
Changing Clock Frequencies
The CLK input frequency should be established at power on
and may only be changed while in SLEEP mode (reference
Table 5).
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External Connections
Table 5. External Bias Conditions
A precision 25kohm < +0.2% low TCR < 25ppm/oC resistor is
required to be connected between device pin EXTRES (R15)
and VSS.
Signal Name
NUIH2
TDO
TCK
Package Pin
H1, H20, N1, N2,
N19, N20, P13,
R8, R10, R12,
R13, R14, R16
R7, P16
R5
R9
DQ[47:0]3
ref Table 7
NUIL1
In order to ensure proper operation in conjunction with JTAG
boundary scan (reference applications note MEM-AN-005),
Aeroflex requires that specific package pins be biased through
soft connections to either VDDQ or VSSQ. Table 5 is a list of
these required external biases.
Bias Condition
>10kΩ to VSSQ
>10kΩ to VDDQ
>10kΩ to VDDQ
>10kΩ to VSSQ
>10kΩ to VDDQ or
VSSQ
Notes:
1. NUIL = Not Used Input Low
2. NUIH = Not Used Input High
3. Aeroflex recommends connecting all DQ[47:0] to either VDDQ or VSSQ
through >10kΩ resistors.
Table 6: Truth Table for UT8SF2M48 [1,2,3,4,5,6,7]
Address
Used
CSx*
ZZ
SHUT
DOWN
ADV_LD
WE
BWEx
OE
CEN
CLK
DQs
Standby Mode
None
H
L
L
L
X
X
X
L
L-H
3-State
Continue Deselect
None
X
L
L
H
X
X
X
L
L-H
3-State
Read Cycle (Start Burst)
External
L
L
L
L
H
X
L
L
L-H
Data Out
Read Cycle (Cont. Burst)
Next
X
L
L
H
X
X
L
L
L-H
Data Out
NOP/Dummy Read
(Start)
External
L
L
L
L
H
X
H
L
L-H
3-State
NOP/Dummy Read
(Cont.)
Next
X
L
L
H
X
X
H
L
L-H
3-State
Write Cycle (Start Burst)
External
L
L
L
L
L
L
X
L
L-H
Data In
Write Cycle (Cont. Burst)
Next
X
L
L
H
X
L
X
L
L-H
Data In
Dummy Write (Start)
None
L
L
L
L
L
H
X
L
L-H
3-State
Dummy Write (Cont.
Burst)
Next
X
L
L
H
X
H
X
L
L-H
3-State
Clock Inhibit (Stall)
N/A
X
L
L
X
X
X
X
H
L-H
N/A
Sleep Mode
N/A
H
H
L
X
X
X
X
X
X
3-State
Shutdown Mode
None
X
X
H
X
X
X
X
X
X
3-State
Operation
Notes:
* All chip selects active when L, at least one chip select inactive when H
1. X = “Don't Care”, H = Logic HIGH, L = Logic LOW.
2. Write is defined by WE and BWEx
3. When a Write cycle is detected, all I/Os are tri-stated.
4. The DQ pins are controlled by the current cycle and the OE signal.
5. CEN = H inserts wait states.
6. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally
during Write cycles. During a Read cycle DQs = tri-state when OEis inactive or when
the device is deselected and DQs= data when OE is active.
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Table 7. 288-Lead Pipelined Signal Locations
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
VDDQ
CS2
WE
VSS
A10
A8
A4
A18
A19
A14
A15
A2
A0
CS0
BWE5
BWE1
VSS
VSS
OE
BWE2
A11
A9
A6
A17
VSS
A20
A16
A13
A12
A1
ZZ
BWE3
SHUT
DOWN
VSS
C VDDQ
VSSQ
VSS
READY
BWE0
BWE4
A7
A5
VSS
VDD
VSS
VSSQ
VDD
VDD
A3
ADV_LD
CS1
VSS
VSSQ
D DQ33
DQ35
VDD
VSS
VSS
VDD
VDD
VSS
VDD
VDD
VSSQ
VDDQ
VDD
VSS
VSS
VDD
VDDQ DQ32
E DQ37
DQ1
DQ39
VDD
VSSQ
VSS
VSS
VSS
VSS
VSSQ
VDDQ
VSS
VSS
VSSQ
VDD
DQ38
DQ36
DQ34
F
DQ3
DQ5
DQ7
VDDQ
VDDQ
VSSQ
VSS
VSS
VDD
VSS
VDD
VSS
VSS
VDDQ
VSSQ
VDDQ
VDDQ
DQ4
DQ0
DQ2
G DQ9
DQ11
DQ13
VDD
VSSQ
VDD
VDDQ
VDD
VSS
VDD
VSS
VDD
VDDQ
VSSQ
VDD
VSSQ
VDD
DQ10
DQ6
DQ8
H NUIL3
DQ15
CEN
VSS
VSS
VDD
VDD
VDD
VSS
VSS
VSS
VDD
VDD
VSS
VSS
VSS
VSS
CLK
DQ12
NUIL
J
DQ19
DQ17
DQ21
VDD
VSSQ
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VSSQ
VDD
VSSQ
VDD
DQ14
DQ16
DQ18
K DQ27
DQ25
DQ23
VDDQ
VDDQ
VSSQ
VSS
VDDQ VDD
VSS
VDD
VDDQ
VSS
VDDQ
VSSQ
VDDQ
VDDQ
DQ20
DQ24
DQ22
L DQ31
DQ41
DQ29
VDD
VSSQ
VSS
M DQ45
DQ47
DQ43
VDD
N NUIL3 NUIL3
VSS
P
A
B
VSS
R
VDDQ VSSQ
VSSQ VDDQ
19
20
VDD
VSSQ VDDQ
VSS
VSS
VSS
VSSQ
VDDQ
VSS
VSS
VSSQ
VDD
DQ26
DQ30
DQ28
VSS
VSSQ VDDQ VSSQ
VDD
VSS
VDD
VDD
VSSQ
VDDQ
VSSQ
VSS
VDD
DQ40
DQ44
DQ42
VSS
VDD
VDDQ VSSQ
VDD
VSS
VDD
VSS
VSS
VDD
VSSQ
VSSQ
VDD
VSS
DQ46
NUIL3 NUIL3
VSS
VDD
VDDQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VDDQ MODE NUIL3 VDDQ
TMS
NUIH4
VSSQ
VSS
VDD
TDI
TDO1
VDD
NUIH4 NUIL3 TCK2 NUIL3 RESET NUIL3 NUIL3
NUIL3
VDDQ
VDD
NUIL3 EXTRES
VSS
Notes:
1. Pin requires pull-up to VDDQ of >10kΩ±10%.
2. Pin requires pull-down to VSS of >10kΩ±10%.
3. NUIL = Not used Input Low. NUIL pins requires >10kΩ±10% pull-down to VSSQ.
4. NUIH = Not Used Input High. NUIH pins requires >10kΩ + 10% pull-up to VDDQ.
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ABSOLUTE MAXIMUM RATINGS1
(Referenced to VSS)
SYMBOL
VDD/VDDQ
PARAMETER
Supply Voltage2
VALUE
UNIT
-0.5 to 4.0
V
-0.3 to VDDQ+0.3
V
VIN
Voltage on any pin2
IIO
DC I/O current per pin @ TJ = 135o for 15 years
+10
mA
PD
Package power dissipation permitted @ TC = 105°C3
15
W
TJ
Maximum junction temperature
ΘJC
Thermal resistance junction to case
TSTG
Storage temperature
o
+150
3
-65 to +150
C
o
C/W
o
C
Notes:
1. Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation should be restricted to recommended operating conditions.
2. All voltages are referenced to VSS.
3. Per MIL-STD-883, Method 1012, Section 3.4.1 PD = (TJ(max) - TC(max))
ΘJC
OPERATIONAL ENVIRONMENTS
PARAMETER
LIMIT
UNITS
100
krad(Si)
1.7x10-6
Errors/Bit-Day
≤ 100
MeV-cm2/mg
Total Ionizing Dose (TID)
Heavy Ion Error Rate 1
Single Event Latchup (SEL) Immune2
Notes:
1. Adams 90% worst case environment, Geosynchronous orbit, 100mils of aluminum
2. Temperature = 105oC; VDD and VDDQ = 3.6V
RECOMMENDED OPERATING CONDITIONS
SYMBOL
LIMITS
VDD
Core supply voltage
2.3V to VDDQ
VDDQ
I/O power supply voltage
2.3V to 3.6V
TC
Case temperature range
VIN
DC input voltage
TJ
36-00-01-003
Ver. 1.1.0
PARAMETER
Junction Temperature
-9-
-55°C to +105°C
0V to VDDQ
-55°C to +125°C
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DC ELECTRICAL CHARACTERISTICS (Pre and Post-Radiation)*
(VDD= 2.3V to VDDQ, VDDQ = 2.3 to 3.6V; Unless otherwise noted, Tc is per the temperature range ordered)
PARAMETER
DESCRIPTION
CONDITION
MIN
MAX
UNIT
VDD
Core Power Supply
Voltage
2.3
VDDQ
V
VDDQ
I/O Power Supply Voltage
2.3
3.6
V
VOH
Output HIGH Voltage
VOL
VIH
VIL
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
For 3.0V I/O, IOH=-4mA
0.8 *
VDDQ
V
For 2.3V I/O, IOH=-1mA
2.0
V
For 3.0V I/O, IOL=8mA
0.4
V
For 2.3V I/O, IOL=1mA
0.4
V
For 3.0V I/O
2.0
V
For 2.3V I/O
1.7
V
For 3.0V I/O
0.8
V
For 2.3V I/O
0.7
V
2
μA
2
μA
IIN1
Input Leakage Current
VIN = VDDQ and VSS
Except device pins TDI and TMS
IIN2
Input Leakage Current
VIN = VDDQ
Device pins TDI and TMS
-2
VIN = VSS
Device pins TDI and TMS
μA
-100
Three-State Output
Leakage Current
VDD, VDDQ = (Max),
VO = VDDQ and VSS,
OE = VDDQ (Max)
-2
2
μA
IOS1,2
Short-Circuit Output
Current
VDD, VDDQ = (Max),
VO = VDDQ and VSS
-100
100
mA
IDD3
VDD Supply Current in
Active Mode
VDD, VDDQ = (Max),
IOUT = 0mA,
105oC
900
mA
-55oC and 25oC
750
mA
105oC
100
mA
-55oC and 25oC
100
mA
105oC
250
mA
-55oC and 25oC
200
mA
IOZ
f = fmax
IDDQ3
VDDQ Supply Current in
Active Mode
VDD, VDDQ = (Max),
IOUT = 0mA,
f = fmax
ISHTDWN3
36-00-01-003
Ver. 1.1.0
VDD Supply Current in
Shutdown Mode
VDD, VDDQ = (Max),
VIN > VIH or VIN < VIL,
SHUTDOWN > VIH
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ISHTDWNQ3
ISTBY3
105oC
15
mA
VIN > VIH or VIN < VIL,
SHUTDOWN > VIH
-55oC and 25oC
15
mA
VDD, VDDQ = (Max),
VIN > VIH or VIN < VIL,
105oC
650
mA
-55oC and 25oC
500
mA
105oC
100
mA
-55oC and 25oC
100
mA
105oC
500
mA
-55oC and 25oC
350
mA
105oC
85
mA
-55oC and 25oC
85
mA
VDDQ Supply Current in
Shutdown Mode
VDD, VDDQ = (Max),
VDD Supply Current in
Standby Mode
f = fmax, device
deselected
ISTBYQ3
IZZ3
VDDQ Supply Current in
Standby Mode
VDD, VDDQ = (Max),
VIN > VIH or VIN < VIL,
f = fmax, device
deselected
VDD Supply Current in
Sleep Mode
VDD, VDDQ = (Max),
VIN>VIH or VIN < VIL,
ZZ > VIH,
SHUTDOWN < VIL
IZZQ3
VDDQ Supply Current in
Sleep Mode
VDD, VDDQ = (Max),
VIN>VIH or VIN < VIL,
ZZ > VIH,
SHUTDOWN < VIL
CAPACITANCE
SYMBOL
PARAMETER
MIN
MAX
UNIT
CIN4
Input Capacitance
15
pF
CI/O4
I/O Capacitance
15
pF
Notes:
* For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25oC per MIL-STD-883 Method 1019,
Condition A up to the maximum TID level procured.
1. Supplied as a design limit but not guaranteed nor tested.
2. Not more than one output may be shorted at a time for maximum duration of one second.
3. Post-irradiation limits are the 105oC limits when specified.
4. Measured only for initial qualification and after process or design changes that could affect this parameter.
36-00-01-003
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- 11 -
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AC CHARACTERISTICS (Pre and Post-Radiation)*
(VDD= 2.3V to VDDQ, VDDQ = 2.3 to 3.6V; Unless otherwise noted, Tc is per the temperature range ordered.)1
PARAMETER
tPowerup
2
DESCRIPTION
MIN
MAX
UNIT
VDD to first valid command (READ or WRITE)
100
ms
Clock (CLK) cycle time
12.5
25.0
ns
Clock
tCYC6
tCH
CLK HIGH time
0.4 * tCYC
0.6 * tCYC
ns
tCL
CLK LOW time
0.4 * tCYC
0.6 * tCYC
ns
tr, tf2
tclkPJ3,5
tclkCCJ3,5
Input clock rise/fall time (10-90%)
2.25
Input clock period jitter
-100
Input clock cycle to cycle jitter
V/ns
100
ps
150
ps
Setup Times
tAS
Address setup time prior to CLK
2.5
ns
tDS
Data setup time prior to CLK
1.5
ns
tCENS
Clock enable setup (CEN) time prior to CLK
3
ns
tWES
Write enable (WE) setup time prior to CLK
3
ns
tBWES
Byte Write enable (BWE[5:0]) setup time prior to CLK
3
ns
2.5
ns
3
ns
tADVLDS
tCSS
Advance load (ADV_LD) setup time prior to CLK
Chip select (CSx) setup time prior to CLK
Hold Times
tAH
Address hold time after CLK
1.2
ns
tDH
Data hold time after CLK
1.4
ns
tCENH
CEN hold time after CLK
1.2
ns
tWEH
WE hold time after CLK
1.5
ns
tBWEH
Byte Write enable (BWE[5:0]) hold time after CLK
1.5
ns
ADV_LD hold time after CLK
0.9
ns
CSx hold time after CLK
1.8
ns
tADVLDH
tCSH
Output Times
tCQV4
Data valid after rising CLK
12
ns
tOEQV4
Output enable (OE) active to data valid
4.0
ns
tCQOH
Data output hold time after rising CLK
tCQZ5
Rising CLK to output three-state time
tCQX5
Rising CLK to output enable time
36-00-01-003
Ver. 1.1.0
- 12 -
2.0
ns
5.0
1.3
ns
ns
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tOEQZ5
OE inactive to output three-state time
tOEQX5
OE active to output enable time
4.5
0
ns
ns
Notes:
* For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25oC per MIL-STD-883 Method 1019,
Condition A up to the maximum TID level procured
1. AC Characteristics based on compliance with CLOCK input specifications
2. Supplied as a design guideline, not tested or guaranteed.
3. Period and Cycle to Cycle jitter is defined by JEDEC Standard 65B
4. Maximum data output valid times guaranteed up to 25pf load capacitance. For loads >25pf, a derating factor of parameter = [specification max(ns) + (CLoad 25pF)(44.2ps/pF].
5. Guranteed by design.
6. Maximum Cycle Time is tested functionally.
SHUTDOWN AND SLEEP MODE CHARACTERISTICS (Pre and Post-Radiation)*
(VDD= 2.3V to VDDQ, VDDQ = 2.3 to 3.6V; Unless otherwise noted TC is for temperature range ordered.)
PARAMETER
DESCRIPTION
CONDITION
MIN
MAX
UNIT
tZZS3
Device operation to SLEEP mode
ΖΖ > VIH
1 tCYC
ns
tZZH3
SLEEP high pulse width
ΖΖ > VIH
100
μs
tZZL3
SLEEP low pulse width
ΖΖ < VIH
100
μs
Device operation to SHUTDOWN
SHUTDOWN > VIH
2 tCYC
ns
SLEEP recovery time
STANDBY < VIL
100 +
(3*tCYC)
ns
SHUTDOWN recovery time
SHUTDOWN < VIL
Active to SLEEP current
ΖΖ > VIH
Active to SHUTDOWN current
SHUTDOWN > VIH
tRZZI4
Time to exit SLEEP current mode
STANDBY < VIL
0
ns
tRSHTDWNI4
Time to exit SHUDOWN current
mode
SHUTDOWN < VIL
0
ns
tCR1,2,3
Clock recovery prior to exiting ZZ
ΖΖ > VIH
tRLRH
RESET low to high time
Shutdown < VIL
tPDS3
tPDH3
tSHTDWNS3
tZZREC3
tSHTDWNREC1,3
tZZI4
tSHTDWNI4
50
us
100 +
(3*tCYC)
ns
250
ns
20
μs
1
μs
SLEEP setup time prior to CLK
2.0
ns
SLEEP hold time after CLK
0.5
ns
Notes:
* For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25oC per MIL-STD-883 Method 1019,
Condition A up to the maximum TID level procured
1. The clock must start up prior to exiting sleep or shutdown modes. Parameter is guaranteed by design.
2. TCR is necessary anytime the clock is stopped, after initial power on, or exiting shutdown mode.
3. Tested functionally.
4. Guaranteed by design.
36-00-01-003
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tCYC
tCL
CLK
Command
Bus
tCH
64th non- idle
cycle
65th non- idle
cycle
non- idle cycle
non- idle cycle
non- idle cycle
non- idle cycle
non- idle cycle
non- idle cycle
Idle cycle
Any cycle
Any cycle
tCQV
16 cycles MAX
READY
Any cycle
tCQV
Figure 3. Switching Waveform for Internal Housekeeping
tCR
CLK
tZZH
tRZZI
tZZS
ZZ
tZZL
tZZI
tPDH
tPDS
Command
Bus
tZZREC
RD/
WR
RD/
WR
Deselect cycle
RD/
WR
Figure 4. Switching Waveform for SLEEP Mode
CLK
tRSHTDWNI
tSHTDWNS
tSHTDWNREC
SHUTDOWN
Command
Bus
tCR
tSHTDWNI
RD/
WR
RD/
WR
Deselect cycle
tRLRH
RESET
Figure 5. Switching Waveform for SHUTDOWN Mode
CLK
Power-up
tSHTDWNREC
SHUTDOWN
Command
Bus
Deselect cycle
tCR
RD/
WR
RD/
WR
tRLRH
RESET
READY
Figure 6. Switching Waveform for Power-Up
36-00-01-003
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- 14 -
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36-00-01-003
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W&+
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Figure 7. Switching Waveforms for Pipelined Cycle Operations
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VDD
VDD
RTERM
100ohm
CL = 40pF
DUT
Test
Point
Zo = 50ohm
RTERM
100ohm
VDD2
VSS
90%
90%
10%
> 2.25V/ns
10%
CMOS Input Pulses
> 2.25V/ns
Notes:
1. Measurement of data output occurs at the low to high or high to low transition mid-point (i.e., CMOS input = VDD2/2
Figure 8. AC Test Loads and Input Waveforms
36-00-01-003
Ver. 1.1.0
- 16 -
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PACKAGING
Figure 9. 288-Lead CCGA
36-00-01-003
Ver. 1.1.0
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PACKAGING
Figure 10. 288-Lead CLGA
36-00-01-003
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PACKAGING
Figure 11. Advanced 288-lead CBGA, Ball dimensions (A, A1, A2) are subject to change
36-00-01-003
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ORDERING INFORMATION
2M x 48 SSRAM
UT ******* - *
* * *
Lead Finish: (Note 1)
(C) = Gold
(A) = Solder
Screening: (Notes 2, 3)
(F) = HiRel Flow (Temperature Range: -55°C to +105°C) (In development, contact factory)
(P) = Prototype Flow (Temperature Range: 25oC only)
Package Type:
(Z) = 288-Lead Ceramic Land Grid Array (CLGA)
(S) = 288-Lead Ceramic Column Grid Array (CCGA)
(C) = 288-Lead Ceramic Ball Grid Array (CBGA)
Access Time:
(M) = 80MHz Maximum Frequency
Device Type:
(8SF2M48) = 2Mbit x 48 SSRAM Device
Notes:
1. Lead finish is per the table below.
2. Prototype Flow per Aeroflex Manufacturing Flows Document. Devices are tested at 25oC only. Radiation is neither tested nor guaranteed.
3. HiRel flow per Aeroflex Manufacturing Flows Document. Radiation is neither tested nor guaranteed.
36-00-01-003
Ver. 1.1.0
Package Option
Associated Lead Finish Option
(Z) 288-CLGA
(C) Gold
(S) 288-CCGA
(A) Hot Solder Dipped
(C) 288-CBGA
(A) Hot Solder Dipped
- 20 -
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2M x 48 SSRAM: SMD
5962 *
***** ** * * *
Lead Finish: (Note 1)
(C) = Gold
(F) = Solder
Case Outline:
(X) = 288-Lead Ceramic Land Grid Array (CLGA)
(F) = 288 Lead Ceramic Column Grid Array (CCGA)
Class Designator:
(Q) = QML Class Q (In development, contact factory)
Device Type: (Note 2)
(01) = fmax = 80MHz, QML Q only (Temperature Range: -55°C to +105°C)
(02) = fmax = 80MHz Aeroflex Q+ Flow (Temperature Range -55°C to +105°C)
Drawing Number:
(15225) = 2M x 48 SSRAM Flow-thru
Total Dose:
(R) = 100 krad(Si)
Federal Stock Class Designator: No options
Notes:
1. Lead finish is per the table below.
2. Aeroflex’s Q+ assembly flow, as defined in section 4.2.2.d of the SMD, provides QML-Q product through the SMD that is manufactured with Aeroflex’s
QML-V flow.
36-00-01-003
Ver. 1.1.0
Package Option
Associated Lead Finish Option
(X) 288-CLGA
(C) Gold
(F) 288-CCGA
(F) Hot Solder Dipped
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This product is controlled for export under the U.S. Department of Commerce (DoC). A license may be
required prior to the export of this product from the United States.
Cobham Semiconductor Solutions
4350 Centennial Blvd
Colorado Springs, CO 80907
E: [email protected]
T: 800 645 8862
Advanced Datasheets - Product is in Development
Preliminary Datasheet - Prototypes are Shipping
Datasheet - Shipping QML & Reduced Hi - Rel
Aeroflex Colorado Springs Inc., DBA Cobham Semiconductor Solutions, reserves the right to make changes to any products and services described
herein at any time without notice. Consult Aeroflex or an authorized sales representative to verify that the information in this data sheet is current
before using this product. Aeroflex does not assume any responsibility or liability arising out of the application or use of any product or service
described herein, except as expressly agreed to in writing by Aeroflex; nor does the purchase, lease, or use of a product or service from Aeroflex
convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual rights of Aeroflex or of third parties.
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Description of Change History
Revision Date
Description of Change
April 2015
Version 1.0.0
Release of Preliminary Data Sheet
June 2015
Version 1.1.0
Page 1 & 21: Updated the SMD number.
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