UT8RHEEB-288PC Evaluation Board

Standard Products
UT8RHEEB-288PC RadTol Eclipse FPGA
UT6325 Evaluation Board
Advanced Data Sheet
September 2008
www.aeroflex.com/FPGA
INTRODUCTION
FEATURES
‰ User configurable evaluation board for the UT6325 RadTol
Eclipse FPGA
‰ Available with both 280-plastic ball grid array (PBGA) and
288-ceramic quad flatpack (CQFP) sockets
‰ Ideal for rapid evaluation of the UT6325 RadTol Eclipse
FPGA functionality, DC and AC performance
‰ Includes full access to every I/O on the UT6325 RadTol
Eclipse FPGA
- Selectable options include 10K-ohm pull-up, 10K-ohm
pull-down, tri-state
- Logic analyzer and wire-wrap access through dual-row
header strips
‰ JTAG access support
‰ SMA connectors for all clock inputs to the board
‰ BNC connectors for all power supply and voltage reference
inputs
‰ Extensive prototyping area to support convenient inclusion
of customer circuitry
‰ Current sense circuitry for the 2.5V and 3.3V inputs.
The UT8RHEEB-288PC Evaluation Board supplies users of the
UT6325 RadTol Eclipse FPGA with a quick, convenient
environment for evaluating the 280-PBGA and 288- CQFP
packaged versions of the UT6325 RadTol Eclipse FPGA.
To maximize the user’s ability to control and access every FPGA
I/O, the UT8RHEEB-288PC provides 10K-ohm, switchselectable, I/O bias to either VCCIO or VSS. If the user does not
wish to bias an FPGA I/O signal, the net may be isolated from
either power supply rail. All FPGA I/O’s are connected to dualrow headers which are optimized to interface with Tektronix
logic analyzer pods. Furthermore, the header pins protrude
~ 1/2" below the board in order to provide wire-wrap access to
the respective FPGA I/O. Coupling the wire-wrap access with
local prototyping area, the UT8RHEEB-28P8C permits the user
to interface customer circuitry to the UT6325 RadTol Eclipse
FPGA.
The board’s flexible design demonstrates some of the
capabilities of the 280-PBGA and 288-CQFP UT6325 RadTol
Eclipse FPGA devices, and enables fast development with full
pin access and code verification. Because the UT8RHEEB288PC includes both sockets for evaluating the UT6325 and
provides the user with full access to the FPGA’s I/O, the board
can be used to verify proper programming of the device prior to
installing it onto your target PCB.
Bottom Side
Top Side
17
HARDWARE DESCRIPTION
Table 1: The UT8RHEEB-288PC Evaluation Board contains the following functional components
Name
Description
SKT1
SKT2
J47
J48
J62-J69
J13-J21
SW1-4
SW6-11
SW13-16
SW18-23
SW5, SW12, SW17,
SW24
J2-J11
J30-J34
J36-J40
J1, J12, J35, J41
SW25-SW28
J42-J45
J46
SW29
J58
J109
J49, J59, J60, J61
J110, J111
Prototype Area
288-CQFP socket for Aeroflex’s 288 pin Ceramic Quad Flat Pack Eclipse FPGA
devices. SKT1 is on the bottom-side of the board. Note that the 288-CQFP is
loaded with the lid down into the socket for proper contact.
280-PBGA socket for Aeroflex’s 280 pin Plastic Ball Grid Array Eclipse FPGA
devices.
BNC Connector Input for VCC CORE (+2.5V)
BNC Connector Input for VCCIO (+3.3V)
BNC Connectors for INREFA – INREFH
Connectors are tied to ground with a 10K-ohm resistor
Leave INREF signals tied to ground for normal I/O operation (LVTTL,
LVCMOS3, PCI standards). Future compatibility with GTL+ and SSTL3 signals
will require a differential reference voltage.
SMA Connectors for CLK0-CLK8 input clock signals
8-switch and 4-switch SP3T dip switches
• Setting the respective switch to the “+” position ties the corresponding I/O
to VCCIO via a 10K-ohm pull up resistor
• Setting the respective switch to the “-“ position ties the corresponding I/O
to VSS via a 10K-ohm pull down resistor
• Setting the respective switch to the “0” position isolates the corresponding
I/O from either power supply rail by floating the net
16-Pin, and 8-Pin Dual-Row Headers
• FPGA I/Os are available at the connectors
• Tektronix Logic Analyzer Pods can plug directly onto the connectors
• Wire-wrap access is available at these headers on the bottom-side of the
board
4-switch SP3T DIP switches for IOCTRL-IOCTRLH
• Setting the respective switch to the “+” position ties the corresponding
IOCTRL to VCCIO via a 10K-ohm pull up resistor
• Setting the respective switch to the “-“ position ties the corresponding
IOCTRL to VSS via a 10K-ohm pull down resistor
• Setting the respective switch to the “0” position isolates the corresponding
IOCTRL from either power supply rail by floating the net
8-Pin Dual-Row Headers
The IOCTRLA-IOCTRLH signals are available through these connectors
JTAG Connector with removed pin for keyed mating connector
The signals are defined in the PCB silkscreen
PLL Reset Circuitry
• SW29 is a manual PLL reset (result is PLLRST active high at FPGA)
• J58 is an external user PLL reset (active low at pin results in PLL active
high reset at FPGA)
• J109 is a 4-pin PLL reset monitor connector
Note: Hold PLL reset switch or J58 low for at least 1 sec. to reset PLL.
SMA Connectors to monitor PLLOUT0 –PLLOUT 3
2-Pin Headers to monitor current for 3.3V and 2.5V supplies
The translation is 1 Volt/Amp from the current sense ICs, U3 and U2
Prototype area
VCCIO (3.3V), VCC CORE (2.5V), and GND are labeled in the silkscreen
Table 2:
288CQFP to 280 PBGA Pinout (Net Name, Switch used & Access Point)
288 CQFP
280 PBGA
Net Name
Switch
Access Point
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
E5
L5
A18
B17
C16
A17
D15
B16
A16
B15
D14
A15
C14
E6
E10
C11
A14
D13
B13
B14
C13
A13
D12
C12
B12
A12
D11
C15
E11
E7
B11
A11
D10
C10
B10
A10
D9
B9
A9
D8
C8
GND
VCC_25V
PLLRST1
VCC_25V
IOE15
IOE6
IOE23
IOE11
IOE5
IOE10
IOE22
IOE4
IOE14
VCC_25V
GND
VCC_33V
IOCTRLE1
INREFE
IOCTRLE2
IOE9
IOE13
IOE3
IOE21
IOE12
IOE8
IOE2
IOE20
VCC_33V
GND
VCC_25V
IOE7
IOE1
IOE19
CLK5
CLK6
CLK7
CLK8
TMS
IOF6
IOF22
IOF16
N/A
N/A
N/A
N/A
SW19
SW13
SW14
SW19
SW13
SW19
SW14
SW13
SW19
N/A
N/A
N/A
SW27
N/A
SW27
SW19
SW19
SW13
SW14
SW19
SW13
SW13
SW14
N/A
N/A
N/A
SW13
SW13
SW14
N/A
N/A
N/A
N/A
N/A
SW20
SW21
SW15
GND_TP
U2-6,7
J109
U2-6,7
J36
J30
J31
J36
J30
J36
J31
J30
J36
U2-6,7
GND_TP
U3-6,7
J44
J78
J44
J36
J36
J30
J31
J36
J30
J30
J31
U3-6,7
GND_TP
U2-6,7
J30
J30
J31
SKT1
SKT1
SKT1
SKT1
J46
J37
J38
J32
288 CQFP
280 PBGA
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
B8
M5
E14
C5
A8
D7
C7
B7
A7
D6
B6
C6
A6
D5
B5
C9
E15
E8
A5
D4
C4
B4
A4
B3
A3
C3
A1
A2
C2
M15
F5
J5
N5
B2
B1
D3
C1
E4
D2
D1
F4
E2
E1
Net Name
IOF11
VCC_25V
GND
VCC_33V
IOF5
IOF21
IOF15
IOF10
IOF4
IOF20
INREFF
IOCTRLF1
IOCTRLF2
IOF19
IOF9
VCC_33V
GND
VCC_25V
IOF3
IOF18
IOF14
IOF8
IOF2
IOF7
IOF1
IOF13
PLLOUT3
GND
VCC_25V
VCC_25V
GND
GND
VCC_25V
GND
PLLRST0
IOF17
IOF12
IOF23
IOG2
IOG1
IOG6
IOG4
IOG3
Switch
SW15
N/A
N/A
N/A
SW20
SW21
SW15
SW15
SW20
SW21
N/A
SW27
SW27
SW21
SW15
N/A
N/A
N/A
SW20
SW21
SW15
SW20
SW20
SW20
SW20
SW15
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
SW21
SW15
SW21
SW16
SW16
SW16
SW16
SW16
Access Point
J32
U2-6,7
GND_TP
U3-6,7
J37
J38
J32
J32
J37
J38
J79
J44
J44
J38
J32
U3-6,7
GND_TP
U2-6,7
J37
J38
J32
J37
J37
J37
J37
J32
SKT1
GND_TP
U2-6,7
U2-6,7
GND_TP
GND_TP
U2-6,7
GND_TP
J109
J38
J32
J38
J33
J33
J33
J33
J33
288 CQFP
280 PBGA
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
F3
E9
K5
E3
G4
F2
F1
G3
H4
G2
G1
H3
H2
H1
J4
J3
K15
E12
J2
J1
K4
K3
K2
H16
L4
L2
L1
M4
M3
M2
N15
L15
L3
M1
N4
N3
N1
N2
P4
P3
P1
P2
R4
Net Name
IOG5
VCC_25V
GND
VCC_33V
IOG9
IOCTRLG1
INREFG
IOCTRLG2
IOG13
IOG8
IOG7
IOG12
IOG11
IOG10
IOG16
VCC_33V
GND
VCC_25V
IOG15
IOG14
IOG18
IOG17
TCK
VCC_25V
IOH3
IOH2
IOH1
IOH7
IOH6
IOH5
VCC_25V
GND
VCC_33V
IOH4
IOH10
IOH9
IOCTRLH1
IOH8
INREFH
IOCTRLH2
IOH11
IOH12
IOH15
Switch
SW16
N/A
N/A
N/A
SW22
SW28
N/A
SW28
SW22
SW16
SW16
SW22
SW22
SW22
SW22
N/A
N/A
N/A
SW22
SW22
SW17
SW17
N/A
N/A
SW23
SW23
SW23
SW23
SW23
SW23
N/A
N/A
N/A
SW23
SW18
SW18
SW28
SW23
N/A
SW28
SW18
SW18
SW18
Access Point
J33
U2-6,7
GND_TP
U3-6,7
J39
J45
J80
J45
J39
J33
J33
J39
J39
J39
J39
U3-6,7
GND_TP
U2-6,7
J39
J39
J35
J35
J46
U2-6,7
J40
J40
J40
J40
J40
J40
U2-6,7
GND_TP
U3-6,7
J40
J34
J34
J45
J40
J81
J45
J34
J34
J34
288 CQFP
280 PBGA
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
R1
R3
P15
E13
R2
T2
T1
T3
U1
U2
V1
W1
V2
W2
U3
P5
R5
R6
R7
V3
W3
T4
U4
V4
W4
T5
V5
W5
T6
U6
F15
R9
U5
V6
W6
U7
V7
W7
T7
T8
V8
W8
U8
Net Name
IOH13
VCC_33V
GND
VCC_25V
IOH14
IOH17
IOH16
IOA1
IOA8
IOA9
PLLOUT2
GND
GND
PLLRST3
VCC_25V
VCC_25V
GND
GND
VCC_25V
GND
IOA18
IOA2
IOA10
IOA13
IOA19
IOA3
IOA14
IOA20
IOCTRLA1
INREFA
VCC_25V
GND
VCC_33V
IOCTRLA2
IOA21
IOA11
IOA15
IOA22
IOA4
IOA5
IOA16
IOA23
IOA12
Switch
SW18
N/A
N/A
N/A
SW18
SW24
SW18
SW1
SW1
SW7
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
SW2
SW1
SW7
SW7
SW2
SW1
SW7
SW2
SW25
N/A
N/A
N/A
N/A
SW25
SW2
SW7
SW7
SW2
SW1
SW1
SW7
SW2
SW7
Access Point
J34
U3-6,7
GND_TP
U2-6,7
J34
J41
J34
J2
J2
J7
SKT1
GND_TP
GND_TP
J109
U2-6,7
U2-6,7
GND_TP
GND_TP
U2-6,7
GND_TP
J3
J2
J7
J7
J3
J2
J7
J3
J42
J74
U2-6,7
GND_TP
U3-6,7
J42
J3
J7
J7
J3
J2
J2
J7
J3
J7
288 CQFP
280 PBGA
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
T9
U9
R10
G5
V9
T10
W9
U10
V10
W10
T11
V11
W11
T12
U12
V12
R8
R15
U11
W12
U13
V13
W13
T13
U14
V14
W14
T14
V15
W15
U15
--G15
T15
V16
W16
U16
T16
W17
V17
U17
W19
V18
Net Name
IOA6
VCC_33V
GND
VCC_25V
IOA17
IOA7
TDI
CLK0
CLK1
CLK2
CLK3
CLK4
IOB17
IOB1
IOB8
IOB12
VCC_25V
GND
VCC_33V
IOB18
IOB9
IOB13
IOB19
IOB2
IOCTRLB1
INREFB
IOCTRLB2
IOB3
IOB14
IOB20
VCC_33V
GND
VCC_25V
IOB4
IOB15
IOB21
IOB10
IOB5
IOB22
IOB16
TDO
PLLOUT1
GND
Switch
SW1
N/A
N/A
N/A
SW2
SW1
N/A
N/A
N/A
N/A
N/A
N/A
SW9
SW8
SW8
SW3
N/A
N/A
N/A
SW9
SW3
SW3
SW9
SW8
SW25
N/A
SW25
SW8
SW3
SW9
N/A
N/A
N/A
SW8
SW3
SW9
SW3
SW8
SW9
SW3
N/A
N/A
N/A
Access Point
J2
U3-6,7
GND_TP
U2-6,7
J3
J2
J46
SKT1
SKT1
SKT1
SKT1
SKT1
J9
J8
J8
J4
U2-6,7
GND_TP
U3-6,7
J9
J4
J4
J9
J8
J42
J75
J42
J8
J4
J9
U3-6,7
GND_TP
U2-6,7
J8
J4
J9
J4
J8
J9
J4
J46
SKT1
GND_TP
288 CQFP
280 PBGA
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
W18
R11
----R12
V19
T17
U18
U19
T18
T19
R16
R18
P16
R19
P17
H5
--L17
P18
N16
P19
N17
N18
M16
N19
M17
M18
L16
M19
R17
--H15
L18
L19
K16
J16
K18
K19
K1
K17
J18
J19
Net Name
IOB23
VCC_25V
GND
GND
VCC_25V
GND
VCC_25V
PLLRST2
IOB11
IOB6
IOB7
IOC16
IOC17
IOC12
IOC18
IOC13
VCC_25V
GND
VCC_33V
IOC14
IOC10
IOC15
IOC11
IOCTRLC1
INREFC
IOCTRLC2
IOC7
IOC8
IOC4
IOC9
VCC_33V
GND
VCC_25V
IOC5
IOC6
IOC2
IOC1
IOC3
TRSTB
VCC_25V
IOD18
IOD16
IOD17
Switch
SW9
N/A
N/A
N/A
N/A
N/A
N/A
N/A
SW3
SW8
SW8
SW10
SW5
SW10
SW5
SW10
N/A
N/A
N/A
SW10
SW10
SW10
SW10
SW26
N/A
SW26
SW4
SW4
SW4
SW10
N/A
N/A
N/A
SW4
SW4
SW4
SW4
SW4
N/A
N/A
SW12
SW6
SW12
Access Point
J9
U2-6,7
GND_TP
GND_TP
U2-6,7
GND_TP
U2-6,7
J109
J4
J8
J8
J10
J1
J10
J1
J10
U2-6,7
GND_TP
U3-6,7
J10
J10
J10
J10
J43
J76
J43
J5
J5
J5
J10
U3-6,7
GND_TP
U2-6,7
J5
J5
J5
J5
J5
J46
U2-6,7
J12
J6
J12
288 CQFP
280 PBGA
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
H17
H18
R13
--E17
H19
G16
G17
G18
G19
F17
F18
F19
F16
E18
E19
J17
--J15
E16
D18
D19
D17
D16
C19
C18
C17
B19
A19
B18
R14
---
Net Name
IOD13
IOD14
VCC_25V
GND
VCC_33V
IOD15
IOD9
IOD10
IOD11
IOD12
IOD6
IOD7
IOD8
IOCTRLD1
INREFD
IOCTRLD2
VCC_33V
GND
VCC_25V
IOD5
IOD3
IOD4
IOD2
IOD1
IOE18
IOE17
IOE16
PLLOUT0
GND
GND
VCC_25V
GND
Switch
SW6
SW6
N/A
N/A
N/A
SW6
SW6
SW6
SW6
SW6
SW11
SW11
SW11
SW26
N/A
SW26
N/A
N/A
N/A
SW11
SW11
SW11
SW11
SW11
SW14
SW14
SW19
N/A
N/A
N/A
N/A
N/A
Access Point
J6
J6
U2-6,7
GND_TP
U3-6,7
J6
J6
J6
J6
J6
J11
J11
J11
J43
J77
J43
U3-6,7
GND_TP
U2-6,7
J11
J11
J11
J11
J11
J31
J31
J36
SKT1
GND_TP
GND_TP
U2-6,7
GND_TP
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ORDERING INFORMATION
UT6325 288-CQFP and 280-PBGA RadTol FPGA Evaluation Board:
UT8RHEEB-288 **
Configuration options:
(PC) = 280-PBGA and 288-CQFP
Base Part Number: Note 1
UT8RHEEB-288 = UT6325 Evaluation Board with both
280-PBGA and 288-CQFP package support
NOTE 1: The UT8RHEEB-288PC does not include an
FPGA. The user should place an order for the FPGA
required for their evaluation purposes.
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Aeroflex Colorado Springs - Datasheet Definition
Advanced Datasheet - Product In Development
Preliminary Datasheet - Shipping Prototype
Datasheet - Shipping QML & Reduced Hi-Rel
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