AGC/UP-CONVERTER WITH IQ MODULATOR UPC8158K

AGC/UP-CONVERTER
UPC8158K
WITH IQ MODULATOR
22
• SUPPLY VOLTAGE:
VCC = 2.7 to 4.0 V, ICC = 28 mA @ VCC = 3.0 V
21
18
17
16
15
14
13
UE
24
AGC
Reg
12
25
• AGC AMPLIFIER INSTALLED IN LOCAL PORT OF
UPCONVERTER:
GCR = 35 dB MIN. @ fout = 1.5 GHz
LPF
26
Reg
11
27
28
• EXCELLENT PERFORMANCE:
Padj = -65dBc TYP. @ ∆f = ±50 KHz, EVM = 1.2 %rms TYP.
10
I/Q-Mix
9
Phase
Shifter
1
2
3
4
5
6
7
8
IN
DESCRIPTION
The UPC8158K is a silicon microwave monolithic integrated
circuit designed as a quadrature modulator for digital mobile
communication systems. This MMIC consist of a 0.8 GHz to
1.5 GHz up-converter and 100 MHz to 300 MHz quadrature
modulator which are equipped with AGC and power save
functions. This configuration suits IF modulation systems and
is packaged in a 28-pin QFN suitable for high density
mounting. The chip is manufactured using NEC's 20 GHz fT
silicon bipolar process NESATTM III to realize low power
consumption. Consequently the UPC8158K can contribute to
make RF blocks smaller size, higher performance and lower
power consumption.
NT
• Digital cellular phones
(PDC800M, PDC1.5G,TDMA1900 and so on)
• Wireless Communiaction Systems
(MMDS, Broadband wireless access)
19
Up-Mix
23
APLICATIONS
20
AGCcont
• BUILT-IN LPF:
Suppresses spurious multipled by TX local (LO1)
• EXTERNAL IF FILTER:
Can be applied between modulator output and
up converter input terminal
D
INTERNAL BLOCK DIAGRAM
FEATURES
ELECTRICAL CHARACTERISTICS (TA = 25°C, VCC1 = VCC2 = VCC3 = 3.0 V, VPS/VAGC = 2.5 V)
SC
O
PART NUMBER
PACKAGE OUTLINE
SYMBOLS
UPC8158K
PARAMETERS AND CONDITIONS
UNITS
MIN
Total Circuit Current, No input signal
mA
23.7
Total Circuit Current at Power Save Mode, VPS ≤ 0.5 V(low), No input signal
µA
TYP
MAX
UP-CONVERTER + QUADRATURE MODULATOR TOTAL
ICC (TOTAL)
ICC(PS) TOTAL
PRFout1
Total Output Power 1, VAGC = 2.5 V
dBm
-15
PRFout2
-56.5
28
37.6
0.3
10
-11.5
-8
-52
-46.5
Total Output Power 2, VAGC = 1.0 V
dBm
LOL
LO Carrier Leak, fLOL = fLO1 + fLO2
dBc
-40
-30
ImR
Image Rejection (Side Band Leak)
dBc
-40
-30
-50
-30
I/Q 3rd Order Distortion
dBc
GCR
AGC Gain Control Range, VAGC = 2 V →1 V
dB
EVM
Error Vector Magnitude, MOD Pattern PN9
%rms
1.2
3.0
Padj
Adjacent Channel Interference, ∆f = ±50KHz, MOD Pattern: PN9
dBc
-65
-60
Spurious Suppression, fLO1 × 8, fLO1 × 8 (image)Note
DI
IM3(I/Q)
Pout(8fLO1)
35
40
dBc
-70
-65
TPS(Rise)
Power Save Rise Time, VPS(Low) → VPS(High)
µs
2
5
TPS(Fall)
Power Save Fall Time, VPS(High) → VPS(Low)
µs
2
5
ZI/Q
I/Q Input Impedance, Between pin I/Ib, Q/Qb
kΩ
II/Q
I/Q Input Bias Current, Between pin I/Ib, Q/Qb
µA
5
-
1.5 :1
ZLO1
LO1 Input VSWR, fLO1 = 100 M to 300 MHz
80
200
13
Note:
1. Without external LC between Fil1 and Fil2 pin on this frequency conditions. Spectrum analyzer conditions: VBW = 300 Hz, RBW = 300 Hz.
California Eastern Laboratories
UPC8158K
ABSOLUTE MAXIMUM RATINGS1 (TA = 25°C)
VCC
VPS/VAGC
PD
TA
TSTG
PARAMETERS
Supply Voltage
Power Save & AGC Control
Power Dissipation2
UNITS
RATINGS
V
5.0
PART NUMBER
V
5.0
mW
430
SYMBOLS
PARAMETERS
VCC
Supply Voltage
Operating Ambient Temp.
°C
-40 to +85
VPS
Storage Temperature
°C
-55 to +150
VAGCPS
UNITS MIN TYP MAX
V
2.7
V
0
V
1.0
2.5
Operating Ambient Temp.
°C
-30
+25 +80
fRFout
Upconv. RF Output Freq.
MHz
800
1500
fLO2in
LO2 Input Frequency
MHz
600
1750
fI/Qin
I/Q Input Frequency
MHz
DC
PLO1in
LO1 Input Level
dBm
-18
PLO2in
LO2 Input Level
dBm
-18
VI/Qin
I/Q Input Amplitude
Upconverter Input Freq.
fMODout
Modulator Output Freq.
SUPPLY
VOLTAGE (V)
PIN
VOLTAGE (V)
1
lin
Vcc/2
–
2
linb
Vcc/2
3
N.C.
–
–
FUNCTION AND APPLICATION
Qinb
Vcc/2
–
5
Qin
Vcc/2
–
6
N.C.
–
–
7
N.C.
–
–
DI
4
8
N.C.
–
–
9
LO1inb
–
2.98
LO1in
–
2.98
11
Vcc
2.7 to 4.0
–
-15
-12
420 500
100
300
EQUIVALENT CIRCUIT
Input for I signal. This input impedance
is 200 kΩ. In the case of that I/Q input
signals are single ended,Vcc/2 biased
DC signal should be input. In the case of
the I/Q input signals are differential,
amplitude of the signal is 500 m VP-P
max.
1
2
4
5
This pin is not connected to internal
circuit. This pin should be opened or
grounded.
Input for Q signal. This input impedance
is 200 KΩ. In the case of that I/Q input
signals are single ended, amplitude of
the signal is 500 m VP-P max.
Input for I signal. This input impedance
is 200 kΩ. In the case of that I/Q input
signals are single ended,Vcc/2 biased
DC signal should be input. In the case of
the I/Q input signals are differential,
amplitude of the signal is 500 m VP-P
max.
These pins is not connected to internal
circuit. These pins should be opened or
grounded.
Bypass pin of modulator's local input.
This pin should be decoupled with 330
pF capacitor.
9
10
-12
Input for I signal. This input impedance
is 200 kΩ. In the case of that I/Q input
signals are single ended, amplitude of
the signal 500 m VP-P max.
SC
O
–
MHz
10
-15
LO1 Input Frequency
IN
SYMBOL
mVP-P
fUPCONin
NT
PIN
NO.
4.0
0.3
AGC Control Voltage
fLO1in
PIN EXPLANATIONS
3.0
TA
UE
Note:
1. Operation in excess of any one of these conditions may result in
permanent damage.
2. TA = +85º C
Power Save Voltage
UPC8158K
D
SYMBOLS
RECOMMENDED
OPERATING CONDITIONS
Local signal for modulator. This pin must
be coupled with DC cut capacitor 330 pF
and should be terminated with 51 Ω
resistor
Supply Voltage pin modulator, upconverter and AGC circuits.
10
UPC8158K
PIN EXPLANATIONS (CONT.)
PIN
VOLTAGE (V)
12
GND
0
–
13
LO2in
–
1.8
14
LO2inb
–
1.8
15
N.C.
–
–
16
GND
0
–
17
VPS/VAGC
VPS/VAGC
–
FUNCTION AND APPLICATION
Ground pin for modulator, up-converter
and AGC circuits. This pin should be
grounded with minimum inductance.
Form the ground pattern as widely as
possible to minimize ground impedance.
Local signal input for modulator. This pin
must be coupled with DC cut capacitor
33 pF and should be terminated with
51 Ω resistor.
14
This pin is not connected to internal
circuit. This pin should be opened or
grounded.
Ground pin for modulator, up-converter
and AGC circuits. This pin should be
grounded with minimum inductance.
Power save control pin for modulator,
upconverter and AGC circuits. This pin
also assigned as gain control pin
forAGC circuits. Operation status with
applied voltages are as follows.
REG
NT
STATE
0 to 0.4
OFF (Sleep Mode)
1 to 2.5
On (AGC Mode)
17
AGC Cont
These pins is not connected to internal
circuit. These pins should be opened or
grounded.
18
N.C.
–
19
GND
0
20
Vcc
2.7 to 4.0
–
Supply Voltage pin for modulator, upconverter and AGC circuits.
21
GND
0
–
Ground pin for RF output buffer. This pin
should be grounded with minimum
inductance.
22
N.C.
–
–
This pin is not connected to internal
circuit. This pin should be opened or
grounded.
23
RFOUT
–
1.75
Ground pin for modulator, up-converter
and AGC circuits. This pin should be
grounded with minimum inductance.
DI
SC
O
–
13
Bypass pin of up-converter's local signal
input. This pin should be decoupled with
33 pF capacitor.
VPS/VAGC (V)
–
EQUIVALENT CIRCUIT
D
SUPPLY
VOLTAGE (V)
UE
SYMBOL
IN
PIN
NO.
RF output pin. This pin is emitter
follower which is low impedance output
port. This pin can be easily matched to
50 Ω impedance using external coupling
and decoupling capacitors.
24
N.C.
–
–
These pins are not connected to internal
circuit. These pins should be opened or
grounded.
25
Vcc
2.7 to 4.0
–
Supply Voltage pin for RF output buffer.
External
23
UPC8158K
PIN EXPLANATIONS (CONT.)
26
SYMBOL
SUPPLY
VOLTAGE (V)
FIL1
PIN
VOLTAGE (V)
–
External inductor and capacitor can
supress harmonics spurious of LO1
frequency.
LC value should be determined
according to LO1 input frequency and
suppression level.
2.76
FIL2
–
2.76
28
GND
0
–
EQUIVALENT CIRCUIT
External
26
27
UE
27
FUNCTION AND APPLICATION
D
PIN
NO.
Ground pin for modulator, up-converter
and AGC circuits. This pin should be
grounded with minimum inductance.
Form the ground pattern as widely as
possible to minimize ground
impedance.
IN
Note:
1. Pin Votages are measured on Vcc = 3.0 V.
TEST CIRCUIT
Voltage Source or
Pulse Pattern Generator
100 pF
0.22 µF
1 000 pF
NT
Voltage
Source
Vector Signal
Analyzer or Spectrum
Analyzer
GND
VPSVAGC
24
28
REG
I/Q Mixer
Phase
Shifter
GND
1
2
100 pF
3
Q
27
GND 12
REG
Fil1
Fil2
Qb
26
I
25
AGC
LPF
Vcc
4
5
100 pF
100 pF
I/Q Signal
Generator
Vcc 11
LO1in 10 330 pF
LO1b 9
330 pF
6
7
100 pF
0.22 µF
LO2b 14 33 pF 51 Ω
51 Ω BPF
LO2in 13 33 pF
UP-CON AGCcount
RFout
1000 pF
GND
Vcc
Signal Generator
100 pF
23
Ib
100 pF
1 000 pF
2 pF
DI
Voltage
Source
0.22 µF
GND
SC
O
22 21 20 19 18 17 16 15
BPF
51 Ω
Signal Generator
or Network
Analyzer
8
TEST CONDITIONS
fLO1in = 178.05 MHz, PLO1in = -15 dBm
fLO2in = 1619.05 MHz, PLO2in = -15 dBm
fRFout = 1441 MHz – fI/Qin
Voltage
Source
UPC8158K
INTERNAL BLOCK DIAGRAM AND PIN
CONNECTIONS (Top View)
SYSTEM APPLICATION
PCS/TDMA PHONE
SUB ANT
UPC8158K
LNA
21
20
19
18
17
16
15
AGCcont
24
2nd MIX
To DEMOD
MAIN ANT
RSSI
RSSI OUT
1st LO
Up-Mix
23
1st MIX
SW
14
SW
AGC
Reg
PLL1
SW
13
12
25
2nd LO
PLL2
D
22
LO2
AGC
LPF
LO1
I
0°
11
9
Phase
Shifter
2
3
8. N.C.
9. LO1inb
10. LO1in
11. VCC
12. GND
13. LO2in
14. LO2inb
4
5
15.
16.
17.
18.
19.
20.
21.
6
7
8
N.C.
GND
Vps/Vagc
N.C.
GND
VCC
GND
22.
23.
24.
25.
26.
27.
28.
N.C.
RFout
N.C.
VCC
Fil1
Fil2
GND
PACKAGE OUTLINE (Units in mm)
UPC8158K
28 PIN PLASTIC QFN
4 -0.5
NT
1.2
0.5
4 -0.5
lin
linb
N.C.
Qinb
Qin
N.C.
N.C.
Filter
IN
1
1.
2.
3.
4.
5.
6.
7.
ORDERING INFORMATION
UPC8158K-E1
28-pin plastic QFN
(5.1x0.95mm)
QUANTITY
QTY. 2.5 kp/Reel.
0.5
0.22
2 x 0.5 = 1
PACKAGE
0.22
Pin 28
Pin 1
PART NUMBER
Q
4.7
I/Q-Mix
90°
PA
10
5.1 ± 0.1
28
(CR)
UE
27
2 x 0.5 = 1
Reg
5.1 ± 0.1
26
0.5
7 x 0.5 = 3.5
5.5 ± 0.1
0.3
0.5
Notes:
1. Embossed tape 12 mm wide. Pin 1 is in pull-out direction.
4.1
0.5
0.125
0.95 ± 0.1
0.22
5.1
0.22
4.5
0.5
0.5
(Bottom View)
DI
SC
O
5.5 ± 0.1
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RF, MICROWAVE & OPTOELECTRONIC SEMICONDUCTORS
CALIFORNIA EASTERN LABORATORIES • Headquarters • 4590 Patrick Henry Drive • Santa Clara, CA 95054-1817 • (408) 988-3500 • Telex 34-6393 • FAX (408) 988-0279
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06/05/2001
DATA SUBJECT TO CHANGE WITHOUT NOTICE