EM MICROELECTRONIC - MARIN SA EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x Sub-1V (0.6V) 8bit Flash MCU DC-DC Converter, E2PROM Architecture The EM6819 is designed to be battery operated for extended lifetime applications. Its large voltage range from 3.6V down to 0.9V makes it a perfect match for today’s demanding applications. Brownout and powercheck functions ensure reliable operation at or near undervoltage conditions, offering greater reliability in complex operation modes. Each of the 24 I/Os are freely programmable and the microcontroller has a dual quartz and trimmable RC oscillator up to 15MHz. It has an 8-bit RISC architecture specially designed for very low power consumption. With 2 clocks per instruction, the EM6819 executes up to 7.5 MIPS at 15MHz and achieves astonishing 4000 MIPS/Watt. Ldcdc DC-DC VREG Power Supply 0.9 – 3.6V VSUP2 VSUP + Cvreg VSSDC VSS2 VSS GPNVM (FLASH) 16.9 kByte Instruction Memory Max 6 kInstr Crystal 32kHz RC 8KHz 15 stages for RTC RC 2 MHz RC 15 MHz Prescaler 2 Tools & Services On chip debug system in the application ISP (In-system) programming C-compiler Windows-based software programs Programmer from different vendors Dedicated team of engineers for outstanding support Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 POWER MANAGEMENT & SECURITY ROM-API CoolRISC 8-bits CR816L 16 registers HW multiplier MEMORIES & CORE Prescaler 1 Crystal or Resonator Sleep Counter wake-up 4MHz 32kHz / 4MHz IRQ & Event controller Reset & wake-up Controller CLOCK & SYSTEM 10 stages Timer1, Timer2 Timer3, Timer4 2x8 bit or 16 bit PWM , Freq Gen Input capure Output compare 2x8 bit or 16 bit PWM , Freq Gen Input capure Output compare OPERTIONAL AMPLIFIER SPI ADC 10 BIT 8 bits master or slave 8 BITS PORT A 8 BITS PORT C Pull-up, pull-down Interrupt, Capture Reset & Wake-up ADC, VLD, OPA,VREF Timer start & clock PWM, Signals Pull-up, pull-down Interrupt,Capture ADC, VLD, OPA Timer start & clock PWM, Signals PA[7:0] PC[7:0] 8 channels Temp Sensor 3 terminals, PA, PC Digital & Analog PERIPHERALS GASP 8 BITS PORT B Debug-on-Chip ISP Monitor SPI or soft UART PWM, signals GASP interface IO’s 2 wire & TM PB[5:0] PB[7:6] TM Pinout for 32 lead QFN Others include SO8, TSSOP16/20/28, and QFN20/32 PB6 PB5 PB4 PB3 PB2 VSS 2 VSS VSS_ DC-DC 32 Lead QFN 5x5mm body 32 31 30 29 28 27 26 25 PB7 1 24 DCDC PA0 2 23 VSUP2 PC0 3 22 VSUP PA1 4 21 PB1 PC1 5 20 PB0 PA2 6 19 PC7 PC2 7 18 PA7 PA3 8 17 PA6 10 11 12 13 14 TM 15 16 PC6 9 PA5 EM6819 DCDC PC4 32 – levels VSUP, PA, PC Application subroutines X1(optional) PA4 Fully static PC3 RAM 512 Bytes Data Memory Max 12 kB VREG Wide supply voltage range 0.9 V – 3.6 V Runs down to 0.6V with enabled DCDC and still 10mA load current True low current: typ 140uA at 3V, 1 MIPS Up to 7.5 MIPS at 15MHz DC-DC converter using just external coil and capacitor On-chip brownout detection PowerCheck functions at start-up 32 Voltage Level Detection on Supply or Input pin 3 terminal Operational Amplifier / Comparator ADC 10-bit, 8 channel Temperature sensor Voltage reference input/output Fast wake-up Up to 24 fully configurable I/Os Flash read monitoring system lowest voltages Dual clock mode, quartz and RC oscillators: o 2 MHz – 15MHz RC, pre-trimmed o Low freq RC Oscillator (8kHz) o 32768 Hz Xtal, 4MHz Resonator/Xtal, Ext Clock 8-bit CoolRISC architecture o 16 registers o 8*8bit hardware multiplier Power-On-Reset and watchdog GPNVM Memory o Sharing Instruction code and data Fully static 512 Byte RAM Internal and external interrupts Frequency generator 4 independent PWM outputs 8/16-bit timers Prescaler for RC and XTAL SPI interface Small size, Green mold / lead-free packages Watch Dog Voltage Regulator Features Voltage Level Detector BrownOut & Power Check Power On Reset DC-DC Up-Converter 2.1V, 2.5V, 2.9V, 3.3V Cdcdc PC5 Description Typical Applications 1 Metering Safety and Security devices Heat Cost Allocation Sensor Interfaces, Smoke detector Security Body care Sports Computer peripherals, Bluetooth chipset Wireless www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x Power supply - VLD Low power architecture Voltage regulator for internal logic supply External regulator capacitor Voltage mult: gives internal multiplied voltage to allow 0.9V start-up (Padring remains on VSUP) DC-DC Upconverter: with ext Coil and Cap. Increases the VSUP for the whole circuit I.e to 3V. Running down to 0.6V input voltage. - Parallel In/Output Port A, Port C - CPU - 8-bit CoolRisc 816L Core 16 internal registers 4 hardware subroutine stacks 8-bit hardware multiplier - - 16.9k Byte shared Genaral Purpose Non Volatile Flash memory max 6k Instructions program memory max 12 kByte non volatile data memory RAM - - Active mode: CPU and peripherals are running Standby mode: CPU halted, peripherals on Sleep mode: no clocks, data retained Power-Down mode, Reset state Wake Up Event from PortA inputs - Power On Reset Reset from logic watchdog Brown out (as voltage supervisory function) Reset with Port A selection Flags to identify the reset source - generation of watchdog reset after time out independent low frequency watchdog oscillator - internal RC oscillator, 2MHz and 15MHz pre-trimmed internal 8 KHz RC Oscillator - 32 KHz watch type Crystal or 4MHz Resonator/XTAL Prescaler’s - - - On-chip Brown-Out detection, reset state Power check at Startup ADC - external IRQ’s from Port A, VLD, Comparator internal IRQ’s from Timer, Prescaler, ADC, SPI Event from SPI/ADC and DoC Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 Fully internal temperature sensor Multiplexed input to ADC Brown Out Two clock prescalers (dividers) for the peripheral clock generation: Prescaler 1 is a 15-stage divider Prescaler 2 is a 10-stage divider input clock software selectable fix intervall IRQ’s Interrupt - All 3 terminals mapped on PortA/PortC Output routed to VLD cell Amplifier or Comparator output Temp. Sensor External Oscillator - Automatically wakes up the circuit from sleep mode Enable/disable by register Op. Amplifier / Comparator Oscillator RC - 8 (16) bit wide, Zero Stop and Auto Reload mode External signal pulse width measurement PWM generation, IRQ Event Counter Input capture Output compare Sleep Counter Wake-up (SCWUP) Watchdog timer - 3 wire serial Interface, Sclk, Sin, Sout master and Slave mode Serial datastream output Event / IRQ Maped on port outputs Timer (4 x 8-bit, or 2 x 16-bit) Resets - 8 multipurpose I/O’s 8-bit wide direct input read CMOS or Nch. Open Drain outputs all functions bit-wise configurable Input , output Pullup, pulldown or nopull selectable CMOS or Nch. Open Drain outputs Serial Port Interface SPI 512 x 8-bit static SRAM 48 byte of Ram-cache for EEProm modification support Operating modes - 8-bit wide direct input read all functions bit-wise configurable Input , output Debouncer, IRQ on pos. or neg. edge Input combination reset Pullup, pulldown or nopull selectable Freq. Input for timer Analog In/Out Parallel In/Output Port B Flash/EEPROM - Detection of 32 voltage levels, internal reference Comparison against VSUP, input Pin or Op.Amp output 10-bit, 8 channels ADC Single or Continuous mode External/internal reference voltage available on a pad Event / IRQ DoC (Debug on Chip) - 2 2 wire serial interface debug and programming interface Flash programming Event / IRQ www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x Pin Name Software selectable functions Remarks PA0 Input with pullup/pulldown, IRQ capability, CPU read, wake-up, timer1 ext clock. Output of CPU write and a selection of internal clock and PWM signals. Analog input for ADC. PA1 Input with pullup/pulldown, IRQ capability, CPU read, wake-up, timer2 ext clock. Output of CPU write, selection of internal clock and PWM signals . Analog: input for ADC and VLD; Output for OPAMP. PA2 Input with pullup/pulldown, IRQ capability, CPU read, wake-up, serial data input, timer3 ext clock. Output of CPU write, serial data out and selection of internal clock and PWM signals Analog: input for ADC,VLD and Opamp; PA3 Input with pullup/pulldown, IRQ capability, CPU read, wake-up, serial data input, timer4 ext clock. Output of CPU write, serial data out and selection of internal clock and PWM signals Analog: input for ADC,VLD and Opamp; PA4 Input with pullup/pulldown, IRQ capability, CPU read, wake-up, serial data. Output of CPU write and a selection of internal clock and PWM signals. Analog: XTAL/Resonator connection. PA5 Input with pullup/pulldown, IRQ capability, CPU read, wake-up. Output of CPU write and a selection of internal clock and PWM signals. PA6 Input with pullup/pulldown, IRQ capability, CPU read, wake-up, serial clock.. Output of CPU write, serial clock and a selection of internal clock and PWM signals. Analog: input for VLD ; Output for VBGP PA7 Input with pullup/pulldown, IRQ capability, CPU read, wake-up, serial clock.. Output of CPU write, serial data and a selection of internal clock and PWM signals. Analog: input for VLD ; Output for internal reference voltage PB0 Input with pullup/pulldown, CPU read, serial data. Output of CPU write and a selection of internal clock and PWM signals. PB1 Input with pullup/pulldown, CPU read. Output of CPU write and a selection of internal clock and PWM signals. PB2 Input with pullup/pulldown, CPU read, serial clock. Output of CPU write, serial clock and a selection of internal clock and PWM signals. PB3 Input with pullup/pulldown, CPU read. Output of CPU write and a selection of internal clock and PWM signals. PB4 Input with pullup/pulldown, CPU read. Output of CPU write, serial data and a selection of internal clock and PWM signals. PB5 Input with pullup/pulldown, CPU read. Output of CPU write and a selection of internal clock and PWM signals. PB6 Input with pullup/pulldown, CPU read. GASP clock Output of CPU write and a selection of internal clock and PWM signals. PB7 Input with pullup/pulldown, CPU read. GASP data Output of CPU write and a selection of internal clock and PWM signals. Input with pullup/pulldown, IRQ capability, CPU read, timer1 ext clock. PC0 Output of CPU write and a selection of internal clock and PWM signals. Analog input for ADC. Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 3 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x PC1 Input with pullup/pulldown, IRQ capability, CPU read, timer2 ext clock. Output of CPU write, selection of internal clock and PWM signals . Analog: input for ADC and VLD; Output for OPAMP. PC2 Input with pullup/pulldown, IRQ capability, CPU read. Output of CPU write, serial data, selection of internal clock and PWM signals . Analog: input for ADC and OPAMP. PC3 Input with pullup/pulldown, IRQ capability, CPU read, timer4 ext clock. Output of CPU write, selection of internal clock and PWM signals . Analog: input for ADC and OPAMP. PC4 Input with pullup/pulldown, IRQ capability, CPU read, external clock input Output of CPU write, selection of internal clock and PWM signals . Analog: XTAL/Resonator connection PC5 Input with pullup/pulldown, IRQ capability, CPU read. Output of CPU write, selection of internal clock and PWM signals . Analog: input for VLD. PC6 Input with pullup/pulldown, IRQ capability, CPU read, serial clock, timer1 ext clock Output of CPU write, serial clock, selection of internal clock and PWM signals . Analog: input for VLD. PC7 Input with pullup/pulldown, IRQ capability, CPU read, timer3 ext clock Output of CPU write, selection of internal clock and PWM signals . TM GASP mode entry VREG External Capacitance to maintain internal regulated voltage DC-DC Coil connection in in case of DC-DC converter VSUP Main power supply pin. GASP mode Connect to positive terminal of the DC-DC charge holder capacitance VSUP2 Supply filtering pin in case of DC-DC converter Connect to positive terminal of the DC-DC charge holder capacitance Only on DCDC Versions Connect to VSUP if DC-DC not used VSS Main GND. This is also the circuit substrate potential. Connect to negative terminal of the DC-DC charge holder capacitance VSS2 Ground noise filtering in case of DCDC converter used Connect to negative terminal of the DC-DC charge holder capacitance Only on DCDC versions Connect to VSS if DC-DC not used VSS_ DC-DC DCDC ground connection Connect to negative terminal of the DC-DC charge holder capacitance Only on DCDC versions Connect to VSS if DC-DC not used Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 4 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x TABLE OF CONTENTS 1. EM6819 FAMILY 11 2. SYSTEM OVERVIEW 12 2.1 OPERATING MODES 2.1.1 Active mode 2.2 LOW POWER MODES 2.2.1 Standby mode 2.2.2 Sleep mode 2.2.3 Sleep Wake-up 2.2.4 Power-down mode 2.2.5 Operation mode registers 2.3 REGISTER TYPES 2.4 POWER MANAGEMENT 2.4.1 Brownout 2.4.2 Powercheck 2.4.3 POR 2.4.4 Power managment Registers 2.5 REGISTER MAP 2.6 PORT TERMINAL CONNECTION REFERENCE TABLE 2.7 TSSOP PACKAGE PINOUT CIRCUIT WITHOUT DC-DC AND S08 2.8 TSSOP PACKAGE PINOUT CIRCUIT WITH DC-DC 2.9 QFN PACKAGES WITH AND WITHOUT DCDC 3. CPU CORE CR816 13 13 13 13 14 14 15 16 17 18 18 18 18 19 20 27 28 29 30 31 3.1 PM_MISS FUNCTION (FLASH READ MONITOR) 4. NVM MEMORY 31 32 4.1 INTRODUCTION 4.2 NVM ARCHITECTURE 4.3 RAM CACHE 4.4 W RITE DATA IN NVM 4.4.1 Row and sector selection 4.4.2 Fast/slow operation 4.4.3 Erase 4.4.4 Write 4.5 ROW 61 SECTOR 5 4.6 ROW 62 SECTOR 5 4.6.1 Temperature tolerance 4.7 ROW 63 SECTOR 5 4.8 READ DATA IN NVM 4.9 ROW TO CACHE 4.9.1 NVM configuration registers 5. CRC CHECK 32 32 33 33 34 34 34 34 35 35 35 36 37 37 38 39 5.1 CRC CHECK ON PROGRAM AREA 5.2 CRC CHECK ON DATA AREA 6. ROM API ROUTINES 39 39 40 6.1 BOOT SEQUENCE 6.2 SUB-ROUTINES USED FOR APPLICATION 7. RAM 40 41 42 8. 43 RESET CONTROLLER 8.1 RESET SOURCES 8.2 RESET SIGNALS 8.2.1 POR 8.2.2 PorLog 8.2.3 ResAna 8.2.4 ResSys 8.2.5 Reset Flags Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 43 43 43 43 43 43 44 5 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 9. 8.3 RESET REGISTERS OSCILLATOR AND CLOCKING STRUCTURE 44 45 9.1 EXTERNAL CLOCK SELECTION 9.2 INTERNAL HIGH AND LOW FREQUENCY CLOCK SELECTION 9.2.1 external clock selection Restrictions 9.2.2 CPU Clock selection 9.2.3 Prescaler1 Clock selection 9.2.4 Prescaler 2 Clock selection 9.3 CLOCK CONTROL 9.4 OSCILLATORS CONTROL 9.5 CLOCK CONTROL REGISTERS 10. PRESCALER1 46 46 47 47 48 48 49 50 52 54 10.1 PRESCALER1 CLOCK SELECTION 10.2 PRESCALER1 RESET 10.3 PRESCALER REGISTERS 11. PRESCALER2 54 55 55 56 11.1 PRESCALER2 CLOCK SELECTION 11.2 PRESCALER2 RESET 11.3 PRESCALER2 REGISTERS 12. INTERRUPT AND EVENT CONTROLLER 56 56 56 57 12.1 INTERRUPTS GENERAL 12.1.1 Basic features 12.2 INTERRUPT ACQUISITION 12.3 INTERRUPTS FROM IO PORTS 12.4 INTERRUPT ACQUISITION MASKING. 12.4.1 Pre and Postmasking of interrupts 12.5 INTERRUPT ACQUISITION CLEARING 12.5.1 Software Interrupt acquisition set 12.6 INTERRUPT REGISTERS 12.7 EVENT GENERAL 12.7.1 Basic features 12.8 EVENT ACQUISITION 12.9 EVENT MASKING 12.10 EVENT ACQUISITION CLEARING 12.11 SOFTWARE EVENT SETTING 12.12 EVENT REGISTERS 13. CPU INTERRUPT AND EVENT HANDLING 57 57 58 59 59 59 60 60 60 63 63 63 64 65 65 65 66 13.1 INTERRUPT PRIORITY 13.2 CPU STATUS REGISTER 13.3 CPU STATUS REGISTER PIPELINE EXCEPTION 13.4 PROCESSOR VECTOR TABLE 13.5 CONTEXT SAVING 14. PORT A 66 67 67 68 68 69 14.1 PORT A TERMINAL MAPPING 14.2 PORT A IO OPERATION 14.3 OUTPUT SIGNALS ON PORT A 14.4 PORT A DEBOUNCER 14.5 PORT A INTERRUPT GENERATION 14.5.1 PA Irq in Active and Standby mode 14.5.2 PA Irq in Sleep Mode 14.6 PORT A RESET FUNCTION 14.7 PORT A WAKE-UP FUNCTION 14.8 PORT A REGISTERS 15. PORT B 69 69 71 72 72 72 72 72 72 73 75 15.1 PORT B TERMINAL MAPPING Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 75 6 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 15.2 PORT B IO OPERATION 15.2.1 Gasp communication on PB7, PB6 15.3 OUTPUT SIGNALS ON PORT B 15.4 PORT B REGISTERS 16. PORT C 75 76 77 78 79 16.1 PORT C TERMINAL MAPPING 16.2 PORT C IO OPERATION 16.3 OUTPUT SIGNALS ON PORT C 16.4 PORT C DEBOUNCER 16.5 PORT C INTERRUPT GENERATION 16.5.1 PC Irq in Active and Standby mode 16.5.2 PC Irq in Sleep Mode 16.6 PORT C REGISTERS 17. TIMERS 79 79 81 82 82 82 82 83 85 17.1 TIMER CHAINING 17.2 TIMER CLOCK SOURCES 17.3 TIMER START 17.3.1 Software start - Stop 17.3.2 Hardware Start – Stop (period counting) 17.3.3 Hardware Start – Stop (puls counting) 17.4 AUTO-RELOAD MODE 17.5 AUTO-STOP MODE 17.6 TIMER INPUT CAPTURE 17.7 OUTPUT COMPARE 17.8 OUTPUT COMPARE - PWMX SIGNAL PORT MAPPING 17.9 TIMER INTERRUPTS 17.10 TIMER REGISTERS 18. SPI – SERIAL INTERFACE 85 86 87 87 87 88 89 89 90 92 93 94 94 98 18.1 SCLK - SPI MASTER/ SLAVE MODE AND CLOCK SELECTION 18.2 SIN PORT MAPPING 18.3 SOUT PORT MAPPING 18.4 SPI START – STOP 18.5 AUTO-START 18.6 RTZ POSITIVE EDGE TRANSMISSION 18.7 RTO POSITIVE EDGE TRANSMISSION 18.8 RTZ NEGATIVE EDGE TRANSMISSION 18.9 RTO NEGATIVE EDGE TRANSMISSION 18.10 SPI REGISTERS 19. WATCHDOG 99 100 100 100 100 101 101 101 102 102 103 19.1 W ATCHDOG CLEAR 19.2 W ATCHDOG DISABLING 19.3 W ATCHDOG REGISTERS 20. SLEEP COUNTER WAKE-UP 103 103 104 105 20.1 SC WAKE-UP ENABLING 20.2 SC WAKE-UP DISABLING 20.3 SC WAKE-UP REGISTERS 21. 10-BITS ADC 105 106 107 108 21.1 CONDITIONER 21.1.1 Range selection 21.1.2 Reference selection 21.1.3 Analog input selection 21.2 ADC OFFSET TRIM SELECTION 21.2.1 Running mode 21.2.2 ADC enabling 21.2.3 ADC sampling rate 21.2.4 Low noise mode Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 108 108 109 110 110 111 111 112 112 7 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 21.2.5 8bit ADC selection 21.3 ADC ACQUISITION SEQUENCE 21.4 ADC REGISTERS 22. TEMPERATURE SENSOR 112 113 113 114 22.1 TEMPERATURE SENSOR ENABLING 22.2 TEMPERATURE SENSOR REGISTERS 23. DC/DC CONVERTER 114 114 115 23.1 DC/DC ENABLING 23.2 DC/DC VOLTAGE SELECTION 23.3 DC/DC LOW NOISE MODE 23.4 DC-DC REGISTER 24. BAND GAP 115 115 115 116 117 24.1 BAND GAP REGISTER 25. VLD 117 118 25.1 VLD SOURCE AND LEVEL SELECTION 25.2 VLD ENABLE 25.3 VLD RESULT 25.4 VLD INTERRUPT 25.5 VLD TRIMMING 25.6 VLD REGISTERS 26. RC OSCILLATOR 118 118 118 119 119 119 120 26.1 RC OSCILLATORS REGISTERS 27. XTAL OSCILLATOR 32KHZ 120 121 28. RESONATOR 4MHZ 122 29. 8KHZ OSCILLATOR 123 30. ANALOG OPAMP 124 30.1 SELECT OPAMP/COMPARATOR 30.2 SUPPLY SELECTION 30.3 COMPARATOR RESULT 30.4 OPAMP REGISTERS 31. BLOCKS CONSUMPTION 124 124 125 125 126 32. TYPICAL T AND V DEPENDENCIES 127 32.1 IDD CURRENTS 32.1.1 General conditions 32.2 IOL AND IOH DRIVES 32.3 PULL-UP AND PULL-DOWN 32.4 RC OSCILLATOR 15MHZ AND 2MHZ 33. ELECTRICAL SPECIFICATION 127 127 134 137 139 140 33.1 33.2 33.3 33.4 33.5 33.6 33.7 33.8 33.9 33.10 33.11 33.12 33.13 33.14 33.15 ABSOLUTE MAXIMUM RATINGS HANDLING PROCEDURES STANDARD OPERATING CONDITIONS TYPICAL 32KHZ CRYSTAL SPECIFICATION TYPICAL 4MHZ CRYSTAL SPECIFICATION TYPICAL 4MHZ RESONATOR SPECIFICATION DC CHARACTERISTICS - POWER SUPPLY CURRENTS DC CHARACTERISTICS – VOLTAGE DETECTION LEVELS DC CHARACTERISTICS – REFERENCE VOLTAGE DC CHARACTERISTICS – DC-DC CONVERTER DC CHARACTERISTICS – OSCILLATORS DC CHARACTERISTICS – VHIGH DC CHARACTERISTICS – OPAMP DC CHARACTERISTICS – ADC DC CHARACTERISTICS – TEMPERATURE SENSOR Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 140 140 140 141 141 141 142 144 144 145 145 146 146 146 147 8 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 33.16 DC CHARACTERISTICS - I/O PINS (ON PACKAGE) 33.17 DC CHARACTERISTICS - I/O PINS (ON DIE) 34. WAKEUP AND BOOT SEQUENCE TIMING 147 148 149 35. PACKAGE DRAWINGS 150 35.1 DIMENSIONS OF TSSOP28 PACKAGE 35.2 DIMENSIONS OF TSSOP24 PACKAGE 35.3 DIMENSIONS OF TSSOP20 PACKAGE 35.4 DIMENSIONS OF TSSOP16 PACKAGE 35.5 DIMENSIONS OF SO8 PACKAGE 35.6 DIMENSIONS OF QFN32 PACKAGE 35.7 DIMENSIONS OF QFN20 PACKAGE 35.8 PAD LOCATION OF THE DIE (VERSION 005 AND 006) 35.9 PAD LOCATION OF THE DIE (ALL OTHER VERSIONS) 36. PACKAGE MARKING 150 151 152 153 154 155 156 157 158 159 37. ERRATA 160 38. ORDERING INFORMATION 161 Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 9 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x Acronyms used in this document MSB LSB CR / CPU/ NVM ROM RAM API GASP SW HW ‘1’ / H / high ‘0’ / L / low POR PWRC SCWUP VLD (T) (Q) (D) most significant bit least significant bit CoolRisc 816 CPU core Non Volatile Memory Read Only Memory Random Access Memory Application Program Interface General Access Serial Port Software Hardware Determines HIGH value, logical true Determines LOW value, logical false Power on reset Power check Sleep Counter Wake-up Voltage Level Detector Tested in the production Validated during qualification Guaranteed by the design Nomenclature Bit order scheme in this document is [n:0] where bit ‘n’ is the MSB and bit ‘0’ is the LSB, unless otherwise stated. Positive logic is assumed, High (‘1’) values means asserted or active state and Low (‘0’) value means not asserted or inactive state, unless otherwise stated. Register names and register bit names are written in bold typeface. Signal names are written in italic-bold type face. API subroutines are written in italic Naming convention The XTAL frequency is 32.768 kHz but is this document it is written 32 KHz (k=1000, K=1024). Related Documents [1] [2] CoolRISC 816L 8-bit Microprocessor Core, Hardware und Software Reference Manual V1.1 Mai 2002 ROM API document Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 10 www.emmicroelectronic.com Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 2K word Flash (5.6kByte) 4K word Flash (11.5kByte) 11 8 12 12 12 12 8 8 8 8 8 8 4 4 512 512 512 512 512 512 512 512 512 256 256 512 512 1.8 - 5.5 1.8 - 3.6 1.8 - 3.6 0.9 - 3.6 0.9 - 3.6 1.8 - 5.5 1.8 - 3.6 0.9 - 3.6 0.9 - 3.6 0.9 - 3.6 0.9 - 3.6 1.8 - 5.5 0.9 - 3.6 0.9 - 3.6 Non Volatile Memory Random Access Memory General Purpose Input Output Serial Peripheral Interface Fully embedded RC Oscillator Oscillator on chip Digital Watch-dog 6 EM6819F6-B300 NVM RAM GPIO SPI RC Crystal WD 6 EM6819F6-A100 6 EM6819F6-B004 6 4 EM6819F4-B300 EM6819F6-B100 4 EM6819F4-B100 6 4 EM6819F4-B000 EM6819F6-A000 4 EM6819F4-A000 4 EM6819F4-B005 4 2 EM6819F4-A005 2 EM6819F2-B300 512 PWM ADC OPAMP PwrCk VLD ISP SCWUP 16 to 24 12 to 24 - 12 to 24 12 to 24 04 to 24 16 to 24 12 to 24 - - - - 12 to 24 12 to 24 - 08 to 12 04 to 12 - 16 to 24 12 to 20 - 12 to 24 - 04 to 12 EM6819F2-A000 4 - 2 256 0.9 - 3.6 EM6819F2-B000 4 2 EM6819F2-B006 ) ds or Part number W ) B ) (K or (V a rt t e ve da e ng n ns d a o r pi c VM (B) co s ly N C h p O M D p as ax PI A C Fl m R Su D G (K m m co i 15MHz 15MHz 15MHz 15MHz 15MHz 15MHz 15MHz 15MHz 15MHz 15MHz 15MHz 15MHz 15MHz 15MHz 15MHz lo C ck I lo na er nt s to lla ci r RC 8kHz 2MHz 15MHz RC 8kHz 2MHz 15MHz Crystal 32kHz - 4Mhz RC 8kHz 2MHz 15MHz Crystal 32kHz - 4Mhz RC 8kHz 2MHz 15MHz Crystal 32kHz - 4Mhz RC 8kHz 2MHz 15MHz Crystal 32kHz - 4Mhz RC 8kHz 2MHz 15MHz RC 8kHz 2MHz 15MHz Crystal 32kHz - 4Mhz RC 8kHz 2MHz 15MHz Crystal 32kHz - 4Mhz RC 8kHz 2MHz 15MHz Crystal 32kHz - 4Mhz RC 8kHz 2MHz 15MHz Crystal 32kHz - 4Mhz RC 8kHz 2MHz 15MHz RC 8kHz 2MHz 15MHz RC 8kHz 2MHz 15MHz Crystal 32kHz - 4Mhz RC 8kHz 2MHz 15MHz Crystal 32kHz - 4Mhz RC 8kHz 2MHz 15MHz Crystal 32kHz - 4Mhz d ee sp Pulse Width Modulation Analog to Digital Converter Operational Amplifier Power Check on start-up Voltage Level Detector In System Programming Sleep Counter Wake-Up SPI SW-UART / I2C SPI SW-UART / I2C SPI SW-UART / I2C SPI SW-UART / I2C SPI SW-UART / I2C SPI SW-UART / I2C SPI SW-UART / I2C SPI SW-UART / I2C SPI SW-UART / I2C SPI SW-UART / I2C SPI SW-UART / I2C SPI SW-UART / I2C SPI SW-UART / I2C SPI SW-UART / I2C SPI SW-UART / I2C ig D l ita un n tio ca ) el 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 8 8 8 8 8 8 8 8 8 4 4 - - SCWUP WD SCWUP WD SCWUP WD SCWUP WD SCWUP WD SCWUP WD SCWUP WD SCWUP WD SCWUP WD SCWUP WD SCWUP WD SO08 TSSOP16 TSSOP16-20 QFN20 TSSOP20-28 QFN20-32 TSSOP16-20-28 QFN20 TSSOP16-20-28 QFN20 TSSOP20-28 QFN20 te da up e P ar l tw / IS ta of ip s gi h i r fo n C (s) ld e e na rit g O ag 1 tio w i u ck te lf dd eb A se D Pa No SCWUP SO08 WD TSSOP16 SCWUP TSSOP16-20-28 WD QFN20 SCWUP TSSOP20-28 WD QFN20 SCWUP TSSOP20-28 WD QFN20 SO08 TSSOP16-20-28 TSSOP20-28 QFN20-32 TSSOP16-20-28 QFN20 TSSOP20-28 QFN20-32 TSSOP16-20-28 QFN20 28.12.09 jag Note 1 : Ask for package & volume availability PwrCk Brown-Out OPAMP VLD PwrCk Brown-Out OPAMP VLD PwrCk Brown-Out OPAMP VLD PwrCk Brown-Out OPAMP VLD PwrCk Brown-Out OPAMP VLD PwrCk Brown-Out OPAMP VLD PwrCk Brown-Out OPAMP VLD PwrCk Brown-Out OPAMP VLD PwrCk Brown-Out OPAMP VLD PwrCk Brown-Out OPAMP VLD PwrCk Brown-Out OPAMP VLD l) ne ch g an lo to ch na or up a ( s o s t n C al er p D Se ion (u im A p. it it M tT d m i b d 8b PW 10 Te A PwrCk Brown-Out VLD 4 4 PwrCk Brown-Out OPAMP VLD 4 4 8 PwrCk Brown-Out OPAMP VLD 4 4 8 PwrCk Brown-Out OPAMP VLD 4 4 8 n an 1. 6K word Flash (16.9kByte) EM6819 family ensures 0.9V battery operations and much more … EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x EM6819 FAMILY www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 2. SYSTEM OVERVIEW The circuit’s function blocks can be splitted in 5 different categories: Power management and security functions Memories and CPU Core Clock selection, clock switching and system peripherals Digital and Analog internal peripherals Communication interfaces via the IO pads Figure 1, EM6819 overview Ldcdc DC-DC VREG VSUP2 VSUP + Cvreg Cdcdc VSSDC VSS2 VSS Power Supply 0.9 – 3.6V DC-DC Up-Converter 2.1V, 2.5V, 2.9V, 3.3V Power On Reset BrownOut & Power Check Voltage Level Detector Watch Dog 32 – levels VSUP, PA, PC POWER MANAGEMENT & SECURITY Voltage Regulator GPNVM (FLASH) 16.9 kByte Data Memory Max 12 kB Instruction Memory Max 6 kInstr Crystal 32kHz RC 8KHz RAM 512 Bytes Fully static ROM-API CoolRISC 8-bits Application subroutines CR816L 16 registers HW multiplier MEMORIES & CORE Prescaler 1 15 stages for RTC X1(optional) Crystal or Resonator 32kHz / 4MHz 4MHz RC 2 MHz RC 15 MHz Timer1, Timer2 Prescaler 2 Sleep Counter wake-up Reset & wake-up Controller CLOCK & SYSTEM 10 stages Timer3, Timer4 OPERTIONAL AMPLIFIER SPI ADC 10 BIT 2x8 bit or 16 bit PWM , Freq Gen Input capure Output compare IRQ & Event controller 2x8 bit or 16 bit PWM , Freq Gen Input capure Output compare 8 bits master or slave 8 BITS PORT A 8 BITS PORT C Pull-up, pull-down Interrupt, Capture Reset & Wake-up ADC, VLD, OPA,VREF Timer start & clock PWM, Signals Pull-up, pull-down Interrupt,Capture ADC, VLD, OPA Timer start & clock PWM, Signals PA[7:0] PC[7:0] 8 channels Temp Sensor 3 terminals, PA, PC Digital & Analog PERIPHERALS GASP 8 BITS PORT B SPI or soft UART PWM, signals GASP interface Debug-on-Chip ISP Monitor IO’s 2 wire & TM PB[5:0] PB[7:6] TM Power management and security functions The power managment block assures a proper system start at power up with Power on reset and power check function. The internal Brownout supervises the CPU and core internal power supply and asserts a reset at undervoltage. The watchdog function monitors the CPU execution, wheras the VLD can be used to monitor internal or external voltages. Its results are available to the user to take actions accordingly. The DC-DC upconverter can be switched on by demand. Memories and CPU Core This part contains all user program memory (FLASH), the non volatile data memory (mapped into the FLASH memory), the RAM and the vendor supplied application subroutines (ROM-API) for non volatile memory modifications. An essential part of this block is also the CR816 microprocessor core. Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 12 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x Clock selection, clock switching and system pheripherals This block takes care of all internal and external clock sources. It synchronizes the clocks where needed and assures that the system can not hang-up due to faulty clock switching (i.e avoids switching to a non-present clock source). This block is also an essential part of the low power architecture by minimizing the total energy consumption by keeping the active clocking nodes to a strict minimum. Digital and Analog internal peripherals This part contains all the user peripherals such as timer, SPI, ADC, etc … These peripherals are user configurable and fully adjustable to the user application. Communication interfaces via the IO pads Here are all the external communication channels grouped. All communication goes through at least 1 of the max 24 IO’s. Several internal functions such as, serial interface, PWM, freq outputs, etc. are mapped to the IO’s. 2.1 OPERATING MODES The circuit has 4 distinctive operations modes wheras Standby, Sleep and Power-Down mode are specific low power modes Active CPU running all functions may be used StandBy CPU in Standby not clocked. Peripheral functions may be running Sleep CPU in Standby not clocked. Peripherals stopped except for specifically enabled functions Power-Down CPU and peripheral functions in reset. No Clocks. Pad configuration maintained. 2.1.1 ACTIVE MODE The active mode is the default mode after any system reset. In this mode all peripherals are powered and ready to be used. All Low power modes are initiated from the active mode by executing the HALT instruction. If using an external high frequency clock input and the derived CPU clock is higher 6MHz the user shall set the bit FrcFastRead which acts as a booster for the Flash reading. For all internal clock selection the boosting is done automatically. 2.2 LOW POWER MODES The Low power modes are enabled by the CPU HALT instruction execution. The resulting Low power mode selection then depends on the SelPwrDwn and SelSleep bit settings, both are located in the system register RegSysCfg1. Mode HALT Instruction RegSysCfg1.SelSleep RegSysCfg1.SelPwrDwn No Yes Yes Yes X 0 1 X X 0 0 1 Active StandBy Sleep Power-Down 2.2.1 STANDBY MODE This mode is activated by HALT instruction if SelPwrDwn=’0’ and SelSleep=’0’. The active clock oscillator for the CPU clock source as selected by SelCkCR will be disabled in StandBy mode if it is not used by other block/peripheral or it’s not forced-on. The Flash memory is disabled to save power. If fast wake-up is needed the user can choose to leave the Flash memory enabled in StandBy mode by setting the bit StdByFastWkUp in register RegSysCfg1 to ‘1’. Resume from standby mode and going back to active mode with an Event, an Interrupt or a system reset. Wake-up time from Standby mode is 1.5us if StdByFastWkUp =’1’ and CPU is on 15 MHz with the 15 MHz RC oscillator forced on. Wake-up time from Standby mode is 10us if StdByFastWkUp =’1’ and CPU is on 2 MHz with the 2 MHz RC oscillator forced on. Wake-up time from Standby mode is 150us if StdByFastWkUp =’0’ and CPU is on 2 MHz with the 2 MHz RC oscillator forced on. Wake-up delay is measured from the time of the wake-up interrupt until the result of the first CPU instruction. Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 13 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x The bit StdByFastWkUp =’1’ will increase the standby power consumption by ~1.5uA at any CPU freq settings except if the CPU is set to RC_15MHz, RC_15MHz/2 or the bit FrcFastRead is set. In these cases the extra power consumption will be ~35uA. To avoid this extra 35uA of current the user must predivide the CPU clock just before going to standby mode to values below 6MHz by a) use RC_15MHz/4 or lower frequencies based on 2MHz, 32kHz, RC8k, b) or in case of external high freq clock input, set the CK_CPU predivider such that the resulting CPU frequeny is below 6MHz After wake-up the original high frequency CPU clock can immediately be reinstalled with little wake-up time penalty. Using StdByFastWkUp =’1’ together with FrcFastRead=’1’ will draw additional 35uA independent of the selected CPU clock source. It should therefore be avoided by clearing FrcFastRead before going into standby mode. 2.2.2 SLEEP MODE This mode is activated by HALT instruction if SelPwrDwn=’0’ and SelSleep=’1’. In Sleep mode the Temperature sensor and the ADC are disabled. All oscillators are forced off except the RC 8kHz oscillator if used for sleep counter wake-up function. All register data are maintained during sleep. The Flash memory is switched off for power save. Resume from Sleep mode back to active mode with selected Interrupts and Events or by a system reset or by the sleep counter wakeup function SCWUP. 2.2.3 SLEEP WAKE-UP st Normal Wake-up from Sleep mode will take typically 250us until the 1 instruction after wake-up is executed. By setting the bit StdByFastWkUp prior to entering sleep mode the wake-up from sleep mode is greatly reduced. In case of 2MHz RC Oscillator as CPU clock the wake-up time in fast mode is typically 18us In case of 15MHz RC Oscillator as CPU clock the wake-up time in fast mode is typically 11us rd This wakeup time is measured from the wake-up event until the 3 instruction after the wakeup event is changing a port output pin status. The bit StdByFastWkUp =’1’ will increase the sleep power consumption by ~1.5uA at any CPU freq settings except if the CPU is set to RC_15MHz, RC_15MHz/2 or the bit FrcFastRead is set. In these cases the extra power consumption will be ~35uA. To avoid this extra 35uA of current the user must predivide the CPU clock just before going to sleep mode to values below 6MHz by c) use RC_15MHz/4 or lower frequencies based on 2MHz, 32kHz, RC8k, d) or in case of external high freq clock input, set the CK_CPU predivider such that the resulting CPU frequeny is below 6MHz After sleep wake-up the original high frequency CPU clock can immediately be reinstalled with almost no wake-up time penalty. Using StdByFastWkUp =’1’ together with FrcFastRead=’1’ will draw additional 35uA independent of the selected CPU clock source. It should therefore be avoided by clearing FrcFastRead before going into sleep mode. Note: DC/DC has to be switched off by the user before entering Sleep mode. Note: Interrupt sources for wake-up from the Sleep mode are defined in 12.2 Interrupt acquisition Note: Event sources for wake-up from the Sleep mode are defined in 12.8 Event acquisition Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 14 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 2.2.4 POWER-DOWN MODE This mode is activated by HALT instruction if SelPwrDwn=’1’. All Clocks and oscillators including the RC 8 KHz are stopped. No circuit activity anymore. All register and RAM data are lost in Power-Down mode. The device is woken-up by a level change on PortA bits or by TM=’1’; RegEnWkUpPA[n] will enable the related bit of PortA for this purpose when it is at high level. The wake-up from Power-Down acts as a reset, the CPU will start from scratch. The wake-up time from power down back to active mode is approximativly 6ms, and up to 10ms in low power mode. Note: Going into PowerDown mode without pad configuration latch shall be down in the following order: 1. Set the wake-up condition 2. Write the SelPwrDown bit 3. Execute HALT instruction 2.2.4.1 PAD CONFIGURATION LOCK IN POWER-DOWN If the bit LckPwrCfg in register RegResFlag is set, the configurations of all Ports bits (direction, pull-up, pull-down, qblock) are locked in the pad latches. As soon as the LckPwrCfg is set back to ‘0’ the actual register configuration will be taken over. Note: To keep pad configuration in Power-Down mode, SW shall set LckPwrCfg to ‘1’ just before going into Power-Down mode and sets it to ‘0’ after wake-up from Power-Down mode. Note: Going into PowerDown mode without pad configuration latch shall be down in the following order: 1. Set the wake-up condition 2. Write the SelPwrDown bit 3. Write the LckPwrCfg bit 4. Execute HALT instruction Note: No data are kept in the registers and in the RAM in the Power-Down mode Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 15 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 2.2.5 OPERATION MODE REGISTERS 0x0000 Bits Name 7 SelSleep 6 SelPwrDwn 4 EnBrownOut 3:2 XtalCldStart 1 StdByFastWkUp 0 VSUPLow RegSysCfg1 Type ResVal RW 0 RW 0 RW 1 RW '00' RW 0 RO 0 0x0006 Bits Name RegResFlg Type ResVal ResSrc Reset Flags Description 7 6 5 4 3 0 ResFlg ResFlg ResFlg ResFlg ResFlg RW PorLog PorLog PorLog PorLog PorLog Por Flag Reset from Port-A Flag Reset from WatchDog Flag Reset from Brown-Out Flag Reset from GASP Flag Reset from CoolRisc Bus-Error Lock configurations to be kept in Power-Down mode 16 www.emmicroelectronic.com ResFlgPA ResFlgWD ResFlgBO ResFlgGasp ResFlgBE LckPwrCfg Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 0 0 0 0 0 0 ResSrc ResSys ResSys ResAna ResSys ResSys System Configuration - 1 Description Select Sleep mode on Halt Select Power-Down mode on Halt Enable Brown Out Select Xtal Osc. ColdStart length Stand-by mode fast Wakeup VSUP is Low - Tripler activated EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 2.3 REGISTER TYPES The peripheral registers are of different types. The specific type of the register is marked in its table definition. Used types are: RW, RO, OS, INT, INT-SET, STS, NI, RESFLG Read-Write Register (RW) - the software is able to write high and low values - the software is able to read out the last written value - the initial and reset value is according to its specified reset value Read Only register (RO) - the software is able to read out the current status of the hardware status - the initial and reset value is according to the value of the initial hardware status or hardware status after reset One Shot register (OS) - the software wriring of the specified value is producing the given action - the software always reads a low value Interrupt status register (INT) - Software writing ‘0’ will clear a pending interrupt, clear has priority over a new arriving interrupt. - Software writing ‘1’ will set the interrupt status bit (software interrupt). This has highest priority. - If the software reads the interrupt status at ‘1’ it will clear it after the reading. - If the software reads ‘0’, no action is performed. - An incoming hardware interrupt event will set the status bit, this action has priority over clear by software read. - The reset value is ‘0’ Status register (STS) - the software can write only the allowed values into the register. These values are specified case-by-case. - the hardware may also be able to change the register value according to its function - the access priority software over hardware is specified case-by-case. - the readout value corresponds to the last change (software or hardware change) - the initial and reset value are specified case-by-case Not Implemented register (NI) - no action on write - the software is reading the specified constant value (normaly ‘0’) Reset flag register (RESFLG) - an incoming hardware event sets or clears the register according on its specification - the readout value is according to the last hardware event and specified case-by-case. - The initial and reset value is according to the value specified case-by-case defined by its last hardware event - The software is able to clear the flag by writing ‘1’ to it, writing ‘0’ has no effect - Hardware event has priority over software access. Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 17 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 2.4 POWER MANAGEMENT The internal voltage regulator and the voltage multiplier assure a constant voltage VREG to the memory cells, GPNVM, RAM, ROM, the logic, the CPU core and sensible analog cells over the whole voltage range. For voltages below typ 2.2V the internal voltgage multiplier may become active and deliver the energy to sustain VREG voltage. While the internal voltage multiplier is enabled the maximum current draw of all VREG supplied peripherals is limited and the user shall not use operation frequencies above 2MHz nor switch on the 15Mhz RC oscillator. The flag VSUPLow shows the status of the voltage multiplier, if read ‘1’ it means the multiplier is active and the current rescrictions apply.On low voltage supply status 1’ the internal voltage multiplier maintains VREG voltage. Full frequency range can be used as long as VSUPLow = ‘0’, the voltage multiplier is disabled and the logic regulator maintains VREG stable. Figure 2, Power Management architecture PwrDown Internal Power Managment VSUP VSUP En En Voltage Multiplier VREG VSUP VSUP VSUP_low VSUP VSUP VSUP PwrCheck Analog Periphery BrownOut GPNVMMemory RAM ROM Logic Periphery & CPU En PA PB PC ref 2.4.1 BROWNOUT If enabled, the BrownOut supervises the VREG voltage. As soon as Vreg drop below the minimal safe operation voltage for core operations and as such underpasses the brownout limits, reset ResBO is asserted. The circuit goes in reset state and can only recover from reset if the voltage rises above the PwrCheck level. (V PWRCheck > VBrwnout). The brownout can be disabled by EnBrownOut bit. The function is also automatically stopped in sleep mode if none of the Bandgap reference, ADC or OPAMP is active. 2.4.2 POWERCHECK Powercheck is enabled on system power-up, it keeps the circuit in idle state until VREG voltage is sufficient high for safe core operation. ( VREG > VPWRCheck > VBrwnoutt) Powercheck is active after initial power-up, wake-up from Power-Down, wake-up from sleep after any system reset 2.4.3 POR POR circuitry supervises the supply voltage VSUP at start-up and during all operation modes. As long as VSUP is below the VPOR voltage the circuit is in reset state. If the VSUP falls below V POR the circuit will enter reset state even if brownout was disabled. At power-up the POR initializes the whole circuit except the RAM and powercheck is initiated. Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 18 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 2.4.4 POWER MANAGMENT REGISTERS 0x0000 Bits Name 7 SelSleep 6 SelPwrDwn 4 EnBrownOut 3:2 XtalCldStart 1 StdByFastWkUp 0 VSUPLow RegSysCfg1 Type ResVal RW 0 RW 0 RW 1 RW '00' RW 0 RO 0 Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 ResSrc ResSys ResSys ResAna ResSys ResSys 19 System Configuration - 1 Description Select Sleep mode on Halt Select Power-Down mode on Halt Enable Brown Out Select Xtal Osc. ColdStart length fast Wakeup for Stand-by and Sleep mode VSUP is Low - Tripler activated www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 2.5 REGISTER MAP RegName Address Init. Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 RegSysCfg1 0x0000 0x10 SelSleep SelPwrDwn - EnBrownOut XtalCldStart(1) XtalCldStart(0) StdByFastWkUp VSUPLow RegEnResPA 0x0001 0x00 EnResPA(7) EnResPA(6) EnResPA(5) EnResPA(4) EnResPA(3) EnResPA(2) EnResPA(1) EnResPA(0) RegEnWkUpPA 0x0002 0x00 EnWkUpPA(7) EnWkUpPA(6) EnWkUpPA(5) EnWkUpPA(4) EnWkUpPA(3) EnWkUpPA(2) EnWkUpPA(1) EnWkUpPA(0) RegClockCfg1 0x0003 0x18 SelCkExt(1) SelCkExt(0) SelCkHi(1) SelCkHi(0) SelCkLo(1) SelCkLo(0) - FrcFastRead RegClockCfg2 0x0004 0x03 FrcEnRC15M FrcEnRC2M FrcEnRC8k FrcEnExt SelCkCR(3) SelCkCR(2) SelCkCR(1) SelCkCR(0) RegClockCfg3 0x0005 0x70 SelCkPr1(2) SelCkPr1(1) SelCkPr1(0) SelCkPr2(2) SelCkPr2(1) SelCkPr2(0) - - RegResFlg 0x0006 0x00 ResFlgPA ResFlgWD ResFlgBO ResFlgGasp ResFlgBE - - LckPwrCfg RegPrescCfg 0x0007 0x00 Presc1Clr Presc1Len Presc1SelIntCk5/3 Presc2Clr - - - - RegPresc1Val 0x0008 0xFF Presc1Val(7) Presc1Val(6) Presc1Val(5) Presc1Val(4) Presc1Val(3) Presc1Val(2) Presc1Val(1) Presc1Val(0) RegPresc2Val 0x0009 0xFF Presc2Val(7) Presc2Val(6) Presc2Val(5) Presc2Val(4) Presc2Val(3) Presc2Val(2) Presc2Val(1) Presc2Val(0) RegPADIn 0x000A 0x00 PADIn(7) PADIn(6) PADIn(5) PADIn(4) PADIn(3) PADIn(2) PADIn(1) PADIn(0) RegPADOut 0x000B 0x00 PADOut(7) PADOut(6) PADOut(5) PADOut(4) PADOut(3) PADOut(2) PADOut(1) PADOut(0) RegPAInpE 0x000C 0x00 PAInpE(7) PAInpE(6) PAInpE(5) PAInpE(4) PAInpE(3) PAInpE(2) PAInpE(1) PAInpE(0) RegPAOE 0x000D 0x00 PAOE(7) PAOE(6) PAOE(5) PAOE(4) PAOE(3) PAOE(2) PAOE(1) PAOE(0) RegPAPU 0x000E 0x00 PAPU(7) PAPU(6) PAPU(5) PAPU(4) PAPU(3) PAPU(2) PAPU(1) PAPU(0) RegPAPD 0x000F 0x00 PAPD(7) PAPD(6) PAPD(5) PAPD(4) PAPD(3) PAPD(2) PAPD(1) PAPD(0) RegPAOD 0x0010 0x00 PAOD(7) PAOD(6) PAOD(5) PAOD(4) PAOD(3) PAOD(2) PAOD(1) PAOD(0) RegPAOutCfg0 0x0011 0x00 PA3OutSel(1) PA3OutSel(0) PA2OutSel(1) PA2OutSel(0) PA1OutSel(1) PA1OutSel(0) PA0OutSel(1) PA0OutSel(0) RegPAOutCfg1 0x0012 0x00 PA7OutSel(1) PA7OutSel(0) PA6OutSel(1) PA6OutSel(0) PA5OutSel(1) PA5OutSel(0) PA4OutSel(1) PA4OutSel(0) RegPADebCfg1 0x0013 0x00 PA3DebSel(1) PA3DebSel(0) PA2DebSel(1) PA2DebSel(0) PA1DebSel(1) PA1DebSel(0) PA0DebSel(1) PA0DebSel(0) RegPADebCfg2 0x0014 0x00 PA7DebSel(1) PA7DebSel(0) PA6DebSel(1) PA6DebSel(0) PA5DebSel(1) PA5DebSel(0) PA4DebSel(1) PA4DebSel(0) Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 20 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x RegName Address Init. Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 RegPAIntEdg 0x0015 0xFF PAIntEdg(7) PAIntEdg(6) PAIntEdg(5) PAIntEdg(4) PAIntEdg(3) PAIntEdg(2) PAIntEdg(1) PAIntEdg(0) RegPBDIn 0x0016 0x00 PBDIn(7) PBDIn(6) PBDIn(5) PBDIn(4) PBDIn(3) PBDIn(2) PBDIn(1) PBDIn(0) RegPBDOut 0x0017 0x00 PBDOut(7) PBDOut(6) PBDOut(5) PBDOut(4) PBDOut(3) PBDOut(2) PBDOut(1) PBDOut(0) RegPBInpE 0x0018 0x00 PBInpE(7) PBInpE(6) PBInpE(5) PBInpE(4) PBInpE(3) PBInpE(2) PBInpE(1) PBInpE(0) RegPBOE 0x0019 0x00 PBOE(7) PBOE(6) PBOE(5) PBOE(4) PBOE(3) PBOE(2) PBOE(1) PBOE(0) RegPBPU 0x001A 0x00 PBPU(7) PBPU(6) PBPU(5) PBPU(4) PBPU(3) PBPU(2) PBPU(1) PBPU(0) RegPBPD 0x001B 0x00 PBPD(7) PBPD(6) PBPD(5) PBPD(4) PBPD(3) PBPD(2) PBPD(1) PBPD(0) RegPBOD 0x001C 0x00 PBOD(7) PBOD(6) PBOD(5) PBOD(4) PBOD(3) PBOD(2) PBOD(1) PBOD(0) RegPBOutCfg0 0x001D 0x00 PB3OutSel(1) PB3OutSel(0) PB2OutSel(1) PB2OutSel(0) PB1OutSel(1) PB1OutSel(0) PB0OutSel(1) PB0OutSel(0) RegPBOutCfg1 0x001E 0x00 PB7OutSel(1) PB7OutSel(0) PB6OutSel(1) PB6OutSel(0) PB5OutSel(1) PB5OutSel(0) PB4OutSel(1) PB4OutSel(0) RegPCDIn 0x001F 0x00 PCDIn(7) PCDIn(6) PCDIn(5) PCDIn(4) PCDIn(3) PCDIn(2) PCDIn(1) PCDIn(0) RegPCDOut 0x0020 0x00 PCDOut(7) PCDOut(6) PCDOut(5) PCDOut(4) PCDOut(3) PCDOut(2) PCDOut(1) PCDOut(0) RegPCInpE 0x0021 0x00 PCInpE(7) PCInpE(6) PCInpE(5) PCInpE(4) PCInpE(3) PCInpE(2) PCInpE(1) PCInpE(0) RegPCOE 0x0022 0x00 PCOE(7) PCOE(6) PCOE(5) PCOE(4) PCOE(3) PCOE(2) PCOE(1) PCOE(0) RegPCPU 0x0023 0x00 PCPU(7) PCPU(6) PCPU(5) PCPU(4) PCPU(3) PCPU(2) PCPU(1) PCPU(0) RegPCPD 0x0024 0x00 PCPD(7) PCPD(6) PCPD(5) PCPD(4) PCPD(3) PCPD(2) PCPD(1) PCPD(0) RegPCOD 0x0025 0x00 PCOD(7) PCOD(6) PCOD(5) PCOD(4) PCOD(3) PCOD(2) PCOD(1) PCOD(0) RegPCOutCfg0 0x0026 0x00 PC3OutSel(1) PC3OutSel(0) PC2OutSel(1) PC2OutSel(0) PC1OutSel(1) PC1OutSel(0) PC0OutSel(1) PC0OutSel(0) RegPCOutCfg1 0x0027 0x00 PC7OutSel(1) PC7OutSel(0) PC6OutSel(1) PC6OutSel(0) PC5OutSel(1) PC5OutSel(0) PC4OutSel(1) PC4OutSel(0) RegPCDebCfg1 0x0028 0x00 PC3DebSel(1) PC3DebSel(0) PC2DebSel(1) PC2DebSel(0) PC1DebSel(1) PC1DebSel(0) PC0DebSel(1) PC0DebSel(0) RegPCDebCfg2 0x0029 0x00 PC7DebSel(1) PC7DebSel(0) PC6DebSel(1) PC6DebSel(0) PC5DebSel(1) PC5DebSel(0) PC4DebSel(1) PC4DebSel(0) RegPCIntEdg 0x002A 0xFF PCIntEdg(7) PCIntEdg(6) PCIntEdg(5) PCIntEdg(4) PCIntEdg(3) PCIntEdg(2) PCIntEdg(1) PCIntEdg(0) RegGaspDIn 0x002B 0x00 GaspDIn(7) GaspDIn(6) GaspDIn(5) GaspDIn(4) GaspDIn(3) GaspDIn(2) GaspDIn(1) GaspDIn(0) RegGaspDOut 0x002C 0x00 GaspDOut(7) GaspDOut(6) GaspDOut(5) GaspDOut(4) GaspDOut(3) GaspDOut(2) GaspDOut(1) GaspDOut(0) Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 21 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x RegName Address Init. Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 RegGaspMode 0x002D 0x00 GaspTM GaspMode GaspSU GaspISP GaspDoC GaspTest - - RegDoCPM1L 0x002E 0x00 DoCPM1L(7) DoCPM1L(6) DoCPM1L(5) DoCPM1L(4) DoCPM1L(3) DoCPM1L(2) DoCPM1L(1) DoCPM1L(0) RegDoCPM1M 0x002F 0x00 - - - DoCPM1M(4) DoCPM1M(3) DoCPM1M(2) DoCPM1M(1) DoCPM1M(0) RegDoCPM2L 0x0030 0x00 DoCPM2L(7) DoCPM2L(6) DoCPM2L(5) DoCPM2L(4) DoCPM2L(3) DoCPM2L(2) DoCPM2L(1) DoCPM2L(0) RegDoCPM2M 0x0031 0x00 - - - DoCPM2M(4) DoCPM2M(3) DoCPM2M(2) DoCPM2M(1) DoCPM2M(0) RegDoCPM3L 0x0032 0x00 DoCPM3L(7) DoCPM3L(6) DoCPM3L(5) DoCPM3L(4) DoCPM3L(3) DoCPM3L(2) DoCPM3L(1) DoCPM3L(0) RegDoCPM3M 0x0033 0x00 - - - DoCPM3M(4) DoCPM3M(3) DoCPM3M(2) DoCPM3M(1) DoCPM3M(0) RegDoCDM1L 0x0034 0x00 DoCDM1L(7) DoCDM1L(6) DoCDM1L(5) DoCDM1L(4) DoCDM1L(3) DoCDM1L(2) DoCDM1L(1) DoCDM1L(0) RegDoCDM1M 0x0035 0x00 DoCDM1M(7) DoCDM1M(6) DoCDM1M(5) DoCDM1M(4) DoCDM1M(3) DoCDM1M(2) DoCDM1M(1) DoCDM1M(0) RegDoCEn 0x0036 0x00 DoCEnPM1 DoCEnPM2 DoCEnPM3 DoCEnDM1(1) DoCEnDM1(0) - - - RegDoCStat 0x0037 0x00 DoCPM1Stat DoCPM2Stat DoCPM3Stat DoCDM1Stat - - - - RegCRC16DIn 0x0038 0x00 CRC16DIn(7) CRC16DIn(6) CRC16DIn(5) CRC16DIn(4) CRC16DIn(3) CRC16DIn(2) CRC16DIn(1) CRC16DIn(0) RegCRC16L 0x0039 0x00 CRC16L(7) CRC16L(6) CRC16L(5) CRC16L(4) CRC16L(3) CRC16L(2) CRC16L(1) CRC16L(0) RegCRC16M 0x003A 0x00 CRC16M(7) CRC16M(6) CRC16M(5) CRC16M(4) CRC16M(3) CRC16M(2) CRC16M(1) CRC16M(0) RegTimersCfg 0x003B 0x00 Tim12Chain Tim34Chain Tim1AR Tim2AR Tim3AR Tim4AR Tim1SWCpt Tim3SWCpt RegTimersStart 0x003C 0x00 Tim1SWStart Tim1Pulse Tim2SWStart Tim2Pulse Tim3SWStart Tim3Pulse Tim4SWStart Tim4Pulse RegTim1Cfg 0x003D 0x00 Tim1EnPWM Tim1IntSel Tim1SelStart(2) Tim1SelStart(1) Tim1SelStart(0) Tim1SelClk(2) Tim1SelClk(1) Tim1SelClk(0) RegTim1CptCmpCfg 0x003E 0x00 Tim1CptEdg(1) Tim1CptEdg(0) Tim1CptEvtSrc(1) Tim1CptEvtSrc(0) Tim1CmpFullAct(1) Tim1CmpFullAct(0) Tim1CmpValAct(1) Tim1CmpValAct(0) RegTim1Status 0x003F 0x00 Tim1Status(7) Tim1Status(6) Tim1Status(5) Tim1Status(4) Tim1Status(3) Tim1Status(2) Tim1Status(1) Tim1Status(0) RegTim1Full 0x0040 0xFF Tim1Full(7) Tim1Full(6) Tim1Full(5) Tim1Full(4) Tim1Full(3) Tim1Full(2) Tim1Full(1) Tim1Full(0) RegTim1CmpVal 0x0041 0x00 Tim1CmpVal(7) Tim1CmpVal(6) Tim1CmpVal(5) Tim1CmpVal(4) Tim1CmpVal(3) Tim1CmpVal(2) Tim1CmpVal(1) Tim1CmpVal(0) RegTim1CptVal 0x0042 0x00 Tim1CptVal(7) Tim1CptVal(6) Tim1CptVal(5) Tim1CptVal(4) Tim1CptVal(3) Tim1CptVal(2) Tim1CptVal(1) Tim1CptVal(0) RegTim2Cfg 0x0043 0x00 Tim2EnPWM Tim2IntSel Tim2SelStart(2) Tim2SelStart(1) Tim2SelStart(0) Tim2SelClk(2) Tim2SelClk(1) Tim2SelClk(0) RegTim2CptCmpCfg 0x0044 0x00 Tim2CptEdg(1) Tim2CptEdg(0) Tim2CptEvtSrc(1) Tim2CptEvtSrc(0) Tim2CmpFullAct(1) Tim2CmpFullAct(0) Tim2CmpValAct(1) Tim2CmpValAct(0) Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 22 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x RegName Address Init. Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 RegTim2Status 0x0045 0x00 Tim2Status(7) Tim2Status(6) Tim2Status(5) Tim2Status(4) Tim2Status(3) Tim2Status(2) Tim2Status(1) Tim2Status(0) RegTim2Full 0x0046 0xFF Tim2Full(7) Tim2Full(6) Tim2Full(5) Tim2Full(4) Tim2Full(3) Tim2Full(2) Tim2Full(1) Tim2Full(0) RegTim2CmpVal 0x0047 0x00 Tim2CmpVal(7) Tim2CmpVal(6) Tim2CmpVal(5) Tim2CmpVal(4) Tim2CmpVal(3) Tim2CmpVal(2) Tim2CmpVal(1) Tim2CmpVal(0) RegTim2CptVal 0x0048 0x00 Tim2CptVal(7) Tim2CptVal(6) Tim2CptVal(5) Tim2CptVal(4) Tim2CptVal(3) Tim2CptVal(2) Tim2CptVal(1) Tim2CptVal(0) RegTim3Cfg 0x0049 0x00 Tim3EnPWM Tim3IntSel Tim3SelStart(2) Tim3SelStart(1) Tim3SelStart(0) Tim3SelClk(2) Tim3SelClk(1) Tim3SelClk(0) RegTim3CptCmpCfg 0x004A 0x00 Tim3CptEdg(1) Tim3CptEdg(0) Tim3CptEvtSrc(1) Tim3CptEvtSrc(0) Tim3CmpFullAct(1) Tim3CmpFullAct(0) Tim3CmpValAct(1) Tim3CmpValAct(0) RegTim3Status 0x004B 0x00 Tim3Status(7) Tim3Status(6) Tim3Status(5) Tim3Status(4) Tim3Status(3) Tim3Status(2) Tim3Status(1) Tim3Status(0) RegTim3Full 0x004C 0xFF Tim3Full(7) Tim3Full(6) Tim3Full(5) Tim3Full(4) Tim3Full(3) Tim3Full(2) Tim3Full(1) Tim3Full(0) RegTim3CmpVal 0x004D 0x00 Tim3CmpVal(7) Tim3CmpVal(6) Tim3CmpVal(5) Tim3CmpVal(4) Tim3CmpVal(3) Tim3CmpVal(2) Tim3CmpVal(1) Tim3CmpVal(0) RegTim3CptVal 0x004E 0x00 Tim3CptVal(7) Tim3CptVal(6) Tim3CptVal(5) Tim3CptVal(4) Tim3CptVal(3) Tim3CptVal(2) Tim3CptVal(1) Tim3CptVal(0) RegTim4Cfg 0x004F 0x00 Tim4EnPWM Tim4IntSel Tim4SelStart(2) Tim4SelStart(1) Tim4SelStart(0) Tim4SelClk(2) Tim4SelClk(1) Tim4SelClk(0) RegTim4CptCmpCfg 0x0050 0x00 Tim4CptEdg(1) Tim4CptEdg(0) Tim4CptEvtSrc(1) Tim4CptEvtSrc(0) Tim4CmpFullAct(1) Tim4CmpFullAct(0) Tim4CmpValAct(1) Tim4CmpValAct(0) RegTim4Status 0x0051 0x00 Tim4Status(7) Tim4Status(6) Tim4Status(5) Tim4Status(4) Tim4Status(3) Tim4Status(2) Tim4Status(1) Tim4Status(0) RegTim4Full 0x0052 0xFF Tim4Full(7) Tim4Full(6) Tim4Full(5) Tim4Full(4) Tim4Full(3) Tim4Full(2) Tim4Full(1) Tim4Full(0) RegTim4CmpVal 0x0053 0x00 Tim4CmpVal(7) Tim4CmpVal(6) Tim4CmpVal(5) Tim4CmpVal(4) Tim4CmpVal(3) Tim4CmpVal(2) Tim4CmpVal(1) Tim4CmpVal(0) RegTim4CptVal 0x0054 0x00 Tim4CptVal(7) Tim4CptVal(6) Tim4CptVal(5) Tim4CptVal(4) Tim4CptVal(3) Tim4CptVal(2) Tim4CptVal(1) Tim4CptVal(0) RegADCCfg1 0x0055 0x00 EnADC RunContMeas RunSinglMeas EnTempSens ADCSmplRate(2) ADCSmplRate(1) ADCSmplRate(0) ADC8bit RegADCCfg2 0x0056 0x00 ADCSelRef(1) ADCSelRef(0) ADCSelRange(1) ADCSelRange(0) ADCLowNoise - - - RegADCOut0 0x0057 0x00 ADCOut0(7) ADCOut0(6) ADCOut0(5) ADCOut0(4) ADCOut0(3) ADCOut0(2) ADCOut0(1) ADCOut0(0) RegADCOut1 0x0058 0x00 ADCBusy ADCSelSrc(2) ADCSelSrc(1) ADCSelSrc(0) StsTempSens ADCOutLSB ADCOut1(1) ADCOut1(0) RegADCOffsetL 0x0059 0x00 ADCOffsetL(7) ADCOffsetL(6) ADCOffsetL(5) ADCOffsetL(4) ADCOffsetL(3) ADCOffsetL(2) ADCOffsetL(1) ADCOffsetL(0) RegADCOffsetM 0x005A 0x04 - - - - - ADCOffsetM(2) ADCOffsetM(1) ADCOffsetM(0) RegOpAmpCfg1 0x005B 0x00 EnOpAmp EnComp OpAmpSup CompRes SelCompInt(1) SelCompInt(0) - - RegOpAmpCfg2 0x005C 0x00 OpAmpSelInpPos(1) OpAmpSelInpPos(0) OpAmpSelInpNeg(1) OpAmpSelInpNeg(0) OpAmpSelOut - - - Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 23 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x RegName Address Init. Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 RegDC-DCCfg 0x005D 0x00 EnDC-DC DC-DCLevel(1) DC-DCLevel(0) DC-DCIdle DC-DCStartSts - - - RegVLDCfg1 0x005E 0x00 EnVLD VLDRes VLDSelSrc(2) VLDSelSrc(1) VLDSelSrc(0) - - - RegVLDCfg2 0x005F 0x00 - - - VLDSelLvl(4) VLDSelLvl(3) VLDSelLvl(2) VLDSelLvl(1) VLDSelLvl(0) RegBgrCfg 0x0060 0x00 BgrEnOut NVMEnWrite - - - - - - RegInt0Sts 0x0061 0x00 Int0StsPort(0) Int0StsTim1 Int0StsPr1Ck0 Int0StsADC Int0StsDoCDM Int0StsDoCPM Int0StsGasp Int0StsPMMiss RegInt1Sts 0x0062 0x00 Int1StsPort(2) Int1StsPort(1) Int1StsTim2 Int1StsTim3 Int1StsOpAmp Int1StsPr1Ck5/3 Int1StsSPIStop Int1StsSPIStart RegInt2Sts 0x0063 0x00 Int2StsVLD Int2StsSlpCnt Int2StsPort(7) Int2StsPort(6) Int2StsPort(5) Int2StsPort(4) Int2StsPort(3) Int2StsTim4 RegInt0Msk 0x0064 0x00 Int0MskPort(0) Int0MskTim1 Int0MskPr1Ck0 Int0MskADC Int0MskDoCDM Int0MskDoCPM Int0MskGasp Int0MskPMMiss RegInt1Msk 0x0065 0x00 Int1MskPort(2) Int1MskPort(1) Int1MskTim2 Int1MskTim3 Int1MskOpAmp Int1MskPr1Ck5/3 Int1MskSPIStop Int1MskSPIStart RegInt2Msk 0x0066 0x00 Int2MskVLD Int2MskSlpCnt Int2MskPort(7) Int2MskPort(6) Int2MskPort(5) Int2MskPort(4) Int2MskPort(3) Int2MskTim4 RegInt0PostMsk 0x0067 0x00 Int0PostMskPort(0) Int0PostMskTim1 Int0PostMskPr1Ck0 Int0PostMskADC Int0PostMskDoCDM Int0PostMskDoCPM Int0PostMskGasp Int0PostMskPMMiss RegInt1PostMsk 0x0068 0x00 Int1PostMskPort(2) Int1PostMskPort(1) Int1PostMskTim2 Int1PostMskTim3 Int1PostMskOpAmp Int1PostMskPr1Ck5/3 Int1PostMskSPIStop Int1PostMskSPIStart RegInt2PostMsk 0x0069 0x00 Int2PostMskVLD Int2PostMskSlpCnt Int2PostMskPort(7) Int2PostMskPort(6) Int2PostMskPort(5) Int2PostMskPort(4) Int2PostMskPort(3) Int2PostMskTim4 RegIntPortSrc 0x006A 0x00 IntPortSrc(7) IntPortSrc(6) IntPortSrc(5) IntPortSrc(4) IntPortSrc(3) IntPortSrc(2) IntPortSrc(1) IntPortSrc(0) RegEvtSts 0x006B 0x00 - - - - Evt1StsSlpCnt Evt1StsSPI Evt1StsADC Evt0StsGasp RegEvtCfg 0x006C 0x00 Evt1PostMskSC Evt1MskSC Evt1PostMskSPI Evt1MskSPI Evt1PostMskADC Evt1MskADC Evt0PostMskGasp Evt0MskGasp RegWDCfg 0x006D 0x00 WDDis - - - - - - WDClear RegWDKey 0x006E 0x00 WDKey(7) WDKey(6) WDKey(5) WDKey(4) WDKey(3) WDKey(2) WDKey(1) WDKey(0) RegWDLdValL 0x006F 0x00 WDLdValL(7) WDLdValL(6) WDLdValL(5) WDLdValL(4) WDLdValL(3) WDLdValL(2) WDLdValL(1) WDLdValL(0) RegWDLdValM 0x0070 0x80 WDLdValM(7) WDLdValM(6) WDLdValM(5) WDLdValM(4) WDLdValM(3) WDLdValM(2) WDLdValM(1) WDLdValM(0) RegWDStatL 0x0071 0x00 WDStatL(7) WDStatL(6) WDStatL(5) WDStatL(4) WDStatL(3) WDStatL(2) WDStatL(1) WDStatL(0) RegWDStatM 0x0072 0x80 WDStatM(7) WDStatM(6) WDStatM(5) WDStatM(4) WDStatM(3) WDStatM(2) WDStatM(1) WDStatM(0) RegSCCfg 0x0073 0x00 SCDis SCStart - - - - - - RegSCLdVal0 0x0074 0x00 SCLdVal0(7) SCLdVal0(6) SCLdVal0(5) SCLdVal0(4) SCLdVal0(3) SCLdVal0(2) SCLdVal0(1) SCLdVal0(0) Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 24 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x RegName Address Init. Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 RegSCLdVal1 0x0075 0x80 SCLdVal1(7) SCLdVal1(6) SCLdVal1(5) SCLdVal1(4) SCLdVal1(3) SCLdVal1(2) SCLdVal1(1) SCLdVal1(0) RegSCLdVal2 0x0076 0x00 SCLdVal2(7) SCLdVal2(6) SCLdVal2(5) SCLdVal2(4) SCLdVal2(3) SCLdVal2(2) SCLdVal2(1) SCLdVal2(0) RegSCStat0 0x0077 0x00 SCStat0(7) SCStat0(6) SCStat0(5) SCStat0(4) SCStat0(3) SCStat0(2) SCStat0(1) SCStat0(0) RegSCStat1 0x0078 0x80 SCStat1(7) SCStat1(6) SCStat1(5) SCStat1(4) SCStat1(3) SCStat1(2) SCStat1(1) SCStat1(0) RegSCStat2 0x0079 0x00 SCStat2(7) SCStat2(6) SCStat2(5) SCStat2(4) SCStat2(3) SCStat2(2) SCStat2(1) SCStat2(0) RegSPICfg1 0x007A 0x03 SPIEn SPIMode(2) SPIMode(1) SPIMode(0) SPINegEdg SPIRTO SPIMSB1st SPIAutoStart RegSPICfg2 0x007B 0x00 SPISelSClk(1) SPISelSClk(0) SPISelSIn(1) SPISelSIn(0) - - - - RegSPIStart 0x007C 0x00 SPIStart - - - - - - - RegSPIDIn 0x007D 0x00 SPIDIn(7) SPIDIn(6) SPIDIn(5) SPIDIn(4) SPIDIn(3) SPIDIn(2) SPIDIn(1) SPIDIn(0) RegSPIDOut 0x007E 0x00 SPIDOut(7) SPIDOut(6) SPIDOut(5) SPIDOut(4) SPIDOut(3) SPIDOut(2) SPIDOut(1) SPIDOut(0) RegCacheB00 0x0280 0x00 CacheB00(7) CacheB00(6) CacheB00(5) CacheB00(4) CacheB00(3) CacheB00(2) CacheB00(1) CacheB00(0) RegCacheB01 0x0281 0x00 CacheB01(7) CacheB01(6) CacheB01(5) CacheB01(4) CacheB01(3) CacheB01(2) CacheB01(1) CacheB01(0) RegCacheB02 0x0282 0x00 CacheB02(7) CacheB02(6) CacheB02(5) CacheB02(4) CacheB02(3) CacheB02(2) CacheB02(1) CacheB02(0) RegCacheB03 0x0283 0x00 CacheB03(7) CacheB03(6) CacheB03(5) CacheB03(4) CacheB03(3) CacheB03(2) CacheB03(1) CacheB03(0) RegCacheB04 0x0284 0x00 CacheB04(7) CacheB04(6) CacheB04(5) CacheB04(4) CacheB04(3) CacheB04(2) CacheB04(1) CacheB04(0) RegCacheB05 0x0285 0x00 CacheB05(7) CacheB05(6) CacheB05(5) CacheB05(4) CacheB05(3) CacheB05(2) CacheB05(1) CacheB05(0) RegCacheB06 0x0286 0x00 CacheB06(7) CacheB06(6) CacheB06(5) CacheB06(4) CacheB06(3) CacheB06(2) CacheB06(1) CacheB06(0) RegCacheB07 0x0287 0x00 CacheB07(7) CacheB07(6) CacheB07(5) CacheB07(4) CacheB07(3) CacheB07(2) CacheB07(1) CacheB07(0) RegCacheB08 0x0288 0x00 CacheB08(7) CacheB08(6) CacheB08(5) CacheB08(4) CacheB08(3) CacheB08(2) CacheB08(1) CacheB08(0) RegCacheB09 0x0289 0x00 CacheB09(7) CacheB09(6) CacheB09(5) CacheB09(4) CacheB09(3) CacheB09(2) CacheB09(1) CacheB09(0) RegCacheB10 0x028A 0x00 CacheB10(7) CacheB10(6) CacheB10(5) CacheB10(4) CacheB10(3) CacheB10(2) CacheB10(1) CacheB10(0) RegCacheB11 0x028B 0x00 CacheB11(7) CacheB11(6) CacheB11(5) CacheB11(4) CacheB11(3) CacheB11(2) CacheB11(1) CacheB11(0) RegCacheB12 0x028C 0x00 CacheB12(7) CacheB12(6) CacheB12(5) CacheB12(4) CacheB12(3) CacheB12(2) CacheB12(1) CacheB12(0) RegCacheB13 0x028D 0x00 CacheB13(7) CacheB13(6) CacheB13(5) CacheB13(4) CacheB13(3) CacheB13(2) CacheB13(1) CacheB13(0) Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 25 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x RegName Address Init. Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 RegCacheB14 0x028E 0x00 CacheB14(7) CacheB14(6) CacheB14(5) CacheB14(4) CacheB14(3) CacheB14(2) CacheB14(1) CacheB14(0) RegCacheB15 0x028F 0x00 CacheB15(7) CacheB15(6) CacheB15(5) CacheB15(4) CacheB15(3) CacheB15(2) CacheB15(1) CacheB15(0) RegCacheB16 0x0290 0x00 CacheB16(7) CacheB16(6) CacheB16(5) CacheB16(4) CacheB16(3) CacheB16(2) CacheB16(1) CacheB16(0) RegCacheB17 0x0291 0x00 CacheB17(7) CacheB17(6) CacheB17(5) CacheB17(4) CacheB17(3) CacheB17(2) CacheB17(1) CacheB17(0) RegCacheB18 0x0292 0x00 CacheB18(7) CacheB18(6) CacheB18(5) CacheB18(4) CacheB18(3) CacheB18(2) CacheB18(1) CacheB18(0) RegCacheB19 0x0293 0x00 CacheB19(7) CacheB19(6) CacheB19(5) CacheB19(4) CacheB19(3) CacheB19(2) CacheB19(1) CacheB19(0) RegCacheB20 0x0294 0x00 CacheB20(7) CacheB20(6) CacheB20(5) CacheB20(4) CacheB20(3) CacheB20(2) CacheB20(1) CacheB20(0) RegCacheB21 0x0295 0x00 CacheB21(7) CacheB21(6) CacheB21(5) CacheB21(4) CacheB21(3) CacheB21(2) CacheB21(1) CacheB21(0) RegCacheB22 0x0296 0x00 CacheB22(7) CacheB22(6) CacheB22(5) CacheB22(4) CacheB22(3) CacheB22(2) CacheB22(1) CacheB22(0) RegCacheB23 0x0297 0x00 CacheB23(7) CacheB23(6) CacheB23(5) CacheB23(4) CacheB23(3) CacheB23(2) CacheB23(1) CacheB23(0) RegCacheB24 0x0298 0x00 CacheB24(7) CacheB24(6) CacheB24(5) CacheB24(4) CacheB24(3) CacheB24(2) CacheB24(1) CacheB24(0) RegCacheB25 0x0299 0x00 CacheB25(7) CacheB25(6) CacheB25(5) CacheB25(4) CacheB25(3) CacheB25(2) CacheB25(1) CacheB25(0) RegCacheB26 0x029A 0x00 CacheB26(7) CacheB26(6) CacheB26(5) CacheB26(4) CacheB26(3) CacheB26(2) CacheB26(1) CacheB26(0) RegCacheB27 0x029B 0x00 CacheB27(7) CacheB27(6) CacheB27(5) CacheB27(4) CacheB27(3) CacheB27(2) CacheB27(1) CacheB27(0) RegCacheB28 0x029C 0x00 CacheB28(7) CacheB28(6) CacheB28(5) CacheB28(4) CacheB28(3) CacheB28(2) CacheB28(1) CacheB28(0) RegCacheB29 0x029D 0x00 CacheB29(7) CacheB29(6) CacheB29(5) CacheB29(4) CacheB29(3) CacheB29(2) CacheB29(1) CacheB29(0) RegCacheB30 0x029E 0x00 CacheB30(7) CacheB30(6) CacheB30(5) CacheB30(4) CacheB30(3) CacheB30(2) CacheB30(1) CacheB30(0) RegCacheB31 0x029F 0x00 CacheB31(7) CacheB31(6) CacheB31(5) CacheB31(4) CacheB31(3) CacheB31(2) CacheB31(1) CacheB31(0) RegCacheCfg1 0x02A0 0x00 - - CacheRow(5) CacheRow(4) CacheRow(3) CacheRow(2) CacheRow(1) CacheRow(0) RegCacheCfg2 0x02A1 0x80 NVMFastProg - - - - CacheSector(2) CacheSector(1) CacheSector(0) RegTrimOsc15M 0x02A2 0x80 TrimOsc15M(7) TrimOsc15M(6) TrimOsc15M(5) TrimOsc15M(4) TrimOsc15M(3) TrimOsc15M(2) TrimOsc15M(1) TrimOsc15M(0) RegTrimOsc2M 0x02A3 0x80 TrimOsc2M(7) TrimOsc2M(6) TrimOsc2M(5) TrimOsc2M(4) TrimOsc2M(3) TrimOsc2M(2) TrimOsc2M(1) TrimOsc2M(0) RegTrimVLD 0x02A4 0x08 - - - - TrimVLD(3) TrimVLD(2) TrimVLD(1) TrimVLD(0) RegStsCStart 0x02A5 0x39 - - StsCSReson StsCSXtal StsCSPad StsCSRC8k StsCSRC2M StsCSRC15M RegName Address Init. Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 RegStsEnOsc 0x02A6 0x06 - - - StsEnReson StsEnXtal StsEnRC8k StsEnRC2M StsEnRC15M RegCkSw1 0x02A7 0x12 CkSwSelX CkSwStsX CkSwSelHi(2) CkSwSelHi(1) CkSwSelHi(0) CkSwStsHi(2) CkSwStsHi(1) CkSwStsHi(0) RegCkSw2 0x02A8 0x24 - - CkSwSelLo(2) CkSwSelLo(1) CkSwSelLo(0) CkSwStsLo(2) CkSwStsLo(1) CkSwStsLo(0) Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 26 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 2.6 PORT TERMINAL CONNECTION REFERENCE TABLE chip Nbr 1 2 3 4 5 6 7 8 9 10 11 12 Name VSS2 VSS PB2 PB3 PB4 PB5 PB6 PB7 PA0 PC0 PA1 PC1 13 PA2 14 15 16 17 18 PC2 PA3 PC3 VREG PA4 19 PC4 20 21 22 23 24 25 26 27 28 29 30 31 32 TM PA5 PC5 PC6 PA6 PA7 PC7 PB0 PB1 VSUP VSUP2 DCDC VSSDCDC Base SUP SUP IO IO IO IO IO IO IO IO IO IO IO IO IO IO SUP IO IO IN IO IO IO IO IO IO IO IO SUP SUP SUP SUP IRQ ADC Reset & WkUp VREF VLD OPAMP SPI GASP CLOCK Timer clock Timer start PWM high FrqOut drive VSS protection pad to reduce double noise bond main VSS SCLK t2ck0_in start2_in t2ck1_in start3_in sig sig sig sig sig sig sig sig sig sig t3ck0_in start4_in sig t4ck0_in start5_in t4ck1_in start6_in sig sig sig SOUT GASP-SCK GASP-SIO PAIRQ0 PCIRQ0 PAIRQ1 PCIRQ1 ADC0 Rst_Wkup0 ADC1 ADC2 Rst_Wkup1 ADC3 t1ck0_in start1_in VLD VLD OPA_Out OPA_Out PAIRQ2 ADC4 Rst_Wkup2 Vref_ADC VLD OPA_INM PAIRQ2 ADC5 PAIRQ3 ADC6 Rst_Wkup3 PCIRQ3 ADC7 use external Capacitor PAIRQ4 Rst_Wkup4 SIN SOUT OPA_INM SOUT OPA_INP OPA_INP SIN XIN XOUT ExtCk PCIRQ4 HD HD HD HD HD HD HD HD sig sig GASP-Sel PAIRQ5 PCIRQ5 PCIRQ6 PAIRQ6 PAIRQ7 PCIRQ7 Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 Rst_Wkup5 Rst_Wkup6 Vref_out Rst_Wkup7 VLD VLD VLD VLD SCLK SCLK SOUT t1ck1_in start7_in t3ck1_in SIN VSUP protection pad to reduce noise DCDC Coil connection in case of DCDC Version, open (not bonded, if no DCDC) VSS for DCDC, not bonded for non DCDC versions 27 www.emmicroelectronic.com sig sig sig sig sig sig sig sig HD HD HD HD HD HD HD EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 2.7 TSSOP PACKAGE PINOUT CIRCUIT WITHOUT DC-DC AND S08 20-Lead TSSOP 4.40mm body EM6819FX-BXXX 24-Lead TSSOP 4.40mm body EM6819FX-BXXX 28-LeadTSSOP 4.40mm body EM6819FX-BXXX IO 1 PB5 PB4 28 IO/SOUT IO/GASP-CK 2 PB6 PB3 27 IO IO/GASP-DIO 3 PB7 PB2 26 IO/SCLK IO 1 PB5 PB4 24 IO/SOUT IO/GASP-CK 2 PB6 PB3 23 IO IO/GASP-DIO 3 PB7 PB2 22 IO/SCLK 4 PA0 VSS 21 5 PA1 VSUP 20 IO/Tim/Rst1/ VLD/ADC2/OPA-Out PC7 19 IO/Tim PA7 18 1 PB4 PB3 20 IO IO 2 PB5 PB2 19 IO/SCLK IO/GASP-CK 3 PB6 VSS 18 IO/GASP-DIO 4 PB7 VSUP 17 5 PA1 IO/SIN/SOUT/Tim/Rst2/ ADC4/VLD/OPA-INM 6 PA2 IO/SOUT/Rst7/ VLD IO/SOUT/ ADC5/OPA-INM 7 PC2 PA6 17 IO/SCLK/Rst6/ Vref/VLD IO/Tim/Rst3/ ADC6/OPA-INP 8 PA3 9 Vreg TM 12 GASP-Sel 10 PA4 PC4 11 IO/ExtCK/ Xout PA0 VSS 25 IO/ ADC1 5 PC0 VSUP 24 IO/Tim/Rst1/ VLD/ADC2/OPA-Out PB1 23 IO IO/Tim/ VLD/ADC3/OPA-Out 6 PC1 PB0 22 IO/SIN IO/SIN/SOUT/Tim/Rst2/ ADC4/VLD/OPA-INM 7 PA2 PC7 21 IO/Tim IO/SOUT/ ADC5/OPA-INM 8 PC2 PA7 20 IO/SOUT/Rst7/ VLD IO/Tim/Rst3/ ADC6/OPA-INP 9 PA3 PC6 16 IO/SCLK/Tim/ VLD 10 Vreg PC5 15 IO/ VLD IO/SIN/Rst4/ Xin 11 PA4 PA5 14 IO/Rst5/ IO/ExtCK/ Xout 12 PC4 TM 13 IO/Tim/Rst1/ VLD/ADC2/OPA-Out 6 PA1 IO/Tim/ VLD/ADC3/OPA-Out 7 PC1 IO/SIN/SOUT/Tim/Rst2/ ADC4/VLD/OPA-INM 8 PA2 IO/SOUT/ ADC5/OPA-INM 9 PC2 IO/Tim/Rst3/ ADC6/OPA-INP 10 PA3 PA6 19 IO/SCLK/Rst6/ Vref/VLD IO/Tim/ ADC7/OPA-INP 11 PC3 PC6 18 IO/SCLK/Tim/ VLD 12 Vreg PC5 17 IO/ VLD IO/SIN/Rst4/ Xin 13 PA4 PA5 16 IO/Rst5/ IO/ExtCK/ Xout 14 PC4 TM 15 GASP-Sel 1 PB4 PB2 16 IO/GASP-CK 2 PB6 VSS 15 IO/GASP-DIO 3 PB7 VSUP 14 PA2 IO/Tim/Rst3/ ADC6/OPA-INP 6 PA3 7 Vreg IO/SIN/Rst4/ Xin 8 PA4 Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 IO/SOUT 1 PB4 PB2 16 IO/GASP-CK 2 PB6 VSS 15 VSUP 14 IO/GASP-DIO 3 PB7 PA7 13 IO/SOUT/Rst7/ VLD IO/Tim/Rst1/ VLD/ADC2/OPA-Out 4 PA1 PA6 12 IO/SCLK/Rst6/ Vref/VLD IO/SIN/SOUT/Tim/Rst2/ ADC4/VLD/OPA-INM 5 PA2 PC6 11 IO/SCLK/Tim/ VLD IO/SOUT/ ADC5/OPA-INM 6 PC2 GASP-Sel IO/Tim/Rst3/ ADC6/OPA-INP 7 PA3 TM 10 PC4 9 PA6 15 IO/SCLK/Rst6/ Vref/VLD PC6 14 IO/SCLK/Tim/ VLD PC5 13 IO/ VLD IO/ExtCK/ Xout 8 28 8-Lead SOIC-150 EM6819FX-BXXX Vreg IO/SCLK PA6 13 IO/SCLK/Rst6/ Vref/VLD PC6 12 IO/SCLK/Tim/ VLD TM 11 PC4 10 PA4 9 IO/GASP-CK 1 PB6 VSS 8 IO/GASP-DIO 2 PB7 VSUP 7 IO/SIN/SOUT/Tim/Rst2/ ADC4/VLD/OPA-INM 3 PA2 PA6 6 IO/SCLK/Rst6/ Vref/VLD 4 Vreg TM 5 GASP-Sel GASP-Sel IO IO/SIN/Rst4/ www.emmicroelectronic.com EM6819 5 IO/SCLK EM6819 IO/SIN/SOUT/Tim/Rst2/ ADC4/VLD/OPA-INM EM6819 PA1 IO/SOUT/Rst7/ VLD GASP-Sel 16-Lead TSSOP 4.40mm body EM6819FX-BXX5 EM6819FX-BXX6 IO/SOUT 4 IO/SIN/Rst4/ Xin PA7 16 Note: depending on the family type Bxxx not all terminal mappings may be available 16-Lead TSSOP 4.40mm body EM6819FX-BXX0 EM6819FX-BXX4 IO/Tim/Rst1/ VLD/ADC2/OPA-Out EM6819 4 IO/Tim/Rst0/ ADC0 EM6819 IO/Tim/Rst0/ ADC0 EM6819 IO/SOUT EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 2.8 TSSOP PACKAGE PINOUT CIRCUIT WITH DC-DC 20-Lead TSSOP 4.40mm body EM6819FX-AXX0 28-Lead TSSOP 4.40mm body EM6819FX-AXXX IO/SOUT 1 PB4 PB2 28 IO 2 PB5 VSS 27 IO/GASP-CK 3 PB6 VSS2 26 IO/SCLK VSS protect IO/SCLK 1 PB2 VSS 20 IO/SOUT 2 PB4 VSS2 19 VSSDCDC 18 IO/GASP-CK 3 PB6 IO/GASP-DIO 4 PB7 IO/SOUT IO/SOUT PB7 VSSDCDC 25 IO/Tim/Rst0/ ADC0 5 PA0 DCDC 24 IO/Tim/Rst1/ VLD/ADC2/OPA-Out 5 PA1 VSUP2 23 IO/SIN/SOUT/Tim/Rst2/ ADC4/VLD/OPA-INM 6 PA2 IO/SOUT/ ADC5/OPA-INM 7 PC2 IO/Tim/Rst3/ ADC6/OPA-INP 8 9 6 PC0 IO/Tim/Rst1/ VLD/ADC2/OPA-Out 7 PA1 IO/Tim/ VLD/ADC3/OPA-Out 8 PC1 IO/SIN/SOUT/Tim/Rst2/ ADC4/VLD/OPA-INM IO/SOUT/ ADC5/OPA-INM 9 PA2 10 PC2 VSUP protect VSUP 22 PA7 21 IO/SOUT/Rst7/ VLD PA6 20 IO/SCLK/Rst6/ Vref/VLD PC6 19 IO/SCLK/Tim/ VLD IO/Tim/Rst3/ ADC6/OPA-INP 11 PA3 PC5 18 IO/ VLD IO/Tim/ ADC7/OPA-INP 12 PC3 PA5 17 IO/Rst5/ 13 Vreg TM 16 IO/SIN/Rst4/ Xin 14 PA4 PC4 15 IO/SIN/Rst4/ Xin DCDC 17 EM6819 DCDC 4 EM6819 DCDC IO/GASP-DIO IO/ ADC1 VSS protect VSUP2 16 VSUP protect VSUP 15 PA6 14 IO/SCLK/Rst6/ Vref/VLD PA3 PC6 13 IO/SCLK/Tim/ VLD Vreg TM 12 10 PA4 PC4 11 GASP-Sel IO/ExtCK/ Xout GASP-Sel IO/ExtCK/ Xout 16-Lead TSSOP 4.40mm body EM6819FX-AXXX Note: depending on the family type Axxx not all terminal mappings may be available 1 VSS VSS2 16 IO/GASP-CK 2 PB6 VSSDCDC 15 IO/GASP-DIO 3 PB7 IO/Tim/Rst1/ VLD/ADC2/OPA-Out 4 PA1 IO/SIN/SOUT/Tim/Rst2/ ADC4/VLD/OPA-INM 5 PA2 IO/SOUT/ ADC5/OPA-INM 6 PC2 IO/Tim/Rst3/ ADC6/OPA-INP 7 PA3 8 Vreg VSS protect IO/SOUT EM6819 DCDC Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 DCDC 14 VSUP2 13 VSUP protect VSUP 12 PA6 11 IO/SCLK/Rst6/ Vref/VLD PC6 10 IO/SCLK/Tim/ VLD TM 29 9 GASP-Sel www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 2.9 QFN PACKAGES WITH AND WITHOUT DCDC 32 Lead QFN 5x5mm body EM6819FX-AXXX PB6 PB4 PB2 VSS VSS2 PB6 PB5 PB4 PB3 PB2 VSS VSS2 20 Lead QFN 4x4mm body EM6819FX-AXXX 20 19 18 17 16 32 31 30 29 28 27 26 PC2 4 PA3 EM6819 DCDC 13 12 VREG 8 9 PC0 3 22 VSUP PA1 4 21 PB1 PC1 5 20 PB0 PA2 6 19 PC7 PC2 7 18 PA7 PA3 8 17 PA6 VSUP2 VSUP PA6 EM6819 DCDC 9 10 11 12 13 14 15 16 10 PC6 7 PA4 6 TM 11 PC4 5 VSUP2 DC-DC PC6 3 23 PC5 PA2 DCDC 2 PA5 14 24 PA0 TM 2 PB7 PC4 PA1 1 VSS_ DC-DC PA4 15 PC3 1 25 VREG PB7 VSS_ DC-DC with DCDC without DCDC Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 PB3 19 18 VSS PB4 20 PB2 PB5 20 Lead QFN 4x4mm body EM6819FX-BXXX 17 16 PB6 1 15 VSUP PB7 2 14 PB0 PA1 3 13 PA6 PA2 4 PC2 5 EM6819 12 9 10 TM PA3 8 PC4 7 PA4 6 Vreg 11 30 PC6 PC5 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 3. CPU CORE CR816 The full detail of the used CoolRISC 816L core is described in [1]. A brief overview of its highlights is given below. 8-bits RISC register-memory processor based on a Harvard architecture 3 stage pipeline (no delay slots or branch delays) 176 Kbytes max Program Memory size (64 KInstruction, 22 bit wide) 64 Kbytes max Data Memory size (organized in 256 x 256 Kbytes pages) 8 max hardware subroutines and unlimited software subroutines 8 bit x 8 bit hardware multiplier 5 addressing modes o direct addressing o indexed addressing with immediate offset o indexed addressing with register offset o indexed addressing with postincrementation of the offset o indexed addressing with predecrementaion of the offset 16 CPU internal registers (Accu, general purpose, Index, offset, status) Unlike most RISC processors, the CR816L provides instructions which can perform arithmetic and logical operations with operands stored either in the data memory or in internal registers. Similarly to classic 8-bit processors, the CR816L architecture provides an accumulator located at the ALU output that stores the last ALU result. All arithmetic operations support both signed and unsigned operations. The Instruction Set is composed of Branch Instructions Transfer Instructions Arithmetic and Logical Instructions Special Instructions 3.1 PM_MISS FUNCTION (FLASH READ MONITOR) In extreme conditons (very low temperature and ck_hi > 15MHz) the NVM time access could be longer than a CPU cycle. In this case a pm_miss is generated, meaning that the CPU will automatically wait an additional cycle before to fetch the current instruction read in the NVM. Doing so, it guaranttees that the system never fails even if the CPU is running faster than the NVM. Interrupt of priority 0 Int0StsPmMiss is generated on each pm_miss. Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 31 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 4. NVM MEMORY 4.1 INTRODUCTION The circuits Non Volatile Memory (NVM) is used to store the application software but it may also be used to store data (constants or variables). The same physical memory area is shared between the instruction code and the data’s. The boundary in this general purpose NMV memory (GPNVM) between the instruction code and the data’s is not fixed in detail by hardware but given by the linker after compilation. The data read access in NVM (see chapter “Read data in NVM”) is executed as a simple register access. The data write access in NVM (see chapter “Write data in NVM”) is not executed with a simple MOVE. It is necessary to store the data’s in an intermediate memory called RAM cache and to execute an API sub-routine in the ROM. st NVM data read access needs 2 CPU cycles, 1 the read instruction followed with an NVM data access. During the date access phase the CPU is in a wait state. The CR816 instruction is a 22 bits wide bus. When the CPU reads the NVM through the data’s bus, 22 bits are read but only 2 bytes (16-bits) are accessed (the other 6 bits are used for verification). Note: If the additional 6 bits are not equal to 0x3F, the read access to the previous read pair of bytes is denied. The system interprets this access as a forbidden access to the program memory area (code protection feature) Instruction read by CPU is straight foreward; all instruction read take 1 CPU cycle. 4.2 NVM ARCHITECTURE The NVM is divided in 6 sectors, each sector is divided in 64 rows and each row contains either 16 instructions or 32 data bytes. A single row shall not share instructions and data bytes. From the CPU data bus interface point of view, the NVM is mapped from address 0x4000 to 0x6FFF as shown in the following diagram. Figure 3, NVM architecture 0x6FFF SECTOR 5 0x6800 0x67FF SECTOR 4 0x6000 0x5FFF SECTOR 3 0x5800 0x57FF row 63 SECTOR 2 row 62 0x5000 0x4FFF row i SECTOR 1 0x4800 0x47FF row 1 row 0 SECTOR 0 0x4000 Instruction 0 6 non used bits RegCacheB[2j+1] Instruction 1 Instruction j Instruction 14 Instruction 15 RegCacheB[2j] Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 32 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x Note: In the datasheet all the NVM informations are referring to all the devices except EM6819FX-XX5 / -XX6. In the case of EM6819FX-XX5 / -XX6 the sector 3 and its mapping address need considered instead of the sector 5. All devices except EM6819FX-XX5 / -XX6: The row 63 and 62 of sector 5 is reserved for trimming word and EM6819 production tracking code. Write access in this row is denied. The row 61 of sector 5 is used for NVM memory dump and external read/write access protection. Devices EM6819FX-XX5 / -XX6: The row 63 and 62 of sector 3 is reserved for trimming word and EM6819 production tracking code. Write access in this row is denied. The row 61 of sector 3 is used for NVM memory dump and external read/write access protection. 4.3 RAM CACHE The RAM cache is an image of 1 row of the NVM. The write access to the NVM is done row by row. After selecting the row and the sector to access, the RAM cache contents are copied in the selected row by the CPU executing a CALL of the API sub-routine in the ROM. The RAM cache is mapped as follows: DM address (HEX) 0x0280 0x0281 0x0282 0x0283 0x0284 0x0285 0x0286 0x0287 0x0288 0x0289 0x028A 0x028B 0x028C 0x028D 0x028E 0x028F 0x0290 0x0291 0x0292 0x0293 0x0294 0x0295 0x0296 0x0297 0x0298 0x0299 0x029A 0x029B 0x029C 0x029D 0x029E 0x029F RAM cache byte RegCacheB00 RegCacheB01 RegCacheB02 RegCacheB03 RegCacheB04 RegCacheB05 RegCacheB06 RegCacheB07 RegCacheB08 RegCacheB09 RegCacheB10 RegCacheB11 RegCacheB12 RegCacheB13 RegCacheB14 RegCacheB15 RegCacheB16 RegCacheB17 RegCacheB18 RegCacheB19 RegCacheB20 RegCacheB21 RegCacheB22 RegCacheB23 RegCacheB24 RegCacheB25 RegCacheB26 RegCacheB27 RegCacheB28 RegCacheB29 RegCacheB30 RegCacheB31 4.4 WRITE DATA IN NVM Only erased memory space can be written. Write applies always to one full row. Erase and write operation are handled by API-subroutines. Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 33 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 4.4.1 ROW AND SECTOR SELECTION Write access is done row by row (32 bytes at a time). The row selection needs to be done before calling the API subroutine. RegCacheCfg1[5:0] in address 0x02A0 is the row pointer from, it may take values from 0x00 and 0x3F (row 63). RegCacheCfg2[2:0] in address 0x02A1 is the sector pointer, it may take values from 0x00 and 0x05. 4.4.2 FAST/SLOW OPERATION In low voltage conditions (VSUPLow in register RegSysCfg1 = ‘1’) all erase and write accesses to the NVM should be done using the corresponding erase_x_slow_x and write_x_slow_x API subroutine. The ‘slow’ API routines will take more time to execute but will draw instantly less current. 4.4.3 ERASE Erase is a mandatory step before write. The NVM erase state is high, write state low. Only Row erase or sector erase are allowed, below table summaries the available API routines sub-routines erase_sector_apl erase_sector_slow_apl erase_row_apl erase_row_slow_apl Description Erase the selected sector [4:0]. Erase sector 5 is denied. Erase the selected sector [4:0] in slow mode. Erase sector 5 is denied. Erase the selected row [63:0] in the selected sector [5:0]. Erase row 63 & 62 in sector 5 is denied. Erase the selected row [63:0] in the selected sector [5:0] in slow mode. Erase row 63 & 62 in sector 5 is denied. Duration 2 ms 3 ms 2 ms 3 ms Accessing above routines will use the sector and row pointers as defined in RegCacheCfg2,1 4.4.4 WRITE Before writing a specific row, the RAM cache needs to get the new data, the sector and row pointers need to be set according to the desired NVM location, and once everything setup, the CPU may call one of the below listed API subroutines to write the NVM row. Write access is row by row only. Write_row_x API routines include also the erase row. It is therefore not necessary to erase the row before. Write_only_x routines do not include the erase. These routines may only be used if the addressed row was erased earlier. sub-routines Description Duration Erase and write the selected row [63:0] in the write_row_apl selected sector [5:0]. 3 ms Access row 63 & 62 in sector 5 is denied. Erase and write the selected row [63:0] in the write_row_slow_apl selected sector [5:0] in slow mode. 4.5 ms Access row 63 & 62 in sector 5 is denied. Only write the selected row [63:0] in the selected write_only_apl sector [5:0]. 1 ms Write row 63 & 62 in sector 5 is denied. Only write the selected row [63:0] in the selected write_only_slow_apl sector [5:0] in slow mode. 1.5 ms Write row 63 & 62 in sector 5 is denied. Note: It is not allowed to re-write more a given row without prior erase Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 34 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 4.5 ROW 61 SECTOR 5 It is possible to protect the NVM against undesired external access through the GASP interface. There are two kind of protection: Lock: No code or data modification from GASP are allowed; Sector and row erase, write_row and write_only are impossible. Specific GASP reads remain possible in specific user authorized areas. TLock: Same as Lock but in addition: It’s impossible to analyse the NVM data over the GASP interface even with the factory test modes. TLock and Lock are bytes store in row 61 of sector 5. TLock is at address 0x6FBF (RegCacheB31) and 0x6FBE (RegCacheB30). They are active (NVM protected) when they are equal to 0x4E. As mentioned above, it is possible to open external access (GASP access) in read mode in a part of the NVM. The start and stop address of this window is stored in the row 61 of sector 5. The stop and start address are mapped as follows: Limit DM address RAM cache Start address MSB 0x6FBD RegCacheB29 Start address LSB 0x6FBC RegCacheB28 Stop address MSB 0x6FBB RegCacheB27 Stop address LSB 0x6FBA RegCacheB26 The rest of the row 61 of sector 5 is reserved and shall not be accessed by the user. 4.6 ROW 62 SECTOR 5 The row 62 of sector 5 contains different trimming values that are not copied automatically after reset but available to the user. The structure of this row is as follows: DM Address Mapped in RAM cache Function 0x6FDF:D2 RegCacheB31:16 Reserved 0x6FD1 RegCacheB17 Contains MSB[10:8] of ADC offset trim with range 3/8 0x6FD0 RegCacheB16 Contains LSB[7:0] of ADC offset trim with range 3/8 0x6FCF RegCacheB15 Contains MSB[10:8] of ADC offset trim with range 4/8 0x6FCE RegCacheB14 Contains LSB[7:0] of ADC offset trim with range 4/8 0x6FCD RegCacheB13 Contains MSB[10:8] of ADC offset trim with range 6/8 0x6FCC RegCacheB12 Contains LSB[7:0] of ADC offset trim with range 6/8 0x6FCB RegCacheB11 Contains MSB[10:8] of ADC offset trim with range 8/8 0x6FCA RegCacheB10 Contains LSB[7:0] of ADC offset trim with range 8/8 0x6FC9 RegCacheB9 Contains MSB[10:8] of ADC offset using temperature sensor 0x6FC8 RegCacheB8 Contains LSB[7:0] of ADC offset using temperature sensor 0x6FC7:C6 RegCacheB7:6 Reserved 0x6FC5 RegCacheB5 Contains MSB[10:8] of temperature sensor result at 60°C 0x6FC4 RegCacheB4 Contains LSB[7:0] of temperature sensor result at 60°C 0x6FC3 RegCacheB3 Contains MSB[10:8] of temperature sensor result at 25°C 0x6FC2 RegCacheB2 Contains LSB[7:0] of temperature sensor result at 25°C 0x6FC1 RegCacheB1 Contains RC 15MHz trimming value at 60°C 0x6FC0 RegCacheB0 Contains RC 2MHz trimming value at 60°C The user can not update the values in sector 5 row 62, write access is denied. 4.6.1 TEMPERATURE TOLERANCE Above calibration values are measured under the following temperature tolerances: Nominal temperature Tolerance 25°C -3°C / +5°C 60°C +/- 3°C Note: These tolerances have no influence on the RC temperature compensation procedure. It depends only on the linearity of the RC trim and temperature sensor. Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 35 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 4.7 ROW 63 SECTOR 5 The row 63 of sector 5 contains the different trimming values used by the system to position the device at power-up and after each reset. It contains also one EM6819 production tracking code and a CRC code of the row to check at any time the data integrity of this row.. The structure of this row is as follows: DM Address Mapped in RAM cache Function 0x6FFF:FE RegCacheB31:30 Reserved 0x6FFD RegCacheB29 Contains RC 15MHz oscillator trimming byte @ 25°C 0x6FFC RegCacheB28 Contains RC 2MHz oscillator trimming byte @ 25°C 0x6FFB:FA RegCacheB27:26 Reserved 0x6FF9 RegCacheB25 Contains VLD trimming value 0x6FF8:F3 RegCacheB24:19 Reserved 0x6FF2:F1 RegCacheB18:17 CRC calculated on 29:19,14 0x6FF0:EB RegCacheB16:11 Reserved 0x6FEA:E4 RegCacheB10:4 EM6819 production tracking code 0x6FE3:E0 RegCacheB3:0 Reserved The user can not update the values in sector 5 row 63 & 62, write access is denied. Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 36 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 4.8 READ DATA IN NVM Read access to NVM memory is done like a register read access. However only data values may be read, any access to instruction code through the data memory bus in read mode is denied. The limit between data values and instruction code is defined by the linker during compilation. As it is mentioned above, the NVM is mapped in possible data memory areas as follows: Sector 0 1 2 3 4 5 DM address (HEX) 0x4000 to 0x47FF 0x4800 to 0x4FFF 0x5000 to 0x57FF 0x5800 to 0x5FFF 0x6000 to 0x67FF 0x6800 to 0x6FFF When NVM is accessed through the data memory bus, the execution of software is stopped during one cycle (wait state) as the data memory is shared with program memory. Reading NVM accesses always 22 bits split in three elements (2 bytes and 6bits). The two bytes are stored in a buffer; the 6 additional bits discarded. If this pair of bytes is accessed successively, the data memory buffer is read directly and the NVM is not accessed (no wait cycle). 4.9 ROW TO CACHE Figure 4, Row to Cache flowchart When the user wants to change one byte or even one bit in the NVM, he has to write the entire row where the modification has to be done. To simplify this procedure, a sub-routine able to dump one full row to the RAM chache exists: nvm_to_cache_apl. The user has to specify the row (RegCacheCfg1) and the sector (RegCacheCfg2) pointers. After modifying the byte or the bit directly in the RAM cache he can write it’s contents back into the NVM using sub-routine write_row_apl. Select the row RegCacheCfg1[5:0] Select the sector RegCacheCfg2[2:0] Dump NVM row into RAM cache Sub_routine: nvm_to_cache_apl Modify the RAM cache content Write RAM cache in NVM back Sub_routine: write_row_apl Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 37 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 4.9.1 NVM CONFIGURATION REGISTERS 0x02A0 Bits Name 7:6 5:0 CacheRow RegCacheCfg1 Type ResVal NI RW 0x00 ResSrc ResSys NVM Row Cache Configuration - 1 Description Not implemented NVM Row Cache: Row number of Sector (CacheSector) 0x02A1 RegCacheCfg2 NVM Row Cache Configuration - 2 Bits Name Type ResVal ResSrc Description 7 NVMFastProg RW 1 ResSys NVM fast programming mode 2:0 CacheSector RW '000' ResSys NVM Row Cache: Sector number Note: The bit NVMFAstProg is automatically set in the ROM API routine. It is set to ‘0’ automatically when a slow operation is called, otherwise it is set to ‘1’. 0x0280 to 0x029F Bits Name 7:0 CacheB00 … 7:0 CacheB31 RegCacheB00 to RegCacheB31 Type ResVal RW 0x00 … … RW 0x00 Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 ResSrc ResSys … ResSys 38 NVM Row Cache Byte-0 to NVM Row Cache Byte-31 Description NVM Row Cache Byte-0 … NVM Row Cache Byte-31 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 5. CRC CHECK 5.1 CRC CHECK ON PROGRAM AREA It is possible, at any time, to check the content of the NVM by calculating the CRC on the program memory. A subroutine dedicated for this procedure exists: calc_crc_code_apl. The start and stop address of the area to check shall be given as parameter to the sub-routine as follows: Parameter Location (CPU Index registers) CRCStartAddrMSB r3 CRCStartAddrLSB r2 CRCStopAddrMSB r1 CRCStopAddrLSB r0 CRCStopAddr shall be higher to CRCStartAddr otherwise the routine fails and the result is not guaranteed. The full NVM memory range in program memory area is mapped as follows: Sector PM address (HEX) 0 0x0000 to 0x03FF 1 0x0400 to 0x07FF 2 0x0800 to 0x0BFF 3 0x0C00 to 0x0FFF 4 0x1000 to 0x13FF 5 0x1400 to 0x17FF The CRC made on program memory checks all the content of the NVM including the 6 additional bits that are not accessed through the data memory bus. Note: The user can make a CRC on the full NVM including the row 63 & 62 of sector 5. But in this case the CRC will not be constant between different devices. 5.2 CRC CHECK ON DATA AREA It is possible, at any time, to check the content of the NVM by calculating the CRC on the data memory area. A subroutine dedicated for this procedure exists: calc_crc_code_apl. The start and stop address of the area to check shall be given as parameter to the sub-routine as follows: Parameter Location (CPU Index registers) CRCStartAddrMSB r3 CRCStartAddrLSB r2 CRCStopAddrMSB r1 CRCStopAddrLSB r0 CRCStopAddr shall be higher to CRCStartAddr otherwise the routine fails and the result is not guaranteed. The full NVM memory range in data memory area is mapped as follows: Sector DM address (HEX) 0 0x4000 to 0x47FF 1 0x4800 to 0x4FFF 2 0x5000 to 0x57FF 3 0x5800 to 0x5FFF 4 0x6000 to 0x67FF 5 0x6800 to 0x6FFF The CRC made on data memory does not check all the content of the NVM because it excludes the 6 additional bits. It should be used to check constant tables for instance and not the program code integrity. The CRC calculation on data is also possible in the RAM area which is mapped on the following addresses: Block RAM Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 DM address (HEX) 0x0080 to 0x027F 39 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 6. ROM API ROUTINES The circuit has a ROM memory used for the following purposes: Refer also to [2]. System Boot sequence Erase/write operation in NVM Dump NVM row into RAM cache CRC calculation on NVM or RAM ISP functions (Program loading, CRC check) 6.1 BOOT SEQUENCE This sequence runs after any reset. Depending on the reset source, the boot sequence can change as follows: Reste source Start-up Power-Down wakeup VSUP Low (1.0V) Start-up Power-Down wakeup VSUP High (2.5V) ResAna ResSys Description Power-up (voltage-multiplier rising up and power check) All trimming value are copied from NVM into the related registers Power-up (power check) All trimming value are copied from NVM into the related registers All trimming value are copied from NVM into the related registers No trimming value are copied from NVM into the related registers. Duration 7 ms 5 ms 3.5 ms 1 ms At the end of the boot sequence the watchdog is cleared. The user application software starts. All registers have the value as described in the register map depending what reset source is the cause of the boot sequence. Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 40 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 6.2 SUB-ROUTINES USED FOR APPLICATION Using sub-routine in ROM API has an impact on the execution time and the memory. The following table shows for each application routine the number of CPU instructions needed to execute the sub-routine and the addresses in RAM memory used by the sub-routine “software stack” that cannot be recovered. ROM API sub-routine does not use any fixed RAM address for parameter storage. All local variables needed by any of the application sub-routine are stored on the software stack, thus the application programmer shall ensure that: 1. The software stack pointer points to the RAM before any call of the application routine. The software stack pointer is i3 register of CR816. The i3 stack pointer is not initialised by the ROM SW boot sequence. It is under the programmer responsibility to initialise it after boot sequence. 2. The application does not use the the memory in range i3 points too. Depending on the sub-routine, this range can be from i3-21 to i3. All data stored in this range before calling the sub-routine may be lost. It is advised to reserve 22 bytes for software stack in RAM to ensure that any sub-routine will never erase important data. Routine name Stack requirements (bytes) Execution time cacl_crc_code_apl 12 bytes 11.2N + 66 (-3% ; +7%) instructions cacl_crc_data_apl 10 bytes 6N + 64 (-4% ; +3%) instructions erase_row_apl erase_row_slow_apl erase_sector_apl erase_sector_slow_apl nvm_to_cache write_only_apl write_only_slow_apl write_row_apl write_row_slow_apl get_def get_trim 22 bytes 22 bytes 22 bytes 22 bytes 14 bytes 22 bytes 22 bytes 22 bytes 22 bytes 2 ms (no fixed number of instruction) 3 ms (no fixed number of instruction) 2 ms (no fixed number of instruction) 3 ms (no fixed number of instruction) 351 instructions 1 ms (no fixed number of instruction) 1.5 ms (no fixed number of instruction) 3 ms (no fixed number of instruction) 4.5 ms (no fixed number of instruction) Copy’s row 63 in RAM cache Copy’s row 62 in RAM cache Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 N = stop_address – start_address + 1 N = stop_address – start_address + 1 41 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 7. RAM RAM memory size is 512 bytes mapped in the data memory bus. It can be divided in two parts: the first part accessible with direct addressing instruction and the second part not accessible by direct addressing instructions as describe on the following table: DM address (HEX) Addressing 0x0080 to 0x00FF Direct (128 Bytes) 0x0100 to 0x0280 Indirect (384 Bytes) In any condition the RAM is accessed in a single CPU cycle for write and read access. Note: For any information concerning the direct and indirect addressing, refer to the CR816-DL documentation.[1] Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 42 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 8. RESET CONTROLLER The reset controller collects all different reset sources and initializes the needed peripheral registers. Refer to the individual peripheral register mapping tables to see which reset is initializing a specific register. Some of the reset sources are maskable to prevent undesired system reinitialization. After any reset the circuit will perform a power check and go to active mode. Then the reset status bits can be read to identify the reset source. 8.1 RESET SOURCES Possible reset source signals are: POR Power on reset, non-maskable The fully internal POR cell will initialize the full circuit at power-up or if the supply voltge falls below VPOR voltage. PwrDown Power-Down mode In power down all internal registers are initialized, the pad configuration however may be locked to the last good state by setting LckPwrCfg=1 prior to Power-Down mode. ResPA User defined Port A terminal reset function, maskable. Any port A terminal may trigger reset. ResWD Watchdog timer reaching 0, maskable. Logic watchdog reset running on the internal 8kHz Oscillator. ResBO Brown out reset at low regulated voltage, maskable. ResBE CoolRISC bus error when trying to access non-valid instruction space, non-maskable. ResGASP Entering Gasp modes (ISP, DoC), non-maskable. This reset initializes the circuit prior to programming or degugging. 8.2 RESET SIGNALS A combination of the above mentioned reset sources is used to initialize the different peripheral registers. These reset signals are POR, PorLog, ResAna, ResSys. 8.2.1 POR A small logic remains active even in Power-Down mode to allow wake-up. This logic is initialized by POR signal. In the user data memory space this concerns the bit LckPwrCfg. 8.2.2 PORLOG PorLog signal will reinitialize all reset flags and all pullup/pulldown configuration bits PorLog = Por OR PwrDown (logical OR combination) 8.2.3 RESANA ResAna signal will initialize all reset enable bits, the port A input and output enable bits, the port A debouncer selection bits, all trim bits and the analog configuration settings for the DC-DC and Opamp. ResAna = Por OR PwrDown OR ResWD OR ResBE (logical OR combination) 8.2.4 RESSYS ResSys signal initializes all remaining data memory registers, except the RAM which needs to be initialized by the user software if needed. ResSys = Por OR PwrDown OR ResWD OR ResBE OR ResPA OR ResGasp OR ResBO Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 43 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 8.2.5 RESET FLAGS All reset flags are in the Reset flag register: RegResFlg and placed as follows The ResFlgPA bit is asserted by reset from PortA. The ResFlgWD bit is asserted by reset from Watchdog. The ResFlgBO bit is asserted by reset from Brownout. The ResFlgGasp bit is asserted by reset from GASP. The ResFlgBE bit is asserted by reset from CoolRisc Bus-error detection. Note: To detect the Reset from Power-Down, the SW shall read the status of LckPwrCfg. 8.3 RESET REGISTERS 0x0000 Bits Name 7 SelSleep 6 SelPwrDwn 4 EnBrownOut 3:2 XtalCldStart 1 StdByFastWkUp 0 VSUPLow RegSysCfg1 Type ResVal RW 0 RW 0 RW 1 RW '00' RW 0 RO 0 0x0001 Bits Name 7:0 EnResPA RegEnResPA Type ResVal RW 0x00 ResSrc ResAna Enable Reset by PortA bits Description Enable Reset by PortA bits 0x0006 Bits Name 7 ResFlgPA 6 ResFlgWD 5 ResFlgBO 4 ResFlgGasp 3 ResFlgBE 0 LckPwrCfg RegResFlg Type ResVal ResFlg 0 ResFlg 0 ResFlg 0 ResFlg 0 ResFlg 0 RW 0 ResSrc PorLog PorLog PorLog PorLog PorLog Por Reset Flags Description Flag Reset from Port-A Flag Reset from WatchDog Flag Reset from Brown-Out Flag Reset from GASP Flag Reset from CoolRISC Bus-Error Lock configurations to be kept in Power-Down mode 44 www.emmicroelectronic.com Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 ResSrc ResSys ResSys ResAna ResSys ResSys System Configuration - 1 Description Select Sleep mode on Halt Select Power-Down mode on Halt Enable Brown Out Select Xtal Osc. ColdStart length Stand-by mode fast Wakeup VSUP is Low - Tripler activated EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 9. OSCILLATOR AND CLOCKING STRUCTURE The circuit contains 3 independent fully internal RC osillcators, 15Mhz factory pretrimmed 2Mhz factory pretrimmed 8kHz Either one of these external clock sources o 32 KHz watch crystal oscillator (Crystal extern). Mapped on terminals PA4, PC4. o 4 MHz Crystal or Resonator oscillator (Crystal or Resonator extern). Mapped on terminals PA4, PC4. o External high or Low frequency clock input. Mapped on terminal PC4. The oscillator source can be changed on the fly to always use the appropriate oscillator and clock setting according to the desired speed for i.e high speed calculation or low speed controlling, and hence optimise the power consumption. The circuit will always start-up on the 2MHz RC Oscillator. All circuit internal clocks are derived from the above mentioned oscillators. These clock sources may be predivided locally for optimum speed and power. Figure 5; oscillator and clock selection architecture Hi-Freq trimmed RC Oscillators RC_15M RC_2M Oscillators and Clock selection Ck_15M SelCkHi[1:0] SelCkCR[3:0] Ck_2M Ck_Hi SelCkExt[1:0] Ck_CR CR816 /1/2/4/8 CkSwSelHi CoolRISC CkSwStsHi Ck_PC4 PC4/OscOut /1/2/4/8 /16/32/64 ReqCkHi/Lo SelCkPR2[2:0] LF HF Ck_Reson Ck_Ext Ck_Xtal32 PA4/OscIn Clock Synchro switch CkSwSelX CkSwStsX /1/2/4/8 Pr2Ck[10:0] Ck_Pr2 Prescaler2 10 stages Clock source for Timer, SPI, Debouncer FreqOut ReqCkHi/Lo SelCkPR1[2:0] Resonator, 32kHz Crystal Ext Clock Pr1Ck[15:0] SelCkLo[1:0] /1/2/4/8 Ck_Lo /4 Ck_Pr1 Prescaler1 15 stages Clock source for RTC, Debouncer,Timer, SPI, IRQ, FreqOut ReqCkHi/Lo CkSwSelLo Lo-Freq RC Oscillator RC_8k Ck_8k CkSwStsLo SCWakeUp /1/2/4/8 /16/32/64 Ck_ADC 10 bit ADC Watchdog The RC15Mhz Ck_15M and RC_2Mhz Ck_2M oscillators are factory pretrimmed, the RC_8kHz Ck_8k oscillator is the only clock source for the watchdog and the sleep counter reset function, but can also be used as a very low system clock. The RC_8kHz low frequency oscillator is not trimmed. On the PA4 and PC4 an external 32 KHz Crystal Ck_Xtal or 4MHz Resonator/Crystal Ck_Reson oscillator can be connected or one may have an external clock input Ck_PC4 on PC4. The selected output clock signal is Ck_Ext. The Ck_Hi clock signal can come from the 15MHz RC, 2MHz RC, 4MHz Resontor/Crystal or the external high frequency clock input on PC4. The Ck_Lo clock signal can come from the 32 KHz Crystal oscillator, divided 32 KHz, 8 kHz RC or the low frequency external clock on PC4; it is synchronized with the high frequency clock Ck_Hi if present. Ck_Lo clock synchronization Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 45 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x with Ck_Hi allows fully synchronous circuit operation. The synchronization is disabled if the Ck_Hi or divided Ck_Hi clock is not used by any periphery. The CPU input clock Ck_CR is derived from either divided or undivided Ck_Hi or Ck_Lo. The Prescaler 1 Ck_Pr1 and Prescaler 2 CkPr2 input clock is derived fom either divided or undivided Ck_Hi or direct Ck_Lo. The ADC input clock Ck_ADC is derived from either divided or undivided Ck_Hi clock signal. 9.1 EXTERNAL CLOCK SELECTION The External Component or Input clock source Ck_Ext is selected by register RegClockCfg1 bits SelCkExt as follows: SelCkExt 00 01 10 11 Input Ck_Xtal Ck_Reson Ck_PC4 Used PADs PA4, PC4 PA4, PC4 PC4, PCInpE[4]=’1’ Description No clock selection Xtal Resonator External Clock input Used for: Ck_Hi Used for: Ck_Lo Frequency none 32 KHz 4 MHz Min: Ck_Lo * 8; Max: 15 MHz Max: Ck_Hi / 8; Min: 0 Hz The default external clock source after system reset (ResSys) is “00” - None. The Ck_Ext clock signal is tied low. Before using an external clock input source one shall configure the necessary PA4 PC4 pads as analog inputs in case of external XTAL or Resonator, and as logic input with PCInpEn[4]=1 in case of external PC4 clock input. The external clock input on PC4 has min/max frequencies depending on its future use as Ck_Hi or Ck_Lo clock source; refer to the table above for the limits. 9.2 INTERNAL HIGH AND LOW FREQUENCY CLOCK SELECTION The high Ck_Hi and low Ck_Low system frequencies can be selected independently but some restrictions for apply if connecting the external clock source. The High Frequency clock Ck_Hi is selected according to the register RegClockCfg1 bits SelCkHi as follows: SelCkHi Ck_Hi Source Select signal 00 Ck_15M SelRC15M 01 Ck_2M SelRC2M 10 Ck_Ext SelExt 11 Ck_2M SelRC2M The default Ck_Hi clock source after system reset (ResSys) is Ck_2M. The Low Frequency clock Ck_Lo is selected according to the register RegClockCfg1 bits SelCkLo as follows: SelCkLo Ck_Lo Source Select signal 00 Ck_Ext SelExt 01 Ck_Ext Divided by 4 (Ck_Ext/4) SelExt 10 Ck_8k SelRC8k 11 Ck_8k SelRC8k The default Ck_Lo clock source after system reset (ResSys) shall be Ck_8k. Note: If Ck_Hi or Ck_Lo are switched from external clock (SelExt active) to Ck_15M, Ck_2M or Ck_8k the SelCkExt selection must not be changed until the status bits for the selected Ck_Hi external clock RegCkSw1.CkSwStsHi or Ck_Lo external clock RegCkSw2.CkSwStsLo has changed to ‘0’ Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 46 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 9.2.1 EXTERNAL CLOCK SELECTION RESTRICTIONS The external clock source selection for both high and low frequency clocks is very flexible, however some restrictions apply: The external clock must not be connected to both Ck_Hi and Ck_Lo at the same time. Allowed usage for external clock input on either high or low frequency domain: External Clock source SelCkExt Source 00 None 01 Xtal 9.2.2 10 Renonator 11 PC4 Allowed configuration None Ck_Lo: (SelCkLo == 00 || SelCkLo == 01) && SelCkHi !=10 (Ck_Hi on RC Osc and Ck_Lo on either Ck_Ext or Ck_Ext/4) Ck_Hi: SelCkHi == 10 && (SelCkLo != 00 && SelCkLo != 01) (Ck_Hi on Ck_Ext and Ck_Lo on Ck_8k) Ck_Lo: (SelCkLo == 00 || SelCkLo == 01) && SelCkHi !=10 (Ck_Hi on RC Osc and Ck_Lo on either Ck_Ext or Ck_Ext/4 Ck_Hi: SelCkHi == 10 && (SelCkLo != 00 && SelCkLo != 01) (Ck_Hi on Ck_Ext and Ck_Lo on Ck_8k) CPU CLOCK SELECTION The CPU input clock Ck_CR is derived from divided or undivided Ck_Hi or Ck_Lo input clock. Below table is an overview of the different CPU clocking possibilities. The CPU clock divider selection is done in register RegClockCfg2 bits SelCkCR. SelCkCR 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 CoolRisc Clock Ck_Hi (divided by 1) Ck_Hi divided by 2 Ck_Hi divided by 4 Ck_Hi divided by 8 (default) Ck_Hi divided by 16 Ck_Hi divided by 32 Ck_Hi divided by 64 Ck_Hi divided by 8 Ck_Lo (divided by 1) Ck_Lo divided by 2 Ck_Lo divided by 4 Ck_Lo divided by 8 Ck_Lo (divided by 1) Ck_Lo (divided by 1) Ck_Lo (divided by 1) Ck_Lo (divided by 1) The default CR clock source after system reset (ResSys) is Ck_Hi divided by 8 (selection 0x3). The CPU instruction execution cycle corresponds to half the Ck_CR clock frequency. 2 MHz input clock results in 1 MIPS. ReqCkHi or ReqCkLo signals are asserted to the Hi- or Low frequency clock switches depending of the CR multiplexer selection. Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 47 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 9.2.3 PRESCALER1 CLOCK SELECTION The Prescaler1 input clock Ck_Pr1 is derived from divided or undivided Ck_Hi or Ck_Lo input clock. Below table is an overview of the different prescaler1 clocking possibilities. The prescaler clock divider selection is done in register RegClockCfg3 bits SelCkPr1. SelCkPr1 000 001 010 011 100 Others Prescaler1 Clock Ck_Hi (divided by 1) Ck_Hi divided by 2 Ck_Hi divided by 4 Ck_Hi divided by 8 default Ck_Lo (divided by 1) Ck_Hi divided by 8 The default Prescaler1 clock source after system reset (ResSys) shall be Ck_Hi divided by 8 (selection 0x3). ReqCkHi or ReqCkLo signals are asserted to the Hi- or Low frequency clock switches depending of the Prescaler1 multiplexer selection. 9.2.4 PRESCALER 2 CLOCK SELECTION The Prescaler2 input clock Ck_Pr2 is derived from divided or undivided Ck_Hi or Ck_Lo input clock. Below table is an overview of the different prescaler1 clocking possibilities. The prescaler clock divider selection is done in register RegClockCfg3 bits SelCkPr2. SelCkPr2 000 001 010 011 100 Others 1xx Prescaler2 Clock Ck_Hi (divided by 1) Ck_Hi divided by 2 Ck_Hi divided by 4 Ck_Hi divided by 8 Ck_Lo (divided by 1) Ck_Lo (divided by 1) The default Prescaler2 clock source after system reset (res_sys) shall be Ck_Lo divided by 1 (selection 0x4). ReqCkHi or ReqCkLo signals are asserted to the Hi- or Low frequency clock switches depending of the Prescaler2 multiplexer selection. Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 48 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 9.3 CLOCK CONTROL Ck_Hi and Ck_Lo are active only if needed. If Ck_Hi is selected by any of SelCkCR, SelCkPr1, SelCkPr2, its ReqCkHi signal becomes active and the oscillator as selected by the SelCkHi-multiplexer will be enabled, otherwise it shall be disabled. The oscillator is also enabled if forced by the corresponding FrcEn bit in register RegClockCfg2. If Ck_Lo is selected by any of SelCkCR, SelCkPr1, SelCkPr2, its ReqCkLo signal becomes active and the oscillator as selected by the SelCkLo-multiplexer will be enabled, otherwise it shall be disabled. The oscillator is also enabled if forced by the corresponding FrcEn bit in register RegClockCfg2. As such the oscillators are only active if there output clock is needed for either Ck_Hi or Ck_Lo. Alternatively the user may always force-on any RC oscillator and one of the external clock sources (Xtal, resonator, PC4 ext clock) Clock selection/request is provided as information which oscillator(s) are actually selected with its clock requested by a peripheral block. The request/selection bits CkSwSelX, CkSwSelHi, CkSwSelLo is high for the actual selected oscillator on the given clock switch. The coding is one-hot. Clock status information is provided to show which oscillator(s) are actually active and outputting their clock on their clock switch. The status bits CkSwStsX, CkSwStsHi, CkSwstsLo is high for the actual active oscillator on the given clock switch. The coding is one-hot. The clock selection and clock status signals are readable in register RegCkSw1 and RegCkSw2. The coding is onehot. A selected oscillator clock is only applied to the periphery if its selection and status bit match. Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 49 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 9.4 OSCILLATORS CONTROL The oscillator control block assures that only the oscillators which are requested or which are forced-on are really active. The various status signals allow close monitoring of the clock switching and give essential information for power saving. Figure 6; Oscillator control architecture Oscillator control architecture trimOsc15M FrcEnRC15M SelRc15M EnDCDC Cold start 4 pulses RC_15M Ck_15M StsCSRC15M StsEnRC15M trimOsc2M Cold start 2 pulses RC_2M FrcEnRC2M SelRC2M Ck_2M StsCSRC2M StsEnRC2M FrcEnExtOsc SelExt PCInpE[4] SelCkExt= ‘11’ EnExtPad SelCkExt= ‘10’ StsEnReson StsEnXtal SelCkExt=’01' En PC4/OscOut Cold start 16 pulses En Vreg LF StsCSPad En HF Cold start 4096 pulses PA4/OscIn Sleep SCStart SCDis FrcEnRC8k SelRC8k WDDis Ck_PC4 Cold start progammable 8k-32k pulses RC_8k Cold start 32 pulses Ck_Reson StsCSReson Ck_Xtal32 StsCSXTAL Ck_8k StsCSRc8k StsEnRC8k Oscillator availability is delayed by an individual oscillator ColdStart delay. Each disabled oscillator or external clock will go through the ColdStart phase when enabled. Following delays apply: Oscillator RC 15 MHz RC 2MHz RC 8 kHz Ext: from Pad Ext: Resonator Ext: Xtal The 32 KHz Xtal ColdStart delay is programmable by the register bits XtalCldStart as follows: RegXtalCldStart ColdStart delay 00 32K cycles (default) 01 24K cycles 10 16K cycles 11 8K cycles ColdStart delay 4 pulses 2 pulses 32 pulses 16 pulses 4K pulses programmable by register bits XtalCldStart The ColdStart functionality is blocking the given clock propagation to the circuit. The status of ColdStart function for each oscillator shall be readable by the register RegStsCStart bits StsCSReson, StsCSXtal, StsCSPad, StsCSRC8k, StsCSRC2M, StsCSRC15M. Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 50 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x The oscillator Force-On functionality can be used to avoid recurrent coldstart delays on fast clock switching. An Oscillator is enabled if its clock is requested by either of the SelCkCR, SelCkPr1, SelCkPr2 clock selection bits or forced-on by register RegClockCfg2 bits FrcEnXXX as follows: Oscillator Condition Status bit RC15 MHz SelRC15M || FrcEnRC15M || EnDC-DC StsEnRC15M SelRC2M || FrcEnRC2M RC2 MHz StsEnRC2M (SelExt || FrcEnExt) && SelCkExt=”01” Xtal StsEnXtal Resonator (SelExt || FrcEnExt) && SelCkExt=”10” StsEnReson The oscillator enable signals are readable by the register RegStsEnOsc bits StsEnReson, StsEnXtal, StsEnRC8k, StsEnRC2M, StsEnRC15M. An External clock Source from pad PC4 is enabled if selected or forced-on by register RegClockCfg2 bit FrcEnExt , its status is read on StsCSPad: StsCSPad = (SelExt || FrcEnExt) && SelCkExt=”11” PCInpE[4] must be high to allow PC4 clock input The RC 15 MHz oscillator is always automatically enabled if the DC-DC converter is switched on (register RegDCDCCfg bit EnDC-DC). The oscillators (except RC_8K) and the external clock sources are automatically disabled in Sleep mode. This has priority over Select and Force-On functionality. The oscillators and the external clock sources are automatically disabled by power-check functionality. This has priority over Select and Force-On functionality. The RC 8 kHz oscillator is enabled in Sleep mode with active sleepcounter function if the watchdog is enabled, if requested by any of the SelCkCR, SelCkPr1 and SelCkPr2 clock selection and when forced-on. The status bit of the RC_8k is readable in register RegStsEnOsc bit StsEnRC8k StsEnRC8k = FrcEnRC8k || SelRC8k || ((Sleep || SCStart) && !SCDis) || !WDDis Note: The RC_8kHz oscillator can only be disabled at least 300us after its coldstart. ( RegStsCStart.StsCSRC8k) Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 51 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 9.5 CLOCK CONTROL REGISTERS 0x0000 Bits Name 7 SelSleep 6 SelPwrDwn 4 EnBrownOut 3:2 XtalCldStart 1 StdByFastWkUp 0 VSUPLow RegSysCfg1 Type ResVal RW 0 RW 0 RW 1 RW '00' RW 0 RO 0 0x0003 Bits Name 7:6 SelCkExt 5:4 SelCkHi 3:2 SelCkLo 1 0 FrcFastRead RegClockCfg1 Type ResVal RW_Res '00' RW_Res '01' RW_Res '10' NI RW 0 ResSrc ResSys ResSys ResSys ResSys 0x0004 Bits Name 7 FrcEnRC15M 6 FrcEnRC2M 5 FrcEnRC8k 4 FrcEnExt RegClockCfg2 Type ResVal RW 0 RW 0 RW 0 RW 0 ResSrc ResSys ResSys ResSys ResSys 3:0 RW_Res ResSys Clock Configuration - 2 Description Force 15 MHz RC Oscillator ON Force 2 MHz RC Oscillator ON Force 8 kHz RC Oscillator ON Force selected (SelCkExt) External Component/Input clock source ON Select CoolRisc/CPU Clock source SelCkCR 0x3 ResSrc ResSys ResSys ResAna ResSys ResSys System Configuration - 1 Description Select Sleep mode on Halt Select Power-Down mode on Halt Enable Brown Out Select Xtal Osc. ColdStart length Stand-by mode fast Wakeup VSUP is Low - Tripler activated Clock Configuration - 1 Description Select External Component/Input clock source Select High freq. Clock source Select Low freq. Clock source Not implemented Force NVM Fast Read 0x0005 Bits Name 7:5 SelCkPr1 4:2 SelCkPr2 1:0 - RegClockCfg3 Type ResVal RW_Res '011' RW_Res '100' NI - ResSrc ResSys ResSys - Clock Configuration - 3 Description Select Prescaler1 Clock source Select Prescaler2 Clock source - 0x02A5 Bits Name 7:6 5 StsCSReson 4 StsCSXtal 3 StsCSPad 2 StsCSRC8k 1 StsCSRC2M 0 StsCSRC15M RegStsCStart Type ResVal NI RO 1 RO 1 RO 1 RO 0 RO 0 RO 1 ResSrc ResSys ResSys ResSys ResSys ResSys ResSys Ostcillators ColdStart Status Description ColdStart Status of (4 MHz) Resonator Oscillator ColdStart Status of (32K Hz) Xtal Oscillator ColdStart Status of External Pad-Clock ColdStart Status of 8 kHz RC Oscillator ColdStart Status of 2 MHz RC Oscillator ColdStart Status of 15 MHz RC Oscillator 0x02A6 Bits Name 7:5 4 StsEnReson RegStsEnOsc Type ResVal NI RO 0 ResSrc ResSys 3 2 1 0 RO RO RO RO ResSys ResSys ResSys ResSys StsEnXtal StsEnRC8k StsEnRC2M StsEnRC15M Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 0 1 1 0 52 Ostcillators Enable Status Description Not implemented Enabled Status/State of (4 MHz) Resonator Oscillator Enabled Status/State of (32K Hz) Xtal Oscillator Enabled Status/State of 8 kHz RC Oscillator Enabled Status/State of 2 MHz RC Oscillator Enabled Status/State of 15 MHz RC Oscillator www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 0x02A7 Bits Name 7 CkSwSelX RegCkSw1 Type ResVal RO 0 ResSrc ResSys 6 CkSwStsX RO 0 ResSys 5:3 CkSwSelHi RO '010' ResSys 2:0 CkSwStsHi RO '010' ResSys 0x02A8 Bits Name 7:6 5:3 CkSwSelLo RegCkSw2 Type ResVal NI RO '100' ResSrc ResSys 2:0 RO ResSys CkSwStsLo '100' Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 Clock switches Selector/Request and current Status - 1 Description Ck_SW Clock (Ck-Hi/Ck-Lo) Sync. clock switch Selector/Request Status ‘1’ - CK_Lo, ‘0’ - CK_Hi Ck_SW Clock (Ck-Hi/Ck-Lo) Sync. clock switch current Status ‘1’ - CK_Lo, ‘0’ - CK_Hi Ck-Hi Clock switch (one-hot) Selector/Request Status bit0 – Ck_15M, Bit1 – Ck_2M, bit2 – Ck_Ext Ck-Hi Clock switch (one-hot) current Status bit0 – Ck_15M, Bit1 – Ck_2M, bit2 – Ck_Ext Clock switches Selector/Request and current Status - 2 Description Not implemented Ck-Lo Clock switch (one-hot) Selector/Request Status bit0 – Ck_Ext, Bit1 – Ck_Ext/4, bit2 – Ck_8k Ck-Lo Clock switch (one-hot) current Status bit0 – Ck_Ext, Bit1 – Ck_Ext/4, bit2 – Ck_8k 53 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 10. PRESCALER1 The prescaler1 is a 15 stage clock divider. It is typically used to deliver the input clocks to the digital peripherals (timers, SPI, etc..). Its last stage output is on 1Hz (at 32768Hz input clock) and therefore most often used to construct a RTC (Real Time Clock) system. It can also be used as a free running counter by reading the current status of Pr1Ck0(MSB) to Pr1Ck7(LSB) in register RegPresc1Val. 10.1 PRESCALER1 CLOCK SELECTION The Prescaler1 input clock Ck_Pr1 is derived from divided or undivided Ck_Hi or Ck_Lo input clock. Below table is an overview of the different prescaler1 clocking possibilities. The prescaler clock divider selection is done in register RegClockCfg3 bits SelCkPr1. SelCkPr1 Prescaler1 Clock 000 Ck_Hi (divided by 1) 001 Ck_Hi divided by 2 010 Ck_Hi divided by 4 011 Ck_Hi divided by 8 (default) 100 Ck_Lo (divided by 1) Others Ck_Hi divided by 8 The default Prescaler1 clock source after system reset (ResSys) shall be Ck_Hi divided by 8 (selection 0x3). It is possible to run the 15 stage precaler1 on 13 stages only. This is typically used when connecting the RC_8K oscillator as the prescaler1 clock source and allow to keep the nominal prescaler output frequencies as if there would be an 32kHz Xtal oscillator connected (prescaler at 15 stages). The prescaler1 length selection is done in register RegPrescCfg bit Presc1Len (‘0’= 15 stages, ‘1’=13 stages). The Signals Pr1Ck14 and Pr1Ck13 are thus not influenced by the shortening. Assuming a Prescaler1 with N stages, then the signal Pr1Ck[N] is the input of the first stage, Pr1Ck[N-1] is the output of the first stage (input divided by 2) and Pr1Ck0 is the output of the last stage (the lowest frequency). This leads to following clock source name definitions. Prescaler1 Clock Name Presc1Len = ‘0’ Presc1Len = ‘1’ stage Division by Fout Division by Fout 1 2^0 32K 1 2^0 8K Prescaler source: Pr1Ck15 Stage 1 Pr1Ck14 2 2^1 16K 2 2^1 4K Stage 2 Pr1Ck13 4 2^2 8K 4 2^2 2K Stage 3 Pr1Ck12 8 2^3 4K 2 2^1 4K Stage 4 Pr1Ck11 16 2^4 2K 4 2^2 2K Stage 5 Pr1Ck10 32 2^5 1K 8 2^3 1K Stage 6 Pr1Ck9 64 2^6 512 16 2^4 512 Stage 7 Pr1Ck8 128 2^7 256 32 2^5 256 Stage 8 Pr1Ck7 256 2^8 128 64 2^6 128 Stage 9 Pr1Ck6 512 2^9 64 128 2^7 64 Stage 10 Pr1Ck5 1K 2^10 32 256 2^8 32 Stage 11 Pr1Ck4 2K 2^11 16 512 2^9 16 Stage 12 Pr1Ck3 4K 2^12 8 1K 2^10 8 Stage 13 Pr1Ck2 8K 2^13 4 2K 2^11 4 Stage 14 Pr1Ck1 16K 2^14 2 4K 2^12 2 Stage 15 Pr1Ck0 32K 2^15 1 8K 2^13 1 The frequencies Fout given in this table are based on 32 KHz clock selection as a prescaler1 input source. Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 54 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 10.2 PRESCALER1 RESET Writing ‘1’ to the bit Presc1Clr in register RegPrescCfg sets all stages to ‘1’ and counting restarts. 10.2.1.1 PRESCALER1 INTERRUPT GENERATION The prescaler1 generates 2 interrupt signals IntPr1Ck0 interrupt signal is generated on the stage 15 overrun (rising Pr1Ck0 edge) IntPr1Ck5/3 interrupt signal is generated on the stage 10 or stage12 overrun (rising Pr1Ck3 or Pr1Ck5 edge). The selection is done in register PrescCfg bit Presc1SelIntck5/3 as follows: Presc1SelIntck5/3 Int. Freq. (based on 32KHz) Pr1-Ck 0 (Default) 8 Hz Pr1Ck3 1 32 Hz Pr1Ck5 The frequencies given in this table are based on 32 KHz clock selection as a prescaler1 input source. 10.3 PRESCALER REGISTERS 0x0007 Bits Name 7 Presc1Clr 6 Presc1Len 5 Presc1SelIntck5/3 4 Presc2Clr 3:0 - RegPrescCfg Type ResVal OS 0 RW 0 RW 0 OS 0 NI - 0x0008 Bits Name 7:0 Presc1Val RegPresc1Val Type ResVal RO 0xFF Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 - Prescaler-1/2 Configuration Description Prescaler-1 Clear counter Prescaler-1 Length Select Prescaler-1 irq-B source: 0-8Hz, 1-32Hz Prescaler-2 Clear counter Not implemented ResSrc ResSys Prescaler-1 Value (MSB) Description Prescaler-1 Value (MSB) , Pr1Ck0 to Pr1Ck7 status ResSrc ResSys ResSys 55 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 11. PRESCALER2 The prescaler2 is a 10 stage clock divider. It is typically used to deliver the input clocks to the digital peripherals (timers, SPI, etc. It can also be used as a free running counter by reading the current status of Pr2Ck0(MSB) to Pr2Ck7(LSB) in register RegPresc2Val. 11.1 PRESCALER2 CLOCK SELECTION The Prescaler2 input clock Ck_Pr2 is derived from divided or undivided Ck_Hi or Ck_Lo input clock. Below table is an overview of the different prescaler1 clocking possibilities. The prescaler clock divider selection is done in register RegClockCfg3 bits SelCkPr2. SelCkPr2 Prescaler2 Clock 000 Ck_Hi (divided by 1) 001 Ck_Hi divided by 2 010 Ck_Hi divided by 4 011 Ck_Hi divided by 8 100 Ck_Lo (divided by 1) Others Ck_Lo (divided by 1) The default Prescaler-2 clock source after system reset (res_sys) shall be Ck_Lo divided by 1 (selection 0x4). Assuming a Prescaler2 with N stages, then the signal Pr2ck[N] is the input of the first stage, Pr2Ck[N-1] is the output of the first stage (input divided by 2) and Pr2Ck0 is the output of the last stage (the lowest frequency). This leads to following clock source name definitions. Prescaler2 Clock Name Division by Fout stage 1 2^0 2M Prescaler source: Pr2Ck10 Stage 1 Pr2Ck9 2 2^1 1M Stage 2 Pr2Ck8 4 2^2 500 k Stage 3 Pr2Ck7 8 2^3 250 k Stage 4 Pr2Ck6 16 2^4 125 k Stage 5 Pr2Ck5 32 2^5 62500 Stage 6 Pr2Ck4 64 2^6 31250 Stage 7 Pr2Ck3 128 2^7 15625 Stage 8 Pr2Ck2 256 2^8 7812.5 Stage 9 Pr2Ck1 512 2^9 3906.25 Stage 10 Pr2Ck0 1K 2^10 1953.125 The frequencies Fout given in this table are based on 32 KHz clock selection as a prescaler2 input source. 11.2 PRESCALER2 RESET Writing ‘1’ to the bit Presc2Clr in register RegPrescCfg sets all stages to ‘1’ and counting restarts. 11.3 PRESCALER2 REGISTERS 0x0007 Bits Name 7 Presc1Clr 6 Presc1Len 5 Presc1SelIntck5/3 4 Presc2Clr 3:0 - RegPrescCfg Type ResVal OS 0 RW 0 RW 0 OS 0 NI - 0x0009 Bits Name 7:0 Presc2Val RegPresc2Val Type ResVal RO 0xFF Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 - Prescaler-1/2 Configuration Description Prescaler-1 Clear counter Prescaler-1 Length Select Prescaler-1 irq-B source: 0-8Hz, 1-32Hz Prescaler-2 Clear counter Not implemented ResSrc ResSys Prescaler-2 Value (MSB) Description Prescaler-2 Value (MSB), Pr2Ck0 to Pr2Ck7 status ResSrc ResSys ResSys 56 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 12. INTERRUPT AND EVENT CONTROLLER 12.1 INTERRUPTS GENERAL 12.1.1 BASIC FEATURES The circuit handles 24 independent Interrupt sources grouped into 3 priority levels. Highest Priority : Level 0 : Prescaler1, PmMiss, GASP, ADC, Timer, Ports Medium Priority : Level 1 : SPI, Prescaler1, OpAmp, Timer, Ports Lowest Priority : Level 2 : Timer, Ports, Sleep counter, VLD As such the circuit contains 13 external Interrupts (Ports, SPI, OpAmp, VLD, GASP) 12 internal Interrupts (Prescaler, DoC, Timer, SPI, PmMiss, Sleep Counter) Interrupt from SPI and Timer may be initialized by either external or internal actions (i.e. timer running on external clock) Interrupts force a CALL to a fixed interrupt vector, save the program counter (PC) onto the hardware stack and reset the general interrupt bit (GIE). If the CPU was in StandBy mode prior to Interrupt then it will come back in active mode. Each priority level has its own interrupt vector. Level 1 sets bit IN1 in CoolRISC status register Program memory address 1 Call Vector 1 Level 2 sets bit IN2 in CoolRISC status register Program memory address 2 Call Vector 2 Level 0 sets bit IN0 in CoolRISC status register Program memory address 3 Call Vector 0 The GIE bit is restored when returning from interrupt with the RETI instruction. The RET instruction does not reinstall the GIE. Nested interrupts are possible by re-enabling the GIE bit within the interrupt routine. Functions such as interrupt Pre- or Post-masking, enabling and clearing are available on different levels in the interrupt structure. At power up or after any reset all interrupt inputs are masked and the GIE is cleared. The Interrupt handling is split into 2 parts. One part deals with the acquisition, masking and clearing of the interrupts outside of the CPU. Interrupt acquisition, IRQ Controller nd The 2 part covers all aspects of priority and interrupts enabling inside the CoolRISC core. CPU interrupts handling Figure 7, Interrupt top level diagram Interrupt Diagram Level 0 Interrupt sources Level 1 Interrupt sources Level 2 Interrupt sources CPUInt0 Interrupt Controller 8 IN0 CPUInt1 CPU CR816 IN1 CPUInt2 Interrupt handling IN2 8 R/W Control Interrupt acquisition 8 Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 RegInt0Sts RegInt1Sts RegInt2Sts 57 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 12.2 INTERRUPT ACQUISITION A positive edge on any of the unmasked interrupt source signals will set the corresponding interrupt register bit and activate the mapped CPU interrupt input. (I.e. Timer3 interrupt IntTim3 will set bit Int1StsTim3 in register RegInt1Sts and activate the CPUInt1 interrupt input if mask bit Int1MskTim3 is ‘1’ [non-masked] ). The 3 priority branches for interrupt acquisition are totally independent of each other, masking and selective clear of interrupts on one interrupt vector input does not modify the others. All Interrupts inputs are available in active and standby mode. Table 1. Interrupts signal sources and destination Interrupt sources IntPort0 IntTim1 IntPr1Ck0 IntADC IntDoCDM IntDoCPM IntGASP IntPmMiss IntPort2 IntPort1 IntTim2 IntTim3 IntOpAmp IntPr1Ck5/3 IntSPIStop IntSPIStart IntVLD IntSlpCnt IntPort7 IntPort6 IntPort5 IntPort4 IntPort3 IntTim4 Int Mapping vector Int0StsPort0 Int0StsTim1 Int0StsPrCk0 Int0StsADC 0 Int0StsDoCDM Int0StsDoCPM Int0StsGASP Int0StsPmMiss Int1StsPort2 Int1StsPort2 Int1StsTim2 Int1StsTim3 1 Int1StsOpAmp Int1StsPr1Ck5/3 Int1StsSPIStop Int1StsSPIStart Int2StsVLD Int2StsSlpCnt Int2StsPort7 Int2StsPort6 2 Int2StsPort5 Int2StsPort4 Int2StsPort3 Int2StsTim4 remark PA0 or PC0, positive and/or negative edge Timer1 Input capture, Compare value, Compare Full Prescaler1 1Hz (Pr1Ck0) ADC conversion finished DoC data memory address match DoC program memory address match GASP data reception with sign='1' Program memory, wait introduction PA2 or PC2, positive and/or negative edge PA1 or PC1, positive and/or negative edge Timer2, Input capture, Compare value, Compare Full Timer3, Input capture, Compare value, Compare Full Comparator; falling and/or rising output change Prescaler 1, 8Hz or 32Hz (falling edge) SPI, Stop transmission 1 byte SPI, Start transmission 1byte Voltage level detector; input low Sleep counter wakeup timeout PA7 or PC7, positive and/or negative edge PA6 or PC6, positive and/or negative edge PA5 or PC5, positive and/or negative edge PA4 or PC4, positive and/or negative edge PA3 or PC3, positive and/or negative edge Timer4, Input capture, Compare value, Compare Full Sleep wakeup X (PA) X X (PA) X (PA) X X X X (PA) X (PA) X (PA) X (PA) X (PA) The following interrupt sources can wake-up the device from the Sleep mode if enabled by appropriate interrupt masks: Table 2. Wake-Up Interrupts Interrupt Source Interrupt Status IntXStsPort7 to IntXStsPort0 PortA; regardless of RegIntPortSrc Sleep counter Int2StsSlpCnt SVLD Int2StsVLD OpAmp Int1StsOpAmp GASP Int0StsGASP Direct (non-debounced) port A interrupts are, used for the wake-up, totaly independent of the debouncer settings. Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 58 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 12.3 INTERRUPTS FROM IO PORTS The register RegIntPortSrc selects the port interrupt source IntPort coming from port A or port C in Active and StandBy modes. In Sleep mode, the port A is always selected independent of RegIntPortSrc settings. If RegIntPortSrc[X] = ‘0’ then IntPort[X] source shall be IntPA[X] otherwise it is IntPC[X]. The default value of RegIntPortSrc is 0x00, i.e. IntPA[X] is selected. 12.4 INTERRUPT ACQUISITION MASKING. At start up or after any reset all interrupt sources are masked (mask bits are ‘0’). To activate a specific interrupt source input the corresponding mask bit must be set ‘1’. Masking does not clear an existing interrupt but will prevent future interrupts on the same input. Refer to Figure 8, Interrupt acquisition architecture. 12.4.1 PRE AND POSTMASKING OF INTERRUPTS One pair of registers for each level of priority RegIntXMsk and RegIntXPostMsk control the interrupt generation for CPU and catch an incoming request into the status registers RegIntXSts as follows: If RegIntXMsk[Y] =’1’ then the appropriate CPU interrupt line IntX is asserted and interrupt is caught in the status register RegIntXSts[Y]. If RegIntXMsk[Y] =’0’ then the appropriate CPU interrupt line IntX is NOT asserted. The interrupt request is caught in the status register RegIntXSts[Y] only if RegIntXPostMsk[Y] =’1’. If RegIntXMsk[Y] =’0’ then the appropriate CPU interrupt line IntX is NOT asserted. The interrupt request is NOT caught in the status register RegIntXSts[Y] if RegIntXPostMsk[Y] =’0’. Figure 8, Interrupt acquisition architecture Interrupt aquisition SW write ‘1’ to IntXSts bit IntX IntXMsk D IntXPostMask IntXSource IntXSts Q D SW read RegIntXSts Ck Q To Databus En INV SW write ‘1’ to IntXSts bit IntPort0 IntTim1 IntPr1Ck0 IntADC IntDoCDM IntDocPM IntGASP IntPmMiss IntPort2 IntPort1 IntTim2 IntTim3 IntOpAmp IntPr1Ck5/3 IntSPIStop IntSPIStart IntVLD IntSlpCnt IntPort7 IntPort6 IntPort5 IntPort4 IntPort3 IntTim4 7 6 5 4 3 2 1 Int0Msk D 0 Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 Q 8 Int0[8:0] Int0Sts[8:0] CPUInt0 Q CLR 8 Int1Msk Int1PostMsk Int1Source 8 Int1[8:0] 8 D SET 8 CLR Q CPUInt1 Int1STS[8:0] Q 8 0 7 6 5 4 3 2 1 SET Int0Source 0 7 6 5 4 3 2 1 8 8 Int0PostMsk Int2Msk 8 8 Int2PostMsk D SET Q Int2Source 8 CLR Int2STS[8:0] Int2[8:0] CPUInt2 Q 8 59 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 12.5 INTERRUPT ACQUISITION CLEARING A pending interrupt can be cleared in 3 ways Reading the interrupt registers RegInt0Sts, RegInt1Sts and RegInt2Sts will automatically clear all stored interrupts which were set prior to the read in the corresponding register. This read is normally done inside the interrupt subroutine to determine the source of the interrupt. Each interrupt request status bit can be individually cleared (set ‘0’) by writing ‘0’ to the corresponding RegInt0Sts, RegInt1Sts and RegInt2Sts register bit. Software clearing of the interrupt status bit has priority over an incoming interrupt. At power up or after any reset all interrupt registers are reset. 12.5.1 SOFTWARE INTERRUPT ACQUISITION SET Each interrupt request status bit can be individually set (set ‘1’) by writing ‘1’ to the corresponding RegInt0Sts, RegInt1Sts and RegInt2Sts register bit. Write ‘1’ has the highest priority on the status bit. 12.6 INTERRUPT REGISTERS 0x0061 Bits Name 7 Int0StsPort(0) 6 Int0StsTim1 5 Int0StsPr1Ck0 4 Int0StsADC 3 Int0StsDoCDM 2 Int0StsDoCPM 1 Int0StsGASP 0 Int0StsPmMiss RegInt0Sts Type ResVal RW-INT 0 RW-INT 0 RW-INT 0 RW-INT 0 RW-INT 0 RW-INT 0 RW-INT 0 RW-INT 0 ResSrc ResSys ResSys ResSys ResSys ResSys ResSys ResSys ResSys Interrupt level-0 Status Description Interrupt level-0 Status - Port(0) Interrupt level-0 Status - Timer-1 Interrupt level-0 Status - Prescaler1 Ck0 (1Hz) Interrupt level-0 Status - ADC Interrupt level-0 Status - DoC DM Interrupt level-0 Status - DoC PM Interrupt level-0 Status - GASP Interrupt level-0 Status - PM_Miss 0x0062 Bits Name 7 Int1StsPort(2) 6 Int1StsPort(1) 5 Int1StsTim2 4 Int1StsTim3 3 Int1StsOpAmp 2 Int1StsPr1Ck5/3 1 Int1StsSPIStop 0 Int1StsSPIStart RegInt1Sts Type ResVal RW-INT 0 RW-INT 0 RW-INT 0 RW-INT 0 RW-INT 0 RW-INT 0 RW-INT 0 RW-INT 0 ResSrc ResSys ResSys ResSys ResSys ResSys ResSys ResSys ResSys Interrupt level-1 Status Description Interrupt level-1 Status - Port(2) Interrupt level-1 Status - Port(1) Interrupt level-1 Status - Timer-2 Interrupt level-1 Status - Timer-3 Interrupt level-1 Status - OpAmp Interrupt level-1 Status – Prescaler1 Ck5 or Ck3 Interrupt level-1 Status - SPI_Stop Interrupt level-1 Status - SPI_Start 0x0063 Bits Name 7 Int2StsVLD 6 Int2StsSlpCnt 5 Int2StsPort(7) 4 Int2StsPort(6) 3 Int2StsPort(5) 2 Int2StsPort(4) 1 Int2StsPort(3) 0 Int2StsTim4 RegInt2Sts Type ResVal RW-INT 0 RW-INT 0 RW-INT 0 RW-INT 0 RW-INT 0 RW-INT 0 RW-INT 0 RW-INT 0 ResSrc ResSys ResSys ResSys ResSys ResSys ResSys ResSys ResSys Interrupt level-2 Status Description Interrupt level-2 Status - VLD Interrupt level-2 Status - Sleep Counter Interrupt level-2 Status - Port(7) Interrupt level-2 Status - Port(6) Interrupt level-2 Status - Port(5) Interrupt level-2 Status - Port(4) Interrupt level-2 Status - Port(3) Interrupt level-2 Status - Timer-4 Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 60 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 0x0064 Bits Name 7 Int0MskPort(0) 6 Int0MskTim1 5 Int0MskPr1Ck0 4 Int0MskADC 3 Int0MskDoCDM 2 Int0MskDoCPM 1 Int0MskGASP 0 Int0MskPmMiss RegInt0Msk Type ResVal RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 ResSrc ResSys ResSys ResSys ResSys ResSys ResSys ResSys ResSys Interrupt level-0 Mask Description Interrupt level-0 Mask - Port(0) Interrupt level-0 Mask - Timer-1 Interrupt level-0 Mask - Prescaler1 1Hz Interrupt level-0 Mask - ADC Interrupt level-0 Mask - DoC DM Interrupt level-0 Mask - DoC PM Interrupt level-0 Mask - GASP Interrupt level-0 Mask - PM_Miss 0x0065 Bits Name 7 Int1MskPort(2) 6 Int1MskPort(1) 5 Int1MskTim2 4 Int1MskTim3 3 Int1MskOpAmp 2 Int1MskPr1Ck5/3 1 Int1MskSPIStop 0 Int1MskSPIStart RegInt1Msk Type ResVal RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 ResSrc ResSys ResSys ResSys ResSys ResSys ResSys ResSys ResSys Interrupt level-1 Mask Description Interrupt level-1 Mask - Port(2) Interrupt level-1 Mask - Port(1) Interrupt level-1 Mask - Timer-2 Interrupt level-1 Mask - Timer-3 Interrupt level-1 Mask - OpAmp Interrupt level-1 Mask - Prescaler1 Ck5 or Ck3 Interrupt level-1 Mask - SPI_Stop Interrupt level-1 Mask - SPI_Start 0x0066 Bits Name 7 Int2MskVLD 6 Int2MskSlpCnt 5 Int2MskPort(7) 4 Int2MskPort(6) 3 Int2MskPort(5) 2 Int2MskPort(4) 1 Int2MskPort(3) 0 Int2MskTim4 RegInt2Msk Type ResVal RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 ResSrc ResSys ResSys ResSys ResSys ResSys ResSys ResSys ResSys Interrupt level-2 Mask Description Interrupt level-2 Mask - VLD Interrupt level-2 Mask - Sleep Counter Interrupt level-2 Mask - Port(7) Interrupt level-2 Mask - Port(6) Interrupt level-2 Mask - Port(5) Interrupt level-2 Mask - Port(4) Interrupt level-2 Mask - Port(3) Interrupt level-2 Mask - Timer-4 0x0067 Bits Name 7 Int0PostMskPort(0) 6 Int0PostMskTim1 5 Int0PostMskPr1Ck0 4 Int0PostMskADC 3 Int0PostMskDoCDM 2 Int0PostMskDoCPM 1 Int0PostMskGASP 0 Int0PostMskPmMiss RegInt0PostMsk Type ResVal RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 ResSrc ResSys ResSys ResSys ResSys ResSys ResSys ResSys ResSys Interrupt level-0 Post_Mask Description Interrupt level-0 Post_Mask - Port(0) Interrupt level-0 Post_Mask - Timer-1 Interrupt level-0 Post_Mask - Prescaler1 1Hz Interrupt level-0 Post_Mask - ADC Interrupt level-0 Post_Mask - DoC DM Interrupt level-0 Post_Mask - DoC PM Interrupt level-0 Post_Mask - GASP Interrupt level-0 Post_Mask - PM_Miss 0x0068 Bits Name 7 Int1PostMskPort(2) 6 Int1PostMskPort(1) 5 Int1PostMskTim2 4 Int1PostMskTim3 3 Int1PostMskOpAmp 2 Int1PostMskPr1Ck5/3 1 Int1PostMskSPIStop 0 Int1PostMskSPIStart RegInt1PostMsk Type ResVal RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 ResSrc ResSys ResSys ResSys ResSys ResSys ResSys ResSys ResSys Interrupt level-1 Post_Mask Description Interrupt level-1 Post_Mask - Port(2) Interrupt level-1 Post_Mask - Port(1) Interrupt level-1 Post_Mask - Timer-2 Interrupt level-1 Post_Mask - Timer-3 Interrupt level-1 Post_Mask - OpAmp Interrupt level-1 Post_Mask - Prescaler1 Ck5 or Ck3 Interrupt level-1 Post_Mask - SPI_Stop Interrupt level-1 Post_Mask - SPI_Start 61 www.emmicroelectronic.com Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 0x0069 Bits Name 7 Int2PostMskVLD 6 Int2PostMskSlpCnt 5 Int2PostMskPort(7) 4 Int2PostMskPort(6) 3 Int2PostMskPort(5) 2 Int2PostMskPort(4) 1 Int2PostMskPort(3) 0 Int2PostMskTim4 RegInt2PostMsk Type ResVal RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 ResSrc ResSys ResSys ResSys ResSys ResSys ResSys ResSys ResSys Interrupt level-2 Post_Mask Description Interrupt level-2 Post_Mask - VLD Interrupt level-2 Post_Mask - Sleep Counter Interrupt level-2 Post_Mask - Port(7) Interrupt level-2 Post_Mask - Port(6) Interrupt level-2 Post_Mask - Port(5) Interrupt level-2 Post_Mask - Port(4) Interrupt level-2 Post_Mask - Port(3) Interrupt level-2 Post_Mask - Timer-4 0x006A Bits Name 7:0 IntPortSrc RegIntPortSrc Type ResVal RW 0x00 ResSrc ResSys Port Interrupt source selector: 0-PortA, 1-PortC Description Port Interrupt source selector: 0-PortA, 1-PortC Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 62 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 12.7 EVENT GENERAL 12.7.1 BASIC FEATURES Events are most commonly used to restart the processor from the StandBy mode without jumping to the interrupt vector. Events can also be combined with the JEV instruction (Jump on Event) or been used for wake-up from Sleep mode. The circuit handles 4 independent event sources grouped into 2 event sources, both of same priority Bank 0 Source : EV0: GASP Bank 1 Source : EV1: ADC, SPI, Sleep Counter Figure 9, Event top level diagram Event Diagram Bank 0 Event sources CPUEvt0 EV0 CPU CR816 1 CPUEvt1 Bank 1 Event sources Event Controller 3 EV1 Interrupt handling R/W Control Event acquisition RegEvtSts 12.8 EVENT ACQUISITION A positive edge on any of the unmasked event source signals will set the corresponding event status bit and activate the mapped CPU event input. (I.e. ADC event EvtADC will set bit Evt1StsADC in register RegEvtSts and activate the CPUEvt1 event input if mask bit Evt1MskADC is ‘1’ [non-masked] ). The 2 branches for event acquisition are totally independent of each other, masking and selective clear of events on one event status input does not modify the others. Table 3. Event signal sources and destination Event sources EvtGASP EvtSlpCnt EvtSPI EvtADC Event Mapping bank 0 Evt0StsGASP Evt1StsSlpCnt 1 Evt1StsSPI Evt1StsADC Sleep wakeup X X remark GASP data reception Sleep counter wakeup timeout SPI, Start or Stop transmission ADC conversion finished The following event sources shall wake-up the device from the Sleep mode if enabled by appropriate event masks: Table 4. Wake-Up Events Event Source Sleep counter GASP Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 Event Status Evt1StsSlpCnt Evt0StsGASP 63 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 12.9 EVENT MASKING At start up or after any reset all event sources are masked (mask bits are ‘0’). To activate a specific event source input the corresponding mask bit must be set ‘1’. Masking does not clear an existing event but will prevent future events on the same input. Refer to Figure 10, Event acquisition architecture. 12.9.1.1 PRE AND POSTMASKING OF EVENTS One pair of registers bits for each event EvtXMsk and EvtXPostMsk in register RegEvtCfg control the event generation for CPU and catch an incoming request into the status registers RegEvtSts as follows: If EvtXMsk=’1’ then the appropriate CPU event line EVX is asserted and the event is caught in the status bit EvtXSts. If EvtXMsk=’0’ then the appropriate CPU interrupt line EVX is NOT asserted. The event is caught in the status register EvtXSts only if EvtXPostMsk=’1’. If EvtXMsk=’0’ then the appropriate CPU interrupt line EVX is NOT asserted. The event is NOT caught in the status register EvtXSts only if EvtXPostMsk=’0’. Figure 10, Event acquisition architecture Event acquisition SW write ‘1’ to EvtXSts bit EvtX EvtXMsk D EvtXPostMask EvtXSource EvtXSts Q Ck D SW read RegEvtXSts Q To Databus En INV SW write ‘1’ to EvtXSts bit Evt0Msk Evt0PostMsk Evt0Gasp 1 EvtGasp 1 SET D 1 CLR Q EV0 Ev0StsGASP Q 1 Evt1Msk 3 3 EvtSlpCnt EvtSPI EvtADC 3 2 1 Evt1PostMsk D SET Q Evt1Source 3 CLR Ev1STS EvtSlpCnt, EvtSPI, EvtADC EV1 Q 3 Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 64 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 12.10 EVENT ACQUISITION CLEARING A pending event can be cleared in 3 ways 1. Reading the event register RegEvtSts will automatically clear all stored events which were set prior to the read in the corresponding register. 2. Each event status bit can be individually cleared (set ‘0’) by writing ‘0’ to the corresponding EvtXSts bit. At power up or after any reset all event registers bits are reset. 12.11 SOFTWARE EVENT SETTING Each event status bit can be individually set (set ‘1’) by writing ‘1’ to the corresponding EvtXSts bit in register RegEvtCfg. 12.12 EVENT REGISTERS 0x006B Bits Name 7:4 3 Evt1StsSlpCnt 2 Evt1StsSPI 1 Evt1StsADC 0 Evt0StsGASP RegEvtSts Type NI RW-INT RW-INT RW-INT RW-INT ResVal 0 0 0 0 ResSrc ResSys ResSys ResSys ResSys Event Status Description Not implemented Event level-1 Status - Sleep Counter Event level-1 Status - SPI Event level-1 Status - ADC Event level-0 Status - GASP 0x006C Bits Name 7 Evt1PostMskSC 6 Evt1MskSC 5 Evt1PostMskSPI 4 Evt1MskSPI 3 Evt1PostMskADC 2 Evt1MskADC 1 Evt0PostMskGasp 0 Evt0MskGasp RegEvtCfg Type ResVal RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 ResSrc ResSys ResSys ResSys ResSys ResSys ResSys ResSys ResSys Event Configuration Description Event level-1 Post-Mask - Sleep Counter Event level-1 Mask - Sleep Counter Event level-1 Post-Mask - SPI Event level-1 Mask - SPI Event level-1 Post-Mask - ADC Event level-1 Mask - ADC Event level-0 Post-Mask - GASP Event level-0 Mask - GASP Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 65 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 13. CPU INTERRUPT AND EVENT HANDLING The CPU has three interrupt inputs of different priority. These inputs are directly connected to the peripheral interrupt acquisition block. Each of these inputs has its own interrupt vector. Individual interrupt enabling mechanism is provided for the 2 low priority inputs (IE1, IE2). The GIE acts as a master enable, if GIE is cleared no interrupt can reach the CPU, but may still be stored in the interrupt acquisition block. If the hardware stack of the CPU is full, all interrupt inputs are blocked. The number of implemented hardware stack levels is 5 but If CPU HW stack level is on level 4, only IntGASP, IntDoCPM and IntDoCDM shall generate a CPU interrupt. Figure 11, CPU Interrupt architecture and Status register shows the architectural details concerning the interrupt and event latching and its enabling mechanism. Figure 11, CPU Interrupt architecture and Status register block 5 5 EV1 EV0 IN0 Status_e interrupt and envent latch Status_in[4:0] 1 5 0 ck1 IN1 IE2 IN2 ck3 5 CPUInt0 CPUInt1 CPUInt2 CPUEvent0 IE1 GIE (=DebWakeUp) (CPUEvent1=VSS) HW stack not full CPU Status register MSB IE2 IE1 Mask GIE IN2 IN1 IRQ status IN0 LSB EV1 EV2 Event status An interrupt from the peripheral acquisition block i.e. CPUInt2 is synchronized in the CPU interrupt latch and fed to the CPU interrupt handler signal IN2 if enable bits IE2 and GIE are set and the hardware stack is not full. Same thing applies to CPUInt1. CPUint0 is maskable only with GIE. As soon as the interrupt is latched, the GIE bit will be automatically cleared to avoid interleaved interrupts. Reading the interrupt acquisition register will clear the pending interrupt and at the end of the interrupt routine the RETI instruction will reinstall the GIE bit. The CPU will loop in the interrupt routine as long as there is a CPU interrupt input active and the corresponding IE1, IE2 and GIE are set. Refer to 12.5 for Interrupt acquisition Clearing. An interrupt or Event will also clear the CPU Halt mode. The HALT mode disabling remains active as long as one of the EV0, EV1, IN0, IN1, and IN2 signals is set. Before leaving the interrupt service routine one needs to clear the active IRQ acquisition bit (inside RegIntxx) and the corresponding status bit (IN0, IN1, and IN2) in the CoolRISC status register. Failure to do so will re-invoke the interrupt service routine just after the preceding RETI instruction. Software Interrupts and Events The above shown CPU Interrupt handling implementation is an extension to the base structure and as such allows software interrupts and software events to be written directly in the interrupt and event latches (write ‘1’ to CPU status register bit 0 to 4, signals status_e and status_in). Software written interrupts and events remain stored in the interrupt latch until they get cleared again (write ‘0’ to status register bit 0 to bit 4). 13.1 INTERRUPT PRIORITY Interrupt priority is used only to select which interrupt will be processed when multiple interrupt requests occur simultaneously. In such case the higher priority interrupt is handled first. At the end of the interrupt routine RETI the processor will immediately go back into the interrupt routine to handle the next interrupt of highest priority. If a high priority interrupt occurs while the CPU is treating a low priority interrupt, the pending interrupt must wait until the GIE is enabled, usually by the RETI instruction. Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 66 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 13.2 CPU STATUS REGISTER The status register, used to control the interrupts and events, is an internal register to the CoolRISC CPU. It therefore does not figure in the peripheral memory mapping. All CPU enable bits for the interrupts and the current status of the events and the interrupts are part of this register. Bit Name Reset Table 5. CPU status register description Reset by R/W Description 7 IE2 0 ResSys R/W Level 2 Interrupt enable ‘1’ = enabled, ‘0’ = disabled 6 IE1 0 ResSys R/W Level 1 Interrupt enable ‘1’ = enabled, ‘0’ = disabled 5 GIE 0 ResSys R/W* General interrupt enable ‘1’ = enabled, ‘0’ = disabled 4 IN2 0 ResSys R/W Interrupt request level 2 flag, shows CPUInt2 ‘1’ = IRQ pending, ‘0’ = no IRQ The IRQ may only take place if IN2, IE2, and GIE are set 3 IN1 0 ResSys R/W Interrupt request level 1 flag, shows CPUInt1 ‘1’ = IRQ pending, ‘0’ = no IRQ The IRQ may only take place if IN1, IE1, and GIE are set 2 IN0 0 ResSys R/W Interrupt request level 0 flag, shows CPUInt1 ‘1’ = IRQ pending, ‘0’ = no IRQ The IRQ may only take place if IN0 and GIE are set 1 EV1 0 ResSys R/W Event request 1 0 EV0 0 ResSys R/W Event request 0 *Clear General Interrupt Enable bit GIE. Special care must be taken clearing the GIE bit. If an interrupt arrives during the clear operation the software may still branch into the interrupt routine and will set the GIE bit by the interrupt routine ending RETI instruction. This behavior may prevent from creating 'interrupt protected' areas within your code. A suitable workaround is to check if the GIE clearing took effect (Instruction) TSTB before executing the protected section . 13.3 CPU STATUS REGISTER PIPELINE EXCEPTION Another consequence of the above interrupt implementation is that several instruction sequences work in a different way than expected. These instructions are mostly related to interrupt and event signals. For ‘normal’ instructions the pipeline is completely transparent. If an interrupt is set by software (i.e. write into the status register with a MOVE stat) the pipeline causes the next instruction to be executed before the processor jumps to the interrupt subroutine. This allows one to supply a parameter to a ‘trap’ as in Code shown below. SETB stat, MOVE a #4 #parameter ; trap ; If an event bit is set by software (i.e. write into the CPU status register with a MOVE stat) and if a JEV (jump on event) instruction immediately follows the move, the jump on event will act as if the move has not been executed, since the write into the CPU status register will occur only once the JEV has been executed. The move takes 3 cycles to be executed and the JEV only one. Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 67 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 13.4 PROCESSOR VECTOR TABLE Address 1, 2 and 3 of the program memory are reserved for interrupt subroutine calls. Generally the first four addresses of the program memory are reserved for the processor vector table. The address 0 of the program memory contains the jump to the start-up routine Table 6. Processor vector table Address Accessed by 0 ResSys 1 IN1 2 IN2 3 IN3 Description Any reset, start-up address Interrupt level 1 Interrupt level 2 Interrupt level 0 Priority Maximal, above interrupts medium low high 13.5 CONTEXT SAVING Since an interrupt may occur any time during normal program execution, there is no way to know which processor registers are used by the user program. For this reason, all resources modified in the interrupt service routine have to be saved upon entering and restored when leaving the service routine. The flags(C, V) and the accumulator (A) must always be saved, since most instructions will modify them. Other registers need only to be saved when they are modified in the interrupt service routine. There is a particular way to follow when saving resources. The accumulator should be saved first, followed by the flags and then the other registers Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 68 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 14. PORT A The port A is general purpose 8-bit input output port. Each of the 8 Port A terminals can be configured to receive either Analog or digital Input or drive out analog or digital data. 14.1 PORT A TERMINAL MAPPING Several digital and analog functions are mapped on the port A terminals. Please refer also to the concerned chapters. Table 14.1-1 Port A terminal mapping Name IRQ Reset & WkUp ADC VREF VLD OPAMP PA0 PAIRQ0 ADC0 Rst_Wkup0 PA1 PAIRQ1 ADC2 Rst_Wkup1 VLD PA2 PAIRQ2 ADC4 Rst_Wkup2 Vref_ADC VLD OPA_INM PA3 PAIRQ3 ADC6 Rst_Wkup3 PA4 PAIRQ4 Rst_Wkup4 PA5 PAIRQ5 Rst_Wkup5 PA6 PAIRQ6 Rst_Wkup6 PA7 PAIRQ7 Rst_Wkup7 SPI OPA_Out SIN SOUT OPA_INP SIN Vref_out Timer clock CLOCK Timer start PWM output FrqOut strength t1ck0_in start1_in sig t2ck0_in start2_in sig t3ck0_in start4_in sig t4ck0_in start5_in sig XIN HD sig sig HD VLD SCLK sig HD VLD SOUT sig HD Note: on all bit of port A debouncers are enable by default after reset. 14.2 PORT A IO OPERATION All IO modes are individually selectable for each port A terminal. Refer to table below. Modes PAOE [n] PA[n] Output data PAOD[n] PAPU[n] PAPD[n] PAInpE[n] PA[n] Terminal Table 14.2-1 Port A IO selections Analog signal connection (in out) Analog signal connection (in out) with weak load to VDD or VSS 0 0 0 X X X X X X 0 1 0 0 X 1 0 0 0 High-Z RLoad to VDD RLoad to VSS Input mode 0 X X 0 0 1 High-Z Input mode with pull-up Input mode with pull-down Output, CMOS high level drive Output, CMOS low level drive 0 0 1 1 X X 1 0 X X 0 0 1 0 X X X 1 X X 1 1 X X Weak Hi Weak Lo 1 0 Output, open drain, high-Z 1 1 1 0 X X High-Z Output, open drain with pull-up Output, open drain low level drive 1 1 1 0 1 1 1 X X X X X Weak Hi 0 Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 69 Notes Digital input is blocked, Analog functions can be connected CPU reads ‘0’ Digital input, no-pull, needs external driver Digital input with pullup Digital input with pulldown Pull resistors disabled Pull resistors disabled Pull-down disabled, Usually ext Resistor pull-up Pull-up active Pull-up disabled www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x Figure 12; Port A IO configuration PA IO configuration architecture PAPU[n] ANALOG IO PAOD[n] 70 KOhm PADOut[n] clocks clocks clocks Read RegPADin PA[n] PA[n] output data PADIn[n] Data-bus PA[n]OutSel1,0 PA wake-up PAInpEn[n] Debouncer 70 KOhm PA[n]DebSel1,0 ck -clocked mode -transparent mode PAPD[n] PADeb[n] PA input data to: - timer - SPI - PA reset - PA-IRQ For maximum flexibility all Port A configuration bits are are fully user configurable. The pull resistors are only active if the pad driver is not driving the pad terminal, and pullup or pulldown resistors are enabled. Pullup has priority over pulldown. The CPU read of the port A terminal logic value (PA[n]) in register RegPADIn is depending of the PAInpEn blocking bit. As such one reads ‘0’ if PAInpEn=’0’ (Input blocked) and the terminal logic value if PAInpEn=’1’. At power-up, the PA[n] terminals are tristate with pullup and pulldown resistors disconnected and the input is disabled. As such all PA terminal can float without the penalty of additional power consumption. All PA input signal sources for Timer, SPI, PA-Reset, PA-IRQ are coming from the debouncer output PADeb[n]. Note: Make sure to setup the terminal correctly before using it as either digital IO or as an analog connection. Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 70 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 14.3 OUTPUT SIGNALS ON PORT A Different internal clock frequencies and PWM signals can be outout on all port A terminals. (PA[n] Output data) The selection is done with the registers PA[n]OutSel1,0 . All clock outputs (PR1_x, PR2_x) have a 50% duty cycle. The Clock outputs CK_x have a duty cycle corresponding to the duty cycle of their clock source. By default the register data PADOut[n] value is seleted as data output. Data is only output if the corresponding PAOutEn[n] bit is high. Table 14.3-1 Port AOutput signal selection PA0OutSel1 PA0OutSel0 PA0 Output Data remarks 0 0 PADOut[0] 0 1 PWM3_N 1 0 PWM2_N 1 1 PWM4_N PA1OutSel1 PA1OutSel0 PA1 Output Data remarks 0 0 PADOut[1] 0 1 Pr1Ck11 2kHz if CK_PR1=32kHz 1 0 PWM1 1 1 PWM2_N PA2OutSel1 PA2OutSel0 PA2 Output Data remarks 0 0 PADOut[2] 0 1 SOUT 1 0 PWM1 1 1 Ck_Hi PA3OutSel1 PA3OutSel0 PA3 Output Data remarks 0 0 PADOut[3] 0 1 Ck_Lo 1 0 Pr1Ck11 2kHz if CK_PR1=32kHz 1 1 Pr1Ck10 1kHz if CK_PR1=32kHz PA4OutSel1 PA4OutSel0 PA4 Output Data remarks 0 0 PA-DOut[4] 0 1 Ck_Hi_N 1 0 Pr2Ck6_N 125kHz if CK_PR2=2MHz 1 1 Pr2Ck4_N 31kHz if CK_PR2=2MHz PA5OutSel1 PA5OutSel0 PA5 Output Data remarks 0 0 PADOut[5] 0 1 PWM3 1 0 PWM2 1 1 PWM4 PA6OutSel1 PA6OutSel0 PA6 Output Data remarks 0 0 PADOut[6] 0 1 SCLK 1 0 PWM1_N 1 1 CK_8K PA7OutSel1 PA7OutSel0 PA7 Output Data remarks 0 0 PADOut[7] 0 1 SOUT 1 0 Pr1Ck11_N 2kHz if CK_PR1=32kHz 1 1 Pr1Ck10_N 1kHz if CK_PR1=32kHz Wheras: PWM3 = PWM output of timer 3 (refer to timer section) PWM3_N = inverse PWM output of timer 3 Ck_Lo = Low frequency base clock (refer to clock selection) CK_Lo_N = inverse Low frequency base clock Pr1Ck11 = Prescaler 1, ck11 output (refer to prescaler) Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 71 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 14.4 PORT A DEBOUNCER Each Port A input has its own debouncer with an independent clock selection. The debouncer is either transparent or clocked. The debouncer output signal is called PADeb[n] Transparent Mode: The input is immediately available on its output. Clocked mode: The debouncer copies is input state to its output only if during 2 consecutive debouncer clock events the debouncer input signal remains stable. The debouncer is reset on POR, in Power-Down mode, by a watchdog reset and a bus error reset. Table 14.4-1 Port A Debouncer Mode and Clock selection PA[n]DebSel1 0 0 1 1 PA[n]DebSel0 0 1 0 1 Clock Pr1Ck7 Pr1Ck15 Pr2Ck10 no clock Mode Clocked Clocked Clocked Transparent remarks Clocked; 128 Hz if ck_pr1=32kHz Clocked; Pr1 input clock Clocked; Pr2 input clock Output = Input 14.5 PORT A INTERRUPT GENERATION Each port A input may be used as Interrupt source with individual masking possibilities. 14.5.1 PA IRQ IN ACTIVE AND STANDBY MODE The clocked PortA interrupt is generated in the Active and Standby modes only. A positive or negative edge of the debouncer output signal PADeb[n] shall generate the IntPA[n]. The edge selection is done by the register bit PAIntEdg[n] (‘1’ means a positive edge and it’s the default state). The IntPA signal is the input to the interrupt controller.(refer to the interrupt controller for Irq masking and handling). All interrupt settings are independent for each PA input. 14.5.2 PA IRQ IN SLEEP MODE In Sleep mode, any edge (positive or negative) of the PA[n] input while PAInpEn[n]=1 will generate an IntPA request. The IntPA signal is the input to the interrupt controller.(refer to the interrupt controller for Irq masking and handling). All interrupt settings are independent for each PA input. 14.6 PORT A RESET FUNCTION Each port A input can be used to generate a system reset (ResSys in Reset controller). The Port A reset signal ResPA is a logical OR function of all PA input reset sources after masking. The input signals for the port A reset function are coming from the Port A debouncer output PADeb[n] and can be masked individually with RegEnResPA[n]=’0’ . Default: all inputs are masked and no PA reset is generated. The ResPA is the output of the port A reset function and the input signal to the reset controller. 14.7 PORT A WAKE-UP FUNCTION Each port A input can be used to wake-up the circuit from Power-Down mode. In Power-Down mode, any state change of a selected PA[n] input while its PAInpEn[n]=1 will cancel wake-up and resume to active mode. A PA[n] input is only selected for wake-up if its EnWkUp[n] bit is at high level. Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 72 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 14.8 PORT A REGISTERS 0x000A Bits Name 7:0 PADIn RegPADIn Type ResVal RO 0x00 ResSrc ResSys Port-A Data Input Description Port-A Data Input 0x000B Bits Name 7:0 PADOut RegPADOut Type ResVal RW_Res 0x00 ResSrc ResSys Port-A Data Output Description Port-A Data Output 0x000C Bits Name 7:0 PAInpE RegPAInpE Type ResVal RW_Res 0x00 ResSrc ResAna Port-A Input Enable Description Port-A Input Enable 0x000D Bits Name 7:0 PAOE RegPAOE Type ResVal RW_Res 0x00 ResSrc ResAna Port-A Output Enable Description Port-A Output Enable 0x000E Bits Name 7:0 PAPU RegPAPU Type ResVal RW 0x00 ResSrc PorLog Port-A Pull Up Description Port-A Pull Up 0x000F Bits Name 7:0 PAPD RegPAPD Type ResVal RW 0x00 ResSrc PorLog Port-A Pull Down Description Port-A Pull Down 0x0010 Bits Name 7:0 PAOD RegPAOD Type ResVal RW 0x00 ResSrc ResSys Port-A Open Drain Description Port-A Open Drain 0x0015 RegPAIntEdg Bits 7:0 Type RW ResVal 0xFF ResSrc ResSys Port-A Interrupt Edge Selection: 1-Rising, 0-Falling Description Port-A Interrupt Edge Selection: 1-Rising, 0-Falling 0x0011 Bits Name 7:6 PA3OutSel 5:4 PA2OutSel 3:2 PA1OutSel 1:0 PA0OutSel RegPAOutCfg0 Type ResVal RW ‘00’ RW ‘00’ RW ‘00’ RW ‘00’ ResSrc ResSys ResSys ResSys ResSys Port-A Output Configuration/Selection - 0 Description Port-A3 Output Configuration/Selection Port-A2 Output Configuration/Selection Port-A1 Output Configuration/Selection Port-A0 Output Configuration/Selection 0x0012 Bits Name 7:6 PA7OutSel 5:4 PA6OutSel 3:2 PA5OutSel 1:0 PA4OutSel RegPAOutCfg1 Type ResVal RW ‘00’ RW ‘00’ RW ‘00’ RW ‘00’ ResSrc ResSys ResSys ResSys ResSys Port-A Output Configuration/Selection - 1 Description Port-A7 Output Configuration/Selection Port-A6 Output Configuration/Selection Port-A5 Output Configuration/Selection Port-A4 Output Configuration/Selection 0x0013 Bits Name 7:6 PA3DebSel 5:4 PA2DebSel 3:2 PA1DebSel 1:0 PA0DebSel RegPADebCfg1 Type ResVal RW ‘00’ RW ‘00’ RW ‘00’ RW ‘00’ ResSrc ResAna ResAna ResAna ResAna Port-A Deboucer Configuration - 1 Description PA(3) Deboucer clock Selection/Enable PA(2) Deboucer clock Selection/Enable PA(1) Deboucer clock Selection/Enable PA(0) Deboucer clock Selection/Enable Name PAIntEdg Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 73 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 0x0014 Bits Name 7:6 PA7DebSel 5:4 PA6DebSel 3:2 PA5DebSel 1:0 PA4DebSel RegPADebCfg2 Type ResVal RW ‘00’ RW ‘00’ RW ‘00’ RW ‘00’ ResSrc ResAna ResAna ResAna ResAna Port-A Deboucer Configuration - 2 Description PA(7) Deboucer clock Selection/Enable PA(6) Deboucer clock Selection/Enable PA(5) Deboucer clock Selection/Enable PA(4) Deboucer clock Selection/Enable 0x0001 Bits Name 7:0 EnResPA RegEnResPA Type ResVal RW 0x00 ResSrc ResAna Enable Reset by PortA bits Description Enable Reset by PortA bits 0x0002 Bits Name 7:0 EnWkUpPA RegEnWkUpPA Type ResVal RW 0x00 ResSrc ResSys Enable of Wake Up from Power-Down by PortA Description Enable of Wake Up from Power-Down by PA bits Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 74 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 15. PORT B The port B is general purpose 8-bit input output port. Each of the 8 Port B terminals can be configured to receive either Analog or digital Input or drive out analog or digital data. The port B, PB7 and PB6 terminals, are special inputs for device programming and debugging. These 2 ports will have special configurations as soon as TM terminal is high to allow Gasp (ISP, DoC) accesses. 15.1 PORT B TERMINAL MAPPING Several digital and analog functions are mapped on the port B terminals. Please refer also to the concerned chapters. Table 15.1-1 Port B terminal mapping Name IRQ ADC Reset & VREF WkUp VLD OPAMP SPI PB0 GASP CLOCK Timer clock SIN PB1 PB2 SCLK PB3 PB4 SOUT PB5 Timer start PWM output FrqOut strength sig HD sig HD sig HD sig HD sig HD sig HD PB6 GASP-SCK sig HD PB7 GASP-SIO sig HD 15.2 PORT B IO OPERATION All IO modes are individually selectable for each port B terminal. Refer to table below. Modes PBOE [n] PB[n] Output data PBOD[n] PBPU[n] PBPD[n] PBInpE[n] PB[n] Terminal Table 15.2-1 Port B IO selections Analog signal connection (in out) Analog signal connection (in out) with weak load to VDD or VSS 0 0 0 X X X X X X 0 1 0 0 X 1 0 0 0 High-Z RLoad to VDD RLoad to VSS Input mode 0 X X 0 0 1 High-Z Input mode with pull-up Input mode with pull-down Output, CMOS high level drive Output, CMOS low level drive 0 0 1 1 X X 1 0 X X 0 0 1 0 X X X 1 X X 1 1 X X Weak Hi Weak Lo 1 0 Output, open drain, high-Z 1 1 1 0 X X High-Z Output, open drain with pull-up Output, open drain drive low 1 1 1 0 1 1 1 X X X X X Weak Hi 0 Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 75 Notes Digital input is blocked, Analog functions can be connected CPU reads ‘0’ Digital input, no-pull, needs external driver Digital input with pullup Digital input with pulldown Pull resistors disabled Pull resistors disabled Pull-down disabled, Usually ext Resistor pull-up Pull-up active Pull-up disabled www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x Figure 13; Port B IO configuration PB IO configuration architecture PBPU[n] PBOD[n] 70 KOhm PBDOut[n] clocks clocks clocks Read RegPBDin PB[n] PB[n] output data PBDIn[n] Data-bus PB[n]OutSel1,0 PBInpEn[n] 70 KOhm PBPD[n] For maximum flexibility all Port B configuration bits are are fully user configurable. The pull resistors are only active if the pad driver is not driving the pad terminal, and pullup or pulldown resistors are enabled. Pullup has priority over pulldown. The CPU read of the port B terminal logic value (PB[n]) in register RegPBDIn is depending of the PBInpEn blocking bit. As such one reads ‘0’ if PBInpEn=’0’ (Input blocked) and the terminal logic value if PBInpEn=’1’. At power-up, the PB[n] terminals are tristate with pullup and pulldown resistors disconnected and the input is disabled. As such all PB terminal can float without the penalty of additional power consumption. Note: Make sure to setup the terminal correctly before using it.. 15.2.1 GASP COMMUNICATION ON PB7, PB6 As soon as TM terminal becomes high the terminal PB7 and PB6 configurations are forced by the Gasp module without altering the port B register settings. Gasp mode has priority over normal IO mode on these 2 terminals. Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 76 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 15.3 OUTPUT SIGNALS ON PORT B Different internal clock frequencies and PWM signals can be outout on all port B terminals. (PB[n] Output data) The selection is done with the registers PB[n]OutSel1,0 . All clock outputs (Pr1ckx, Pr2ckx) have a 50% duty cycle. The Clock outputs CK_x have a duty cycle corresponding to the duty cycle of their clock source. By default the register data PBDOut[n] value is seleted as data output. Data is only output if the corresponding PBOutEn[n] bit is high. Table 15.3-1 Port B Output signal selection remarks PB0OutSel1 PB0OutSel0 PB0 Output Data 0 0 PBDOUT[0] 0 1 PWM3 1 0 PWM2 1 1 PWM4 remarks PB1OutSel1 PB1OutSel0 PB1 Output Data 0 0 PBDOUT[1] 0 1 PWM3_N 1 0 PWM2_N 1 1 PWM4_N remarks PB2OutSel1 PB2OutSel0 PB2 Output Data 0 0 PBDOUT[2] 0 1 SCLK 1 0 PWM1 1 1 PWM3 remarks PB3OutSel1 PB3OutSel0 PB3 Output Data 0 0 PBDOUT[3] 0 1 CK_Hi 1 0 PWM1_N 1 1 PWM3_N remarks PB4OutSel1 PB4OutSel0 PB4 Output Data 0 0 PBDOUT[4] 0 1 SOUT 1 0 PWM1 1 1 PWM3 remarks PB5OutSel1 PB5OutSel0 PB5 Output Data 0 0 PBDOUT[5] 0 1 PWM3 1 0 PWM2 1 1 PWM4 remarks PB6OutSel1 PB6OutSel0 PB6 Output Data 0 0 PBDOUT[6] 0 1 PWM1_N 1 0 PWM3_N 1 1 Pr1Ck11 2kHz if CK_PR1=32kHz remarks PB7-OutSel1 PB7-OutSel0 PB7 Output Data 0 0 PBDOUT[7] 0 1 PWM1 1 0 PWM3 1 1 Pr1Ck10 1kHz if CK_PR1=32kHz Wheras: PWM3 = PWM output of timer 3 (refer to timer section) PWM3_N = inverse PWM output of timer 3 Ck_Hi = High frequency base clock (refer to clock selection) Pr1Ck10 = Prescaler 1, ck10 output (refer to prescaler) Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 77 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 15.4 PORT B REGISTERS 0x0016 Bits Name 7:0 PBDIn RegPBDin Type ResVal RO 0x00 ResSrc ResSys Port-B Data Input Description Port-B Data Input 0x0017 Bits Name 7:0 PBDOut RegPBDOut Type ResVal RW_Res 0x00 ResSrc ResSys Port-B Data Output Description Port-B Data Output 0x0018 Bits Name 7:0 PBInpE RegPBInpE Type ResVal RW_Res 0x00 ResSrc ResSys Port-B Input Enable Description Port-B Input Enable 0x0019 Bits Name 7:0 PBOE RegPBOE Type ResVal RW_Res 0x00 ResSrc ResSys Port-B Output Enable Description Port-B Output Enable 0x001A Bits Name 7:0 PBPU RegPBPU Type ResVal RW_Res 0x00 ResSrc PorLog Port-B Pull Up Description Port-B Pull Up 0x001B Bits Name 7:0 PBPD RegPBPD Type ResVal RW_Res 0x00 ResSrc PorLog Port-B Pull Down Description Port-B Pull Down 0x001C Bits Name 7:0 PBOD RegPBOD Type ResVal RW_Res 0x00 ResSrc ResSys Port-B Open Drain Description Port-B Open Drain 0x001D Bits Name 7:6 PB3OutSel 5:4 PB2OutSel 3:2 PB1OutSel 1:0 PB0OutSel RegPBOutCfg0 Type ResVal RW '00' RW '00' RW '00' RW '00' ResSrc ResSys ResSys ResSys ResSys Port-B Output Configuration/Selection - 0 Description Port-B3 Output Configuration/Selection Port-B2 Output Configuration/Selection Port-B1 Output Configuration/Selection Port-B0 Output Configuration/Selection 0x001E Bits Name 7:6 PB7OutSel 5:4 PB6OutSel 3:2 PB5OutSel 1:0 PB4OutSel RegPBOutCfg1 Type ResVal RW '00' RW '00' RW '00' RW '00' ResSrc ResSys ResSys ResSys ResSys Port-B Output Configuration/Selection - 1 Description Port-B7 Output Configuration/Selection Port-B6 Output Configuration/Selection Port-B5 Output Configuration/Selection Port-B4 Output Configuration/Selection Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 78 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 16. PORT C The port C is general purpose 8-bit input output port. Each of the 8 Port C terminals can be configured to receive either Analog or digital Input or drive out analog or digital data. 16.1 PORT C TERMINAL MAPPING Several digital and analog functions are mapped on the port C terminals. Please refer also to the concerned chapters. Table 16.1-1 Port C terminal mapping Name IRQ ADC Reset & VREF VLD WkUp OPAMP SPI Timer clock CLOCK PC0 PCIRQ0 ADC1 PC1 PCIRQ1 ADC3 PC2 PAIRQ2 ADC5 OPA_INM SOUT PC3 PCIRQ3 ADC7 OPA_INP PC4 PCIRQ4 PC5 PCIRQ5 VLD PC6 PCIRQ6 VLD PC7 PCIRQ7 Timer start PWM output FrqOut strength sig VLD OPA_Out t2ck1_in start3_in sig sig t4ck1_in start6_in XOUT ExtCk SCLK sig HD sig sig HD t1ck1_in start7_in sig HD t3ck1_in sig 16.2 PORT C IO OPERATION All IO modes are individually selectable for each port C terminal. Refer to table below. Modes PCOE [n] PC[n] Output data PCOD[n] PCPU[n] PCPD[n] PCInpE[n] PC[n] Terminal Table 16.2-1 Port C IO selections Analog signal connection (in out) Analog signal connection (in out) with weak load to VDD or VSS 0 0 0 X X X X X X 0 1 0 0 X 1 0 0 0 High-Z RLoad to VDD RLoad to VSS Input mode 0 X X 0 0 1 High-Z Input mode with pull-up Input mode with pull-down Output, CMOS high level drive Output, CMOS low level drive 0 0 1 1 X X 1 0 X X 0 0 1 0 X X X 1 X X 1 1 X X Weak Hi Weak Lo 1 0 Output, open drain, high-Z 1 1 1 0 X X High-Z Output, open drain with pull-up Output, open drain drive low 1 1 1 0 1 1 1 X X X X X Weak Hi 0 Notes Digital input is blocked, Analog functions can be connected CPU reads ‘0’ Digital input, no-pull, needs external driver Digital input with pullup Digital input with pulldown Pull resistors disabled Pull resistors disabled Pull-down disabled, Usually ext Resistor pull-up Pull-up active Pull-up disabled Note: on all bit of port C debouncers are enable by default after reset, Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 79 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x Figure 14; Port C IO configuration PC IO configuration architecture PCPU[n] ANALOG IO PCOD[n] 70 KOhm PCDOut[n] clocks clocks clocks Read RegPADin PC[n] PA[n] output data PADIn[n] Data-bus PC[n]OutSel1,0 PCInpEn[n] 70 KOhm PC[n]DebSel1,0 ck Debouncer PCDeb[n] -clocked mode -transparent mode PC input data to: - timer - SPI - PC-IRQ PCPD[n] For maximum flexibility all Port C configuration bits are are fully user configurable. The pull resistors are only active if the pad driver is not driving the pad terminal, and pullup or pulldown resistors are enabled. Pullup has priority over pulldown. The CPU read of the port C terminal logic value (PC[n]) in register RegPCDIn is depending of the PCInpEn blocking bit. As such one reads ‘0’ if PCInpEn=’0’ (Input blocked) and the terminal logic value if PCInpEn=’1’. At power-up, the PC[n] terminals are tristate with pullup and pulldown resistors disconnected and the input is disabled. As such all PC terminal can float without the penalty of additional power consumption. All PC input signal sources for Timer, SPI, PC-IRQ are coming from the debouncer output PCDeb[n]. Note: Make sure to setup the terminal correctly before using it as either digital IO or as an analog connection. Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 80 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 16.3 OUTPUT SIGNALS ON PORT C Different internal clock frequencies and PWM signals can be outout on all port C terminals. (PA[n] Output data) The selection is done with the registers PC[n]OutSel1,0 . All clock outputs (Pr1ckx, Pr2ckx) have a 50% duty cycle. The Clock outputs CK_x have a duty cycle corresponding to the duty cycle of their clock source. By default the register data PCDOut[n] value is seleted as data output. Data is only output if the corresponding PCOutEn[n] bit is high. Table 16.3-1 Port C Output signal selection remarks PC0OutSel1 PC0OutSel0 PC0 Output Data 0 0 PCDOUT[0] 0 1 Pr2Ck6 125kHz if CK_PR2=2MHz 1 0 Pr2Ck4 31kHz if CK_PR2=2MHz 1 1 Pr2Ck0 2kHz if CK_PR2=2MHz remarks PC1OutSel1 PC1OutSel0 PC1 Output Data 0 0 PCDOUT[1] 0 1 PWM4_N 1 0 PWM1_N 1 1 PWM3_N remarks PC2OutSel1 PC2OutSel0 PC2 Output Data 0 0 PCDOUT[2] 0 1 SOUT 1 0 PWM1_N 1 1 Ck_Lo remarks PC3OutSel1 PC3OutSel0 PC3 Output Data 0 0 PCDOUT[3] 0 1 CK_LO_N 1 0 Pr1Ck11_N 2kHz if CK_PR1=32kHz 1 1 Pr1Ck10_N 1kHz if CK_PR1=32kHz remarks PC4OutSel1 PC4OutSel0 PC4 Output Data 0 0 PCDOUT[4] 0 1 Ck_Hi 1 0 Pr2Ck6 125kHz if CK_PR2=2MHz 1 1 Pr2Ck4 31kHz if CK_PR2=2MHz remarks PC5OutSel1 PC5OutSel0 PC5 Output Data 0 0 PCDOUT[5] 0 1 CK_8K 1 0 Pr2Ck6 125kHz if CK_PR2=2MHz 1 1 Pr2Ck4 31kHz if CK_PR2=2MHz remarks PC6OutSel1 PC6OutSel0 PC6 Output Data 0 0 PCDOUT[6] 0 1 SCLK 1 0 PWM1_N 1 1 ck_lo remarks PC7OutSel1 PC7OutSel0 PC7 Output Data 0 0 PCDOUT[7] 0 1 PWM1 1 0 PWM3_N 1 1 Pr1Ck12 4kHz if CK_PR1=32kHz Wheras: PWM1 = PWM output of timer 1 (refer to timer section) PWM1_N = inverse PWM output of timer 1 Ck_Hi = High frequency base clock (refer to clock selection) Pr1Ck12 = Prescaler 1, ck12 output (refer to prescaler) Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 81 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 16.4 PORT C DEBOUNCER Each Port C input has its own debouncer with an independent clock selection. The debouncer is either transparent or clocked. The debouncer output signal is called PCDeb[n]. Transparent Mode: The input is immediately available on its output. Clocked mode: The debouncer copies is input state to its output only if during 2 consecutive debouncer clock events the debouncer input signal remains stable. The debouncer is reset on POR, in Power-Down mode, by a watchdog reset and a bus error reset. Table 16.4-1 Port C Debouncer Mode and Clock selection PC[n]DebSel1 PC[n]DebSel0 Clock 0 0 Pr1Ck7 0 1 Pr1Ck15 1 0 Pr2Ck10 1 1 no clock Mode Clocked Clocked Clocked Transparent remarks Clocked; 128 Hz if ck_pr1=32kHz Clocked; Pr1 input clock Clocked; Pr2 input clock Output = Input 16.5 PORT C INTERRUPT GENERATION Each port C input may be used as Interrupt source with individual masking possibilities. 16.5.1 PC IRQ IN ACTIVE AND STANDBY MODE The clocked port C interrupt is generated in the Active and Standby modes only. A positive or negative edge of the debouncer output signal PCDeb[n] shall generate the IntPC[n] interrupt request. The edge selection is done by the register bit PCIntEdg[n] (‘1’ means a positive edge and it’s the default state). The IntPC signal is the input to the interrupt controller. (Refer to the interrupt controller for Irq masking and handling). All interrupt settings are independent for each PC input. 16.5.2 PC IRQ IN SLEEP MODE There is no port C interrupt possibility in Sleep mode. Port C interrupt input will automatically switch to the corresponding port A in Sleep mode. Refer also to the interrupt controller section 10 Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 82 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 16.6 PORT C REGISTERS 0x001F Bits Name 7:0 PCDIn RegPCDin Type ResVal RO 0x00 ResSrc ResSys Port-C Data Input Description Port-C Data Input 0x0020 Bits Name 7:0 PCDOut RegPCDOut Type ResVal RW_Res 0x00 ResSrc ResSys Port-C Data Output Description Port-C Data Output 0x0021 Bits Name 7:0 PCInpE RegPCInpE Type ResVal RW_Res 0x00 ResSrc ResSys Port-C Input Enable Description Port-C Input Enable 0x0022 Bits Name 7:0 PCOE RegPCOE Type ResVal RW_Res 0x00 ResSrc ResSys Port-C Output Enable Description Port-C Output Enable 0x0023 Bits Name 7:0 PCPU RegPCPU Type ResVal RW_Res 0x00 ResSrc PorLog Port-C Pull Up Description Port-C Pull Up 0x0024 Bits Name 7:0 PCPD RegPCPD Type ResVal RW_Res 0x00 ResSrc PorLog Port-C Pull Down Description Port-C Pull Down 0x0025 Bits Name 7:0 PCOD RegPCOD Type ResVal RW_Res 0x00 ResSrc ResSys Port-C Open Drain Description Port-C Open Drain 0x002A RegPCIntEdg Bits 7:0 Type RW ResVal 0xFF ResSrc ResSys Port-C Interrupt Edge Selection: 1-Rising, 0-Falling Description Port-C Interrupt Edge Selection: 1-Rising, 0-Falling 0x0026 Bits Name 7:6 PC3OutSel 5:4 PC2OutSel 3:2 PC1OutSel 1:0 PC0OutSel RegPCOutCfg0 Type ResVal RW '00' RW '00' RW '00' RW '00' ResSrc ResSys ResSys ResSys ResSys Port-C Output Configuration/Selection - 0 Description Port-C3 Output Configuration/Selection Port-C2 Output Configuration/Selection Port-C1 Output Configuration/Selection Port-C0 Output Configuration/Selection 0x0027 Bits Name 7:6 PC7OutSel 5:4 PC6OutSel 3:2 PC5OutSel 1:0 PC4OutSel RegPCOutCfg1 Type ResVal RW '00' RW '00' RW '00' RW '00' ResSrc ResSys ResSys ResSys ResSys Port-C Output Configuration/Selection - 1 Description Port-C7 Output Configuration/Selection Port-C6 Output Configuration/Selection Port-C5 Output Configuration/Selection Port-C4 Output Configuration/Selection 0x0028 Bits Name 7:6 PC3DebSel 5:4 PC2DebSel 3:2 PC1DebSel 1:0 PC0DebSel RegPCDebCfg1 Type ResVal RW '00' RW '00' RW '00' RW '00' ResSrc ResSys ResSys ResSys ResSys Port-C Deboucer Configuration - 1 Description PC(3) Deboucer clock Selection/Enable PC(2) Deboucer clock Selection/Enable PC(1) Deboucer clock Selection/Enable PC(0) Deboucer clock Selection/Enable Name PCIntEdg Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 83 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 0x0029 Bits Name 7:6 PC7DebSel 5:4 PC6DebSel 3:2 PC5DebSel 1:0 PC4DebSel RegPCDebCfg2 Type ResVal RW '00' RW '00' RW '00' RW '00' Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 ResSrc ResSys ResSys ResSys ResSys 84 Port-C Deboucer Configuration - 2 Description PC(7) Deboucer clock Selection/Enable PC(6) Deboucer clock Selection/Enable PC(5) Deboucer clock Selection/Enable PC(4) Deboucer clock Selection/Enable www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 17. TIMERS The circuit contains 4 independent 8-bit timers configurable as 2 16-bit timers. Each of it can be individually configured with: 6 internal clock sources and 2 external clock sources from PA, PC terminals Individual Start/Stop selection by SW or from various IO terminals Timer interrupt selection Auto-reload(free-running) and Auto-Stop mode Input Capture on hardware events (terminal input) or SW driven Output Compare for signal generation PWM and Frequency output RTZ, RTO output clock capabilities Timer outputs mapping on various IO terminals Always also provides complementary level output to increase overall voltage swing. The timers are implemented as up-counters, counting from 0x00 to RegTimXFull or as a free running counter cycling from 0x00 to RegTimXFull. If the full value changes while the timer is running, the previous full value will be used for the full event detection. The new full value will be used for the next counting cycle. The timer status value (actual count value) is readable in registers RegTimXStatus. 17.1 TIMER CHAINING Possible configurations are: Timer1, Timer2, Timer3, Timer4 used independently Timer1 and Timer2 chained together (Timer12); Timer3 and Timer 4 used independently Timer1 and Timer2 used independently; Timer3 and Timer4 chained (=Timer34) Timer1 and Timer2 chained together (Timer12); Timer3 and Timer4 chained (=Timer34) Timer1 and Timer2 are chained and able to work as 16-bits timer when Tim12Chain in RegTimersCfg is high. In this case, the configuration is set by the Timer1 and Timer2 (slave) is the MSB. Timer3 and Timer4 are chained and able to work as 16-bits timer when Tim34Chain in RegTimersCfg is high. In this case, the configuration is set by the Timer3 and Timer4 (slave) is the MSB. Figure 15, Timer chaining Timer 1, 2, 3, 4 - HW/SW start-stop - clock source selection - Autoreload mode - Input Capure - Output Compare PWM , Freq Gen Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 Timer12 (16 bit) Timer1 8 bit Timer2 8 bit Timer3 8 bit Timer4 8 bit 85 Timer1 Timer2 LSB MSB Timer34 (16 bit) Timer3 Timer4 LSB MSB www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 17.2 TIMER CLOCK SOURCES The timer clock inputs connect directly to the prescaler1 and prescaler2 outputs. The prescalers themselves connect to Ck_Hi or Ck_Lo which are derived from the internal RC oscillators or the external clock sources from XTAL, Resonator or PC4 input. Please refer to the chapter Clock selection and Clock switching for more details about the basic clock setup. Additionaly to the prescaler clock sources the timers may also run on 2 external clocks sources, one from PA the other from PC. The clock source selection is done in registers RegTimXCfg bits TimXSelClk as follows (X stands for 1,2,3,4) Table 17.2-1 Timer clock configuration Tim1SelClk Timer1, Tim2SelClk Timer2 Tim3SelClk Timer3, Tim4SelClk Timer4 [2:0] Timer12 [2:0] [2:0] Timer34 [2:0] 000 PA0 000 PA1 000 PA2 000 PA3 001 PC6 001 PC1 001 PC7 001 PC3 010 Pr2Ck10 010 Pr2Ck10 010 Pr2Ck10 010 Pr2Ck10 011 Pr2Ck8 011 Pr1Ck15 011 Pr2Ck8 011 Pr1Ck15 100 Pr2Ck6 100 Pr1Ck14 100 Pr2Ck4 100 Pr1Ck13 101 Pr1Ck15 101 Pr1Ck12 101 Pr1Ck15 101 Pr1Ck11 110 Pr1Ck13 110 Pr1Ck10 110 Pr1Ck13 110 Pr1Ck9 111 Pr1Ck11 111 Pr1Ck8 111 Pr1Ck9 111 Pr1Ck7 Maximal external timer input clock frequency must be lower than to Ck_Hi/2 or Ck_Lo/2 if Ck_Hi is not used. Table 17.2-2 Timer clock configuration overview (decimal values of TimXSelClk) TimXSelClk Tim1-Ck, Tim3-Ck Tim2-Ck Tim4-Ck [2:0] Tim12-Ck Tim34-Ck Timer ck selection to Prescaler 1 freq Pr1Ck15 5 3 5 3 Pr1Ck14 4 Pr1Ck13 6 6 4 Pr1Ck12 5 Pr1Ck11 7 5 Pr1Ck10 6 Pr1Ck9 7 6 Pr1Ck8 7 Pr1Ck7 7 Timer ck selection to Prescaler 2 freq Pr2Ck10 2 2 2 2 Pr2Ck9 Pr2Ck8 3 3 Pr2Ck7 Pr2Ck6 4 Pr2Ck5 Pr2Ck4 4 Timer ck selection to PA input clocks PA[0] 0 PA[1] 0 PA[2] 0 PA[3] 0 PC[1] 1 PC[3] 1 PC[6] 1 PC[7] 1 Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 86 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 17.3 TIMER START The timers can be started and stopped by SW or hardware events. To be able to start the RegTimXFull value must not be equal to 0x00. All timer settings must be performed before starting the timer. The timer start and stop selection are done in registers RegTimXCfg bits TimXSelStart as follows: Table 17.3-1 Timer start selection TimXSelStart Timer1, Timer3, Timer2 Timer4 [2:0] Timer12 Timer34 000 SW start SW start SW start SW start Hardware start - stop selections 001 010 011 100 101 110 111 PA0 PA1 PC1 PA2 PA3 PC3 PC6 PA0 PA1 PC1 PA2 PA3 PC3 PC6 PA0 PA1 PC1 PA2 PA3 PC3 PC6 PA0 PA1 PC1 PA2 PA3 PC3 PC6 Notes: External start/stop signal must be glitch free and debouncer must be used to ensure that no glitch is propagated to the timer When the debouncer is used, then start/stop pulse width should be longer than two clock periods of the debouncer, otherwise incoming pulse is suppressed. Minimal pulse width of external start/stop signal has to be longer than one timer clock period when debouncer is bypassed. Figure 16, Timer SW and Hardware (Pulse, Period) Start-Stop Hardware Start – Stop Control Software Start – Stop Control Pulse Start TimXSWStart HI-Level Start TimX-Ck TimX-Ck TimXStatus 0 1 2 3 4 5 SW-Start 6 7 TimXStatus SW-Stop 0 HW-Start 1 2 3 4 5 6 7 HW-Stop 17.3.1 SOFTWARE START - STOP In case of software start selection (TimXSelStart=’000’) the timers will start counting from 0x00 as soon as TimXSWStart in RegTimersStart goes to high level. When TimXSWStart goes to low level, the timerX will stop counting and RegTimXStatus keeps its status value. 17.3.2 HARDWARE START – STOP (PERIOD COUNTING) In case of hardware start selection (TimXSelStart <> 000) and TimXPulse in RegTimersStart is high, the timer will start counting from 0x00 as soon as the selected external start input ExtTimXStart goes to high level. When another pulse occurs on ExtTimXStart, timerX shall stop to count and RegTimXStatus keeps its status. Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 87 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x Notes: External start/stop period must be glitch free and debouncer must be used to ensure that no glitch is propagated to the timer When the debouncer is used then the pulses width (pulse at ‘1’ and pulse at ‘0’ of PXDIn) should be longer than two clock periods of the debouncer, (otherwise incoming pulse is suppressed). When the debouncer is bypassed, the period of the measured signal (PXDeb) has to be longer than one timer clock period: the timer is able to count the period of the incoming signal if its period is longer than one timer clock period (otherwise the timer is reloaded only). These two conditions need to be fulfilled when the debouncer is enabled and external period needs to be measured (Refer to Figure 12; Port A IO configuration and Figure 14; Port C IO configuration) 17.3.3 HARDWARE START – STOP (PULS COUNTING) In case of hardware start selection (TimXSelStart <> ‘000’) and TimXPulse in RegTimersStart is low, the timer will start counting from 0x00 on the first positive pulse on the selected external start input ExtTimXStart. When ExtTimXStart goes back to low level, timerX will stop to count and RegTimXStatus keeps its status. Notes: External start/stop pulse must be glitch free and debouncer must be used to ensure that no glitch is propagated to the timer When the debouncer is used then the pulse width (PXDIn) should be longer than two clock periods of debouncer (otherwise incoming pulse is suppressed) When the debouncer is bypassed, the start/stop signal pulse width (pulse measurement of PXDeb) has to be longer than one timer clock period: the timer is able to count the pulse width of the incoming signal if its width is longer than one timer clock period (otherwise the timer is reloaded only). These two conditions need to be fulfilled when the debouncer is enabled and external pulse width needs to be measured (Refer to Figure 12; Port A IO configuration and Figure 14; Port C IO configuration) Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 88 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 17.4 AUTO-RELOAD MODE In autoreload mode the timerX always restart counting from 0x00 once its status reaches TimXFull value. It will act as a free running counter. Going into Auto-reload mode: By setting the corresponding TimXAR bit in register RegTimersCfg at high level. Canceling Auto-Reload mode By a sytem reset, stopp immediately, TimXStatus cleared. By a removed start condition, stopp immediately, TimXStatus maintained. By TimXAR written to ‘0’, stopp after reaching TimXFull value. Figure 17, Sample waveforms in Auto-Reload mode Software start, Auto-Reload Auto-Stop TimXFull = 2 Software start, Auto-Reload TimXFull = 2 TimXAR TimXAR TimXSWStart TimXSWStart TimX-Ck TimX-Ck TimXStatus Old value 0 1 2 0 1 2 Start-up Period (min) = TimXFull AR-Period (min) = TimXFull Start-upPeriod (max) = TimXFull + 1 SW-Start Auto-Reload 0 1 2 0 TimXStatus Old value 0 1 2 0 1 2 Start-up Period (min) = TimXFull AR-Period (min) = TimXFull Start-upPeriod (max) = TimXFull + 1 AR-Period (min) = TimXFull Auto-Reload SW-Start Auto-Reload 0 1 2 Last Period (min) = TimXFull Auto-Reload Auto-Stop 17.5 AUTO-STOP MODE In auto-stop mode the timerX counts from 0x00 until it reaches TimXFull value. Going into Auto-Stop mode: By setting the corresponding TimXAR bit in register RegTimersCfg at low level. Stopping the timer By a sytem reset, stopp immediately, TimXStatus cleared. Removed Start condition, stopp immediately, TimXStatus maintained. The timerX automatically stopps when reaching TimXFull value. Figure 18, Sample waveforms in Auto-Stop mode Software start Auto-Stop TimXFull = 8 TimXAR PA0 TimXSWStart TimXSWStart TimX-Ck TimX-Ck TimXStatusOld value 0 SW-Start 1 2 3 4 5 Period (min) = TimXFull Period (max) = TimXFull + 1 Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 6 7 8 Hardware start with PA0 high level Auto-Stop TimXFull = 8 TimXAR TimXStatus Auto-Stop Old value 0 HW-Start 89 1 2 3 4 5 Period (min) = TimXFull Period (max) = TimXFull + 1 6 7 8 Auto-Stop www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 17.6 TIMER INPUT CAPTURE The input capture system allows taking a timer snapshot based on an internal SW event or an external hardware event by writing the timer status value into the capture register at the occurrence of the capture event. An Interrupt IntTimX is generated on all active hardware capture events. Capture events are ignored if the timer is not running. Valid capture events are: Software SW capture (on Timer1, Timer12, Timer3 and Timer34 only) Hardware capture on all timers, Falling edge Hardware capture on all timers, Rising edge Hardware Capture on all timers, Both edges In SW capture, the event is generated by writing ‘1’ to the bit Tim1SWCpt in register RegTimersCfg.Tim1SWCpt Timer3 by wiriting ‘1’ to the bit Tim3SWCpt in register RegTimersCfg.Tim3SWCpt. In hardware capture the active capture inputs are selected in register RegTimXCptCmpCfg bits TimXCptCptEvtSrc as follows: Tim1CptEvtSrc[1:0] External event Tim2CptEvtSrc[1:0] External event 00 PA2 00 PA2 01 COMP 01 PA1 10 VLD 10 PA3 11 PA1 11 VLD Tim3CptEvtSrc[1:0] 00 01 10 11 External event PA2 COMP PC4 PA3 Tim4CptEvtSrc[1:0] 00 01 10 11 External event PC7 PC0 PA0 VLD In hardware caputure the active edge(s) of the selected event source is defined by register RegTimXCptCmpCfg bits TimXCptEdg as follows: TimXCptEdg Selected edge for event signal 00 no action 01 falling edge 10 rising egde 11 both edges Figure 19, Input Capture Architecture Timer Capture Configuration TimXCptEdg[1:0] TimXCptEvtSrc[1:0] X = 1,2,3,4 CptEvtSrc0 0 CptEvtSrc1 1 CptEvtSrc2 MUX 2 4:1 CptEvtSrc3 3 X = 1,2,3,4 Edge detector Rising edge Edge detector Falling edge Edge detector both edges CptXInt 0 1 MUX 2 4:1 RegTimXStatus TimX-Ck ck 3 load RegTimXCptVal Software Capture via TimXSWCpt X = 1,3 Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 90 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x Notes: External input capture event must be glitch free and debouncer must be used to ensure that no glitch is propagated to the timer When the debouncer is used then the pulse width of external capture signal (PXDIn) should be longer than two clock periods of the debouncer (otherwise incoming pulse is suppressed) When the debouncer is bypassed then the pulse width of external capture signal (PXDeb) has to be longer than one timer clock period (otherwise an invalid value could be loaded to the capture register) These two conditions need to be fulfilled when the debouncer is enabled and external input capture event need to be captured (Refer to Figure 12; Port A IO configuration and Figure 14; Port C IO configuration) Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 91 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 17.7 OUTPUT COMPARE Figure 20, Output Compare Description The output compare function allows generating a multitude of different output signal waveforms. PWM, variable or fix frequencies, RTZ (Return To Zero clocks), RTO (Return To One clocks) to name just a few. It may also be used to encode serial protocols i.e Manchester encoding. The compare function is enabled by setting bit TimXEnPWM in register RegTimXCfg to ‘1’. Full value (CmpFull) PWM, RTZ, RTO 0 1 or several compares within the fix load period Successive compare value (CmpVal) Auto-Reload mode The compare function uses the PWMX signal of the timer. At system reset PWMX is forced low. PWMX will maintain its last status when the corresponding TimXEnPWM =’0’. Whenever the timer reaches RegTimXFull or RegTimXCmpVal an action may be performed on PWMX. The action is defined by TimXCmpFullAct when it reaches RegTimXFull and by TimXCmpValAct when it reaches RegTimXCmpVal as defined in tables below: (TimXCmpFullAct action has a priority). CmpFull: counter value = full value 1st compare value (CmpVal) CmpVal: counter value = compare value Full Period = full value + 1 Ratio = compare value / (full value + 1) Full value + 1 Successive compare Compare value Possible signal transitions CmpXVal Successive comparisons may be made. CmpXFull Output compare usually is used in Auto-Reload mode (free running counter). TimXCmpValAct TimXCmpFullAct 00 Action when timerX reaches RegTimXCmpVal No action on PWMX 00 Action when timerX reaches RegTimXFull No action on PWMX 01 10 11 Force 0 on PWMX Force 1 on PWMX Toggle PWMX 01 10 11 Force 0 on PWMX Force 1 on PWMX Toggle PWMX Figure 21, Output Compare Architecture TimXCmpFullAct[1:0] State Machine TimXFull = CmpXFull Force ‘1’ Force ‘0’ Toggle No Action TimXStatus = CmpXVal TimXCmpVal TimXEnPWM X = 1, 2, 3, 4 Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 TimXCmpValAct[1:0] PWMX_N PWMX OutSel OE PA PB PC En InpEn ResSys 92 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 17.8 OUTPUT COMPARE - PWMX SIGNAL PORT MAPPING Mapping of the timers PWM signal to the port A, B and C terminals. The port mapping is made in such a way that usually one has the PWMX and its complementary output PWMX_N available. Using the differential output voltages between PWMX and PWMX_N the output drive energy increases by a factor 4. Figure 22, PWMX complementary outputs Complementary Outputs VSUP PWM1 PortA PWM1 PWM_1N PWM2 PWM_2N PWM3 PWM_3N PWM4 PWM_4N PA0 PortC PWM1 PWM_1N PWM2 PWM_2N PWM3 PWM_3N PWM4 PWM_4N PC0 PortB PWM1 PWM_1N PWM2 PWM_2N PWM3 PWM_3N PWM4 PWM_4N PB0 PA1 X PA2 X PA3 PA4 PA5 PA6 PA7 X X X X X X X X VSS VSUP PWM1_N VSS +VSUP PWM1 PWM1_N VSS -VSUP The corresponding port setup must be made to allow the PWMX and PWMX_N signal to output on the mapped port terminal. Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 93 PC1 PC2 X X PC3 PC4 PC5 PC6 PC7 X X X X X PB1 PB2 X PB3 PB4 X PB5 X PB6 PB7 X X X X X X X X X X X X X X X X www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 17.9 TIMER INTERRUPTS Timer interrupts may be generated on hardware capture events, when the timer reaches the compare value and when the timer reaches the full value. The timer interrupt generation is totally independent of the different timer mode settings. Interrupt generation when: The CmpFull interrupt is only generated when TimXIntSel in register RegTimXCfg is ‘0’, and the counter reaches the TimXFull value The CmpVal interrupt is only generated when TimXIntSel in register RegTimXCfg is ‘1’, and the counter reaches the TimXCmpVal value The capture interrupt is always generated if a valid hardware input capture event is applied to the selected input source. Figure 23, Timer Interrupt structure CptXInt Timer Interrupt structure TimXCptEdg[1:0] TimXCptEvtSrc[1:0] X = 1,2,3,4 X = 1,2,3,4 RegTimXFull CptEvtSrc0 0 0 CptEvtSrc1 1 1 CptEvtSrc2 MUX 2 4:1 MUX 2 4:1 CptEvtSrc3 3 3 = TimX-Ck CmpXFull 0 IntTimX RegTimXStatus ck = CmpXVal 1 load RegTimXCptVal Software Capture via TimXSWCpt 17.10 RegTimXCmpVal TimXIntSel X = 1,3 TIMER REGISTERS 0x003B Bits Name 7 Tim12Chain 6 Tim34Chain 5 Tim1AR 4 Tim2AR 3 Tim3AR 2 Tim4AR 1 Tim1SWCpt 0 Tim3SWCpt RegTimersCfg Type ResVal RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 OS 0 OS 0 ResSrc ResSys ResSys ResSys ResSys ResSys ResSys ResSys ResSys 0x003C Bits Name 7 Tim1SWStart 6 Tim1Pulse RegTimersStart Type ResVal STS 0 RW 0 ResSrc ResSys ResSys 5 4 Tim2SWStart Tim2Pulse STS RW 0 0 ResSys ResSys 3 2 Tim3SWStart Tim3Pulse STS RW 0 0 ResSys ResSys 1 0 Tim4SWStart Tim4Pulse STS RW 0 0 ResSys ResSys Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 94 Timers Configuration Description Chain Timer1 & Timer2 into one 16bit Timer Chain Timer3 & Timer4 into one 16bit Timer Autoreload mode of Timer1 Autoreload mode of Timer2 Autoreload mode of Timer3 Autoreload mode of Timer4 Timer1/12 SW event for Capture Timer3/34 SW event for Capture Timers Start Event Configuration Description Start/Run Timer1 by SW 1-Start-Stop Timer1 by Event, 0-Enable/Run by active level Start/Run Timer2 by SW 1-Start-Stop Timer2 by Event, 0-Enable/Run by active level Start/Run Timer3 by SW 1-Start-Stop Timer3 by Event, 0-Enable/Run by active level Start/Run Timer4 by SW 1-Start-Stop Timer4 by Event, 0-Enable/Run by active level www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 0x003D Bits Name 7 Tim1EnPWM 6 Tim1IntSel 5:3 Tim1SelStart 2:0 Tim1SelClk RegTim1Cfg Type ResVal RW 0 RW 0 RW '000' RW '000' 0x003E RegTim1CptCmpCfg Bits 7:6 5:4 3:2 Name Tim1CptEdg Tim1CptEvtSrc Tim1CmpFullAct Type RW RW RW ResVal '00' '00' '00' ResSrc ResSys ResSys ResSys 1:0 Tim1CmpValAct RW '00' ResSys ResSrc ResSys ResSys ResSys ResSys Timer1 Configuration Description Enable PWM function of Timer1 0-Int. on Full value, 1-Int. on Compare value Start source selection Clock source selection Timer1 Compare & Capture functions configuration Description Capture event Edge Selection Capture Event External Source Selection. Action selection on PWM1 when status reaches Load value Action selection on PWM1 when status reaches Compare value 0x003F Bits Name 7:0 Tim1Status RegTim1Status Type ResVal RO 0x00 ResSrc ResSys Timer1 Status Description Timer1 Status 0x0040 Bits Name 7:0 Tim1Full RegTim1Full Type ResVal RW 0xFF ResSrc ResSys Timer1 Full / End Of Count value Description Timer1 Full / End Of Count value 0x0041 Bits Name 7:0 Tim1CmpVal RegTim1CmpVal Type ResVal RW 0x00 ResSrc ResSys Timer1 Compare Value Description Timer1 Compare Value 0x0042 Bits Name 7:0 Tim1CptVal RegTim1CptVal Type ResVal RO 0x00 ResSrc ResSys Timer1 Captured Value Description Timer1 Captured Value 0x0043 Bits Name 7 Tim2EnPWM 6 Tim2IntSel 5:3 Tim2SelStart 2:0 Tim2SelClk RegTim2Cfg Type ResVal RW 0 RW 0 RW '000' RW '000' ResSrc ResSys ResSys ResSys ResSys Timer2 Configuration Description Enable PWM function of Timer2 0-Int. on Full value, 1-Int. on Compare value Start source selection Clock source selection 0x0044 RegTim2CptCmpCfg Bits 7:6 5:4 3:2 Name Tim2CptEdg Tim2CptEvtSrc Tim2CmpFullAct Type RW RW RW ResVal '00' '00' '00' ResSrc ResSys ResSys ResSys 1:0 Tim2CmpValAct RW '00' ResSys Timer2 Compare & Capture functions configuration Description Capture event Edge Selection Capture Event External Source Selection. Action selection on PWM2 when status reaches Load value Action selection on PWM2 when status reaches Compare value 0x0045 Bits Name 7:0 Tim2Status RegTim2Status Type ResVal RO 0x00 ResSrc ResSys Timer2 Status Description Timer2 Status 0x0046 Bits Name 7:0 Tim2Full RegTim2Full Type ResVal RW 0xFF ResSrc ResSys Timer2 Full / End Of Count value Description Timer2 Full / End Of Count value Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 95 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 0x0047 Bits Name 7:0 Tim2CmpVal RegTim2CmpVal Type ResVal RW 0x00 ResSrc ResSys Timer2 Compare Value Description Timer2 Compare Value 0x0048 Bits Name 7:0 Tim2CptVal RegTim2CptVal Type ResVal RO 0x00 ResSrc ResSys Timer2 Captured Value Description Timer2 Captured Value 0x0049 Bits Name 7 Tim3EnPWM 6 Tim3IntSel 5:3 Tim3SelStart 2:0 Tim3SelClk RegTim3Cfg Type ResVal RW 0 RW 0 RW '000' RW '000' ResSrc ResSys ResSys ResSys ResSys Timer3 Configuration Description Enable PWM function of Timer3 0-Int. on Full value, 1-Int. on Compare value Start source selection Clock source selection 0x004A RegTim3CptCmpCfg Bits 7:6 5:4 3:2 Name Tim3CptEdg Tim3CptEvtSrc Tim3CmpFullAct Type RW RW RW ResVal '00' '00' '00' ResSrc ResSys ResSys ResSys 1:0 Tim3CmpValAct RW '00' ResSys Timer3 Compare & Capture functions configuration Description Capture event Edge Selection Capture Event External Source Selection. Action selection on PWM3 when status reaches Load value Action selection on PWM3 when status reaches Compare value 0x004B Bits Name 7:0 Tim3Status RegTim3Status Type ResVal RO 0x00 ResSrc ResSys Timer3 Status Description Timer3 Status 0x004C Bits Name 7:0 Tim3Full RegTim3Full Type ResVal RW 0xFF ResSrc ResSys Timer3 Full / End Of Count value Description Timer3 Full / End Of Count value 0x004D Bits Name 7:0 Tim3CmpVal RegTim3CmpVal Type ResVal RW 0x00 ResSrc ResSys Timer3 Compare Value Description Timer3 Compare Value 0x004E Bits Name 7:0 Tim3CptVal RegTim3CptVal Type ResVal RO 0x00 ResSrc ResSys Timer3 Captured Value Description Timer3 Captured Value 0x004F Bits Name 7 Tim4EnPWM 6 Tim4IntSel 5:3 Tim4SelStart 2:0 Tim4SelClk RegTim4Cfg Type ResVal RW 0 RW 0 RW '000' RW '000' ResSrc ResSys ResSys ResSys ResSys Timer4 Configuration Description Enable PWM function of Timer4 0-Int. on Full value, 1-Int. on Compare value Start source selection Clock source selection 0x0050 RegTim4CptCmpCfg Bits 7:6 5:4 3:2 Name Tim4CptEdg Tim4CptEvtSrc Tim4CmpFullAct Type RW RW RW ResVal '00' '00' '00' ResSrc ResSys ResSys ResSys 1:0 Tim4CmpValAct RW '00' ResSys Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 96 Timer4 Compare & Capture functions configuration Description Capture event Edge Selection Capture Event External Source Selection. Action selection on PWM4 when status reaches Load value Action selection on PWM4 when status reaches Compare value www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 0x0051 Bits Name 7:0 Tim4Status RegTim4Status Type ResVal RO 0x00 ResSrc ResSys Timer4 Status Description Timer4 Status 0x0052 Bits Name 7:0 Tim4Full RegTim4Full Type ResVal RW 0xFF ResSrc ResSys Timer4 Full / End Of Count value Description Timer4 Full / End Of Count value 0x0053 Bits Name 7:0 Tim4CmpVal RegTim4CmpVal Type ResVal RW 0x00 ResSrc ResSys Timer4 Compare Value Description Timer4 Compare Value 0x0054 Bits Name 7:0 Tim4CptVal RegTim4CptVal Type ResVal RO 0x00 ResSrc ResSys Timer4 Captured Value Description Timer4 Captured Value Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 97 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 18. SPI – SERIAL INTERFACE The circuit contains a synchronous 3-wire (SDI, SDOUT and SCLK) master and slave serial interface. Its ports are mapped on different PA, PB and PC IO terminals. SCLK: Serial Clock Input/ Output: Input in Slave mode, Output in Master mode SDIN: Serial Interface Data Input. Input in Master and Slave mode SDOUT: Serial Interface Data Output. Output in Master and Slave mode The serial interface always transmits or receives 8-bit packages at a time, followed by an interrupt request allowing the CPU to treat the data. An Interrupt IntSPIStart is generated at transmission start and an IntSPIStop at the end of the transmission. An Event EvtSPI is generated at transmission start and at the end of the transmission. The interface may also be used to generate a fix datastream output by using the Auto-Start mode. The internal shift register clock edge is user selectable; the interface may run on RTZ (Return To Zero) or RTO (Return to One) type of clocks The full SPI setup shall be configured before enabling the SPI (SPIEn=’1’). Once enabled the configuration must not be changes anymore. While SPIEn is ‘0’, SPIStart is reset. SPIEn must be written ‘1’ before SPIStart is set. The transmission may start as soon as SPIStart is set ‘1’. Always make first full SPI setup and only at the end set the bit SPIStart to ‘1’ to begin the data exchange. The register RegSPIDOut and RegSPIDIn act as a buffer for outgoing and incoming data. The RegSPIDOut must be th written before the transmission starts. The RegSPIDIn will be updated after the 8 active clock with the actual received input data. The transmission direction is configurable with bit SPIMSB1st. Set to ‘1’ the first transmission bit is the MSB bit , if set ‘0’ then it is the LSB bit. Figure 24, Serial Interface Architecture OE SIN PA4 PB0 PA2 RegSPIDOut RegSPIDIn OutSel InpEn EvtSPI SPIAutoStart SPIMSB1st IntSPIStart Shiftregister & State count SPIStart SPINegEdg IntSPIStop OE SPIRTO SPIMode[2:0] Pr1Ck12 Pr1Ck13 Ck_Lo Pr2Ck7 Pr2Ck8 Pr2Ck9 Ck_Hi OutSel 1 Shift_Clk 8th PB4 PA2 PC2 Clear Start 0 OE OutSel Slave clock SCLK and SIN, if selected on PA or PC are going through the debouncer Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 SOUT InpEn 98 InpEn SCLK PA6 PB2 PC6 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 18.1 SCLK - SPI MASTER/ SLAVE MODE AND CLOCK SELECTION Master and Slave mode as well as master mode clock selection are done in register RegSPICfg1 bits SPIMode. In Slave mode the serial input clock is coming from PA6, PB2 or PC6 input. The selection depends on SPISelSClk bits in register RegSPICfg2 and the corresponding port input enable bit must be ‘1’. SCLK Frequency selection SPIMode SCLK base clock SCLK Slave mode input selection Input Input condition terminal SLAVE Mode SCLK from port inputs 000 SPIMode[2:0] Slave Mode SPISelSClk='00' PA6InpE='1' SPISelSClk='01' PB2InpE='1' SPISelSClk='10' PC6InpE='1' SPISelSClk='11' PA6InpE='1' PA6 from PA6, PB2 PC6 Master mode, Prescaler 2 clocks PB2 001 Ck_Hi PC6 010 Pr2Ck9 PA6 011 Pr2Ck8 100 Pr2Ck7 000 (slave) 000 (slave) 000 (slave) 000 (slave) SCLK Master mode output selection Output Output condition terminal Master mode, Prescaler 1 clocks Master Mode PA6OutSel[1:0]='01' PA6OE='1' PB2OutSel[1:0]='01' PB2 110 Pr1Ck13 PB2OE='1' PC6OutSel[1:0]='01' PC6 111 Pr1Ck12 PC6OE='1' The used PA, PB and PC IO port terminals must be set up for SPI before SPIStart is set high. 101 PA6 Ck_Lo Following table shows the different SCLK clock possibilities RTZ and RTO with the internal shift clock dependencies. SCLK IDLE Clock ShiftEdge Example on SCLK SPIRTO SPINegEdg SCLK pulse value type 0 0 High Pulse High Pos edge RTZ RTZ, pos edge 0 1 High Pulse High Neg edge RTZ RTZ, neg edge 1 0 Low pulse Low Pos edge RTO RTO, pos edge 1 1 Low pulse Low Neg edge RTO RTO, neg edge SPIRTO defines a RTZ clock type if set to ‘1’ or RTO clock type if set to ‘0’ SPINegEdg defines the internal shift register shift clock edge, set to ‘1’ shift takes place on the negative SCLK clock edge. Set to ‘0’, the shift will take on the positive SCLK clock edge. Both bits are placed in register RegSPICfg1. Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 99 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 18.2 SIN PORT MAPPING The serial data input may come from PA4, PB0 or PA2. On PA2 and PA4 the debounced signal PADeb2 or PADeb4 is used as serial data input, from PB0 it is directly the pad input while the input enable is high. The data shifted in through SIN terminal will be stored th into the buffer register RegSPIDIn after the 8 shift clock. MSB or LSB first on the SIN reception is selected with bit SPIMSB1st. Input terminal PA4 PB0 PA2 PA4 Input condition SPISelSIN[1:0]='00' PA4InpE='1' SPISelSIN[1:0]='01' PB0InpE='1' SPISelSIN[1:0]='10' PA2InpE='1' SPISelSIN[1:0]='11' PA4InpE='1' 18.3 SOUT PORT MAPPING The serial data output is mapped on PB4, PA2 or PC2. The corresponding port output must be setup by the corresponding port output selection bits as SDOUT output with its output enable high. The data to be shift out must be written into the output buffer register RegSPIDOut before the transmission is started. MSB or LSB first on the SOUT transmission is selected with bit SPIMSB1st. Output terminal PB4 PA2 PA7 PC2 Output condition PB4OutSel[1:0]='01' PB4OE='1' PA2OutSel[1:0]='01' PA2OE='1' PA7OutSel[1:0]='01' PA7OE='1' PC2OutSel[1:0]='01' PC2OE='1' 18.4 SPI START – STOP th In master mode writing bit SPIStart=’1’ will launch the transmission when it goes high and SPIEn=’1’. After the 8 active SCLK clock edge the SPIStart will be forced low. SPISart can be used as a status register to momitor ongoing transmission. Writing ‘0’ to SPIStart during the transmission will stop the SPI. In this case the content of RegSPIDIn is not guaranteed. Note: Chipselect handling for master mode shall be handled by the user software on any user defined PA, PB or PC output. In slave mode, the transmission starts as soon as the 1st clock pulse occurs after SPIStart was written ‘1’. Note: In slave mode, for the synchronization, the user can generate a flag by software on a terminal to indicate to the master that the SPI is ready. 18.5 AUTO-START With Auto-Start one can transmit several 8-bit packages without any delay between the packages. As such it allows generating a fix datastream output. The bit SPIAutoStart needs to be high to allow Auto-Start For Auto-Start to take place one needs to write the next package data into the RegSPIDOut during the ongoing th transmission. The SPIStart will in this case stay high after the 8 active clock edge and the new transmission will follow immediately after. All interrupts IntSPIStart, IntSPIStop and the event EvtSPI are generated also in Auto-Start mode. If the bit SPIAutoStart is at ‘0’, the auto start mode is be disabled, writing to RegSPIDOut during the transmission will have no effect. Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 100 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 18.6 RTZ POSITIVE EDGE TRANSMISSION With RTZ (Return To Zero) positive edge transmission the SCLK clock is low between successive transmissions. An interrupt request IntSPIStart and an event EvtSPI st are generated by the rising edge of the 1 SCLK clock. An interrupt request IntSPIStop and an event EvtSPI th are generated by the rising edge of the 8 SCLK clock. The SOUT data will change on the on the rising SCLK st clock edge. The 1 bit of data SPIDout data will be shift st out on the rising edge of the 1 SCLK clock and the last th on the 8 SCLK clock rising edge. Figure 25, RTZ Positive edge transmission RTZ positive edge, MSB first SCLK The SIN data must be stable at the SCLK rising edge to be properly shifted in, the buffer RegSPIDIn will be updated with the received data at the rising edge of the th 8 shift clock. SOUT SIN MSB MSB 6 6 5 5 4 4 3 3 2 2 1 1 LSB LSB _____________________________________________________________________________________________ 18.7 RTO POSITIVE EDGE TRANSMISSION The buffer register RegSPIDIn will be updated with the th received data on the rising edge of the 8 SCLK clock. An interrupt request IntSPIStart and an event EvtSPI st are generated by the rising edge of the 1 SCLK clock. An interrupt request IntSPIStop and an event EvtSPI th are generated by the rising edge of the 8 SCLK clock. With RTO (Return To One) positive edge transmission the SCLK clock is high between successive transmissions. st The 1 bit contains in RegSPIDOut will be on SOUT before the first transmission if SPIEn = ‘1’ or on the th falling edge of the 7 SCLK pulse after the nd transmission. The 2 bit contains in RegSPIDOut will st be shifted out on the rising edge of the 1 SCLK pulse. th The 8 bit contained in RegSPIDOut will be shifted out th on the rising edge of the 7 SCLK pulse. Figure 26, RTO Positive edge transmission RTO positive edge, MSB first SCLK SOUT SIN data must be stable on the rising edge of SCLK to be properly aquired and shifted. SIN MSB 6 MSB 5 6 4 5 3 4 2 3 1 2 LSB 1 LSB _____________________________________________________________________________________________ 18.8 RTZ NEGATIVE EDGE TRANSMISSION The buffer register RegSPIDIn will be updated with the th received data on the falling edge of the 8 SCLK clock. An interrupt request IntSPIStart and an event EvtSPI st are generated by the falling edge of the 1 SCLK clock. An interrupt request IntSPIStop and an event EvtSPI th are generated by the falling edge of the 8 SCLK clock. With RTZ (Return To Zero) negative edge transmission the SCLK clock is low between successive transmissions. st The 1 bit contains in RegSPIDOut will be on SOUT before the first transmission if SPIEn = ‘1’ or on the th falling edge of the 7 SCLK pulse after the nd transmission. The 2 bit contains in RegSPIDOut will st be shifted out on the falling edge of the 1 SCLK pulse. th The 8 bit contains in RegSPIDOut will be shifted out th on the falling edge of the 7 SCLK pulse. Figure 27, RTZ Negative edge transmission RTZ negative edge, MSB first SCLK SOUT SIN data must be stable on the falling of SCLK to be properly aquired and shifted. SIN MSB MSB 6 5 6 4 5 3 4 2 3 1 2 LSB 1 LSB _____________________________________________________________________________________________ Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 101 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 18.9 RTO NEGATIVE EDGE TRANSMISSION With RTO (Return To One) negative edge transmission the SCLK clock is high between successive transmissions. An interrupt request IntSPIStart and an event EvtSPI st are generated by the falling edge of the 1 SCLK clock. An interrupt request IntSPIStop and an event EvtSPI th are generated by the falling edge of the 8 SCLK clock. The SOUT data will change on the on the falling SCLK st clock edge. The 1 bit of data SPIDout data will be shift st out on the falling edge of the 1 SCLK clock and the th last on the 8 SCLK clock falling edge. Figure 28, RTO Negative edge transmission RTO negative edge, MSB first SCLK The SIN data must be stable at the SCLK falling edge to be properly shifted in, the buffer RegSPIDIn will be updated with the received data at the falling edge of the th 8 shift clock. SOUT SIN MSB MSB 6 6 5 5 4 4 3 3 2 2 1 1 LSB LSB Note: The SPI signals has the following setup and hold time parameters: Conditions: VSUP = 2.0 V, Temp = -40°C to 85°C, external Cload on pad = 30 pF SCLK frequency, port A and C fSPIAC max 8 MHz SCLK frequency, port B fSPIB max 10 MHz SIN setup time, slave mode tsuSINS min 6 ns SIN setup time, master mode tsuSINM min 29 ns (portA,C), min 25ns (port B) SIN hold time thdSIN min 5 ns SOUT delay_time TdelSOUT max 32ns (port A, C), max 26ns (port B) Above values are not verified on production testing. 18.10 SPI REGISTERS 0x007A Bits Name 7 SPIEn 6:4 SPIMode 3 SPINegEdg 2 SPIRTO 1 SPIMSB1st 0 SPIAutoStart RegSPICfg1 Type ResVal RW 0 RW '000' RW 0 RW 0 RW 1 RW 1 ResSrc ResSys ResSys ResSys ResSys ResSys ResSys SPI Configuration - 1 Description SPI Enable SPI Mode and SClk selection SPI active on Negative Edge SPI RTO (Return To One) SPI MSB First SPI Auto Start Enabled 0x007B Bits Name 7:6 SPISelSClk 5:4 SPISelSIn 3:0 - RegSPICfg2 Type ResVal RW '00' RW '00' NI - ResSrc ResSys ResSys - SPI Configuration - 2 Description SPI SClk Selection SPI SIn Selection Not implemented 0x007C Bits Name 7 SPIStart 6:0 - RegSPIStart Type ResVal STS 0 NI - ResSrc ResSys - SPI Start Description SPI Start Not implemented 0x007D Bits Name 7:0 SPIDIn RegSPIDIn Type ResVal RO 0x00 ResSrc ResSys SPI Received Data Description SPI Received Data 0x007E Bits Name 7:0 SPIDOut RegSPIDOut Type ResVal RW 0x00 ResSrc ResSys SPI Data to Transmit Description SPI Data to Transmit Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 102 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 19. WATCHDOG The function of the watchdog is to generate a reset ResSys and ResAna by asserting the ResWD signal if during a given timeout period the CPU did not clear the WD counter (WDClear). It therefore uses a 16-bits counter that counts down from start (RegWDLdValM (MSB) and RegWDLdValL (LSB)) value down to 0x0000. The counter uses directly the RC 8 KHz clock. This RC clock is always enabled together with the watchdog. Refer also to chapter Oscillator and Clock selection for the RC 8 KHz clock. Figure 29, Watchdog architecture Watchdog 8 WDClr Sleep WDDis WDKey ResWD 16 16 bit Watchdog timer Load Ck WDStatM WDStatL MSB LSB data bus Control RC 8KHz ResSys Reset WDLdValM WDLdValL 19.1 WATCHDOG CLEAR The software writes ‘1’ to the one shot register RegWDCfg bit WDClear to avoid watchdog reset, at the same time the counter will reload the initial start value given by registers RegWDLdValM and RegWDLdValL. If the counter reaches 0x0000 and WDDis = ‘0’ then signal WatchDog timeout ResWD will be asserted. The watchdog counter status can be read in registers RegWDStatM (MSB) and RegWDStatL (LSB). Note: Due to asynchronous domain crossing the SW may read the status during its change i.e. a nonsense value. Only two consecutive reads of the same stable value can assure about its correctness if the WD is running. The occurrence of a watchdog reset can be read in the rest flag register RegResFlag bit ResFlagWD. The timeout, based on the 8 KHz RC oscillator can be set as high as 8.2s (load value of 0xFFFF) with a LSB value of typical 125us. The default load value of 0x8000 corresponds to 4.1 secondes. In sleep mode watchdog is always disable. 19.2 WATCHDOG DISABLING If the register RegWDKey contains the value (watch_dog_key = 0xCA) it becomes possible to disable the WD by writing ‘1’ to register RegWDCfg bit WDDis. If RegWDKey contains the watchdog a value <> 0xCA it will be impossible to disable the WD, register RegWDCfg bit WDDis will be forced low. The WatchDog counter is disabled in Sleep mode and if RegWDCfg.WDDis = ‘1’ while watch_dog_key is valid. The counter will reload the start value when started and/or re-enabled. Note: The WatchDog Clear may take up to 3 WD clocks (~375 us). The WatchDog Start-up may take up to 4 WD clocks (~500 us). Any change in RegWdLdValM or RegWdLdValL during this time will affect the WD Counter value. Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 103 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 19.3 WATCHDOG REGISTERS 0x0006 Bits Name 7 ResFlgPA 6 ResFlgWD 5 ResFlgBO 4 ResFlgGasp 3 ResFlgBE 0 LckPwrCfg RegResFlg Type ResVal ResFlg 0 ResFlg 0 ResFlg 0 ResFlg 0 ResFlg 0 RW 0 0x006D Bits Name 7 WDDis 0 WDClear RegWDCfg Type ResVal RW 0 OS 0 0x006E Bits Name 7:0 WDKey RegWDKey Type ResVal RW 0x00 ResSrc ResSys WatchDog Key (0xCA) for disabling Description WatchDog Key (0xCA) for disabling 0x006F Bits Name 7:0 WDLdValL RegWDLdValL Type ResVal RW 0x00 ResSrc ResSys WatchDog Start/Load value LSB Description WatchDog Start/Load value LSB 0x0070 Bits Name 7:0 WDLdValM RegWDLdValM Type ResVal RW 0x80 ResSrc ResSys WatchDog Start/Load value MSB Description WatchDog Start/Load value MSB 0x0071 Bits Name 7:0 WDStatL RegWDStatL Type ResVal RO 0x00 ResSrc ResSys WatchDog Status LSB Description WatchDog Status LSB 0x0072 Bits Name 7:0 WDStatM RegWDStatM Type ResVal RO 0x80 ResSrc ResSys WatchDog Status MSB Description WatchDog Status MSB Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 ResSrc PorLog PorLog PorLog PorLog PorLog Por ResSrc ResSys 104 Reset Flags Description Flag Reset from Port-A Flag Reset from WatchDog Flag Reset from Brown-Out Flag Reset from GASP Flag Reset from CoolRisc Bus-Error Lock configurations to be kept in Power-Down mode WatchDog Configuration Description WatchDog Disable WatchDog Clear - Restart Counting www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 20. SLEEP COUNTER WAKE-UP The SC wake-up function generates a timeout which may be used as a sleep wake-up or as an asynchronous interrupt or event generation timer in active or standby mode. The max delay is 35min, programmable in 125us steps. When the timeout is reached an interrupt IntSlpCnt or event EvtSlpCnt will be asserted. If the circuit was in sleep mode the interrupt or event will wake it up and software execution will start, if the circuit was in active or standby mode it will interpret the interrupts or events excecute the instruction code. In order to wake-up from sleep or to see the interrupt or event the corresponding interrupt and event must not be masked. The SCWU uses a 24-bit counter down counter running on the internal RC 8 KHz oscillator. Figure 30, Sleep wake-up counter architecture SC-Wake-Up IntSlpCnt 8 16 24 EvtSlpCnt 24 bit Sleep Counter Wake-up timer Sleep Load Ck SCStart SCDis SCStat2 MSB SCStat1 SCStat0 LSB data bus Control RC 8KHz ResSys Reset SCLdVal2 SCLdVal1 SCLdVal0 The counter state shall be readable by registers RegSCStat2 (MSB), RegSCStat1 and RegSCStat0. Note: Due to asynchronous domain crossing the SW may read the status during its change i.e. a nonsense value. Only two consecutive reads of the same stable value can assure about its correctness if the SC is running. Note: As sleep counter is a state machine running at low frequency, two consecutive actions from CPU on sleep-counter as stop or start shall be separated by at least 2.5 ms delay. Once the counter reaches 0x000000 value then IntSlpCnt and EvtSlpCnt will be asserted regardless of the mode. The counting is stopped. 20.1 SC WAKE-UP ENABLING The counter can only start when SCDis=’0’ (enabled). If SCDis = ‘0’ the counter starts automatically when system enters in sleep mode. When the counter starts it will first load the RegSCLdVal2,1,0 and then downcount from the loaded value. The current counter value can be read in the status registers RegSCStat2,1,0. The default load value is 0x008000 which corresponds to a timeout of 4.1s. An active SC wake-up will automatically switch on the internal RC 8 kHz oscillator. SCStart can be used to trim the SC in active mode. Charge sharing effects influence the SCWKUP timing slightly when going into Sleep mode. Resulting timings are therefore up to 2.2ms longer than expected. Note: SCStart shall not be set to ‘1’ before going in sleep mode it shall be used only in active mode to trim the sleep counter wake-up delay. Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 105 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 20.2 SC WAKE-UP DISABLING If SCDis = ‘1’ the counter will be disabled regardless of the mode. The counter will stop when SCStart is set to ‘0’ or after Sleep mode wake-up. Once stopped, the counter will keep its current value. The SC wake-up function is reset by ResSys. Note: Due to asynchronous domain crossing the reload and following start takes 2-3 SC clocks (~250-375 us). Note: If in sleep mode system is woke-up by another source as SC wake-up (by PortA) before SC reaches 0x000000 then the SC needs 2-3 clocks cycle before stopping. If system enter again in sleep mode before proper SC stop, SC do not reload RegSCLdVAl2,1,0 then SC delay is shorter than expected. Note: Sleep counter can be used in two ways: The sequence to use it as a true sleep counter (sleep mode) shall be down in the following order: Write RegSCLdVal2,1,0 registers Set SelSleep bit in RegSysCfg1 register, Enable Sleep counter (clear SCDis bit). By enabling it the sleep counter configuration shall be latched. Each time the CPU executes HALT instruction, it enters sleep mode. The sleep counter starts counting and will wake-up the CPU at end of counting (if interrupt or event not masked). The sequence to use it as a simple counter (no sleep mode) shall be down in the following order: Write RegSCLdVal2,1,0 Clear SelSleep bit in RegSysCfg1 register, To run a single counting cycle the counter the following code need to be executed Enable the sleep counter (clear SCDis bit). Start the counter (set SCStart bit) Once the counter has reached its countdown it is necessary to disable the sleep counter (set RegSCCfg.SCDis bit) before restarting it (Enable and Start). Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 106 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 20.3 SC WAKE-UP REGISTERS 0x0073 Bits Name 7 SCDis 6 SCStart 5:0 - RegSCCfg Type RW RW NI ResVal 0 0 - ResSrc ResSys ResSys - SleepCounter Configuration Description SleepCounter Disable SleepCounter Start/Run Not implemented 0x0074 Bits Name 7:0 SCLdVal0 RegSCLdVal0 Type ResVal RW 0x00 ResSrc ResSys SleepCounter Start/Load value B0-LSB Description SleepCounter Start/Load value B0-LSB 0x0075 Bits Name 7:0 SCLdVal1 RegSCLdVal1 Type ResVal RW 0x80 ResSrc ResSys SleepCounter Start/Load value B1 Description SleepCounter Start/Load value B1 0x0076 Bits Name 7:0 SCLdVal2 RegSCLdVal2 Type ResVal RW 0x00 ResSrc ResSys SleepCounter Start/Load value B2-MSB Description SleepCounter Start/Load value B2-MSB 0x0077 Bits Name 7:0 SCStat0 RegSCStat0 Type ResVal RO 0x00 ResSrc ResSys SleepCounter Status B0-LSB Description SleepCounter Status Byte0-LSB 0x0078 Bits Name 7:0 SCStat1 RegSCStat1 Type ResVal RO 0x80 ResSrc ResSys SleepCounter Status B1 Description SleepCounter Status Byte1 0x0079 Bits Name 7:0 SCStat2 RegSCStat2 Type ResVal RO 0x00 ResSrc ResSys SleepCounter Status B2-MSB Description SleepCounter Status Byte2-MSB Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 107 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 21. 10-BITS ADC Two blocks compose the ADC: The conditioner The ADC converter The conditioner allows sampling different range of analog inputs even signal having a dynamic higher than VSUP. It consists to decrease the reference and the analog input in a range adapted for the ADC converter. 21.1 CONDITIONER 21.1.1 RANGE SELECTION It consists to attenuate the external analog input range and external reference. It is used to adapt external range to internal range limited to maximum 1.7V as illustrated in the following diagram. Vref_ext min Minimum internal range Vref_int min vss Maximum internal range Vref_int max Minimum external range Maximum external range Vref_ext max Vref_ext max: Maximum external range Vref_ext min: Minimum external range Vref_int max: Maximum internal range = 1.7V Vref_int min: Minimum internal range = 1.1V External reference and attenuation factor called range shall be calculated to get an internal refenrence in a window of 1.1V to 1.7V. There is another condition to fullfil; the maximum external reference shall not be above VSUP if VSUP > VREG. If VSUP < VREG the maximum external reference is 1.7V. There are 4 possible ranges. The factor shall be chosen to get an internal reference in the window of 1.1V to 1.7V according to the following table: Range 8/8 6/8 4/8 3/8 Vref_ext min 1.10 V 1.47 V 2.20 V 2.93 V Vref_ext max 1.70 V 2.27 V 3.40 V 3.60 V (1) (1) The maximum external range is limitated by maximum power supply 3.6V Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 108 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x External – internal references relation with 8/8 range External – internal references relation with 6/8 range Vref_ext [V] External – internal references relation with 3/8 range 3.6 External reference window 1.9 1.8 1.7 1.6 1.5 1.4 1.8 Internal reference window 1.3 1.2 1.1 1.0 0.9 0.8 1.7 1.6 1.5 1.4 1.3 Vref_int [V] Internal reference window 1.9 0.7 0.6 0.5 0.4 0.3 3.4 3.2 Vref_ext [V] External – internal references relation with 4/8 range External reference window 1.2 1.1 1.0 0.9 0.8 0.7 0.6 /8 e4 g ran ge ran 0.5 0.4 3/8 3.6 3.4 3.2 3.0 2.8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.2 3.6 3.4 3.2 3.0 2.8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.0 0.8 0.6 0.4 0.1 0.2 0.2 0.1 0.4 0.3 0.2 1.2 Vref_int [V] 3.0 2.8 2.6 2.4 2.2 2.0 1.8 1.6 8 6/ 1.4 0.6 0.4 0.2 3.6 3.4 3.2 3.0 2.8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.1 0.6 0.2 0.1 0.4 0.2 0.2 e ng ra 1.2 0.8 0.7 0.6 0.5 0.4 0.3 ra 0.7 0.6 0.5 0.4 0.3 1.0 ng e 0.8 1.3 1.2 1.1 1.0 0.9 0.8 8/ 8 1.3 1.2 1.1 1.0 0.9 Vref_int [V] 1.8 1.7 1.6 1.5 1.4 Internal reference window 1.8 1.7 1.6 1.5 1.4 Internal reference window External reference window 1.9 0.8 Vref_int [V] External reference window 1.9 Vref_ext [V] Vref_ext [V] The selection of the attenuation factor is done with ADCSelRange[1:0] in the register RegADCCfg2[5:4]. ADCSelRange[1:0] 00 01 10 11 Attenuation factor 8/8 6/8 4/8 3/8 21.1.2 REFERENCE SELECTION There are three different possible references selectable with ADCSelRef[1:0] in the register RegADCCfg2[7:6]. ADCSelRef[1:0] 00 01 10 11 reference VBGR VREF_EXT VSUP unused origin Internal reference PA2 Main supply VSUP - When external reference VREF_EXT is used, PA[2] shall be configured in analog mode: RegPAOE[2] = ‘0’, RegPAInpE[2] = ‘0’, RegPAPU[2] = ‘0’ and RegPAPD[2] = ‘0’. Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 109 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x Note: Always allow the reference voltage to stabilize before starting an ADC measure. When running on the internal reference this stabilization time is 130us from ADCEn until stable reference voltage. It is possible to start the reference prior to enabling of the ADC, refer to 24. 21.1.3 ANALOG INPUT SELECTION There are 9 possible analog inputs selectable with ADCSelSrc[2:0] in register ADCOut1[6:4]. When the temperature sensor is active (EnTempSens in register RegADCCfg1[4] = ‘1’) the temperature sensor is automatically set as ADC analog input. StsTempSens in register RegADCOut1[3] is a copy of EnTempSens and is not writable. It allows checking if the temperature sensor is enable at each read of ADC data output. EnTempSens 0 0 0 0 0 0 0 0 1 ADCSelSrc[2:0] 000 001 010 011 100 101 110 111 xxx ADC source PA0 PC0 PA1 PC1 PA2 PC2 PA3 PC3 temperature sensor 21.2 ADC OFFSET TRIM SELECTION Depending on the ADC configuration or if the ADC is used with the temperature sensor, the ADC offset shall be set differently. When the internal voltage is used, the ADC range selection has effect only on the analog input signal. Then the offset has to be adapted to the selected range. There is also a dedicated offset trim word used when the analog input is the temperature sensor in order to remove the offset error introduced by the sensor itself. All these trimming words are contained in the row 62 sector 5 of the NVM (refer to the chapter 3.6). The offset trim to use according to the configuration is as follows: ADC configuration ADC ref = internal Vref Range 3/8 ADC ref = internal Vref Range 4/8 ADC ref = internal Vref Range 6/8 ADC offset trim ADCOffsetRng3_8[10:0] ADCOffsetRng4_8[10:0] ADCOffsetRng6_8[10:0] Temperature sensor ADCOffsetTemp[10:0] All other configurations ADCOffsetRng8_8[10:0] DM address MSB 0x6FD1[10:8] LSB 0x6FD0[7:0] MSB 0x6FCF[10:8] LSB 0x6FCE[7:0] MSB 0x6FCD[10:8] LSB 0x6FCC[7:0] MSB 0x6FC9[10:8] LSB 0x6FC8[7:0] MSB 0x6FCB[10:8] LSB 0x6FCA[7:0] The trimming word has to be copied from the NVM to the related registers: MSB in RegADCOffsetM DM address 0x005A and LSB in RegADCOffsetL DM address 0x0059. Note: ADC offset is coded and memorized in NVM on 11 bits. Their value can be above 0x3FF. Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 110 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x ADC configurations 21.2.1 RUNNING MODE The 6819 ADC has two possible running modes: Continuous mode: the ADC runs continuously until the software stopps it. One shot mode: the ADC makes just one single acquisition. To start the ADC in continuous mode, RunContMeas in register RegADCCfg1[6] shall be set at ‘1’. To start a single sample, RunSinglMeas in register RegADCCfg1[5] shall be set at ‘1’. Continuous mode has the priority over single measurement. Always fully define the ADC setup before starting any ADC measurement. 21.2.2 ADC ENABLING Before to start an acquisition, EnADC in register RegADCCfg1[7] shall be set at ‘1’. When the ADC is stopped in continuous mode, EnADC shall be set at ‘0’ before to launch any other acquisition otherwise all next measurement will be corrupted. Note: EnADC will also enable the bandgap reference voltage. If the BGR is used as ADC reference the user must wait for the BGR to stabilize before starting any measurement. Refer to 24. If an external reference is used or the BGR was already enabled before - and is stabilized - still allow 5us setup time from EnADC to start of measuring. Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 111 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 21.2.3 ADC SAMPLING RATE The ADC can select 8 different sampling rates. ADC is running on Ck_Hi whatever the clock configuration. When the CPU and the Prescalers are not running on Ck_Hi, the clock for ADC shall be forced. Meaning that FrcEnRC15M or FrcEnRC2M or FrcEnExt shall be forced at ‘1’ and Ck_Hi shall be connected to the clock source forced. The maximum sampling rate of the ADC is 100kS/s, the ADC needs 22 clocks for each sample, than the maximum selectable ADC frequency is 2.2MHz. The clock selection is done with ADCSmplRate[2:0] in register RegADCCfg1[3:1]. Following table shows the relation between the clock source selection and the sampling rate. ADCSmplRate[2:0] 000 001 010 011 100 101 110 111 Clock division factor 1 (default) 2 4 8 16 32 64 1 Ck_Hi = 15MHz denied denied denied 83.78 41.89 20.95 10.47 denied Sampling rate kS/s Ck_Hi = 2MHz 90.91 45.45 22.73 11.36 5.68 2.84 1.42 90.91 Ck_Hi = 4MHz Xtal denied 90.91 45.45 22.73 11.36 5.68 2.84 denied The first conversion shall be ignored. Then in single mode the conversion need 44 clocks. This is automatically managed by the 6819, the event is generated only after the second conversion. Following table shows the relation between the conversion duration and the clock source selection. ADCSmplRate[2:0] 000 001 010 011 100 101 110 111 Clock division factor 1 (default) 2 4 8 16 32 64 1 Ck_Hi = 15MHz denied denied denied 23.87 47.74 95.49 190.97 denied Conversion duration us Ck_Hi = 2MHz Ck_Hi = 4MHz Xtal 22.00 denied 44.00 22.00 88.00 44.00 176.00 88.00 352.00 176.00 704.00 352.00 1408.00 704.00 22.00 denied 21.2.4 LOW NOISE MODE There is two way to decrease the noise due to activity of 6819: Force DC-DC in idle mode for a short time. Make ADC acquisition only when the CPU is in halt mode. When the DC-DC is used, it is possible to stop it for a short time by setting DC-DCIdle in register RegDC-DCCfg[4] at ‘1’. In this case the only source of energy is the external capacitor. Then it is recommended to ensure that no big consumer is working when the DC-DC is in idle mode (refer to DC-DC chapter). As soon as the ADC convertion is done the DCDIdle shall be set at ‘0’ again. The ADC should be used only in one shot mode in this case to recharge the external capacitor between between each ADC acquisition. ADC low noise mode consists to start the ADC convertion only when the CPU is in stand by mode by setting ADCLowNoise in register RegADCCfg2[3] at ‘1’. The CPU is waked up by ADC event or ADC interrupt when the convertion is done and ADC result available if they are unmasked. 21.2.5 8BIT ADC SELECTION It is possible to set the size of the ADC result between 10 or 8-bits. If high precision is not required, it allows simplifying the software as the data are in 8bit. In this case two LSB bits are lost. The other bits are shifted in register RegADCOut0[7:0]. In 10-bits mode the result is split in registers RegADCOut1[1:0] (2 MSB bits) and RegADCOut0[7:0] (8 LSB bits). Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 112 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 21.3 ADC ACQUISITION SEQUENCE The ADC generates an interrupt or an event when the acquisition is done and the result available for CPU. Thank to the event it is possible to force the CPU in std-by mode, the event wake-up the CPU automatically when the ADC result is available. It allows in continuous saving time because the CPU does not need to go through the handler. It is also possible to react by polling the event with conditional jump JEV. Int0StsADC in register RegInt0Sts[4] is the interrupt generated at the end of each acquisition. Evt1StsADC in register RegEvtSts[1] is the event generated at the end of each acquisition. The ADC result is available in registers RegADCOut1[1:0] (2 MSB bits) and RegADCOut0[7:0] (8 LSB bits). To ensure that a new acquisition between reading RegADCOut1[1:0] and RegADCOut0[7:0] does not corrupt the ADC result, RegADCOut0[7:0] is stored in a shadow register when RegADCOut1[1:0] is read. Both registes are read in fact exactly in the same time. RegADCOut1[1:0] shall always be read first. th RegADCOut1.ADCOutLSB is the 11 bits result LSB and it is not guaranteed. The bit ADCBusy in read-only register RegADCOut1[7] is at ‘1’ when the ADC is working. It allows detecting the end of acquisition in one shot mode by polling. 21.4 ADC REGISTERS 0x0055 Bits Name 7 EnADC 6 RunContMeas 5 RunSinglMeas 4 EnTempSens 3:1 ADCSmplRate 0 ADC8bit RegADCCfg1 Type ResVal RW 0 RW 0 STS 0 RW 0 RW '000' RW 0 ResSrc ResSys ResSys ResSys ResSys ResSys ResSys ADC Configuration - 1 Description Enable ADC Block Run Continues measurement Run/Start Single measurement Enable Temperature Sensor ADC Sample Rate setup - continues mode. ADC 8bit Result mode 0x0056 Bits Name 7:6 ADCSelRef 5:4 ADCSelRange 3 ADCLowNoise 2:0 - RegADCCfg2 Type ResVal RW '00' RW '00' RW 0 NI - ResSrc ResSys ResSys ResSys - ADC Configuration - 2 Description ADC Reference selection ADC Range selection ADC Low noise measurement mode Not implemented 0x0057 Bits Name 7:0 ADCOut0 RegADCOut0 Type ResVal RO 0x00 ResSrc ResSys ADC Output-0 (LSB) Description ADC Output-0: 10bit=LSB(8:1), 8bit-(10:3) 0x0058 Bits Name 7 ADCBusy 6:4 ADCSelSrc 3 StsTempSens 2 ADCOutLSB 1:0 ADCOut1 RegADCOut1 Type ResVal RO 0 RW '000' RO 0 RO 0 RO '00' ResSrc ResSys ResSys ResSys ResSys ResSys ADC Output-1 (MSB) Description ADC in progress ADC Input Source selection Enable Temperature Sensor Status ADC Output HW-LSB(0) ADC Output-1: 10bit-MSB(10:9), 8bit-N/A 0x0059 Bits Name 7:0 ADCOffsetL RegADCOffsetL Type ResVal RW 0x00 ResSrc ResSys ADC Offset LSB (7:0) Description ADC Offset LSB (7:0) 0x005A Bits Name 7:3 2:0 ADCOffsetM RegADCOffsetM Type ResVal NI RW '100' ResSrc ResSys ADC Offset MSB (10:8) Description Not implemented ADC Offset MSB (10:8) Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 113 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 22. TEMPERATURE SENSOR 22.1 TEMPERATURE SENSOR ENABLING The temperature sensor is enabled when EnTempSens in register RegADCCfg1 is written at ‘1’. When the temperature sensor is enabled it is automatically selected by the ADC as input source. Read-only bit StsTempSens in register RegADCOut1 is a copy of EnTempSens. Thank to it the status of temperature sensor is given on each ADC result read access. 22.2 TEMPERATURE SENSOR REGISTERS 0x0055 Bits Name 7 EnADC 6 RunContMeas 5 RunSinglMeas 4 EnTempSens 3:1 ADCSmplRate 0 ADC8bit RegADCCfg1 Type ResVal RW 0 RW 0 STS 0 RW 0 RW '000' RW 0 ResSrc ResSys ResSys ResSys ResSys ResSys ResSys ADC Configuration - 1 Description Enable ADC Block Run Continues measurement Run/Start Single measurement Enable Temperature Sensor ADC Sample Rate setup - continues mode. ADC 8bit Result mode 0x0058 Bits Name 7 ADCBusy 6:4 ADCSelSrc 3 StsTempSens 2 ADCOutLSB 1:0 ADCOut1 RegADCOut1 Type ResVal RO 0 RW '000' RO 0 RO 0 RO '00' ResSrc ResSys ResSys ResSys ResSys ResSys ADC Output-1 (MSB) Description ADC in progress ADC Input Source selection Enable Temperature Sensor Status ADC Output HW-LSB(0) ADC Output-1: 10bit-MSB(10:9), 8bit-N/A Note: Temperature sensor calibration values are stored in row 62 sector 5 as described in chapter 4.6. Temperature tolerances of production test are described in chapter 4.6.1. When EnTempSens is written at ‘1’ it is necessary to wait 10ms before to launch an ADC acquisition. Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 114 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 23. DC/DC CONVERTER The DC-DC converter allows supplying the chip and external elements on the board using a low voltage supply source. The DC-DC converter is not enabled by default but by the software. 6819 is able to start-up with a low voltage supply using the internal voltage multiplier. As the voltage multiplier is not able to deliver more than 100uA, it is recommended to enable the DC-DC before to enable the big consumers. 23.1 DC/DC ENABLING Enable the DC-DC consists to write ‘1’ in EnDC-DC in register RegDC-DCCfg[7]. During the start-up phase of DC-DC the read-only bit DC-DCStartSts in RegDC-DCCfg[3] is at ‘1’. The current driven shall not exceed 10mA during the start-up phase. 23.2 DC/DC VOLTAGE SELECTION There are 4 target voltages selectable with DC-DCLevel[1:0] in register RegDC-DCCfg[6:5]. It is possible to change the voltage level of DC-DC on the fly while DC-DC is enabled but when the voltage rise up the current driven shall not exceed 10mA. DC-DCLevel[1:0] Voltage level 0x00 2.1 0x01 2.5 0x10 2.9 0x11 3.3 23.3 DC/DC LOW NOISE MODE The noise level generated by the DC-DC converter can possibly influence precise voltage monitoring on VLD and ADC. To avoid such noise influence the DC-DC converter can be put in IDLE mode during such measurements. The IDLE duration is purely software controlled. Writing ‘1’ in DC-DCIdle in register RegDC-DCCfg[4] force the DC-DC off, in this mode the external capacitance becomes the only source of energy. Then the big consumer shall be switched off when DC-DCIdle is set to ‘1’. It is recommended to use the VLD to supervise VSUP and switch the DC-DC on when the supply is to low. The time the DC-DC can be in idle is related to the maximum voltage drop on VSUP, the external capacitor value and the current consumption as follows. TDC-DCIdle: Delay in idle mode C EXT VSUP Cext: External capacitor value T DCDCIdle VSUP: Drop on VSUP I SUP ISUP: Current consumption on VSUP Note: The DC-DC – Step-Up converter does not allow Voltage down conversion. Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 115 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 23.4 DC-DC REGISTER Bits 7 6:5 4 3 2:0 0x005D Name EnDC-DC DC-DCLevel DC-DCIdle DC-DCStartSts - RegDC-DCCfg Type ResVal ResSrc RW 0 ResAna RW '00' ResAna RW 0 ResAna RO 0 NI - Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 116 DC-DC Configuration Description Enable DC-DC Select DC-DC Output Level DC-DC Idle mode DC-DC Start-up status Not implemented www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 24. BAND GAP The band gap voltage reference, written also BGR in this document, generates the reference voltage used for the following peripherals: VLD (while VLD enabled) ADC, (while ADC enabled CPU in active or standby mode) DC-DC, (while DCDC enabled) OPAMP (while OPAMP enabled and the BGR or the VLD reference is selected as one of the OPAMP inputs BGR output on PA[6], (while the reference voltage is output) NVM memory modification (fully controlled by ROM-API) First time enabled allow for 130us reference voltage stabilization time before using one of the above mention functions needing the BGR voltage. The reference voltage is automatically enabled as soon as one of the above mentioned functions is enabled. The reference voltage can be forced on by writing the bit NVMEnWrite in register RegBgrCfg[6] to ‘1’ prior to use it for destination function. This allows using the VLD and ADC immediately after enabling (no need to wait first for BGR stabilization). The BGR can be used as an external reference as well. Writing ‘1’ in BgrEnOut in register RegBgrCfg[7] connects the voltage reference to PA[6] that shall be configured as analog pad before (digital output and input mode off and no pull’s). 24.1 BAND GAP REGISTER 0x0060 Bits Name 7 BgrEnOut 6 NVMEnWrite 5:0 - RegBgrCfg Type ResVal RW 0 RW 0 NI - ResSrc ResSys ResSys - BandGap reference configuration Description Enable BandGap reference output to Port Enables BandGap in active mode Not implemented Note: When connecting the reference voltage to the PA[6] output , the reference voltage may drop during the switching transition due to charge sharing from the internal reference voltage node to the external PA[6] pad and its attached capacitance. In this case the settling time can be longer than 130us. Always use the reference voltage only once it is completely stabilized. Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 117 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 25. VLD The Voltage Level Detector (VLD) compares a voltage on a terminal pad to a fix reference and returns the result ‘1’ or generates an interrupt if the voltage is below the reference. The measurement is static meaning that there is no need to start any sequence and the selected voltage source terminal is continuously supervised. The reference voltage VVLD is factory pretrimmed. 25.1 VLD SOURCE AND LEVEL SELECTION There are 8 terminals selectable with VLDSelSrc[2:0] in register RegVLDCfg1[5:3] as follows: VLDSelSrc[2:0] Source 000 001 010 011 100 101 110 111 VSUP (default) PA1 PA2 PC1 PC5 PA6 PC6 PA7 The are 32 target level selectable with VLDSelLev[4:0] in register RegVLDCfg2[4:0] as follows: Refer to the electricalspecification for the voltage levels (spread from 0.8V to 3.0V) VLDSelLev[4:0] 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 Level VLD0 VLD1 VLD2 VLD3 VLD4 VLD5 VLD6 VLD7 VLD8 VLD9 VLD10 VLD11 VLD12 VLD13 VLD14 VLD15 VLDSelLev[4:0] 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 Level [V] VLD16 VLD17 VLD18 VLD19 VLD20 VLD21 VLD22 VLD23 VLD24 VLD25 VLD26 VLD27 VLD28 VLD29 VLD30 VLD31 25.2 VLD ENABLE VLD is enable writing ‘1’ in EnVLD in register RegVLDCfg1[7]. After enabling it is recommended to wait 150us before enabling the related interrupt or read the VLD result to allow the reference voltage to stabilize. This stabilization wait is only needed if the internal BGR voltage was not enabled for 150us prior to enabling the VLD. If the BGR was already enabled before still allow 20us for the VLD reference to stabilize after VLD enabling. Refer also to 24. 25.3 VLD RESULT When the voltage measured is below the VLD level the read-only bit VLDRes in register RegVLDCfg1[6] is at ‘1’. Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 118 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 25.4 VLD INTERRUPT An interrupt is generated when the voltage measured is below the VLD level. The VLD interrupt IntSts2Vld is in register RegInt2Sts[7]. 25.5 VLD TRIMMING The VLD reference voltage VVLD is trimmed in production independently of the BGR. The trimming value is stored in the NVM at the address 0x6FF9. During the boot ROM sequence this value is copied in TrimVLD[3:0] in register RegTrimVLD. The user can modify this register to move slightly all VLD levels. 25.6 VLD REGISTERS 0x005E Bits Name 7 EnVLD 6 VLDRes 5:3 VLDSelSrc 2:0 - RegVLDCfg1 Type ResVal RW 0 RO 0 RW '000' NI - 0x005F Bits Name 7:5 4:0 VLDSelLev RegVLDCfg2 Type ResVal NI RW 0x00 0x02A4 Bits Name 7:4 3:0 TrimVLD RegTrimVLD Type ResVal NI RW 0x8 Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 ResSrc ResSys ResSys ResSys - VLD Configuration - 1 Description Enable VLD VLD Result/Output Select VLD Input/Source Not implemented ResSrc ResSys VLD Configuration - 2 Description Not implemented Select VLD Level ResSrc ResAna Trimming value for VLD Description Not implemented Trimming value for VLD 119 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 26. RC OSCILLATOR There are 2 main internal RC oscillators: 15MHz oscillator (runs at 14.7456 MHz but called 15MHz oscillator) 2MHz oscillator Thes 2 oscillators are factory pretrimmed, the trim value is stored in the NVM at the following addresses: 15MHz oscillator: 0x6FFD 2MHz oscillator: 0x6FFC The boot ROM sequence copies the 15MHz trimming value from the NVM into TrimOsc15M in register RegTrimOsc15M and the 2MHz trimming value from the NVM into TrimOsc2M in register RegTrimOsc2M. The user can modify these two trimming in their destination register RegTrimOsc15M, RegTrimOsc2M. Note: Before any CALL of sub-routine erasing or writing the NVM, the default RC timming values from NVM shall be restored. 26.1 RC OSCILLATORS REGISTERS 0x02A2 Bits Name 7:0 TrimOsc15M RegTrimOsc15M Type ResVal RW 0x80 0x02A3 Bits Name 7:0 TrimOsc2M RegTrimOsc2M Type ResVal RW 0x80 Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 ResSrc ResAna Trimming value for the 15 MHz Oscillator Description Trimming value for the 15 MHz Oscillator ResSrc ResAna Trimming value for the 2 MHz Oscillator Description Trimming value for the 2 MHz Oscillator 120 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 27. XTAL OSCILLATOR 32KHZ XTAL oscillator is connected to the terminal pads PA4 (XIN) and PC4 (XOUT). These two pads shall be configured in analog mode (output and input mode disable and no pull’s) before to launch the XTAL oscillator. Note: The XTAL oscillator shall be located as close as possible to the 6819. Both wires XIN and XOUT shall be routed as short as possible on the board. For all information concerning the different configuration related to the 32 KHz XTAL oscillator, refer to the chapter “Oscillator and Clocking structure”. Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 121 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 28. RESONATOR 4MHZ RC resonator is connected to the terminal pads PA4 (XIN) and PC4 (XOUT). These two pads shall be configured in analog mode (output and input mode disable and no pull’s) before to launch the resonator. Note: The Resonator shall be located as close as possible to the 6819. Both wires XIN and XOUT shall be routed as short as possible on the board. Two capacitors of 39pF shall be implemented on the board. The first between XIN and VSS, the second between XOUT and VSS as describe in the following schematic: XIN XOUT Ls Rs Cs 39pF 39pF Cp For all information concerning the different configuration related to the 4MHz resonator, refer to the chapter “Oscillator and Clocking structure”. Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 122 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 29. 8KHZ OSCILLATOR The 8kHz oscillator is used mainly for the watch-dog and the sleep counter wake-up system. Its frequency is not trimmable. However timings generated by the 8kHz oscillator can be calibrated with the trimmed 2Mhz or 15Mhz oscillator. For very low power applications it is also possible possible to use the 8kHz oscillator for the CPU and the prescalers For all information concerning the different configuration related to the 8kHz oscillator, refer to the chapter “Oscillator and Clocking structure”. Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 123 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 30. ANALOG OPAMP Each pin of the OPAMP in 6819 can be connected to different terminal or other peripherals. The positive input selection is done with OpAmpSelInpPos[1:0] in register RegOpAmpCfg2[7:0] as following: OpAmpSelInpPos[1:0] positive input 00 PA3 01 PC3 10 VBGR 11 VVLD The negative input selection is done with OpAmpSelInpNeg[1:0] in register RegOpAmpCfg[7:0] as following: OpAmpSelInpNeg[1:0] negative input 00 01 10 11 PA2 PC2 VBGR VVLD When the OPAMP is enable and comparator disable, the output can be mapped on to different terminal with OpAmpSelOut in register RegOpAmpCfg[3] as follows: OpAmpSelOut 0 1 output PA1 PC1 30.1 SELECT OPAMP/COMPARATOR To enable the OPAMP, EnOpAmp in register RegOpAmpCfg1[7] shall be set at ‘1’. In this case the selected terminals are connected to the OPAMP. The terminal shall be configure in analog mode before to enable the OPAMP, it is not done automatically (output and input mode disable and no pull’s). To enable the comparator EnOpAmp in register RegOpAmpCfg1[7] and EnComp in register RegOpAmpCfg1[6] shall set at ‘1’. In this mode the output is not mapped on any of the two terminals PA1 or PC1. 30.2 SUPPLY SELECTION The OPAMP and the comparator are able to work under VREG or VSUP voltage to be able to select two different swings. Even when 6819 is supplied at 0.9V it is possible to get a swing of 1.6V if the OPAMP is supplied by VREG. When OpAmpSup in register RegOpAmpCfg1 is at ‘0’ VSUP is selected, if it is at ‘1’ VREG is selected. VSUP VREG Opamp architecture OpaInpPos PA3 PC3 VBGR VVLD SelOpampSup EnOpamp CompRes OpaInpNeg IntOpAmp PA2 PC2 VBGR VVLD OpampOutSel EnOpamp && !EnComp EnComp PA1 PC1 Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 124 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 30.3 COMPARATOR RESULT The comparator result is mapped on the read-only bit CompRes in register RegOpAmpCfg1[4]. The comparator can generate an interrupt mapped on Int1StsOpAmp in register RegInt1Sts[3]. It is possible to set on which edge the interrupt is generated with SelCompInt[1:0] in register RegOpAmpCfg1[3:2] as follows: SelCompInt[1:0] interrupt generation 00 01 10 11 no interrupt interrupt on rising edge interrupt on falling edge interrupt on both edges 30.4 OPAMP REGISTERS 0x005B Bits Name 7 EnOpAmp 6 EnComp 5 OpAmpSup 4 CompRes 3:2 SelCompInt 1:0 - RegOpAmpCfg1 Type ResVal RW 0 RW 0 RW 0 RO 0 RW '00' NI - 0x005C Bits Name 7:6 5:4 3 2:0 OpAmpSelInpPos[1:0] OpAmpSelInpNeg[1:0] OpAmpSelOut - ResSrc ResSys ResSys ResSys ResSys ResSys - OpAmp Configuration - 1 Description Enable OP Amplifier Enable/Select OpAmp as Comparator OpAmp Supply: 0-Vbat, 1-Vreg Comparator Result Selector/Enable of Comparator Interrupt Not implemented RegOpAmpCfg2 Type Bits Name OpAmp Configuration - 2 Type RW RW RW NI ResAna ResAna ResAna - Select opamp positive input source Select opamp negative input source Select opamp output pad Not implemented Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 0 0 0 - 125 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 31. BLOCKS CONSUMPTION Following table shows the consumption of different blocks of EM6819 in typical conditions. Consumption of system, CPU, NVM access etc… have been excluded for each block to get only the consumption of the block itself. Temperature: 25°C VSUP: 3V Block Consumption Brown-out Watch-dog Sleep counter wake-up RC 15 MHz RC 2 MHz RC 8 kHz Xtal BGR VLD 600 nA 40 nA 90 nA 23 uA 6 uA 90 nA 400 nA 11 uA 7.2 uA ADC 50 uA OpAmp 52 uA 18 uA Timers 26 uA SPI 16 uA Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 Special conditions VLD source: VSUP VLD level: 0 Sampling rate: 12.5 kS/s Range: 8/8 Reference: BGR (Not included in consumption) ADC Input: PC1 = 0.618 V (Vref / 2) Comparator mode: Off OpAmp supply: VSUP Input neg: PA2 = 0V Input pos: PA3 = VSUP (3V) Output: PC1 = VSUP (3V) Comparator mode: Off OpAmp supply: VSUP Input neg: PA2 = VSUP (3V) Input pos: PA3 = 0V Output: PC1 = 0V Timer1 consumption considered CPU clock: 8kHz Prescaler1 clock: 2 MHz Prescaler2 clock: 8 kHz Timer1 clock: Prescaler1 Ck15 (2 MHz) SPI mode: Master, Auto start SCLK clock: 2 MHz (not mapped on any pad) SIN: PA4 = 0V SOUT: Not mapped on any pad Sequence: Write 0xAA ; 0x55 continously in RegSPIDOut 126 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 32. TYPICAL T AND V DEPENDENCIES 32.1 IDD CURRENTS 32.1.1 GENERAL CONDITIONS Mode Active Stand-by Sleep Powerdown Description CPU: Software: Prescaler1: Prescaler2: Brown-out: Watch-dog: Regulator: CPU: Software: Prescaler1: Prescaler2: Brown-out: Watch-dog: Regulator: CPU: Software: Prescaler1: Prescaler2: Brown-out: Watch-dog: Regulator: CPU: Software: Prescaler1: Prescaler2: Brown-out: Watch-dog: Regulator: running at selected clock makes a loop and writes/reads continuously the RAM Running on ck_hi when available otherwise ck_lo Always running on ck_lo Enable Running on 8kHz Vreg = 1.8V enable ; multiplier enable when VSUP is low ; retention voltage off Halt state No software executed Running on ck_hi when available otherwise ck_lo Always running on ck_lo Enable Running on 8kHz Vreg = 1.8V enable ; multiplier enable when VSUP is low ; retention voltage off Halt state No software executed Disable Disable Disable Disable Vreg = 1.8V enable ; multiplier off ; retention voltage enable Halt state No software executed Disable Disable Disable Disable Vreg = 1.8V off ; multiplier off ; retention voltage off Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 127 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x Figure 31, Temperature and supply dependency for consumption @ 15 MHz Idd 15MHz active over temperature @ VSUP = 3V 1200 1200 1000 1000 800 800 Idd [uA] Idd [uA] Idd 15MHz active over VSUP @ Temperature = 25°C 600 600 400 400 200 200 0 0 2.2 2.4 2.6 2.8 3 3.2 3.4 -40 3.6 -20 0 40 60 80 60 80 Idd 15MHz std-by over temperature @ VSUP = 3V Idd 15MHz std-by over VSUP @ Temperature = 25°C 100 100 90 90 80 80 70 70 60 60 Idd [uA] Idd [uA] 20 Temperature [°C] VSUP [V] 50 50 40 40 30 30 20 20 10 10 0 0 2.2 2.4 2.6 2.8 3 3.2 3.4 -40 3.6 Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 -20 0 20 40 Temperature [°C] VSUP [V] 128 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x Figure 32, Temperature and supply dependency for consumption @ 2 MHz Idd 2MHz active over temperature @ VSUP = 3V 1000 200 900 180 800 160 700 140 600 120 Idd [uA] Idd [uA] Idd 2MHz active over VSUP @ Temperature = 25°C 500 100 400 80 300 60 200 40 100 20 0 0 0.9 1.4 1.9 2.4 2.9 -40 3.4 -20 0 Idd 2MHz std-by over VSUP @ Temperature = 25°C 40 60 80 60 80 Idd 2MHz std-by over temperature @ VSUP = 3V 100 20 90 18 80 16 70 14 60 12 Idd [uA] Idd [uA] 20 Temperature [°C] VSUP [V] 50 10 40 8 30 6 20 4 10 2 0 0 0.9 1.4 1.9 2.4 2.9 3.4 -40 VSUP [V] Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 -20 0 20 40 Temperature [°C] 129 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x Figure 33, Temperature and supply dependency for consumption @ 4 MHz resonator Idd 4MHz resonator active over temperature @ VSUP = 3V 500 500 450 450 400 400 350 350 300 300 Idd [uA] Idd [uA] Idd 4MHz resonator active over VSUP @ Temperature = 25°C 250 250 200 200 150 150 100 100 50 50 0 0 2.2 2.4 2.6 2.8 3 3.2 3.4 -40 3.6 -20 0 40 60 80 60 80 Idd 4MHz resonator std-by over temperature @ VSUP = 3V Idd 4MHz resonator std-by over VSUP @ Temperature = 25°C 50 50 45 45 40 40 35 35 30 30 Idd [uA] Idd [uA] 20 Temperature [°C] VSUP [V] 25 25 20 20 15 15 10 10 5 5 0 0 2.2 2.4 2.6 2.8 3 3.2 3.4 -40 3.6 Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 -20 0 20 40 Temperature [°C] VSUP [V] 130 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x Figure 34, Temperature and supply dependency for consumption @ 32 kHz XTAL Idd 32kHz active over temperature @ VSUP = 3V Idd 32kHz active over VSUP @ Temperature = 25°C 20 9 18 8 16 7 6 12 Idd [uA] Idd [uA] 14 10 5 4 8 3 6 2 4 1 2 0 0 0.9 1.4 1.9 2.4 2.9 -40 3.4 -20 0 20 40 60 80 60 80 Temperature [°C] VSUP [V] Idd 32kHz std-by over temperature @ VSUP = 3V Idd 32kHz std-by over VSUP @ Temperature = 25°C 6 10 9 5 8 4 6 Idd [uA] Idd [uA] 7 5 3 4 2 3 2 1 1 0 0 0.9 1.4 1.9 2.4 2.9 -40 3.4 Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 -20 0 20 40 Temperature [°C] VSUP [V] 131 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x Figure 35, Temperature and supply dependency for consumption @ 8 kHz Idd 8kHz active over temperature @ VSUP = 3V Idd 8kHz active over VSUP @ Temperature = 25°C 7 20 18 6 16 5 12 Idd [uA] Idd [uA] 14 10 8 6 4 3 2 4 1 2 0 0 0.9 1.4 1.9 2.4 2.9 -40 3.4 -20 0 20 40 60 80 60 80 Temperature [°C] VSUP [V] Idd 8kHz std-by over temperature @ VSUP = 3V Idd 8kHz std-by over VSUP @ Temperature = 25°C 6 20 18 5 16 4 12 Idd [uA] Idd [uA] 14 10 3 8 2 6 4 1 2 0 0 0.9 1.4 1.9 2.4 2.9 -40 3.4 Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 -20 0 20 40 Temperature [°C] VSUP [V] 132 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x Figure 36, Temperature and supply dependency for consumption in sleep mode Idd sleep without sleep counter wake-up over temperature @ VSUP = 3V 5 5 4.5 4.5 4 4 3.5 3.5 3 Idd [uA] Idd [uA] Idd sleep without sleep counter wake-up over VSUP @ Temperature = 25°C 2.5 3 2.5 2 2 1.5 1.5 1 1 0.5 0.5 0 0 0.9 1.4 1.9 2.4 2.9 -40 3.4 -20 0 40 60 80 Idd sleep with sleep counter wake-up over temperature @ VSUP = 3V Idd sleep with sleep counter wake-up over VSUP @ Temperature = 25°C 5 5 4.5 4.5 4 4 3.5 3.5 3 Idd [uA] Idd [uA] 20 Temperature [°C] VSUP [V] 2.5 3 2.5 2 2 1.5 1.5 1 1 0.5 0.5 0 0 0.9 1.4 1.9 2.4 2.9 -40 3.4 Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 -20 0 20 40 60 80 Temperature [°C] VSUP [V] 133 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x Figure 37, Temperature and supply dependency for consumption in power-down mode Idd power-down over temperature @ VSUP = 3V Idd power-down over VSUP @ Temperature = 25°C 700 1200 600 1000 500 Idd [nA] Idd [nA] 800 400 300 600 400 200 200 100 0 0 0.9 1.4 1.9 2.4 2.9 -40 3.4 -20 0 20 40 60 80 Temperature [°C] VSUP [V] 32.2 IOL AND IOH DRIVES Figure 38, Temperature and supply dependency for IOL & IOH on PA[7:5,3] & PC[6:5,3] IOL on PA[7:5,3] & PC[6:5,3] over temperature @ VSUP = 3V @ VDS = 0.3V IOL on PA[7:5,3] & PC[6:5,3] over VSUP @ Temperature = 25°C @ VDS = 0.3V 14 12 12 10 10 Idd [mA] Idd [mA] 8 6 8 6 4 4 2 2 0 0 0.9 1.4 1.9 2.4 2.9 -40 3.4 -20 0 40 60 80 IOH on PA[7:5,3] & PC[6:5,3] over temperature @ VSUP = 3V @ VDS = VUSP - 0.3V IOH on PA[7:5,3] & PC[6:5,3] over VSUP @ Temperature = 25°C @ VDS = VUSP - 0.3V 0 0 -2 -2 -4 -4 -6 -6 Idd [mA] Idd [mA] 20 Temperature [°C] VSUP [V] -8 -8 -10 -10 -12 -12 -14 -14 -16 -16 0.9 1.4 1.9 2.4 2.9 -40 3.4 Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 -20 0 20 40 60 80 Temperature [°C] VSUP [V] 134 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x Figure 39, Temperature and supply dependency for IOL & IOH on PA[4,2:0] & PC[7,4,2:0] IOL on PA[4,2:0] & PC[7,4,2:0] over temperature @ VSUP = 3V @ VDS = 0.3V IOL on PA[4,2:0] & PC[7,4,2:0] over VSUP @ Temperature = 25°C @ VDS = 0.3V 7 6 6 5 5 Idd [mA] Idd [mA] 4 3 4 3 2 2 1 1 0 0 0.9 1.4 1.9 2.4 2.9 -40 3.4 -20 0 20 0 -0.5 -1 -1 -1.5 -1.5 Idd [mA] Idd [mA] 0 -0.5 -2 -2.5 -2 -3 -3.5 -3.5 -4 -4 -4.5 -4.5 1.9 80 -2.5 -3 1.4 60 IOH on PA[4,2:0] & PC[7,4,2:0] over temperature @ VSUP = 3V @ VDS = VUSP - 0.3V IOH on PA[4,2:0] & PC[7,4,2:0] over VSUP @ Temperature = 25°C @ VDS = VUSP - 0.3V 0.9 40 Temperature [°C] VSUP [V] 2.4 2.9 -40 3.4 Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 -20 0 20 40 60 80 Temperature [°C] VSUP [V] 135 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x Figure 40, Temperature and supply dependency for IOL & IOH on PB[7:0] IOL on PB[7:0] over temperature @ VSUP = 3V @ VDS = 0.3V IOL on PB[7:0] over VSUP @ Temperature = 25°C @ VDS = 0.3V 14 12 12 10 10 Idd [mA] Idd [mA] 8 6 4 8 6 4 2 2 0 0 0.9 1.4 1.9 2.4 2.9 -40 3.4 -20 0 40 60 80 60 80 IOH on PB[7:0] over temperature @ VSUP = 3V @ VDS = VUSP - 0.3V IOH on PB[7:0] over VSUP @ Temperature = 25°C @ VDS = VUSP - 0.3V 0 0 -2 -2 -4 -4 -6 -6 Idd [mA] Idd [mA] 20 Temperature [°C] VSUP [V] -8 -8 -10 -10 -12 -12 -14 -14 -16 -16 0.9 1.4 1.9 2.4 2.9 -40 3.4 Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 -20 0 20 40 Temperature [°C] VSUP [V] 136 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 32.3 PULL-UP AND PULL-DOWN Figure 41, Temperature and supply dependency for pull-down & pull_up on PA[7:0] & PC[7:0] Pull-down on PA[7:0] & PC[7:0] over temperature @ VSUP = 3V 80000 80000 79000 79000 78000 78000 77000 77000 76000 76000 R [Ohm] R [Ohm] Pull-down on PA[7:0] & PC[7:0] over VSUP @ Temperature = 25°C 75000 75000 74000 74000 73000 73000 72000 72000 71000 71000 70000 70000 0.9 1.4 1.9 2.4 2.9 -40 3.4 -20 0 40 60 80 Pull-up on PA[7:0] & PC[7:0] over temperature @ VSUP = 3V Pull-up on PA[7:0] & PC[7:0] over VSUP @ Temperature = 25°C 80000 80000 79000 79000 78000 78000 77000 77000 76000 76000 R [Ohm] R [Ohm] 20 Temperature [°C] VSUP [V] 75000 75000 74000 74000 73000 73000 72000 72000 71000 71000 70000 70000 0.9 1.4 1.9 2.4 2.9 -40 3.4 Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 -20 0 20 40 60 80 Temperature [°C] VSUP [V] 137 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x Figure 42, Temperature and supply dependency for pull-down & pull_up on PB[7:0] Pull-down on PB[7:0] over temperature @ VSUP = 3V 75000 75000 74000 74000 73000 73000 72000 72000 71000 71000 R [Ohm] R [Ohm] Pull-down on PB[7:0] over VSUP @ Temperature = 25°C 70000 70000 69000 69000 68000 68000 67000 67000 66000 66000 65000 65000 0.9 1.4 1.9 2.4 2.9 -40 3.4 -20 0 40 60 80 60 80 Pull-up on PB[7:0] over temperature @ VSUP = 3V Pull-up on PB[7:0] over VSUP @ Temperature = 25°C 75000 75000 74000 74000 73000 73000 72000 72000 71000 71000 R [Ohm] R [Ohm] 20 Temperature [°C] VSUP [V] 70000 70000 69000 69000 68000 68000 67000 67000 66000 66000 65000 65000 0.9 1.4 1.9 2.4 2.9 -40 3.4 Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 -20 0 20 40 Temperature [°C] VSUP [V] 138 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 32.4 RC OSCILLATOR 15MHZ AND 2MHZ Figure 43, Temperature and supply dependency for internal RC oscillators RC 15Mhz frequency error over temperature @ VSUP 3V 10 10 8 8 6 6 4 4 Frequency error [%] Frequency error [%] RC 15Mhz frequency error over VSUP @ Temperature = 25°C 2 0 -2 -4 -6 2 0 -2 -4 -6 -8 -8 -10 -10 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 -40 -20 0 VSUP [V] RC 2Mhz frequency error over VSUP @ Temperature = 25°C 40 60 80 60 80 RC 2Mhz frequency error over temperature @ VSUP = 3V 10 10 8 8 6 6 4 4 Frequency error [%] Frequency error [%] 20 Temperature [°C] 2 0 -2 -4 -6 2 0 -2 -4 -6 -8 -8 -10 -10 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 3.3 3.6 -40 VSUP [V] Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 -20 0 20 40 Temperature [°C] 139 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 33. ELECTRICAL SPECIFICATION 33.1 ABSOLUTE MAXIMUM RATINGS Min. Max. Units Power supply VSUP-VSS - 0.2 +3.8 V Input voltage VSS – 0.2 VSUP+0.2 V Storage temperature - 40 + 125 °C Electrostatic discharge to -2000 +2000 V Mil-Std-883C method 3015.7 with ref. to VSS Maximum soldering conditions As per Jedec J-STD-020C Packages are Green-Mold and Lead-free Stresses above these listed maximum ratings may cause permanent damage to the device. Exposure beyond specified electrical characteristics may affect device reliability or cause malfunction 33.2 HANDLING PROCEDURES This device has built-in protection against high static voltages or electric fields; however, anti-static precautions should be taken as for any other CMOS integrated circuit. Unless otherwise specified, proper operation can only occur when all terminal voltages are kept within the supply voltage range. 33.3 STANDARD OPERATING CONDITIONS Parameter Temperature VSUP_range MIN -40 0.9 DCDC VSUP min IVSS max IVSUP max DCDC input current VSS CVREG (1) CVSUP (with dc-dc) LDCDC (with dc-dc) Flash data retention TYP 25 3 MAX 85 3.6 Unit °C V 0.6 V 80 80 mA mA 500 mA 0 V nF uF uH 400 40 39 20 yrs Description Voltage at power-up Minimum battery voltage after start-up with DC-DC enabled; maximum current load 10 mA at 0.6V Maximum current out of VSS Pin Maximum current into VSUP Pin Maximum current from the Battery into the DCDC Reference terminal regulated voltage capacitor Supply voltage capacitor with DC-DC DC-DC coil Read and Erase state retention 1 cycle is one erase followed by 1 write Note 1: This capacitor filters switching noise from VSUP to keep it away from the internal logic and memory cells. In noisy systems the capacitor should be chosen higher than minimum value. Flash cycling Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 10k cycle 140 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 33.4 TYPICAL 32KHZ CRYSTAL SPECIFICATION Fq 32768 Hz nominal frequency Rqs 35 KOhm typical quartz serial resistance CL 8.2 pF typical quartz load capacitance df/f ppm quartz frequency tolerance 30 Watch type crystal oscillator (i.e Microcrystal DS15 ), connected between QIN and Qout terminal. 33.5 TYPICAL 4MHZ CRYSTAL SPECIFICATION FR RS CS CP LS df/f 4 22 3.8 19.8 460 30 MHz Ohm pF pF uH ppm nominal frequency Typical equivalent resistor Typical equivalent serial capacitor Typical equivalent parallel capacitor Typical equivalent inductor quartz frequency tolerance 33.6 TYPICAL 4MHZ RESONATOR SPECIFICATION FR 4 MHz nominal frequency RS 9 Ohm Typical equivalent resistor CS 0.007 pF Typical equivalent serial capacitor CP 2.39 pF Typical equivalent parallel capacitor LS 210 mH Typical equivalent inductor df/f % Resonator frequency tolerance 0.5 Watch type resonator oscillator CERALOCK Murata CSTLS4M00G53–B0, connected between QIN and Qout terminal. Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 141 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 33.7 DC CHARACTERISTICS - POWER SUPPLY CURRENTS Conditions: In active mode, the software makes a loop and writes/reads continuously the RAM, the following blocks are active: NVM instructions read access Regulator RAM read/write access Voltage multiplier in low voltage mode Prescalers 1 & 2 Brown-out Selected oscillator Power on reset RC 8kHz Internal bias current generation In stand-by mode, the software execution is stopped; the following blocks are active: Prescalers 1 & 2 Voltage multiplier in low voltage mode Selected oscillator Brown-out RC 8kHz Power on reset Regulator Internal bias current generation In sleep mode, the software execution is stopped; the following blocks are active: RC 8kHz Brown-out Regulator Power on reset Voltage multiplier in low voltage mode Internal bias current generation In power-down mode, the software execution is stopped; the following blocks are active: Power on reset Internal bias current generation Following table includes product: EM6819FX-AXX0 / -BXX0 / -BXX4 , all measures without DCDC Parameter Conditions Symbol Min. Typ. Max. Unit ACTIVE Supply Current VSUP =3V, -40 to 85°C, 7.5 MIPS IVSUPA15MD1 1.05 1.7 mA CPU on RC=15MHz, no div ACTIVE Supply Current CPU on RC=2MHz, no div ACTIVE Supply Current CPU on XTal=32KHz, no div ACTIVE Supply Current CPU on RC=8KHz, no div Std-by Supply Current Peri on RC=15MHz, no div Std-by Supply Current Peri on RC=2MHz, no div Std-by Supply Current Peri on RC=2MHz (2), no div Std-by Supply Current Peri on XTal=32KHz, no div Std-by Supply Current Peri on RC=8KHz, no div Sleep Supply Current Wake-up counter on Sleep Supply Current Wake-up counter off IVSUPA2MD1 140 IVSUPA2MD1 490 VSUP =3V, -40 to 60°C, 16 kIPS IVSUPA32K IVSUPA32K 4.2 4.2 VSUP =3V, -40 to 85°C, 4 kIPS IVSUPA8K 3.5 uA VSUP =3V, -40 to 85°C, HF Div=1 IVSUPH15MD1 72 uA VSUP =3V, -40 to 85°C, HF Div=1 StdByFastWkUp=0 IVSUPH2MD1 14 uA VSUP =1.2V, -40 to 85°C, HF Div=1 IVSUPH2MD1 35 uA VSUP =3V, -40 to 85°C, HF RC off StdByFastWkUp=0 VSUP =1.2V, -40 to 85°C, HF RC off StdByFastWkUp=0, Note2 VSUP =3V, -40 to 60°C, HF RC off StdByFastWkUp=0 VSUP =3V, -40 to 85°C, HF RC off StdByFastWkUp=0 VSUP =3V, -40 to 60°C, HF RC off StdByFastWkUp=0 VSUP =3V, -40 to 85°C StdByFastWkUp=0 VSUP =3V, -40 to 60°C, RC 8kHz on StdByFastWkUp=0 VSUP =3V, -40 to 85°C, RC8kHz off StdByFastWkUp=0 IVSUPH32K 2.3 IVSUPH32K 5 IVSUPH32K 2.3 5 uA IVSUPH8K 2.3 9 uA IVSUPH8K 2.3 5 uA IVSUPSWK 1.95 8 uA IVSUPSWK 1.95 4 uA IVSUPSLEEP 1.9 IVSUPPWDWN IVSUPPWDWN IVSUPPWDWN 0.45 0.45 0.45 VSUP =3V, -40 to 85°C, 1 MIPS VSUP =1.2V, -40 to 85°C, 1MIPS Note2 VSUP =3V, -40 to 85°C, 16 kIPS VSUP =3V, -40 to 25°C Powerdown VSUP =3V, -40 to 60°C VSUP =3V, -40 to 85°C 250 uA uA 13 8 10 uA uA uA uA uA 0.65 0.8 1.65 uA uA uA Note 2: Internal voltage multiplier enable. Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 142 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x Following table includes product: EM6819FX-XX5 / -XX6, all measures without DCDC Parameter Conditions Symbol Min. Typ. ACTIVE Supply Current VSUP =3V, -40 to 85°C, 7.5 MIPS I 0.85 VSUPA15MD1 CPU on RC=15MHz, no div ACTIVE Supply Current CPU on RC=2MHz, no div ACTIVE Supply Current CPU on XTal=32KHz, no div ACTIVE Supply Current CPU on RC=8KHz, no div Std-by Supply Current Peri on RC=15MHz, no div Std-by Supply Current Peri on RC=2MHz, no div Std-by Supply Current Peri on XTal=32KHz, no div Std-by Supply Current Peri on RC=8KHz, no div Sleep Supply Current Wake-up counter on 1.2 mA 180 uA 116 IVSUPA2MD1 490 VSUP =3V, -40 to 60°C, 16 kIPS IVSUPA32K IVSUPA32K 4.2 4.2 VSUP =3V, -40 to 85°C, 4 kIPS IVSUPA8K 3.5 uA VSUP =3V, -40 to 85°C, HF Div=1 IVSUPH15MD1 72 uA VSUP =3V, -40 to 85°C, HF Div=1 IVSUPH2MD1 14 uA IVSUPH32K 2.3 10 uA IVSUPH32K 2.3 5 uA IVSUPH8K 2.3 9 uA IVSUPH8K 2.3 5 uA IVSUPSWK 1.95 8 uA IVSUPSWK 1.95 4 uA IVSUPSLEEP 1.9 IVSUPPWDWN IVSUPPWDWN IVSUPPWDWN 0.45 0.45 0.45 VSUP =3V, -40 to 85°C, HF RC off StdByFastWkUp=0 VSUP =3V, -40 to 60°C, HF RC off StdByFastWkUp=0 VSUP =3V, -40 to 85°C, HF RC off StdByFastWkUp=0 VSUP =3V, -40 to 60°C, HF RC off StdByFastWkUp=0 VSUP =3V, -40 to 85°C StdByFastWkUp=0 VSUP =3V, -40 to 60°C, RC 8kHz on StdByFastWkUp=0 VSUP =3V, -40 to 85°C, RC8kHz off VSUP =3V, -40 to 25°C Powerdown Current Unit IVSUPA2MD1 VSUP =3V, -40 to 85°C, 1 MIPS VSUP =1.2V, -40 to 85°C, 1MIPS Note2 VSUP =3V, -40 to 85°C, 16 kIPS Sleep Supply Current Wake-up counter off Max. VSUP =3V, -40 to 60°C VSUP =3V, -40 to 85°C uA 13 8 uA uA uA 0.65 0.8 1.65 uA uA uA Note 2: Internal voltage multiplier enable. Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 143 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 33.8 DC CHARACTERISTICS – VOLTAGE DETECTION LEVELS Parameter Conditions POR VSUP static level on rising -40 to 85°C edge POR VSUP static level on falling -40 to 85°C edge -40 to 25°C Temperature coefficient 25 to 85°C VLD0, VBAT decreasing 25°C VLD1, VBAT decreasing 25°C VLD2, VBAT decreasing 25°C VLD3, VBAT decreasing 25°C VLD4, VBAT decreasing 25°C VLD5, VBAT decreasing 25°C VLD6, VBAT decreasing 25°C VLD7, VBAT decreasing 25°C VLD8, VBAT decreasing 25°C VLD9, VBAT decreasing 25°C VLD10, VBAT decreasing 25°C VLD11, VBAT decreasing 25°C VLD12, VBAT decreasing 25°C VLD13, VBAT decreasing 25°C VLD14, VBAT decreasing 25°C VLD15, VBAT decreasing 25°C VLD16, VBAT decreasing 25°C VLD17, VBAT decreasing 25°C VLD18, VBAT decreasing 25°C VLD19, VBAT decreasing 25°C VLD20, VBAT decreasing 25°C VLD21, VBAT decreasing 25°C VLD22, VBAT decreasing 25°C VLD23, VBAT decreasing 25°C VLD24, VBAT decreasing 25°C VLD25, VBAT decreasing 25°C VLD26, VBAT decreasing 25°C VLD27, VBAT decreasing 25°C VLD28, VBAT decreasing 25°C VLD29, VBAT decreasing 25°C VLD30, VBAT decreasing 25°C VLD31, VBAT decreasing 25°C VLD trim bit step / LSB Symbol Typ. Max. Unit VPORRIS 0.7 0.86 V VPORFAL 0.58 0.74 V 0.01 0.01 0.800 0.820 0.840 0.860 0.880 0.900 0.920 0.940 0.960 0.980 1.000 1.100 1.150 1.200 1.300 1.400 1.450 1.500 1.600 1.700 1.900 2.100 2.300 2.400 2.500 2.550 2.600 2.700 2.800 2.900 2.950 3.000 1.7 0.134 0.142 %/°C %/°C V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V mV/V TVLD_COEF_LO TVLD_COEF_HI VVLD0 VVLD1 VVLD2 VVLD3 VVLD4 VVLD5 VVLD6 VVLD7 VVLD8 VVLD9 VVLD10 VVLD11 VVLD12 VVLD13 VVLD14 VVLD15 VVLD16 VVLD17 VVLD18 VVLD19 VVLD20 VVLD21 VVLD22 VVLD23 VVLD24 VVLD25 VVLD26 VVLD27 VVLD28 VVLD29 VVLD30 VVLD31 Min. -0.110 -0.117 2.981 3.025 33.9 DC CHARACTERISTICS – REFERENCE VOLTAGE Parameter Temperature coefficient Temperature coefficient Reference voltage after trimming Output load current on PA[2] Conditions -40 to 25°C 25 to 85°C Symbol TBGR_COEF_LO TBGR_COEF_HI VSUP =3V, 25°C VBGP 10 VSUP =3V, -40 to 85°C, VBGP output Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 Min. Typ. Max. -0.102 0.01 0.128 -0.112 0.01 0.136 1.225 1.236 1.247 144 Unit %/°C %/°C V uA www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 33.10 DC CHARACTERISTICS – DC-DC CONVERTER VBAT is input voltage of DC-DC (main Battery), VSUP is output voltage of DC-DC Parameter Conditions Symbol Min. -40 to 85°C Battery voltage range VBAT 0.9 -40 to 85°C ; DC-DC level 2.1 VDCDC2.1 DC-DC level 2.5 DC-DC level 2.9 DC-DC level 3.3 Output ripple Max external current current load DC-DC efficiency VBATMIN to VBATMAX -40 to 85°C ; VBATMIN to VBATMAX -40 to 85°C ; VBATMIN to VBATMAX -40 to 85°C ; VBATMIN to VBATMAX -40 to 85°C ; VBATMIN to VBATMAX -40 to 85°C ; @VBATMIN @ VBATMax, VDCDC =3.3V Typ. 2.1 Unit V V VDCDC2.5 2.5 V VDCDC2.9 2.9 V VDCDC3.3 3.3 V VRIP ILOAD09V ILOAD18V DCDCEFF -40 to 85°C ; VBATMIN to VBATMAX Max. 1.8 +/-100 mV 40 mA 150 mA % 85 33.11 DC CHARACTERISTICS – OSCILLATORS Parameter 32KHz XTAL Integrated Input capacitor 32KHz Xtal Integrated Output capacitor Conditions Reference on VSS Symbol T=25C Reference on VSS T=25C 32KHz Xtal Oscillator start VSUP > VSUPMin time T=25C 4MHz resonator start time 4MHz XTal start time RC oscillator 15MHz Temperature coefficient RC oscillator 15MHz Temperature coefficient RC Oscillator 15MHz RC Oscillator 15MHz Trimm range 15MHz RC Oscillator 15MHz Trimm step / LSB RC oscillator 2MHz Temperature coefficient RC oscillator 2MHz Temperature coefficient RC Oscillator 2MHz RC oscillator 2MHz Trimm range 2MHz RC oscillator 2MHz Trimm step / LSB RC Oscillator 8kHz VSUP > VSUPMin T=25C VSUP > VSUPMin T=25C Min. Typ. Max. Unit CIN 7 pF COUT 14 pF tdosc 0.5 4 s tdosc 1 10 ms tdosc 3 30 ms -40 to 25°C TRC15_COEF_LO -0.018 0.04 0.106 %/°C 25 to 85°C TRC15_COEF_HI -0.055 0.004 0.069 %/°C FRC15M 14.6129 14.7456 14.8783 MHz After trimming, 25°C +50/-30 % 47.8 kHz -40 to 25°C TRC2_COEF_LO -0.031 0.08 0.177 %/°C 25 to 85°C TRC2_COEF_HI -0.058 0.05 0.164 %/°C FRC1MHz 1.976 2 2.024 MHz % After trimming, 25°C Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 +50/-30 145 8.3 kHz 6.7 kHz www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 33.12 DC CHARACTERISTICS – VHIGH Parameter VHIGH level VSUP low VHIGH level VSUP high Conditions Symbol VHighLOW VSUP < 1.6V, -40 to 85°C VSUP > 1.6V, -40 to 85°C Min. 1.6 VSUP0.1 Typ. Max. 2.0 VSUP Unit V V Symbol A0 GBW PM PSRR CMRR NOISE VINOFFSET TON Min. Typ. 70 0.7 60 -24 -47 10 +/-10 20 Max. Unit dB MHz ° dB dB uV mV us VOS 1.3 ILOAD ILOAD SR -180 VHighHI 33.13 DC CHARACTERISTICS – OPAMP Parameter Open loop gain Gain band width Phase margin PSRR @ 100kHz CMRR @ 100kHz Noise Input offset Reaction time to enable signal Output voltage swing Current load IOH Current load IOL Slew rate Conditions VSUP =3V, -40 to 85°C VSUP =3V, -40 to 85°C VSUP =3V, -40 to 85°C VSUP =3V, -40 to 85°C VSUP =3V, -40 to 85°C VSUP =3V, -40 to 85°C VSUP =3V, -40 to 85°C VSUP =3V, -40 to 85°C VSUP =3.0V, -40 to 85°C VINCM=350mV OPAMP supply Vreg VSUP =3V, -40 to 85°C VSUP =3V, -40 to 85°C VSUP =3.0V, -40 to 85°C VINCM=350mV - 1.85 V 150 uA uA V/us 0.6 33.14 DC CHARACTERISTICS – ADC 10 bits ADC considered (RegADCOut1.ADCOutLSB is ignored) Parameter Conditions Symbol ADC offset -40 to 25°C TADC_COEF_LO Temperature coefficient ADC offset 25 to 85°C TADC_COEF_HI Temperature coefficient VSUP =3V, 25°C ADC offset ADC ADC DNL ADC INL + gain error ADC INL best fit ADC DNL range 8/8 ADCref = VBGP ; Rate 91kS/s Range 8/8 VSUP =3V, -40 to 85°C ADCref = VBGP ; Rate 91kS/s ; Range 8/8 VSUP =3V, -40 to 85°C ADCref = VBGP ; Rate 91kS/s ; Range 8/8 VSUP =3V, -40 to 85°C ADCref = VBGP ; Rate 91kS/s ; Range 8/8 VSUP =3V, -40 to 85°C ADCref = VBGP ; Rate 45kS/s ; Range 8/8 Min. Typ. Max. Unit -0.108 0.01 0.135 %/°C -0.114 0.02 0.150 %/°C -4 0 4 LSB ADCDNL -2 0 2 LSB ADCINLT -13 0 13 LSB ADCINLbestfit -6 0 6 LSB Offset ADCDNL6/8 +/0.5 +/0.5 +/0.5 LSB ADC DNL range 6/8 VSUP =3V, -40 to 85°C ADCref = VBGP ; Rate 45kS/s ; Range 6/8 ADCDNL6/8 ADC DNL range 4/8 VSUP =3V, -40 to 85°C ADCref = VBGP ; Rate 45kS/s ; Range 4/8 ADCDNL4/8 ADC INL best fit range 6/8 ADC INL best fit range 4/8 ADC INL best fit range 3/8 VSUP =3V, -40 to 85°C ADCref = VBGP ; Rate 45kS/s ; Range 6/8 ADCINLT6/8 +/- 4 LSB VSUP =3V, -40 to 85°C ADCref = VBGP ; Rate 45kS/s ; Range 4/8 ADCINLT4/8 +/- 4 LSB VSUP =3V, -40 to 85°C ADCref = VBGP ; Rate 45kS/s ; Range 3/8 ADCINLT4/8 +/- 4 LSB Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 146 LSB LSB www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 33.15 DC CHARACTERISTICS – TEMPERATURE SENSOR 10 bits ADC considered (RegADCOut1.ADCOutLSB is ignored) Parameter Conditions Symbol Min. Typ. Max. Unit VSUP =3V Temp sensor result at 25° Tempsens25 416 LSB Temp sensor result at -40° VSUP =3V Tempsens-40 183 LSB V =3V SUP Temp sensor result at 60° Tempsens60 550 LSB VSUP =3V Temp sensor result at 85° Tempsens85 639 LSB V =3V ; Temp range 0° 60° SUP Temp sensor slope Tempsensslope 3.8 LSB/° VSUP =3V ; Temp range 0° - 60° Temp sensor linearity Tempsenslin +/-0.8 % Note: offset & calibration values stored in NVM are coded on 11bits than values are twice values in above table. 33.16 DC CHARACTERISTICS - I/O PINS (ON PACKAGE) Conditions: T= -40 to 85C, VSUP=3.0V (unless otherwise specified) Parameter Conditions Symbol Input Low voltage Ports A,B, C VIL Input High voltage Ports A,B, C Input Hysteresis PA[7:0], PB[7:0], PC[7:0] IOL (high current drives) PA[7:5,3], PB[7:0], PC[6:5,3] VIH Temp=25°C Max. Unit VSS 0.2* VSUP V 0.8* VSUP VSUP V VHyst VSUP =3.0V , VOL=0.3V VSUP =3.0V , VOL=0.6V VSUP =3.0V , VOL=1.0V VSUP =3.0V , VOL=0.3V IOL VSUP =3.0V , VOL=0.6V PA[4,2:0], PC[7,4,2:0] VSUP =3.0V , VOL=1.0V IOH (high current drives) VSUP =3.0V , VOH= VSUP - 0.3V PA[7:5,3], PB[7:0], VSUP =3.0V , VOH= VSUP - 0.6V PC[6:5,3] VSUP =3.0V , VOH= VSUP - 1.0V VOH (high current drives) VSUP=3.3V, IOH= -20mA PA[3], PA[6], PB[6], PB[7] VSUP =3.0V , VOH= VSUP - 0.3V IOH VSUP =3.0V , VOH= VSUP - 0.6V PA[4,2:0], PC[7,4,2:0] VSUP =3.0V , VOH= VSUP - 1.0V Input Pull-down VSUP =3.0V, Pin at 3.0V Port A,B,C Input Pull-up Port A,B,C VSUP =3.0V, Pin at 0.0V Input Pull-down VSUP =3.0V, Pin at 3.0V TM Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 Min. 147 IOL IOL IOL IOL IOL IOL IOH IOH IOH VOH 4.2 1.6 VSUP0.82 IOH IOH IOH RPD RPU RPDTM Typ. 0.42 V 9.9 19.8 33.0 5.2 10.4 17.3 -12.7 -25.4 -42.3 VSUP0.6 -3.3 -6.6 -11.0 mA mA mA mA mA mA mA mA mA V -6.5 VSUP -1.0 mA mA mA 35k 70k 100k Ohm 35k 70k 100k Ohm 20k Ohm www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 33.17 DC CHARACTERISTICS - I/O PINS (ON DIE) Conditions: T= -40 to 85C, VSUP=3.0V (unless otherwise specified) Parameter Conditions Symbol Input Low voltage Ports A,B, C VIL Input High voltage Ports A,B, C Input Hysteresis PA[7:0], PB[7:0], PC[7:0] IOL (high current drives) PA[7:5,3], PB[7:0], PC[6:5,3] VIH Temp=25°C Max. Unit VSS 0.2* VSUP V 0.8* VSUP VSUP V VHyst VSUP =3.0V , VOL=0.3V VSUP =3.0V , VOL=0.6V VSUP =3.0V , VOL=1.0V VSUP =3.0V , VOL=0.3V IOL VSUP =3.0V , VOL=0.6V PA[4,2:0], PC[7,4,2:0] VSUP =3.0V , VOL=1.0V IOH (high current drives) VSUP =3.0V , VOH= VSUP - 0.3V PA[7:5,3], PB[7:0], VSUP =3.0V , VOH= VSUP - 0.6V PC[6:5,3] VSUP =3.0V , VOH= VSUP - 1.0V VOH (high current drives) VSUP=3.3V, IOH= -20mA PA[3], PA[6], PB[6], PB[7] VSUP =3.0V , VOH= VSUP - 0.3V IOH VSUP =3.0V , VOH= VSUP - 0.6V PA[4,2:0], PC[7,4,2:0] VSUP =3.0V , VOH= VSUP - 1.0V Input Pull-down VSUP =3.0V, Pin at 3.0V Port A,B,C Input Pull-up Port A,B,C VSUP =3.0V, Pin at 0.0V Input Pull-down VSUP =3.0V, Pin at 3.0V TM Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 Min. 148 IOL IOL IOL IOL IOL IOL IOH IOH IOH VOH 3.57 1.36 VSUP0.82 IOH IOH IOH RPD RPU RPDTM Typ. 0.42 V 9.9 19.8 33.0 5.2 10.4 17.3 -12.7 -25.4 -42.3 VSUP0.6 -3.3 -6.6 -11.0 mA mA mA mA mA mA mA mA mA V -5.52 VSUP -0.85 mA mA mA 35k 70k 100k Ohm 35k 70k 100k Ohm 20k Ohm www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 34. WAKEUP AND BOOT SEQUENCE TIMING Wakeup timing from stand-by mode: Refer to paragraph 2.2.1 Standby mode Wakeup timing from sleep mode: Refer to paragraph 2.2.3 Sleep Wake-up Wakeup timing from power-done mode. Refer to paragraph 2.2.4 Power-down mode Boot sequence timing from power-on-reset: Refer to paragraph 6.1 Boot sequence Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 149 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 35. PACKAGE DRAWINGS 35.1 DIMENSIONS OF TSSOP28 PACKAGE S 3 2 B 1 C B M B E1 e E L C OC N END VIEW A2 0.05 0.85 0.19 0.19 0.09 4.30 0.50 0° 0.90 0.22 9.70 BSC 4.40 0.65 BSC 6.40 BSC 0.60 1.10 0.15 0.95 0.30 0.25 0.20 4.50 0.70 8° A1 (14°) 0.25 A e L DIMENSIONS in MILLIMETERS MIN. NOM. MAX. SEE DETAIL "A" TOP VIEW b O A A1 A2 b b1 c D E1 CL E Y SEATING PLANE L C ( O)C D (1.00) DETAIL 'A' (14°) (VIEW ROTATED 90° C.W.) TSSOP28 Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 150 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 35.2 DIMENSIONS OF TSSOP24 PACKAGE S 3 2 B 1 C B M B E1 e E L C OC N END VIEW A2 0.05 0.85 0.19 0.19 0.09 4.30 0.50 0° 0.90 0.22 7.80 BSC 4.40 0.65 BSC 6.40 BSC 0.60 1.10 0.15 0.95 0.30 0.25 0.20 4.50 0.70 8° A1 (14°) 0.25 A e L DIMENSIONS in MILLIMETERS MIN. NOM. MAX. SEE DETAIL "A" TOP VIEW b O A A1 A2 b b1 c D E1 CL E Y SEATING PLANE L C ( O)C D (1.00) DETAIL 'A' (14°) (VIEW ROTATED 90° C.W.) TSSOP24 (0.65mm pitch, 4.4mm body width) Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 151 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 35.3 DIMENSIONS OF TSSOP20 PACKAGE S 3 2 B 1 C B M B E1 e E L C OC N END VIEW A2 0.05 0.85 0.19 0.19 0.09 4.30 0.50 0° 0.90 0.22 6.4 BSC 4.40 0.65 BSC 6.40 BSC 0.60 1.10 0.15 0.95 0.30 0.25 0.20 4.50 0.70 8° A1 (14°) 0.25 A e L DIMENSIONS in MILLIMETERS MIN. NOM. MAX. SEE DETAIL "A" TOP VIEW b O A A1 A2 b b1 c D E1 CL E Y SEATING PLANE L C (O )C D (1.00) DETAIL 'A' (14°) (VIEW ROTATED 90° C.W.) TSSOP20 Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 152 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 35.4 DIMENSIONS OF TSSOP16 PACKAGE S 3 2 B 1 C B M B E1 e E L C OC N END VIEW A2 0.05 0.85 0.19 0.19 0.09 4.30 0.50 0° 0.90 0.22 5.00 BSC 4.40 0.65 BSC 6.40 BSC 0.60 1.10 0.15 0.95 0.30 0.25 0.20 4.50 0.70 8° A1 (14°) 0.25 A e L DIMENSIONS in MILLIMETERS MIN. NOM. MAX. SEE DETAIL "A" TOP VIEW b O A A1 A2 b b1 c D E1 CL E Y SEATING PLANE L C ( O)C D (1.00) DETAIL 'A' (14°) (VIEW ROTATED 90° C.W.) TSSOP16 (0.65mm pitch, 4.4mm body width) Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 153 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 35.5 DIMENSIONS OF SO8 PACKAGE 3 SO8 - 150 1 2 H THIS TABLE IN MILLIMETERS PARTING LINE S Y M B O L C OC N A A1 A2 B C D E e H 5.84 L DETAIL A TOP VIEW B e D A1 C A2 A COMMON DIMENSIONS MIN. NOM. MAX. 1.55 1.63 1.73 0.127 0.15 0.25 1.40 1.47 1.55 0.35 0.41 0.49 0.19 0.20 0.25 4.80 4.93 4.98 3.81 3.94 3.99 L 0.41 N C 0° OC 1.27 BSC 5.99 6.20 0.64 0.89 5° 8° 8 E SEATING PLANE SEE DETAIL A SIDE VIEW Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 END VIEW 154 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 35.6 DIMENSIONS OF QFN32 PACKAGE D MIN. D/2 e D1 D1/2 N 0.50 DIA. E1/2 E/2 E1 L 0.30 0.40 0.50 b 0.18 0.23 0.30 D2 3.40 3.50 3.60 E2 TOP VIEW A2 A SIDE VIEW A1 A3 PLANE MAX. 0.50 E1 E NOM. 4.75 3.40 3.50 3.60 A 0.80 0.85 0.90 A1 0.00 0.01 0.05 A2 0.60 0.65 0.70 A3 0.20 K 0.20min D1 4.75 D 5.0 E 5.0 ALL DIMENSIONS ARE IN MILLIMETERS b D2 D2/2 PIN#1 ID N 0.45 E2 E2/2 (MIN. 0.35) L e (MIN. 0.35) BOTTOM VIEW Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 155 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 35.7 DIMENSIONS OF QFN20 PACKAGE D MIN. e E PIN #1 ID TOP VIEW A A1 A3 SIDE VIEW D2 D2/2 K PIN #1 ID 0.50 L 0.45 0.50 0.55 b 0.18 0.25 0.30 D2 2.50 2.60 2.70 E2 2.50 2.60 2.70 A 0.80 0.85 0.90 A1 0.00 0.02 0.05 A3 0.20 K 0.20min D 4.0 E 4.0 L1 0.15max SEE DETAIL "A" E2/2 TERMINAL/SIDE E2 2 1 K L1 L b e e 4*e SEE DETAIL "A TERMINAL TIP DETAIL "A" BOTTOM VIEW Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 MAX. ALL DIMENSIONS ARE IN MILLIMETERS L 4*e NOM. 156 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 35.8 PAD LOCATION OF THE DIE (VERSION 005 AND 006) Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 157 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 35.9 PAD LOCATION OF THE DIE (ALL OTHER VERSIONS) Notes: The drawn box is not the real sealring Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 158 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 36. PACKAGE MARKING The first line of the package marking contains the Revision ID and the bonding option The remaining lines contain Lot identification information First Line: EM6819 XY wheras XY= Circuit hardware information and package pinout Current Package markings EM6819 EA (hardware E with DCDC available) EM6819 EB (hardware E without DCDC) For changes refer to the Errata section. Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 159 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 37. ERRATA EM6819Fx-A00x, EM6819Fx-A10x package marking ‘EM6819 DA’ EM6819Fx-B00x, EM6819Fx-B10x package marking ‘EM6819 DB’ - unstable IVDD consumption possible in powerdown mode - External reference input for ADC limited to 2.8V Current Revision EM6819Fx-A00x, EM6819Fx-A10x package marking ‘EM6819 EA’ EM6819Fx-B00x, EM6819Fx-B10x package marking ‘EM6819 EB’ - External reference input for ADC limited to 2.8V Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 160 www.emmicroelectronic.com EM6819Fx-A00x, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x 38. ORDERING INFORMATION The full ordering information is composed out of the - Part number - The package type and pin count for given part number (to be found in table EM6819 family on page 11) - The delivery form (Stick, Tape, Tray) depending on the selected package Examples: - EM6819F6-B100-TP028BD - EM6819F4-A000-LF020D - EM6819F4-A000-WS11 Part Number Refer to table EM6819 family on page 11 for the different part numbers I.e EM6819F6-A000 Package Type and package pin count Refer to table EM6819 family on page 11 for available packages for a given part number. Packages: QFN, TSSOP, SO Pincounts: 8, 16, 20, 28, 32 Package and pincount codes: QFN: LF032 LF020 TSSOP: TP028 TP020 TP016 SO: SO008 Wafer: WS11 Delivery Form The delivery form depends on the selected package type For TSSOP, SO packages - BD Tape and Real For QFN packages -D Tray For wafer The wafer delivery is on sawn wafer backlap at 11 mils. Other die/wafer form delivery Other delivery in die or wafer form is also possible. Please contact EM Microelectronic directly if such delivery is requested. EM Microelectronic-Marin SA (“EM”) makes no warranties for the use of EM products, other than those expressly contained in EM's applicable General Terms of Sale, located at http://www.emmicroelectronic.com. EM assumes no responsibility for any errors which may have crept into this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property rights of EM are granted in connection with the sale of EM products, neither expressly nor implicitly. In respect of the intended use of EM products by customer, customer is solely responsible for observing existing patents and other intellectual property rights of third parties and for obtaining, as the case may be, the necessary licenses. Important note: The use of EM products as components in medical devices and/or medical applications, including but not limited to, safety and life supporting systems, where malfunction of such EM products might result in damage to and/or injury or death of persons is expressly prohibited, as EM products are neither destined nor qualified for use as components in such medical devices and/or medical applications. The prohibited use of EM products in such medical devices and/or medical applications is exclusively at the risk of the customer Copyright 2014, EM Microelectronic-Marin SA 6819-DS.doc, Version 9.2, 2-Oct-14 161 www.emmicroelectronic.com