EM3021 Data Sheet - EM Microelectronic

EM MICROELECTRONIC - MARIN SA
EM3021
Ultra Low Power 1-Bit 32 kHz RTC
Description
Features
The V3021 is a low power CMOS real time clock. Data is
transmitted serially as 4 address bits and 8 data bits, over
one line of a standard parallel data bus. The device is
accessed by chip select ( CS ) with read and write control




timing provided by either RD and WR pulse (Intel CPU)
or DS with advanced R/ W (Motorola CPU). Data can
also be transmitted over a conventional 3 wire serial
interface having CLK, data I/O and strobe. The V3021
has no busy states and there is no danger of a clock
update while accessing. Supply current is typically
800 nA at VDD = 3.0V. Battery operation is supported by
complete functionality down to 2.0V. The oscillator is
typically 0.3 ppm/V.





Applications

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









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
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Utility meters
Battery operated and portable equipment
Consumer electronics
White/brown goods
Pay phones
Cash registers
Personal computers
Programmable controller systems
Data loggers
Automotive systems

Typical Operating Configuration
Supply current typically 800 nA at 3V
50 ns access time with 50 pF load capacitance
Fully operational from 2.0V to 5.5V
No busy states or danger of a clock update while
accessing
Serial communication on one line of a standard
parallel data bus or over a conventional 3 wire serial
interface
Interface compatible with both Intel and Motorola
Seconds, minutes, hours, day of month, month, year,
week day and week number in BCD format
Leap year and week number correction
Time set lock mode to prevent unauthorized setting of
the current time or date
Oscillator stability 0.3 ppm / volt
No external capacitor needed
Frequency measurement and test modes
Temperature range: -40°C to +85°C
On request extended temperature range, -40°C to
+125°C
Packages DIP8 and SO8
Pin Assignment
SO8
VDD
XI
XO
WR
V3021
CS
RD
VSS
I/O
Fig. 2
Fig. 1
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Absolute Maximum Ratings
Parameter
Maximum voltage at VDD
Minimun voltage at VDD
Maximum voltage at any
signal pin
Minimum voltage at any signal
pin
Maximum storage
temperature
Minimum storage temperature
Electrostatic discharge
maximum to MIL-STD-883C
method 3015.7 with ref. to VSS
Maximum soldering conditions
Handling Procedures
Symbol
VDDmax
VDDmin
Conditions
VSS + 7.0V
VSS – 0.3V
Vmax
VDD + 0.3V
Vmin
VSS – 0.3V
TSTOmax
+150°C
TSTOmin
-65°C
VSmax
1000V
TSmax
250°C x 10s
This device has built-in protection against high static
voltages or electric fields; however, anti-static precautions
must be taken as for any other CMOS component. Unless
otherwise specified, proper operation can only occur when
all terminal voltages are kept within the voltage range.
Unused inputs must always be tied to a defined logic
voltage level.
Operating Conditions
Parameter
Symbol
Operating temperature
TA
Logic supply voltage
VDD
Supply voltage dv/dt
(power-up & power-down)
Decoupling capacitor
Crystal Characteristics
Frequency 1)
f
Load capacitance
CL
Series resistance
RS
Table 1
Stresses above these listed maximum ratings may cause
permanent damages to the device. Exposure beyond
specified operating conditions may affect device reliability
or cause malfunction.
1)
Min
-40
2.0
Typ
5.0
Max Unit
+125 °C
5.5
V
6
V/µs
100
nF
32.768
8.2
35
kHz
12.5
pF
50
k
Table 2
Typ
0.8
Max
1.8
Unit
µA
1.3
10
µA
3
300
µA
µA
1.0
1
1
V
V
V
V
µA
µA
13
9
1
0.3
0.5
V
pF
pF
s
ppm/V
25
60
µA
7
See Fig. 3
Electrical Characteristics (standard temperature range)
VDD= 5.0V ±10%, VSS = 0V and TA=-40 to +85°C, unless otherwise specified
Parameter
Symbol
Test Conditions
Total static supply
ISS
All outputs open, all inputs at VDD
VDD = 3.0V, address 0 = 0
Total static supply
ISS
All outputs open, all inputs at VDD
VDD = 5V, address 0 = 0
TA = +25°C
Dynamic current
ISS
I/O to VSS through 1M
RD = VSS, WR = VDD,
CS = 4 MHz
address 0 = 0, read all 0
Input / Output
Input logic low
VIL
Input logic high
VIH
Output logic low
VOL
IOL = 4 mA
Output logic high
VOH
IOH = 4 mA
Input leakage
IIN
0.0 < VIN < 5.0V
Output tri-state leakage on I/O
ITS
CS high, and address 0, bit 0, low
pin
Oscillator
Starting voltage
VSTA
Input capacitance on XI
CIN
TA = +25°C
Output capacitance on XO
COUT
TA = +25°C
Start-up time
TSTA
Frequency stability
1.5 ≤ VDD ≤ 5.5V, TA = +25°C
f/f
Frequency Measurement Mode
Current source on I/O pin
IONF
CS high, addr.0, bit 0, high
pulsed on/off @ 256 Hz
VI/O = 1V
Min
3.5
0.4
2.4
0.1
0.1
1.8
10
Table 3
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Electrical Characteristics (extended temperature range)
VDD= 5.0V ±10%, VSS = 0V and TA=-40 to +125°C, unless otherwise specified
Parameter
Symbol
Test Conditions
Total static supply
ISS
All outputs open, all inputs at VDD
VDD = 3.0V, address 0 = 0
Total static supply
ISS
All outputs open, all inputs at VDD
address 0 = 0
Dynamic current
ISS
I/O to VSS through 1M
RD = VSS, WR = VDD,
CS = 4 MHz
address 0 = 0, read all 0
Input / Output
Input logic low
VIL
Input logic high
VIH
Output logic low
VOL
IOL = 4 mA
Output logic high
VOH
IOH = 4 mA
Input leakage
IIN
0.0 < VIN < 5.0V
Output tri-state leakage on I/O
ITS
CS high, and address 0, bit 0, low
pin
Oscillator
Starting voltage
VSTA
Supply voltage dV/dt (power+85°C ≤ TA ≤ +125°C
up & power-down)
Input capacitance on XI
CIN
TA = +25°C
Output capacitance on XO
COUT
TA = +25°C
Series resistance of the
RS
-40°C ≤ TA ≤ +85°C
crystal
Start-up time
TSTA
TA = +125°C (note 1)
Frequency stability
2.0 ≤ VDD ≤ 5.5V, TA = +25°C
f/f
Frequency Measurement Mode
Current source on I/O pin
IONF
CS high, addr.0, bit 0, high
pulsed on/off @ 256 Hz
VI/O = 1V
Min
Typ
Max
4.9
Unit
µA
8.3
µA
300
µA
1.0
1
1
V
V
V
V
µA
µA
6
V
V/µs
90
pF
pF
k
10
0.3
0.5
s
ppm/V
25
60
µA
3.5
0.4
2.4
0.1
0.1
2.0
0.006
13
9
8
Table 3 ex
Note 1: Analyses done at high temperature with crystal type Micro Crystal CX2V-02
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EM3021
The V3021 will run slightly too fast, in order to allow the
user to adjust the frequency, depending on the mean
operating temperature. This is made since the crystal
adjustment can only work by lowering the frequency with
an added capacitor between XO and VSS. The printed
circuit capacitance has also to be taken into
consideration. The V3021 in DIL 8 package, running with
an 8.2 pF crystal at room temperature, will be adjusted to
better than ±1s/day with a 6.8 pF capacitor.
Typical Frequency on I/O Pin
Typical drift for ideal 32'768 Hz quartz
Note: The trimming capacitor value must not exceed
15 pF. Greater values may disturb the oscillator
function
Fig. 3
Quartz Characteristics
F
ppm
= -0.038
(T – TO)2 ± 10%
FO
C2
F/FO
=
T
TO
=
=
the ratio of the change in frequency to the
nominal value expressed in ppm (it can be
thought of as the frequency deviation at any
temperature)
the temperature of interest in °C
the turnover temperature (25 ± 5°C)
To determine the clock error (accuracy) at a given
temperature, add the frequency tolerance at 25°C to the
value obtained from the formula above.
Fig. 4
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Timing Characteristics (standard temperature range)
VSS= 0V and TA=-40 to +85°C, unless otherwise specified
Parameter
Symbol Test Conditions
Chip select duration
tCS
Write cycle
RAM access time (note 1)
tACC
CLOAD = 50pF
Min. Max.
VDD ≥ 2V
200
Min.
Typ.
Max.
VDD = 5.0V ±10%
Unit
50
180
ns
50
60
ns
Time between two transfers
tW
500
100
ns
Rise time (note 2)
tR
10
200
10
Fall time (note 2)
tF
10
200
10
Data valid to Hi-impedance (note 3)
tDF
10
100
15
Write data settle time (note 4)
tDW
60
50
ns
Data hold time (note 5)
tDH
80
25
ns
Advance write time
tADW
25
10
ns
Write pulse time (note 6)
tWC
200
50
ns
30
200
ns
200
ns
40
ns
Table 4
Timing Characteristics (standard temperature range)
VSS= 0V and TA=-40 to +125°C, unless otherwise specified
Parameter
Symbol Test Conditions
Chip select duration
tCS
Write cycle
RAM access time (note 1)
tACC
CLOAD = 50pF
Min. Max.
VDD ≥ 2V
200
Min.
Typ.
Max.
VDD = 5.0V ±10%
Unit
60
180
ns
50
60
ns
Time between two transfers
tW
500
120
Rise time (note 2)
tR
10
100
10
100
ns
Fall time (note 2)
tF
10
100
10
100
ns
Data valid to Hi-impedance (note 3)
tDF
10
100
50
ns
Write data settle time (note 4)
tDW
60
50
ns
Data hold time (note 5)
tDH
80
25
ns
Advance write time
tADW
25
15
ns
Write pulse time (note 6)
tWC
200
60
5
ns
30
ns
Table 4 ex.
Note 1: tACC starts from RD or CS , whichever activates last
Typically, tACC = 5 + 0.9 CEXT in ns; where CEXT (external parasitic capacitance) is in pF
Note 2: CS , RD , DS , WR and R/ W rise and fall times are specified by tR and tF
Note 3: tDF starts from RD or CS , whichever deactivates first
Note 4: tDW ends at WR or CS , whichever deactivates first
Note 5: tDH starts from WR or CS , whichever deactivates first
Note 6: tWC starts from WR or CS , whichever activates last and ends at WR or CS , whichever deactivates first
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Timing Waveforms
Read Timing for Intel ( RD and WR Pulse) and Motorola ( DS (or RD pin tied to CS ) and R/ W )
Fig. 5a
Write Timing for Intel ( RD and WR Pulse)
Fig. 5b
Write Timing for Motorola ( DS (or RD pin tied to CS ) and R/ W )
Fig. 5c
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Communication Cycles
Read Data Cycle for Intel ( RD and WR Pulse)
Fig. 6a
Read Data Cycle for Motorola ( DS (or RD pin tied to CS ) and R/ W )
Fig. 6b
Write Data Cycle for Intel ( RD and WR Pulse)
Fig. 6c
Write Data Cycle for Motorola ( DS (or RD pin tied to CS ) and R/ W )
Fig. 6d
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Address Command Cycle for Intel
( RD and WR Pulse)
Address Command Cycle for Motorola
( DS (or RD pin tied to CS ) and R/ W )
Fig. 6f
Fig. 6e
Block Diagram
Fig. 7
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EM3021
Pin Description
Pin
1
2
3
4
5
6
7
8
Name
XI
XO
CS
VSS
I/O
Function
32 kHz crystal input
32 kHz crystal output
Chip select input
RD
Ground supply
Data input and output
Intel RD , Motorola DS (or tie to CS )
WR
VDD
Intel WR , Motorola R/ W
Positive supply
Table 5
Functional Description
Serial Communication
The V3021 resides on the parallel data and address
buses as a standard peripheral (see Fig.13 and 14).
Address decoding provides an active low chip select
( CS ) to the device. For Intel compatible bus timing the
control signals RD and WR pulse and CS are used for
a single bit read or write (see Fig. 7a and 7b). Two
options exist for Motorola compatible bus timing. The first
is to use the control signals DS with R/ W and CS , the
second is to tie the RD input to CS and use the control
signals R/ W and CS (see Fig. 7a and 7c). Data transfer
is accomplished through a single input/output line (I/O).
Any data bus line can be chosen. A conventional 3 wire
serial interface can also be used to communicate with the
V3021 (see Fig. 15).
Communication Cycles
The V3021 has 3 serial communication cycles. These
are:
1) Read data cycle
2) Write data cycle
3) Address command cycle
A communication cycle always begins by writing the 4
address bits, A0 to A3. A microprocessor read from the
V3021 cannot begin a communication cycle. Read and
write data cycles are similar and consist of 4 address bits
and 8 data bits. The 4 address bits, A0 to A3, define the
RAM location and the 8 data bits D0 and D7 provide the
relevant information. An address command cycle consists
of only 4 address bits.
Read Data Cycle
A read data cycle commences by writing the 4 RAM
address bits (A3, A2, A1 and A0) to the V3021. The LSB,
A0, is transmitted first (see Fig. 6a and 6b). Eight
microprocessor reads from the V3021 will read the RAM
data at this address, beginning with the LSB, D0. The
read data cycle finishes on reading the 8th data bit, D7.
Write Data Cycle
A write data cycle commences by writing the 4 RAM
address bits (A3, A2, A1 and A0) to the V3021. The LSB,
A0, is transmitted first (see Fig. 8c and 8d). Eight
microprocessor writes to the V3021 will write the new
RAM data. The LSB, D0, is loaded first. The write data
cycle finishes on writing the 8th data bit, D7.
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3021-DS, Version 2.0, 3-Aug-15
Address Command Cycle
An address command cycle consists of just 4 address
bits. The LSB, A0, is transmitted first (see Fig. 8e and 8f).
On writing the fourth address bit, A3, the address will be
decoded. If the address bits are recognized as one of the
command codes E hex or F hex (see Table 6), then the
communication cycle is terminated and the corresponding
command is executed.
Subsequent microprocessor
writes to the V3021 begin another communication cycle
with the first bit being interpreted as the address LSB, A0.
Clock Configuration
The V3021 has a reserved clock area and a user RAM
area (see Fig. 7). The clock is not directly accessible, it is
used for internal time keeping and contains the current
time and data. The contents of the RAM is shown in
Table 6, it contains a data space and an address
command space. The data space is directly accessible.
Addresses 0 and 1 contain status information (see Tables
7a and 7b), addresses 2 to 5, time data, and addresses 6
to 9, date data. The address command space is used to
issue commands to the V3021.
RAM Map
Address
Parameter
Dec
Hex
Data Space
0
0
Status 0
1
1
Status 1
2
2
Seconds
3
3
Minutes
4
4
Hours
5
5
Day of month
6
6
Month
7
7
Year
8
8
Week day
9
9
Week number
Address Command Space
14
E
Copy_RAM_to_clock
15
F
Copy_clock_to_RAM
BCD
range
00-59
00-59
00-23
01-31
01-12
00-99
01-07
00-52
Table 6
Commands
Two commands are available (see Table 6).
The
Copy_RAM_to_clock command is used to set the current
time and date in the clock and the Copy_clock_to_RAM
command to copy the current time and date from the clock
to the RAM.
The Copy_RAM_to_clock command,
address data E hex, causes the clock time and date to be
overwritten by the time and date stored in the RAM at
addresses 2 to 9. Address 1 is also cleared (see section
"Time and Date Status Bits").
Prior to using this
command, the desired time and date must be loaded into
the RAM using write data cycles and the time set lock bit,
address 0, bit 4, must be clear (see section "Time Set
Lock").
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EM3021
Status Information
The RAM addresses 0 and 1 contain status control data
for the V3021. The function of each ibt (0 and 7) within
address locations 0 and 1 is shown in Table 7a and 7b
respectively.
On first startup or whenever power has failed (V DD < 2.0V)
the status register 0 and the clock must be initialized by
software Having initialized the interface to expect the
address bit A0, write 0 to status register 0, then set the
clock (see section "Clock and Calendar").
Status Word
Status 0 - address 0
7 6 5 4 3 2 1 0
0 - inactive
1 - active
Read / Write bits
Frequency Measurement Mode
Reserved
Test Mode 0
Test Mode 1
Time Set Lock
Reserved
Reserved
Reserved
Table 7a
Status 1 - address 1
0-
7 6 5 4 3 2 1 0
1-
Read ONLY bits
No change from last
Copy_clock_to_RAM
Change from last
Copy_clock_to_RAM
Seconds
Minutes
Hours
Day of month
Month
Year
Week day
Week number
Table 7b
Reset and Initialization
Upon microprocessor recovery from a system reset, the
V3021 must be initialized by software in order to
guarantee that it is expecting a communication cycle (ie.
the internal serial buffer is waiting for the address bit A0).
Software can initialize the V3021 to expect a
communication cycle by executing 8 microprocessor
reads (see Fig. 8).
Initializing Access to the V3021
Time and Date Status Bits
There are time and date status bits at address 1 in the
RAM. Upon executing a Copy_clock_to_RAM command,
the time and date status bits in the RAM show which time
and date parameters changed since the last time this
command was used. A logic 1 in the seconds status bit
(address1, bit 0) in the RAM indicates that the seconds
location in the RAM (address 2) changed since the last
Copy_clock_to_RAM command and thus need to be read.
The seconds location must change before any other time
or date location can change. If the seconds status bit is
clear, then no time or date location changed since the last
Copy_clock_to_RAM command and so the RAM need not
to be read by software.
Table 7b shows the seconds, minutes, hours, day of the
month, month, year, week day, and week number status
bit locations. They are set or cleared similar to the
seconds location. It should be noted that if the minutes
status bit is clear, then the seconds bit may be set, but ail
other status bits are clear. Similarly with hours, the bits
representing the units less than hours may have been set,
but the bits for the higher units will be clear. This rule
holds true for the week day or day of month locations
also.
The time and date status bits can be used to drive
software routines which need to be executed every
-second,
-minute,
-hour,
-day of month / weekday,
-month,
-year,
or
-week.
In this application it is necessary to poll the V3021 at least
once every time interval used as it does not generate an
interrupt.
Upon executing a Copy _RAM_to_clock command, the
time and date status bits in the RAM are cleared.
Time Set Lock
The time set lock control bit is located at address 0, bit 4
(see Table 7a). When set by software, the bit disables the
Copy_RAM_to_clock
command
(see
section
"Commands".) A set bit prevents unauthorized overwriting
of the current time and date in the clock. Clearing the time
set lock bit by software will re-enable the
Copy_RAM_to_clock command. On first startup or
whenever power has failed (VDD < 2.0 V), the time set lock
bit must be setup by software.
Fig. 8
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Reading the Current Time and Date
Setting the Current Time and Date
Send copy_clock_to_RAM
addr. F hex
Write seconds, minutes, hours, day
of month, week day, month, year and
week number to the RAM
Read time and data status bits,
addr. 1
Clear the time set lock bit,
addr. 0, bit 4
Is the seconds status bit set,
addr. 1, bit 0
No
Send copy_RAM_to_clock command,
addr. E hex
Yes
Set the time set lock bit, addr. 0, bit 4
Read seconds, addr. 2
Is the minutes status bit set,
addr. 1, bit 1
Fig. 10
No
Yes
Read minutes, addr. 3
Similar for hours, day of month, week
day, month, year and week number
Current time and date
Fig. 9
Clock and Calendar
The Time and date addresses in the RAM (see Table 6)
provide access to the seconds, minutes, hours, day of
month, month, year, week day, and week number. These
parameters have the ranges indicated on Table 6 and are
in BCD format. If a parameter is found to be out of range,
it will be cleared on its being next incremented. The
V3021 incorporates leap year correction and week
number calculation. The week number changes only at
the incrementation of the day number from 7 to 1. If week
52 day 7 falls on the 25th, 26th or 27th of December, then
the week number will change to 0, otherwise it will be
week 1. Week days are numbered from 1 to 7 with
Monday as 1.
Reading of the current time and date must be preceded
by a Copy_clock_to_RAM command. The time and date
status bits will indicate which time and date addresses
changed since the last time the command was used (see
Fig. 9).
The time and date from the last
Copy_clock_to_RAM command is held unchanged in the
RAM, except when power (VDD) has failed totally. To
change the current time and date in the clock, the desired
time an date must first be written to the RAM, the time set
lock bit cleared, and then a Copy_RAM_to_clock
command sent (see Fig. 10). The time set lock bit can be
used to prevent unauthorized setting of the clock.
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3021-DS, Version 2.0, 3-Aug-15
Frequency Measurement
Setting bit 0 at address 0 will put a pulsed current source
(25 µA) onto the I/O pin, when the device is not chip
selected (ie. CS input high). The current source will be
pulsed on/off at 256 Hz. The period for ± 0 ppm time
keeping is 3.90625 ms. To measure the frequency signal
on pin I/O, the data bus must be high impedance. The
best way to ensure this is to hold the microprocessor and
peripherals in reset mode while measuring the frequency.
The clarity of the signal measured at pin I/O will depend
on both the probe input impedance (typically 1 M) and
the magnitude of the leakage current from other devices
driving the line connected to pin I/O. If the signal
measured is unclear, put a 200 k resistor from pin I/O to
VSS. It should be noted that the magnitude of the current
source (25 µA) is not sufficient to drive the data bus line in
case of any other device driving the line, but it is sufficient
to take the line to a high logic level when the data bus is in
high impedance.
Use a crystal of nominal CL = 8.2 pF as specified in the
section "Operating Conditions". The MX series from
Microcrystal is recommended. The accuracy of the time
keeping is dependent upon the frequency tolerance and
the load capacitance of the crystal.
11.57 ppm
corresponds to one second a day.
Test
From the various test features added to the V3021 some
may be activated by the user. Table 7a shows the test
mode b its. Table 8 shows the 3 available test modes and
how they can be activated. Test mode 0 is activated by
setting bit 2, address 0, and causes all time keeping to be
accelerated by 32. Test mode 1 is activated by setting bit
3, address 0, and causes all the time and date locations,
address 2 to address9, to be incremented in parallel at 1
Hz with no carry over (independent of each other). The
third test mode combines the previous two resulting in
parallel incrementing at 32 Hz.
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EM3021
Test Modes
Addr. 0 Addr. 0
bit 3
bit 2
0
0
0
1
1
0
1
1
Function
Normal operation
All time keeping accelerated by 32
Parallel increment of all time data
at 1 Hz with no carry over
Parallel increment of all time data
at 32 Hz with no carry over
Crystal Layout
In order to ensure proper oscillator operation we
recommend the following standard practices:
- Keep traces as short as possible
- Use a guard ring around the crystal
Fig. 12 shows the recommended layout.
Oscillator Layout
Table 8
An external signal generator can be used to drive the
divider chain of the V3021. Fig. 11a and 11b show how to
connect the signal generator.
The speed can be
increased by increasing the signal generator frequency to
a maximum of 128 kHz. An external signal generator and
test modes can be combined.
To leave test both test bits (address 0, bits 2 and 3) must
be cleared by software. Test corrupts the current time
and date and so the time and date should be reloaded
after a test session.
Fig. 12
Access Considerations
The section "Communication Cycles" describes the serial
data sequences necessary to complete a communication
cycle. In common with all serial peripherals, the serial
data sequences are not re-entrant, thus a high priority
interrupt, or another software task, should not attempt to
access the V3021 if it is already in the middle of a cycle.
A semaphore (software flag) on access would allow the
V3021 to be shared with other software tasks or interrupt
routines. There is no time limit on the duration of a
communication cycle and thus interrupt routines (which do
not use the V3021) can be fully executed in mid cycles
without any consequences for the V3021.
Signal Generator Connection
Fig. 11a
Note: The peak value of the signal provided by the signal
generator should not exceed 2 V on XO.
Fig. 11b
Note: The peak value of the signal provided by the signal
generator should not exceed 2 V on XO.
Copyright 2015, EM Microelectronic-Marin SA
3021-DS, Version 2.0, 3-Aug-15
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EM3021
Typical Applications
V3021 Interfaced with Intel CPU (RD/WR Pulse)
Fig. 13
V3021 Interfaced with Motorola CPU (Advanced R/W)
Fig. 14
3 Wire Serial Interface
1)
2)
With strobe low bits are written to the V3021, and with strobe high bits are read from the
V3021
For serial ports with byte transfer only, an address command cycle should be combined with
every data cycle to give 8 address bits and 8 data bits. For example to read the current
minutes, write address data F + 3 (1111 + 0011) and then read 8 data bits.
Fig. 15
Copyright 2015, EM Microelectronic-Marin SA
3021-DS, Version 2.0, 3-Aug-15
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EM3021
Battery Switch Over Circuit
a)
*
Use Schottky barrier
diodes. The BAT85
has a typical VF of 250
mV at an IF of 1 mA.
The reverse current is
typically 200 nA at a VR
of 5 V. The reverse,
recovery time is 5 ns.
For surface mount
applications use the
Philips BAT17 in SOT23 or other.
Fig. 16
Ordering and Package Information
Dimensions of 8-Pin SOIC Package
E
D
C
A1
0-8°
A
L
B
e
H
Dimensions in mm
4
3
2
1
5
6
7
8
A
A1
B
C
D
E
e
H
L
Min.
1.35
0.10
0.33
0.19
4.80
3.80
5.80
0.40
Nom.
1.63
0.15
0.41
0.20
4.93
3.94
1.27
5.99
0.64
Max
1.75
0.25
0.51
0.25
5.00
4.00
6.20
1.27
Fig. 17
Dimensions of 8-Pin DIP Package
Fig. 18
Copyright 2015, EM Microelectronic-Marin SA
3021-DS, Version 2.0, 3-Aug-15
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EM3021
Ordering Information
When ordering, please specify the complete Part Number
Part Number
Temperature
Range
V3021SO8B+
V3021SO8A+
-40°C to +85°C
V3021DL8A+
V3021XSO8B+
V3021XSO8A+
-40°C to +125°C
V3021XDL8A+
Package
Delivery Form
8-pin SOIC
Tape & Reel
8-pin SOIC
Stick
8-pin plastic DIP
Stick
8-pin SOIC
Tape & Reel
8-pin SOIC
Stick
8-pin plastic DIP
Stick
Package
Marking
V3021
EM% ##
V3021
EM% ##
V3021
V3021
EM%X##
V3021
EM%X##
V3021 X
Where % and ## refer to the lot number and date (EM internal reference only).
EM Microelectronic-Marin SA (“EM”) makes no warranties for the use of EM products, other than those expressly contained in EM's
applicable General Terms of Sale, located at http://www.emmicroelectronic.com. EM assumes no responsibility for any errors which may
have crept into this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does
not make any commitment to update the information contained herein.
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nor implicitly.
In respect of the intended use of EM products by customer, customer is solely responsible for observing existing patents and other
intellectual property rights of third parties and for obtaining, as the case may be, the necessary licenses.
Important note: The use of EM products as components in medical devices and/or medical applications, including but not limited
to, safety and life supporting systems, where malfunction of such EM products might result in damage to and/or injury or death
of persons is expressly prohibited, as EM products are neither destined nor qualified for use as components in such medical
devices and/or medical applications. The prohibited use of EM products in such medical devices and/or medical applications is
exclusively at the risk of the customer
Copyright 2015, EM Microelectronic-Marin SA
3021-DS, Version 2.0, 3-Aug-15
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