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HD151BF854 2.5 V PLL Clock Buffer for DDR Application ADE-205-696D (Z) Preliminary Rev.4 Jan. 2003 Description The HD151BF854 is a high-performance, low-skew, low-jitter, PLL clock buffer. It is specifically designed for use with DDR (Double Data Rate) PC mother board application. Features • • • • • • • Designed for DDR200/266/333/400 PC mother board clock buffering Supports 60 MHz to 210 MHz operation range Distributes one to six differential clock outputs pairs Spread spectrum clock compatible External feedback pin (FBIN) is used to synchronize the outputs to the clock input Supports 2.5 V analog supply voltage (AVDD), and 2.5 V VDD Ordering Information Part Name Package Type Package Code Package Abbreviation Taping Abbreviation (Quantity) HD151BF854SSEL SSOP-28 pin SSOP-28 SS EL (1,000 pcs / Reel) Note: Please consult the sales office for the above package availability. HD151BF854 Key Specifications • Supply voltages: VDD = AVDD = 2.5 V±0.2 V • Output clock cycle to cycle jitter = ±75 ps • Output clock pin to pin skew = 150 ps Function Table Inputs Outputs AVDD CLK Yn Yn FBOUT PLL GND L L H L Bypass / Off GND H H L H Bypass / Off 2.5 V (typ.) L L H L Running 2.5 V (typ.) H H L H Running H: High level L: Low level Rev.4, Jan. 2003, page 2 of 11 HD151BF854 Pin Arrangement Y0 1 28 GND Y0 2 27 Y5 VDD 3 26 Y5 Y1 4 25 Y4 Y1 5 24 Y4 GND 6 23 VDD NC 7 22 NC CLKIN 8 21 NC NC 9 20 FBIN AVDD 10 19 FBOUT AGND 11 18 NC VDD 12 17 Y3 Y2 13 16 Y3 Y2 14 15 GND (Top view) Rev.4, Jan. 2003, page 3 of 11 HD151BF854 Pin Functions Pin name No. Type Description AGND 11 Ground Analog ground. AGND provides the ground reference for the analog circuitry. AVDD 10 Power Analog power supply. AVDD provides the power reference for the analog circuitry. In addition, AVDD can be used to bypass the PLL for test purposes. When AVDD is strapped to ground, PLL is bypassed and CLK is buffered directly to the device outputs. CLKIN 8 Input Clock input. CLKIN provides the clock signal to be distributed by the HD151BF854 clock buffer. CLK is used to provide the reference signal to the integrated PLL that generates the clock output signals. CLK must have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is powered up and a valid CLK signal is applied, a stabilization time is required for the PLL to phase lock the feedback signal to its reference signal. FBIN 20 Input Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hard-wired to FBOUT to complete the PLL. The integrated PLL synchronizes CLKIN and FBIN so that there is nominally zero phase error between CLKIN and FBIN. FBOUT 19 Output Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency as CLK. When externally wired to FBIN, FBOUT completes the feedback loop of the PLL. GND 6, 15, 28 Ground Ground VDD 3, 12, 23 Power Power supply Y 2, 4, 13, 17, 24, 26 Output Clock outputs. (+Clock) These outputs provide low-skew copies of CLK. Y 1, 5, 14, 16, 25, 27 Output Bar clock outputs. (–Clock) These outputs provide low-skew copies of CLK. NC 7, 9, 18, 21, NC 22 Rev.4, Jan. 2003, page 4 of 11 Don’t connect any VDD or GND. HD151BF854 Logic Diagram AVDD CLKIN 10 Y0 4 5 Y1 Y1 13 14 Y2 17 16 Y3 24 25 Y4 26 27 Y5 19 FBOUT Test Logic Y0 Y2 Y3 Y4 8 PLL FBIN 2 1 Y5 20 Note: All inputs and outputs are associated with VDDQ = 2.5 V. Rev.4, Jan. 2003, page 5 of 11 HD151BF854 Absolute Maximum Ratings Item Symbol Ratings Unit Supply voltage VDD –0.5 to 3.6 V Input voltage VIC –0.5 to 3.6 V VI –0.5 to VDD+0.5 V Output voltage *1 VO –0.5 to VDD+0.5 V Input clamp current IIK –50 mA VI < 0 Output clamp current IOK –50 mA VO < 0 Continuous output current IO ±50 mA VO = 0 to VDD 0.7 W –65 to +150 °C Maximum power dissipation at Ta = 55°C (in still air) Storage temperature Notes: Tstg Conditions CLKIN Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 1. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. Recommended Operating Conditions Item Symbol Min Typ Max Unit Conditions Supply voltage AVDD 2.3 2.5 2.7 V Output supply voltage VDD 2.3 2.5 2.7 V –0.3 — VDD+0.3 V All pins VIH 1.7 — 3.6 V CLKIN High level input voltage VIH 1.7 — VDD+0.3 V FBIN Low level input voltage VIL –0.3 — 0.7 V CLKIN, FBIN Output differential cross point voltage VOX 0.5×VDD –0.2 — 0.5×VDD +0.2 V Output current IOH — — –12 mA DC input signal voltage High level input voltage IOL — — 12 Input clock slew rate SR 1 — — V/ns Operating temperature Ta 0 — 70 °C Note: Unused inputs must be held high or low to prevent them from floating. Rev.4, Jan. 2003, page 6 of 11 HD151BF854 Electrical Characteristics Item Symbol Min Typ *1 Max Unit Test Conditions Input clamp voltage (All inputs) VIK — — –1.2 V II = –18 mA, VDD = 2.3 V Output voltage VOH VDD–0.2 — — V IOH = –100 µA, VDD = 2.3 to 2.7 V 1.7 — VDD IOH = –12 mA, VDD = 2.3 V — — 0.2 IOL = 100 µA, VDD = 2.3 to 2.7 V — — 0.6 IOL = 12 mA, VDD = 2.3 V VOL Input current II –10 — 10 µA VI = 0 V or 2.7 V, VDD = 2.7 V, CLKIN, FBIN Analog supply current AICC — — 12 mA VDD = AVDD = 2.7 V, 170 MHz Dynamic supply current DICC — 250 300 mA VDD = AVDD = 2.7 V, 170 MHz All Yn, Yn, = open CI 2.5 — 3.5 pF CLKIN and FBIN CDi –0.25 — 0.25 pF Input capacitance*2 2 Delta input capacitance* Notes: 1. For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions. 2. Target of design, not 100% tested in production. Rev.4, Jan. 2003, page 7 of 11 HD151BF854 Switching Characteristics Ta = 25°C, VDD = AVDD = 2.5V Item Symbol Min Typ Max Unit Test Conditions & Notes Period jitter tPER — |75| — ps *7, 8 Half period jitter tHPER — |120| — ps *8 Cycle to cycle jitter tCC — |75| — ps Static phase offset tsPE — |150| — ps Output clock skew tsk — 150 — ps Operating clock frequency fCLK(O) 60 — 210 MHz *1, 2 Application clock frequency 80 166 210 MHz *1, 3 Slew rate 1.0 — 2.0 V/ns 20% to 80% Stabilization time — — 0.1 ms fCLK(A) *4, 5 *6 Notes: Target of design, not 100% tested in production. 1. The PLL must be able to handle spread spectrum induced skew. (the specification for this frequency modulation can be found in the latest Intel PC100 Registered DIMM specification) 2. Operating clock frequency indicates a range over which the PLL must be able to lock, but in which it is not required to meet the other timing parameters. (Used for low speed system debug.) 3. Application clock frequency indicates a range over which the PLL must meet all timing parameters. 4. Assumes equal wire length and loading on the clock output and feedback path. 5. Static phase offset does not include jitter. 6. Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of it’s feedback signal to it’s reference signal after power on. 7. Period jitter defines the largest variation in clock period, around a nominal clock period. 8. Period jitter and half period jitter are separate specifications that must be met independently of each other. Rev.4, Jan. 2003, page 8 of 11 HD151BF854 Zo = 60 Ω Yn *1 RT = 120 Ω C = 14 pF Zo = 60 Ω Yn *1 C = 14 pF Note: 1. SDRAM Cin 3.5 pF ×4 Figure 1 Clock outputs test circuit Yn Yn tcycle n tcycle n+1 t CC = (tcycle n) - (tcycle n+1) Figure 2 Cycle to cycle jitter Yx Yx Yy Yy tsk Figure 3 Output clock skew (Differential clock output) Rev.4, Jan. 2003, page 9 of 11 HD151BF854 Package Dimensions Unit : mm 10.2 10.4 Max 15 1 14 5.3 28 0.65 0.32± 0.08 0.30± 0.08 1.3 0.13 M Dimension including the plating thickness Base material dimension Rev.4, Jan. 2003, page 10 of 11 0.1± 0.1 0.10 0.22 ± 0.05 0.20 ± 0.05 2.10 Max 7.9 ± 0.2 0° – 8° 0.6 ± 0.15 SSOP-28 Hitachi Code — JEDEC — EIAJ Weight (reference value) HD151BF854 Disclaimer 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi’s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products. Sales Offices Hitachi, Ltd. Semiconductor & Integrated Circuits Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Tel: (03) 3270-2111 Fax: (03) 3270-5109 URL http://www.hitachisemiconductor.com/ For further information write to: Hitachi Semiconductor (America) Inc. 179 East Tasman Drive San Jose,CA 95134 Tel: <1> (408) 433-1990 Fax: <1>(408) 433-0223 Hitachi Europe Ltd. Electronic Components Group Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA, United Kingdom Tel: <44> (1628) 585000 Fax: <44> (1628) 778322 Hitachi Asia Ltd. Hitachi Tower 16 Collyer Quay #20-00 Singapore 049318 Tel : <65>-6538-6533/6538-8577 Fax : <65>-6538-6933/6538-3877 URL : http://semiconductor.hitachi.com.sg Hitachi Europe GmbH Electronic Components Group Dornacher Str 3 D-85622 Feldkirchen Postfach 201, D-85619 Feldkirchen Germany Tel: <49> (89) 9 9180-0 Fax: <49> (89) 9 29 30 00 Hitachi Asia Ltd. (Taipei Branch Office) 4/F, No. 167, Tun Hwa North Road Hung-Kuo Building Taipei (105), Taiwan Tel : <886>-(2)-2718-3666 Fax : <886>-(2)-2718-8180 Telex : 23222 HAS-TP URL : http://semiconductor.hitachi.com.tw Hitachi Asia (Hong Kong) Ltd. Group III (Electronic Components) 7/F., North Tower World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel : <852>-2735-9218 Fax : <852>-2730-0281 URL : http://semiconductor.hitachi.com.hk Copyright © Hitachi, Ltd., 2003. All rights reserved. Printed in Japan. Colophon 7.0 Rev.4, Jan. 2003, page 11 of 11