2D-FEC IP Core DS-1032 Data Sheet The Altera Two-Dimensional Enhanced Forward Error Correction (2D-FEC) IP Core comprises a high-performance encoder and decoder for Optical Transport Network (OTN) FEC applications. 2D-FEC is a product code comprised of two BoseChaudhuri-Hocquenghem (BCH) codes for iterative decoding of transmitted data. The decoding algorithm provides error correction while eliminating the detection of false errors in the OTN frame. 2D-FEC performs high-gain FEC with 7% overhead for transmission at 40 gigabits per second (Gbps)/Optical Channel Transport Unit (OTU)3. Features 2D-FEC includes the following features: 101 Innovation Drive San Jose, CA 95134 www.altera.com February 2012 ■ High-performance encoder and decoder for error detection and correction ■ 40 Gbps OTN rate with 256 bit datapath width ■ 7% overhead for Stratix® IV and Stratix V devices ■ Latency of 60 µs ■ Net electrical coding gain (NECG) of > 9.3 dB ■ Error statistic monitoring, including the following types: ■ Corrected zeros and ones errors ■ Corrected errors and uncorrectable errors ■ 40 Gbps/OTU3 frame count © 2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. ISO 9001:2008 Registered Altera Corporation Subscribe Page 2 Architecture Architecture Figure 1 illustrates the system architecture of the 2D-FEC IP core. Data from an incoming client is adapted to OTN before it is written to the OTN mapper. The data is encoded with redundant data at the FEC encoder before it is transmitted across the network. The redundant data is decoded at the FEC decoder and identified errors are corrected before the data is written to the OTN framer. The data is then adapted back to the original client. Figure 1. 2D-FEC System Architecture Customer or Altera IP Client Adaptation Altera IP Core OTN Mapper OTN FEC Encoder Altera IP Core OTN Customer or Altera IP OTN FEC Decoder OTN Framer Client Adaptation Device Family Support Table 1 defines the device support levels for Altera IP cores. Table 1. Altera IP Core Device Support Levels FPGA Device Families HardCopy® Device Families Preliminary support—The IP core is verified with preliminary timing models for this device family. The IP core meets all functional requirements, but might still be undergoing timing analysis for the device family. It can be used in production designs with caution. HardCopy Companion—The IP core is verified with preliminary timing models for the HardCopy companion device. The IP core meets all functional requirements, but might still be undergoing timing analysis for the HardCopy device family. It can be used in production designs with caution. Final support—The IP core is verified with final timing models for this device family. The IP core meets all functional and timing requirements for the device family and can be used in production designs. HardCopy Compilation—The IP core is verified with final timing models for the HardCopy device family. The IP core meets all functional and timing requirements for the device family and can be used in production designs. Table 2 lists the level of support for 2D-FEC in each of the Altera device families. Table 2. Device Family Support Device Family Support Stratix IV GT Final Stratix IV E/GX Preliminary Stratix V E/GX/GS/GT Preliminary All other device families Not available IP Core Verification Before releasing a version of the 2D-FEC IP core, Altera runs comprehensive regression tests to verify its quality and correctness. 2D-FEC IP Core February 2012 Altera Corporation Performance and Resource Utilization Page 3 Performance and Resource Utilization Stratix IV devices use combinational adaptive look-up tables (ALUTs) and logic registers. Table 3 shows the typical performance for 40 Gbps 2D-FEC on the Stratix IV GT (EP4S100G5H40I1(N)) device as reported by the Quartus® II software. Table 3. Performance - 40 Gbps 2D-FEC on Stratix IV GT Options ALUTS Logic Registers Decoder Memory (M9K) Memory (144K) Net Electrical Gain (NECG) fMAX (MHz) Encoder 7,219K 7,428 81 blocks 0 blocks 208 Decoder 67,585K 59,306 698 blocks 16 blocks 192 9.3 dB Latency 60 µs Port Listing Table 4 lists the encoder input and output ports for connecting to the 2D-FEC IP core. Table 4. Encoder I/O Port Listing I/O Port Width (Bits) Port Description Input sys_clk 1 Clock port. Input rst 1 This reset port is expected to meet removal and recovery constraints for sys_clk. This is an asynchronous reset and is active high. Input i_enable_n 1 Enable encoder and decoder port. This is a synchronous signal and is active low. Input i_row 2 Input OTN frame row port. This is a synchronous signal. Input i_col 7 Input OTN frame column port. This is a synchronous signal. Input i_data 256 Input data port. Output o_row 2 Output OTN frame row port. This is a synchronous signal. Output o_col 7 Output OTN frame column port. This is a synchronous signal. Output o_data 256 Output data port. Table 5 lists the decoder input and output ports for connecting to the 2D-FEC IP core. All error counts are accumulated on a per-clock cycle basis. Table 5. Decoder I/O Port Listing (Part 1 of 2) I/O Input Input February 2012 Port Width (Bits) Port sys_clk rst Altera Corporation Description 1 Clock port. 1 This reset port is expected to meet removal and recovery constraints for sys_clk. This is an asynchronous reset and is active high. 2D-FEC IP Core Page 4 Port Listing Table 5. Decoder I/O Port Listing (Part 2 of 2) I/O Port Width (Bits) Port Description Input i_enable_n 1 Enable encoder and decoder port. This is a synchronous signal and is active low. Input i_row 2 Input OTN frame row port. This is a synchronous signal. Input i_col 7 Input OTN frame column port. This is a synchronous signal. Input i_data 256 Input data port. Output o_uncorrectable_code_errors_va 1 lid Output o_uncorrectable_code_errors Output o_correctable_code_errors_vali 1 d Output o_correctable_code_errors 1 This output signals the number of correctable RS codes. This is a synchronous signal and is active high. Output o_ones_errors 9 This output signals the total number of corrected ones errors. Output o_odd_ones_errors 8 This output signals the number of corrected odd ones errors. Output o_even_ones_errors 8 This output signals the number of corrected even ones errors. Output o_zeros_errors 9 This output signals the total number of corrected zeros errors. Output o_odd_zeros_errors 8 This output signals the number of corrected odd zeros errors. Output o_even_zeros_errors 8 This output signals the number of corrected even zeros errors. 1 This output is the valid signal for o_ones_errors, o_odd_ones_errors, o_even_ones_errors, o_zeros_errors, o_odd_zeros_errors, and o_even_zeros_errors. This is a synchronous signal and is active high. Output o_errors_valid 1 This output is the valid signal for o_uncorrectable_code_errors. This is a synchronous signal and is active high. This output signals the number of uncorrectable RS codes. This is a synchronous signal and is active high. This output is the valid signal for o_correctable_code_errors. This is a synchronous signal and is active high. Output o_dec_locked 1 This output signals that the decoder has locked to the OTN datapath and valid error correction can occur. This is a synchronous signal and is active high. Output o_row 2 Output OTN frame row port. This is a synchronous signal. Output o_col 7 Output OTN frame column port. This is a synchronous signal. Output o_data 256 Output data port. 2D-FEC IP Core February 2012 Altera Corporation Document Revision History Page 5 Document Revision History Table 6 shows the revision history for this document. Table 6. Document Revision History Date Version February 2012 February 2012 1.0 Altera Corporation Changes Initial release. 2D-FEC IP Core Page 6 2D-FEC IP Core Document Revision History February 2012 Altera Corporation