Interfacing Altera Devices with 3.3/3.0/2.5 V LVTTL/LVCMOS I/O Systems 2014.12.15 AN-447 Subscribe Send Feedback Transmission line effects can cause a large voltage deviation at the receiver. This deviation can damage the input buffer, especially for I/O standards without termination, such as LVTTL or LVCMOS. To manage signal integrity issues and protect the input pin, follow the guidelines in this document if you interface 3.3/3.0/2.5 V LVTTL/LVCMOS I/O systems with these Altera device families: • Cyclone® III • Cyclone IV • MAX® 10 Note: In this document, the term "supported Altera devices" refers to devices in the listed device families only. To ensure device reliability and proper operation, you must design the I/O interfaces within the specifica‐ tions recommended by the guidelines in this document. Receiver Level Requirements You must address signal integrity issues if you use the supported Altera devices in 3.3/3.0/2.5 V LVTTL/LVCMOS interfaces. Otherwise, you may not meet the devices' absolute maximum DC input voltage and maximum allowed overshoot/undershoot voltage requirements. The supported Altera devices have one VCCIO voltage level per I/O bank. Additionally, the devices can also have driver input voltage levels for input signaling. Not all combinations of VCCIO and driver input voltage require attention with regards to the maximum input voltage. Follow the guidelines in this document to manage the voltage overshoot and input requirements. © 2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. www.altera.com 101 Innovation Drive, San Jose, CA 95134 ISO 9001:2008 Registered 2 AN-447 2014.12.15 Receiver Level Requirements Figure 1: Simulation Waveform of 3.3 V LVTTL Output Interfacing 3.3 V LVTTL Input This figure shows an exampe of a supported Altera device with 3.3 V LVTTL interface at the highest drive current setting and without termination. The simulation shows that an excessively large overshoot is present at the receiver when the I/O is driven from a high current driver through an unterminated transmission line. Altera Device LVTTL Out 50.0 Ω 1.054 ns 6.000 in Stripline Altera Device LVTTL In 6.0 5.0 4.0 3.0 Level: 3.3 2.0 1.0 0.0 -1.0 100n 110n 120n 130n 140n t(s) (V) : t(s) v(rx_diepad) 150n Table 1: Receiver Level Requirements for 3.3/3.0/2.5 V LVTTL/LVCMOS This table lists the recommended actions for the I/O interface voltage combinations that require attention. Supported Altera Device Receiver Bank VCCIO 2.5 V LVTTL/LVCMOS Driver Voltage Level 2.5 V No action required 3.0 V 3.3 V Disable diode and apply series termination or use driver selection table. The devices' I/O pin is overdriven by a higher external voltage. You must meet the DC current specification of the diode. Alternatively, you can apply series termination to manage voltage overshoot. In such cases, Altera recommends that you disable the diode due to the possible presence of a high DC current. 3.0 V No action required No action required No action required 3.3 V Apply series termination or use driver selection table. Diode clamped voltage can still exceed the maximum DC and AC specifications due to the high VCCIO voltage level of the bank in which the I/O resides. You must manage the voltage overshoot. You can leave the diode enabled without concern for the DC current as the I/O pin is not overdriven. Altera Corporation Interfacing Altera Devices with 3.3/3.0/2.5 V LVTTL/LVCMOS I/O Systems Send Feedback AN-447 2014.12.15 Guideline: Use Internal PCI Clamp Diode on the Pin 3 • The conditions and actions in the preceding table apply only when the supported Altera device's I/O pin is assigned as input, bidirectional, or tristated output using the 3.3/3.0/2.5 V LVTTL/LVCMOS I/O standards. No attention is required when the device's I/O pin is used as output only. • The Quartus® II software enables the PCI-clamp diode on this pin for each of these conditions by default. • Other I/O standards, such as 1.8/1.5/1.2-V LVTTL/LVCMOS, 3.0-V PCI/PCI-X, voltage-referenced, and differential I/O standards, do not require attention on the maximum input voltage. For more information about the absolute maximum DC input voltage and maximum allowed overshoot/ undershoot voltage for the device families covered in this document, refer to the related information. Related Information • • • • Cyclone III Device Datasheet Cyclone III LS Device Datasheet Cyclone IV Device Datasheet MAX 10 FPGA Device Datasheet Guideline: Use Internal PCI Clamp Diode on the Pin The supported Altera devices provide an optional PCI clamp diode for each I/O pin. You can use this diode to protect I/O pins against voltage overshoot. By default, if the assigned input, bidirectional, or tristated output pins use 3.3/3.0/2.5-V LVTTL/ LVCMOS I/O standards, the Quartus II software enables the PCI clamp diode on the pin. The PCI clamp diode can sufficiently clamp voltage overshoot to within the DC and AC input voltage specifications when the bank supply voltage (VCCIO) is 2.5 V or 3.0 V. You can clamp the voltage for a 3.3 V VCCIO to a level that exceeds the DC and AC input voltage specifications with ± 5% supply voltage tolerance. The clamped voltage is expressed as the sum of the supply voltage (VCCIO) and the diode forward voltage. Note: Dual-purpose configuration pins support the diode in user mode if the specific pins are not used as configuration pins for the selected configuration scheme. Dedicated configuration pins do not support the on-chip diode. Interfacing Altera Devices with 3.3/3.0/2.5 V LVTTL/LVCMOS I/O Systems Send Feedback Altera Corporation 4 AN-447 2014.12.15 Measuring DC Current with PCI Clamp Diode Figure 2: PCI Clamp Diode in Supported Altera Devices VCCIO = 2.5 V PCI Clamp VCCIO = 2.5 V diode I 3.0 V or 3.3 V LVTTL/LVCMOS Driver Altera Device The PCI clamp diode in the supported Altera devices can support a maximum of 10 mA DC current. The diode sinks the DC current when driven by a voltage level that exceeds the bank VCCIO plus the diode forward voltage. You must take the DC sink into consideration current when you interface a 2.5-V VCCIO receiver on the supported Altera device with 3.0 V and 3.3 V LVTTL/LVCMOS I/O systems. Note: The 10 mA DC current limit refers to the current that the diode sinks and not the drive strength of the driver. This limit is only applicable when the PCI clamp diode is enabled and when the 2.5 V receiver of the supported Altera device interfaces with 3.0-V or 3.3-V LVTTL/LVCMOS I/O systems. If you disable the diode in the Quartus II software, ensure that the interface meets the DC and AC specifi‐ cations. If your system has the flexibility to accommodate a selection of driver strengths, you can also use the driver selection guideline to select the appropriate driver without using termination. Related Information • Volume 2: Design Implementation and Optimization, Quartus II Handbook Provides information about disabling the PCI clamp diode using the assignment editor. • Guideline: Select Appropriate Driver on page 8 Measuring DC Current with PCI Clamp Diode The PCI clamp diode is forward-biased when the driver voltage level exceeds the VCCIO plus diode forward voltage. DC current exists when the diode is forward-biased. The amount of DC current depends on the driver output impedance, driver and receiver supply voltage, diode forward voltage, and a small resistance intrinsic to the transmission line. Altera Corporation Interfacing Altera Devices with 3.3/3.0/2.5 V LVTTL/LVCMOS I/O Systems Send Feedback AN-447 2014.12.15 Measuring DC Current with PCI Clamp Diode 5 Figure 3: Simulation Setup and Result to Determine DC Current that Flows into the PCI Clamp Diode Package Model TL1 50.0 Ω 1.054 ns 6.000 in Stripline Altera device (A) 30.0 m 20.0 m (V) 4.0 3.0 Package Model Altera device 2.5 V LVTTL with PCI clamp diode (V) : t(s) v(rx_diepad) Level: 3.1338 (A) : t(s) i(rtap) Level: 20.884m 2.0 10.0 m 1.0 0.0 m 0.0 0.0 2.5n 5n 7.5n 10n 12.5n 15n 17.5n 20n 1. Set up the driver to drive static logic-high signal into the receiver of the supported Altera device with the PCI clamp diode enabled. 2. Apply the maximum supply voltage at the driver and the minimum VCCIO at the receiver of the supported Altera device for the highest DC current. 3. Take the current measurement from the die pad of the supported Altera device—denoted by the red pointer in the preceding figure. You can obtain current measurements using a small sense resistor (in mili-Ω) placed in series to the transmission line. As shown in the preceding figure, a 20.88 mA DC current sink in the PCI clamp diode is measured. The result significantly exceeds the 10 mA maximum current supported by the diode. Related Information Receiver Level Requirements on page 1 Provides guidelines to interface 3.3/3.0/2.5-V LVTTL/LVCMOS I/O standards with supported Altera devices. Interfacing Altera Devices with 3.3/3.0/2.5 V LVTTL/LVCMOS I/O Systems Send Feedback Altera Corporation 6 AN-447 2014.12.15 Guideline: Use Series Termination Resistor Guideline: Use Series Termination Resistor Transmission line effects that cause large voltage deviation at the receiver are associated with impedance mismatch between the driver and transmission line. You can use a series termination resistor placed physically close to the driver to match the total driver impedance to transmission line impedance. You can significantly reduce voltage overshoot by matching the impedance of the driver to the character‐ istic impedance of the transmission line. If the driver device manufacturer specifies the driver buffer output impedance, you can use the following equation to determine the apropriate series termination value: Rdriver+Rseries≈Z0 Where: • Rdriver represents the intrinsic impedance of the driver • Rseries represents the resistance of the external series resistor If the output impedance value of the driver is not available, you can simulate an IBIS model for the driver to determind the appropriate series termination resistor value for the interface. Some drivers offer series on-chip termination (OCT) to minimize impedance mismatch to the transmis‐ sion line. You can select a driver with Rdriver that closely matches the transmission line impedance in such cases. OCT provides sufficient impedance matching without the expense of additional external component. Note: OCT affects the edge rates of the transmitted signal. You must evaluate if the timing impact causes a performance degradation of the interface. Selecting Appropriate Series Termination Resistor Value The series termination scheme works by introducing a resistor placed in series between the driver and receiver. The driver impedance and series resistance become the total effective driver impedance. The transmission line impedance has to match the driver impedance to minimize reflection and manage overshoot. Figure 4: Series Termination Scheme Series Resistor, R S Driver Transmission Line Receiver You must perform a simulation to determine the suitable series resistor value for your interface within the allowable tolerance condition. Choosing the appropriate resistor value for series termination is important: • If the resistance is too small, the termination may not effectively reduce or eliminate the overshoot. • If the resistance is too large, the driver may not sufficiently drive the transmission line and it can result in a stair-step response. Altera Corporation Interfacing Altera Devices with 3.3/3.0/2.5 V LVTTL/LVCMOS I/O Systems Send Feedback AN-447 2014.12.15 Example of Determining Series Termination Resistor Value 7 Example of Determining Series Termination Resistor Value This example shows how to determine the value of the series termination resistor to manage the voltage overshoot effectively. The example uses the terminator wizard feature in the HyperLynx Simulation Software by Mentor Graphics® Corporation. You can explore other appropriate methods via simulation to determine a suitable series resistor value for your interface. In this example, a Cyclone II 3.3-V LVTTL 16 mA is driven to a Cyclone III 2.5-V LVTTL input. You can disable the diode and apply the series termination, or use the driver selection reference. Figure 5: Cyclone II 3.3 V LVTTL 16 mA Interfacing with Cyclone III 2.5 V LVTTL Set up the desired interface in the Schematic Editor as represented in this figure and run the terminator wizard. Cyclone II 2c_ttl33_cio_d16 50.0 Ω 1.054 ns 6.000 in Stripline Cyclone III 3c_ttl25_cin Figure 6: Terminator Wizard Results From HyperLynx Simulation Software by Mentor Graphics Corporation The Terminator Wizard results suggest adding a 33 Ω series resistance. Interfacing Altera Devices with 3.3/3.0/2.5 V LVTTL/LVCMOS I/O Systems Send Feedback Altera Corporation 8 AN-447 2014.12.15 Guideline: Select Appropriate Driver Figure 7: Cyclone II 3.3 V LVTTL 16 mA Interfacing with Cyclone III 2.5 V LVTTL with Recommended 33.0 Ω Series Termination Resistor The suggested 33 Ω series resistance is applied close to the Cyclone II driver. Rs 33.0 Ω Cyclone II 2c_ttl33_cio_d16 TL1 50.0 Ω 1.054 ns 6.000 in Stripline Cyclone III 3c_ttl25_cin Figure 8: Simulation Waveforms Comparing Terminated and Non-Terminated Interface Across Typical, Minimum, and Maximum Conditions The new setup in this example is evaluated at different allowable conditions to ensure that DC and AC specifications are met and to identify the impact of introducing the resistor in the interface. (V) : t(s) 6.0 Maximum: 5.0002 min_Rs_terminated 4.0 (V) typ_Rs_terminated Maximum: 3.747 max_Rs_terminated unterminated 2.0 0.0 -2.0 0.0 2.5n 5n 7.5n 10n 12.5n 15n t(s) 17.5n 20n 22.5n 25n 30n Related Information Driver Selection Reference on page 9 Guideline: Select Appropriate Driver The output characteristics of a driver determines how much overshoot voltage is seen at the receiver when the interface is not terminated. You can address signal integrity concerns in your interface by selecting the appropriate driver. You must select a driver that meets the current limits of the supported Altera device at the appropriate points in the I/V curve. You can obtain the I/V curve of the driver from the IBIS file provided by the device manufacturer. You can also use slew rate control, if it is available on the driver, to address signal integrity concerns. Slew rate control allows you to reduce the edge rate of the output signal to help control voltage overshoot at the receiver. You must perform simulations to ensure that the specifications are met when using the slew rate feature. Altera Corporation Interfacing Altera Devices with 3.3/3.0/2.5 V LVTTL/LVCMOS I/O Systems Send Feedback AN-447 2014.12.15 Driver Selection Reference 9 Driver Selection Reference A driver can drive a receiver without termination even if it produces overshoot, undershoot, and ringing in the interface as long as it meets two key specifications: voltage threshold and maximum input voltage of the receiver device. Conformance to the voltage threshold specification ensures the correct logic-low and logic-high switching. On the other hand, conformance to the maximum DC and AC input specifications ensures the reliability of the receiver device in the system over an extended period. A driver can drive to a supported Altera device without requiring termination if the measured current of the driver is less than the current limit in the preceding table for the desired interface setup. The limits ensure that the DC and AC maximum input voltage specifications and maximum DC current for diode are met, if the driver current value is within the limits. Table 2: VOH Level for Each I/O Standard This table lists the current limits that are the maximum allowable driver current values at the VOH level. Driver I/O Standard VOH Level 2.5 V LVTTL 2.0 V 3.0 V LVTTL 2.4 V 3.0 V LVCMOS VCCIO – 0.2 V 3.3 V LVTTL 2.4 V 3.3 V LVCMOS VCCIO – 0.2 V The current limits in the following table takes into account the DC and AC requirements of the receiver, and the use of the PCI clamp diode. You can use the values as measurements to identify if a driver meets the input specifications of the supported Altera device for the target I/O standard. Using these values, you can select the appropriate driver without performing simulation. Interfacing Altera Devices with 3.3/3.0/2.5 V LVTTL/LVCMOS I/O Systems Send Feedback Altera Corporation 10 AN-447 2014.12.15 Current Limits Measurement Examples Table 3: Maximum Allowed Current Metrics Required to Drive Supported Altera Devices without Termination This table lists the maximum current limits of the drivers that interface with the supported Altera devices without termination in each I/O interface combination. Driver Voltage Level Receiver Bank VCCIO(V)(1) 2.5 ± 5% 3.0 ± 5% 3.3 ± 5% 2.5 V LVTTL No maximum limit No maximum limit 48 mA 3.0 V LVTTL 26 mA No maximum limit 26 mA 3.0 V LVCMOS 8 mA No maximum limit 8 mA No maximum limit 30 mA No maximum limit 12 mA 3.3 V LVTTL 3.0 V LVCMOS 15 mA (30 mA)(2) 4 mA (8 mA) (2) • The pull-up I/V curve represents the current and voltage behavior of the driver when it is sourcing logic-high. • Take the measurement at the driver maximum allowable operating condition, which is at a low temperature and high supply voltage, to account for the worst possible overshoot condition. • The current limit does not represent the current strength of a driver associated with a particular I/O standard. • You must perform the measurement on the I/V curve at the maximum condition. Current Limits Measurement Examples The following examples use the driver selection reference to evaluate an interface from a Cyclone series device to the Cyclone III and Cyclone IV device receiver using the 3.3 V LVTTL I/O standard via unterminated transmission line. For the interface evaluation in these examples, the current strength of the Cyclone device is 8 mA. Example 1: Input Setup with 2.5 V VCCIO The supported Altera device's on-chip PCI diode starts to sink the DC current IDC when driven by a steady state voltage greater than the sum of the supported Altera device's VCCIO and diode forward voltage in the following figure. The diode is forward-biased when the driver's VCC is 3.3 V or 3.0 V and the IDC must not exceed 10 mA. (1) (2) The Quartus II software enables the PCI clamp diode for pins assigned as 3.3/3.0/2.5 V LVTTL/LVCMOS I/O standards by default. The value in brackets is the current limit for the driver if you disable the PCI clamp diode. For this combination, disabling the diode offers the driver slightly more margin. For other combinations, enabling the diode offers the driver better margin. Altera Corporation Interfacing Altera Devices with 3.3/3.0/2.5 V LVTTL/LVCMOS I/O Systems Send Feedback AN-447 2014.12.15 Current Limits Measurement Examples 11 Figure 9: Supported Altera Device Input Setup with 2.5 V VCCIO Driver VCC= 3.3/3.0/2.5 V VCCIO= 2.5 V± 5% Altera Device IDC The amount of IDC through the diode is determined by the potential voltage difference between the driver and the supported Altera device's pin, and the current capability of the driver. The diode can limit the transient voltage level to below the specification limit when the driver's VCC is 2.5 V—effectively limiting it to 3.325 V with the assumption that VCCIO is 2.625 V and diode forward voltage is 0.7 V. Example 2: Input Setup with 3.0 V VCCIO The diode might not be forward-biased even when the driver's VCC is 3.3 V as the potential voltage difference between the driver's VCC and the supported Altera device's VCCIO is less than the diode forward voltage. Therefore, there is no concern on IDC through the diode when driven with an input voltage level of 3.3 V, 3.0 V, or 2.5 V as shown in the following figure. Figure 10: Supported Altera Device Input Setup with 3.0 V VCCIO Driver VCC= 3.3/3.0/2.5 V VCCIO= 3.0 V± 5% Altera Device IDC ≈0 The forward-bias of the diode occurs only momentarily during overshoot conditions to clamp the overshoot voltage level. In such cases, the diode is effective in limiting the transient voltage level to below the specification limit—effectively limiting it to 3.85 V with the assumption that VCCIO is 3.15 V and diode forward voltage is 0.7 V. Interfacing Altera Devices with 3.3/3.0/2.5 V LVTTL/LVCMOS I/O Systems Send Feedback Altera Corporation 12 AN-447 2014.12.15 Evaluating Interface Using Driver Selection Method Example 3: Input Setup with 3.3 V VCCIO IDC is almost zero at a steady input voltage level as the diode might not be forward-biased as shown in the setup in the following figure. At a higher VCC level of the driver, such as 3.465 V, the diode clamps transient voltage level at 4.165 V with the assumption that diode forward voltage is 0.7 V. Figure 11: Supported Altera Device Input Setup with 3.3 V VCCIO Driver VCC= 3.3/3.0/2.5 V VCCIO= 3.3 V± 5% Altera Device IDC ≈0 The use of a lower driver current capability reduces the voltage overshoot level. You must ensure that the duration of the overshoot is below these limits: • For Cyclone III and Cyclone IV devices, the percentage of high time for an overshoot of 4.15 V can be as high as 18.52% over a 10-year period. • For MAX 10 devices, the percentage of high time for an overshoot of 4.17 V can be as high as 11.7% over a 10-year period. Related Information Driver Selection Reference on page 9 Evaluating Interface Using Driver Selection Method An easy and convenient method to determine the current limits is to perform the measurement on the driver pull-up I/V curve in the IBIS model. 1. Obtain the IBIS model for the driver. The model used as the driver is 1c_ttl33_io_d8 from the cyclone.ibs file. You can perform a DC sweep simulation on the HSPICE model and set the buffer to drive logic-high if the IBIS model is not available for the driver. 2. Open the IBIS file using the HyperLynx Visual IBIS Editor. The editor provides a graphical view of IBIS model data, which provides a measurement of the I/V values in graphical format. 3. Run the graphical view mode. a. Navigate to the 1c_ttl33_io_d8 model data from tree-view pane on the left column in the editor. b. Right-click on the model denoted by [Model] 1c_ttl33_io_d8 and select View Data. A dialog box appears with multiple tabs for each data characteristic available for the model. 4. Select the pull-up I/V curve. Altera Corporation Interfacing Altera Devices with 3.3/3.0/2.5 V LVTTL/LVCMOS I/O Systems Send Feedback AN-447 2014.12.15 Evaluating Interface Using Driver Selection Method 13 a. Select the Pullup tab in the dialog window. b. In the Display Curves list, select Ground relative. Figure 12: Current Limit Measurement for IBIS Pull-Up Data Using Graphical Viewer HyperLynx Visual IBIS Editor In the figure, the measured current is 33.8 mA. 5. Identify the appropriate VOH level and perform the current measurement. Based on the driver selection reference, the VOH for the 3.3 V LVTTL driver is 2.4 V (see related information). Look for the maximum I/V curve and make the visual approximation current measure‐ ment at 2.4 V. 6. Identify allowed current limit. Based on the maximum allowed current metrics for the supported Altera device (see related informa‐ tion), the current limit is 30 mA for a 3.3 V LVTTL driver to a 3.3 V receiver bank of a supported Altera device. The measured current exceeds the maximum allowed current limit. From the preceding example, a Cyclone device operating as the driver at 3.3-V LVTTL with 8 mA setting is not able to drive directly the supported Altera device's input at 3.3 V VCCIO supply without termination. The Cyclone device might not meet the DC and AC input voltage specification of the supported Altera devices. Interfacing Altera Devices with 3.3/3.0/2.5 V LVTTL/LVCMOS I/O Systems Send Feedback Altera Corporation 14 AN-447 2014.12.15 Interface Current between Supported Altera Devices To solve the problem, you can apply series termination according to the recommended receiver level requirements. Related Information • Driver Selection Reference on page 9 • Altera IBIS Models Provides the IBIS models for all Altera devices. • Receiver Level Requirements on page 1 Interface Current between Supported Altera Devices The supported Altera devices can drive into each other without termination for certain drive strengths using the 3.3/3.0/2.5 V LVTTL/LVCMOS I/O standards. Table 4: Interface Current Between Supported Altera Devices Without Additional Solution In this table, "Yes" means that you can drive into the supported Altera device receiver unterminated—with the I/O standard drive strengh and corresponding bank VCCIO—without violating the DC and AC input voltage specifications. Driver I/O Standard 2.5 V LVTTL 3.0 V LVTTL 3.0 V LVCMOS (3) Drive Strength Receiver Bank VCCIO(V)(3) 2.5 ± 5% 3.0 ± 5% 3.3 ± 5% 4 mA Yes Yes Yes 8 mA Yes Yes Yes 12 mA Yes Yes — 16 mA Yes Yes — 4 mA Yes Yes Yes 8 mA Yes Yes Yes 12 mA — Yes — 16 mA — Yes — 4 mA Yes Yes Yes 8 mA — Yes — 12 mA — Yes — 16 mA — Yes — The Quartus II software enables the PCI clamp diode for pins assigned as 3.3/3.0/2.5 V LVTTL/LVCMOS I/O standards by default. Altera Corporation Interfacing Altera Devices with 3.3/3.0/2.5 V LVTTL/LVCMOS I/O Systems Send Feedback AN-447 2014.12.15 Document Revision History Driver I/O Standard 3.3 V LVTTL 3.3 V LVCMOS 15 Receiver Bank VCCIO(V)(3) Drive Strength 2.5 ± 5% 3.0 ± 5% 3.3 ± 5% 4 mA Yes Yes Yes 8 mA (4) Yes Yes 2 mA (4) Yes Yes Document Revision History Date Version Changes December 2014 2014.12.15 November 2009 2.0 • Updated all Cyclone IV device references. • Removed "Introduction" heading. • Removed "Referenced Documents" section. June 2009 1.2 • Updated to include Cyclone III LS devices information. • Added support for MAX 10 devices. • Restructured and rewritten the document to improve clarity and for easier reference. • Updated template. • • • • • • • • • • (3) (4) Updated "Introduction" on page 1. Updated "Background" on page 1. Updated "Design Guideline" on page 2. Updated Table 1 on page 2, Table 3 on page 10, Table 4 on page 14. Updated "PCI-Clamp Diode" on page 3. Updated "Termination" on page 4. Updated "Conclusion" on page 5. Updated "Appendix A: DC Current Measurement with PCIClamp Diode" on page 5, "Appendix C: Driver Selection Table and Measurement Method" on page 9, "Appendix D: Cyclone III Device Family to Cyclone III Device Family Interface Matrix" on page 14. Updated Figure 2 on page 5, Figure 10 on page 10, Figure 11 on page 11, Figure 12 on page 12. Updated "Referenced Documents" on page 14. The Quartus II software enables the PCI clamp diode for pins assigned as 3.3/3.0/2.5 V LVTTL/LVCMOS I/O standards by default. With the PCI clamp diode enabled, the supported Altera devices—at this I/O standard, drive strength, and receiver bank VCCIO combination—cannot drive each other unterminated. To use this combination without violating the specifications, disable the PCI clamp diode. Interfacing Altera Devices with 3.3/3.0/2.5 V LVTTL/LVCMOS I/O Systems Send Feedback Altera Corporation 16 AN-447 2014.12.15 Document Revision History Date Version Changes April 2008 1.1 • Added Figure 10, Figure 11, and Figure 12. • Added new note on configuration pins under PCI-Clamp Diode section. • Added new paragraph under Appendix C: Driver Selection Table and Measurement Method section. March 2007 1.0 Initial release. Altera Corporation Interfacing Altera Devices with 3.3/3.0/2.5 V LVTTL/LVCMOS I/O Systems Send Feedback