Enhanced Configuration Devices v1.3 Errata Sheet

Enhanced Configuration
Devices
Errata Sheet
July 2008, Version 1.3
Introduction
This errata sheet provides updated information on enhanced
configuration devices—EPC4, EPC8, and EPC16—which are used to
configure SRAM-based programmable logic devices (PLDs). This
document addresses known issues and includes methods to work around
the issues.
Intel-FlashBased EPC
Device
Protection
Altera performed a die-sub replacement for the EPC4, EPC8, and EPC16
devices with Intel flash. Intel flash devices do not have the lock bit
protection feature to lock the flash for protection during power-up or
power-down. The lock bit protection feature is used to prevent
unintentional writes and ensure data retention.
f
For more information about the flash die change in the Altera® enhanced
configuration devices, refer to Process Change Notification PCN0506:
Addition of Intel Flash Memory as Source for EPC4, EPC8 & EPC16 Enhanced
Configuration Devices.
In the absence of the lock bit protection feature in the EPC4, EPC8, and
EPC16 devices with Intel flash, Altera recommends four methods to
protect the Intel flash content in EPC4, EPC8, and EPC16 devices. Any
method alone is sufficient to protect the flash. The methods are listed
below in the order of descending protection level:
Altera Corporation
ES-DCLKSIG-1.3
1.
Using an RP# of less than 0.3 V on power-up and power-down for a
minimum of 100 ns to a maximum 25 µs disables all control pins,
making it impossible for a write to occur.
2.
Using VPP < VPPLK, where the maximum value of VPPLK is 1 V,
disables writes. VPP < VPPLK means programming or writes cannot
occur. VPP is a programming supply voltage input pin on the Intel
flash. VPP is equivalent to the VCCW pin on EPC devices (Refer to
Figure 1).
3.
Using a high CE# disables the chip. The requirement for a write is a
low CE# and low WE#. A high CE# by itself prevents writes from
occurring.
4.
Using a high WE# prevents writes because a write only occurs when
the WE# is low.
1
Intel-Flash-Based EPC Device Protection
Performing all four methods simultaneously is the safest protection for
the flash content.
The ideal power-up sequence is as follows:
1.
Power up VCC.
2.
Maintain VPP < VPPLK until VCC is fully powered up.
3.
Power up VPP.
4.
Drive RP# low during the entire power-up process. RP# must be
released high within 25 µs after VPP is powered up.
1
CE# and WE# must be high for the entire power-up sequence.
The ideal power-down sequence is as follows:
1.
Drive RP# low for 100 ns before power-down.
2.
Power down VPP < VPPLK.
3.
Power down VCC.
4.
Drive RP# low during the entire power-down process.
1
CE# and WE# must be high for the entire power-down sequence.
The RP# pin is not internally connected to the controller. Therefore, an
external loop-back connection between C-RP# and F-RP# must be made
on the board even when you are not using the external flash interface.
When using the external flash interface, connect the external device to the
RP# pin with the loop back. Tri-state RP# at all times when the flash is not
in use.
If an external power-up monitoring circuit is connected to the RP# pin
with the loop-back, use the following guidelines to avoid contention on
the RP# line:
■
■
The power-up sequence on the 3.3-V supply should complete within
50 ms of power-up. The 3.3-V VCC should reach the minimum VCC
before 50 ms and RP# should then be released.
RP# should be driven low by the power-up monitoring circuit during
power-up. After power-up, RP# should be tri-stated externally by
the power-up monitoring circuit.
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Enhanced Configuration Devices v1.3 Errata Sheet
Altera Corporation
Intel-Flash-Based EPC Device Protection
■
If the preceding guidelines cannot be completed within 50 ms, then
the OE pin must be driven low externally until RP# is ready to be
released.
Figure 1 shows an example of configuration schematic using EPC device
in FPP mode with the extended flash interface in use.
Figure 1. Configuration Example using EPC Device in FPP Mode Note (1)
VCC
Enhanced Configuration
Device
VCC
Stratix Series
or
APEX II Device
n
MSEL
N.C.
PLD or Processor
WE#C
WE#F
RP#C
RP#F
DCLK
DATA[7..0] A[20..0] (2)
OE
RY/BY# (5)
nCS
CE#
nINIT_CONF
OE#
DCLK
DATA[7..0]
nSTATUS
CONF_DONE
nCONFIG
nCEO
WE#
RP#
A[20..0]
RY/BY#
CE#
OE#
DQ[15..0]
nCE
DQ[15..0]
VCC
VCC (6)
WP#
BYTE# (3)
TM1
GND
TMO
VCCW
PORSEL
PGM[2..0]
(4)
(4)
EXCLK
(4)
GND
C-A0 (3)
C-A1 (3)
C-A15 (3)
C-A16 (3)
A0-F
A1-F
A15-F
A16-F
Notes to Figure 1:
(1)
(2)
(3)
(4)
For external flash interface support in EPC8 enhanced configuration device, contact Altera Applications.
Pin A20 in EPC16 devices, pins A20 and A19 in EPC8 devices, and pins A20, A19, and A18 in EPC4 devices should
be left floating. These pins should not be connected to any signal; they are no-connect pins.
In the 100-pin PQFP package, you must externally connect the following pins: C-A0 to F-A0, C-A1 to F-A1, CA15 to F-A15, C-A16 to F-A16, and BYTE # to VCC. Additionally, you must make the following pin connections
in both 100-pin PQFP and 88-pin Ultra FineLine BGA packages: C-RP# to F-RP#, C-WE# to F-WE#, TM1 to VCC,
TM0 to GND, and WP# to VCC.
For PORSEL, PGM[], and EXCLK pin connections, refer to Enhanced Configuration Devices (EPC4, EPC8, and
EPC16) Data Sheet.
(5)
(6)
RY/BY# pin is only available for Sharp flash-based EPC8 and EPC16.
To protect Intel Flash based EPC devices content, you have to isolate the VCCW supply from VCC.
Altera Corporation
3
Enhanced Configuration Devices v1.3 Errata Sheet
Set-Up Time Issue
Set-Up Time
Issue
The set-up time issue described here refers to the revision B silicon of the
Altera enhanced configuration devices. The issue described in this errata
sheet has now been corrected in the revision C silicon of this device. All
revision C devices are fully backward compatible with the revision B
devices. As of the date of this errata sheet, the EPC4, EPC8, and EPC16
devices in the 100-pin quad flat pack (QFP) package are shipped with
revision C silicon.
The EPC16UC88 device has a special ordering code (EPC16UB88AA) to
identify revision C silicon. The EPC16UC88 ordering code is used to
deliver revision B silicon at this time. Once the transition from revision B
to revision C silicon is complete, the EPC16UC88 ordering code will be
used going forward to deliver revision C silicon, and the EPC16UC88AA
ordering code will be made obsolete.
For identification purposes, the fourth character of the 11-character date
code indicates the die revision. For a revision B component, this character
will be a “B”, and for a revision C component, this character will be a “C”.
For more information regarding the device marking, refer to customer
advisories 9916 and 9707.
Customers who are using enhanced configuration devices and
configuring one or more SRAM-based devices may encounter
configuration device failure. This failure may be temperature- or
voltage-dependent.
The problem is due to a set-up time violation of the DATA signal. The
enhanced configuration device generates the DATA and DCLK signals so
that they arrive at the PLD simultaneously.
The PLD requires a set-up time of 10 ns. However, since the DCLK and
DATA signals transition simultaneously, the set-up time at the PLD is
actually zero. Figure 2 shows the DATA and DCLK signals generated by
enhanced configuration devices.
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Enhanced Configuration Devices v1.3 Errata Sheet
Altera Corporation
Set-Up Time Issue
Figure 2. DATA and DCLK Signals Generated by Enhanced Configuration
Devices
DCLK
DATA
Bit/Byte 1
Bit/Byte 2
Bit/Byte 3
Bit/Byte 4
No Set-up Time
Design Guidelines
To achieve a successful configuration, required set-up time must be
provided to the DATA signal or signals of SRAM-based devices.
Depending on the layout of the board, there may already be sufficient
set-up time at the PLD. Measure the DCLK to DATA relationship at the
PLD. If the DATA changes prior to the rising edge of the DCLK signal more
than the required set-up time (10 ns for all SRAM-based devices), then the
board will configure correctly. If the set-up time parameter is not met,
then the DATA signal must be delayed so that it changes after the DCLK
transition (DATA latches on next rising edge of the clock). A delay of 10 ns
is sufficient to provide the required set-up time for the DATA signal or
signals. This delay between DCLK and DATA is measured at the PLD.
Altera Corporation
5
Enhanced Configuration Devices v1.3 Errata Sheet
Set-Up Time Issue
The delay is introduced by adding a resistor to the DATA path from the
enhanced configuration devices to the SRAM-based PLDs, as shown in
Figure 3.
Figure 3. Adding a Resistor to DATA Path
Enhanced
Configuration
Device
SRAM-Based
PLD
Resistor
DATA
DATA
The delay is created by a resistor-capacitor network. The resistor is added
to the circuit and the capacitance is provided by the board trace. The RC
combination should be chosen such that the path delay is equal to 10 ns.
A typical combination would use a 100- to 200-Ω resistor with a trace
length of four inches between the DATA pins of the enhanced
configuration device and the PLD.
After inserting the delay, the DATA transition would shift to the right so
that the first bit or byte of data would be latched on the second rising edge
of DCLK, as shown in Figure 4. This shift meets the required set-up time
for the DATA signal.
Figure 4. DATA Latches on Second Rising Edge of DCLK after DATA Path Delay
DCLK
DATA
Bit/Byte 1
Bit/Byte 2
Bit/Byte 3
Bit/Byte 4
Data Delayed to
Next Clock Cycle
}
}
Set Up Hold
This technique enables existing enhanced configuration devices to
configure PLDs. Future updated versions of enhanced configuration
devices will be modified so that the DCLK and DATA signals arrive at the
PLD to meet the required set-up time.
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Enhanced Configuration Devices v1.3 Errata Sheet
Altera Corporation
Contact Information
A board that is laid out with an in-line resistor will work with updated
versions of enhanced configuration devices, but the maximum frequency
for configuration would be limited to 33 MHz.
Contact
Information
For more information, go to Altera's mySupport website at
www.altera.com/mysupport and click Create New Service Request.
Choose the Product Related Request form.
Revision History
Table 1 shows the revision history for this errata sheet.
Table 1. Enhanced Configuration Devices v1.3 Errata Sheet Revision History
Version
Date
Errata Summary
1.3
July 2008
■
■
Added Figure 1.
Updated Figure 1.
1.2
October 2007
■
■
Added section on “Intel-Flash-Based EPC Device Protection”.
Updated section on “Set-Up Time Issue”.
1.1
December 2003
■
Addressed known issues and includes methods to work around the
issues for enhanced configuration devices EPC4, EPC8, and EPC16.
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Enhanced Configuration Devices v1.3 Errata Sheet
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