AN-701: Scalable Low Latency Ethernet 10G MAC using

2015-09-30
Scalable Low Latency Ethernet 10G MAC using Arria 10
1G/10G PHY
AN-701
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The following design examples demonstrate Altera Low Latency Ethernet 10G MAC IP systems using
Arria 10 PHY.
• Scalable Low Latency Ethernet 10G MAC using Arria 10 1G/10G PHY without IEEE 1588v2
• Scalable Low Latency Ethernet 10G MAC using Arria 10 1G/10G PHY with IEEE 1588v2
These design examples support only Arria 10 devices.
Related Information
• Scalable Low Latency Ethernet 10G MAC using Arria 10 1G/10G PHY without IEEE 1588v2
• Scalable Low Latency Ethernet 10G MAC using Arria 10 1G/10G PHY with IEEE 1588v2
Features
These design examples offer the following features:
• Support multi speed operation of 10 Megabits per second (Mbps) to 10 Gigabits per second (Gbps)
with Arria 10 1G/10G PHY.
• Support scalability from 1 to 12 channels Ethernet MAC and PHY.
• Provide packet monitoring system on transmit and receive data paths and report Ethernet MAC
statistics counters for transmit and receive datapaths.
• Support testing using different types of Ethernet packet transfer with or without IEEE 1588v2 features.
Requirements
Altera uses the following software to test the design examples and testbench in Linux platform:
• Altera Complete Design Suite (ACDS) version 15.0 for software and hardware simulation
• ModelSim-SE 10.3d
• Synopsys VCS Version I-2014.03-SP1
Note: Upgrading prior versions of the design example is not supported in the current ACDS version.
Please use the latest design example files.
Components
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of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
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Components
Figure 1: Block Diagram for Design Example without IEEE 1588v2
altera_eth_multi_channel
altera_eth_channel
altera_eth_channel
address_decoder_channel
address_decoder_multi_channel
S
Avalon-MM
S
FIFO
Avalon-ST
Adapter
S LL MAC
Adapter
Avalon-MM
Master M
Avalon-MM
Master M
TX/RX
Serial
Data
S Arria 10 PHY
Transceiver
Reset Controller
S MDIO
Arria 10
ATX PLL
Legend
Generated with Qsys
PLL
Reset
Controller
Input Clock
Reset
MDIO
Signals
Arria 10
fPLL
Generated with IP Catalog
Figure 2: Block Diagram for Design Example with IEEE 1588v2
altera_eth_multi_channel_1588
altera_eth_channel_1588
altera_eth_channel_1588
address_decoder_channel
address_decoder_multi_channel
S
Avalon-MM
S
PTP Packet
Classifier
Adapter
S LL MAC
Adapter
Avalon-MM
Master M
Avalon-MM
Master M
S
Local
TOD
Arria 10
ATX PLL
PLL
Input Clock
Altera Corporation
TOD
Sync
Reset
Controller
Reset
1G/10G Pulse
Per Second
IEEE 1588v2
Timestamp
TX/RX
Serial
Data
S Arria 10 PHY
Transceiver
Reset Controller
Legend
Generated with Qsys
Avalon-ST
Pulse Per
Second
S MDIO
Arria 10
fPLL
MDIO
Signals
S
Master
TOD
Pulse Per
Second
Master
Pulse Per
Second
Generated with IP Catalog
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Components
3
Table 1: Design Examples Components
Component
Design Example without IEEE 1588v2
Design Example with IEEE 1588v2
Low latency Ethernet 10G Ethernet MAC IP core
MAC
Arria 10 1G/10G PHY
Altera 1G/10G and 10GBASE-KR PHY IP
MDIO
Provides MDIO interface to connect Ethernet MAC to external PHY
Address decoder channel
Address decoder module for each component within the channel, for
example, MAC and PHY.
Address decoder multichannel
Address decoder module for all channels and components within multichannel level, for example Master TOD.
Reset controller
Reset modules which handle reset synchronisation for the components in the
design example.
Master PLL
Generates clocks for all the components in the design example.
Arria 10 ATX PLL
Generates a TX serial clock for Arria 10 10G transceiver.
Arria 10 fractional PLL
Generates a TX serial clock for Arria 10 1G transceiver.
Master Time-of-Day
(TOD)
—
Provides a master TOD for all
channels.
TOD Sync
—
Module to synch time of day from
Master TOD to Local TOD for all
channels.
Local TOD
—
TOD module in each channel.
Master Pulse Per Second
module
—
Returns pulse per second (pps) to
user for all channels.
1G/10G Pulse Per Second
module
—
Returns pulse per second (pps) to
user in each channel.
PTP packet classifier
—
Decodes the packet type of
incoming PTP packets and returns
the decoded information to the
Ethernet MAC.
FIFO
Avalon Streaming (Avalon-ST) singleclock or dual-clock FIFO that buffers
the receive and transmit data between
the MAC and client.
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Parameters
Parameters
Table 2: Parameters for Design Example Customization
Parameter
NUM_CHANNELS
MDIO_MDC_CLOCK_
DIVISOR
SHARED_REFCLK_EN
Description
Default Value
Specify the number of channels of 1-Gbps Ethernet(GbE)/
10GbE that will be instantiated in the design example.
Range from 1 to 12.
2
Use this parameter to set the management data input/
output (MDIO) clock divisor. Range from 8 to 64.
32
Use this parameter to enable the sharing of reference clock
1
refclk between all channels.
• 0 : disable sharing
• 1 : enable sharing
Use this parameter to enable the FIFO in between user
Avalon-ST and MAC interface.
FIFO_OPTIONS
•
•
•
•
1
0: disable FIFO
1: enable SC FIFO
2: enable DC FIFO
3: enable SC + DC FIFO
Note: This parameter is available only for design example
without IEEE 1588v2.
TSTAMP_FP_WIDTH
Use this parameter to set the timestamp fingerprint width
which follows the setting in 1G/10GbE MAC. You must
regenerate the MAC IP if this parameter is changed. Enter
the new width value in MAC IP regeneration page.
4
Note: This parameter is available only for design example
with IEEE 1588v2.
Design Example Walkthrough
The following design examples come with pre-generated RTL files for two channels:
Design Example
File Name
Scalable Low Latency Ethernet 10G MAC using
Arria 101G/10G PHY without IEEE 1588v2
LL_Ethernet_10G_A10_phy_lineside.tar.gz
Scalable Low Latency Ethernet 10G MAC using
Arria 101G/10G PHY with IEEE 1588v2
LL_Ethernet_10G_A10_phy_lineside_1588.tar.gz
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Setting Up the Design Examples
5
Setting Up the Design Examples
To set up the design examples, follow these steps:
1. Unzip and untar the design examples at the project directory.
2. Launch the Quartus II software and open the project file, altera_eth_top.qpf.
3. Click Start Compilation on the Processing menu to compile the design example.
Changing Number of Channels
The design examples are configured to have two channels by default. To change the number of channels,
modify the NUM_CHANNELS parameter of altera_eth_multi_channel or altera_eth_multi_channel_1588.
Configuring PHY Speed
After reset, all ports are set in 10G and auto speed detection mode. Use the PHY memory map to change
to other modes: 10G SerDes Framer Interface (SFI), 1G1000Base-X, or 1G/100M/10M SGMII.
Changing Speed between 10G and 1G in 1000BaseX mode
The software can turn off auto speed detection and force the PHY to either 1G or 10G by writing a
different value to the PHY register address at offset 0x12C0.
Table 3: Register Value for Speed Change in 1000BaseX Mode in Arria 10 Transceiver PHY IP
Value
Description
0x01
Reset back to auto speed detection mode
0x11
Turn off auto speed detection and force the PHY to 1G
0x41
Turn off auto speed detection and force the PHY to 10G
Example 1: Forcing Port 0 to 1000Base-X mode
• Set Port 0 to 1000Base-X: write_32 0x02_52C0 0x11
Example 2: Reset Port 0 to auto speed detection mode
• Set Port 0 to 1000Base-X: write_32 0x02_52C0 0x01
Changing Speed between 1G, 100M, and 10M SGMII
To enable SGMII, the software needs to write a different value to the PHY register address offset 0x1290.
Set the port to 1000Base-X mode first before you select any SGMII modes.
Table 4: Register Value for Speed Change in SGMII Mode in Arria 10 Transceiver PHY IP
Value
Description
0x01
Enable SGMII mode and force speed to 10M
0x03
Enable SGMII mode and use SGMII auto negotiation
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IP Regeneration
Value
Description
0x05
Enable SGMII mode and force speed to 100M
0x09
Enable SGMII mode and force speed to 1G
Example 3: Forcing Port 0 to SGMII 100M mode
1. Set Port 0 to 1000Base-X: write_32 0x02_52C0 0x11
2. Set Port 0 to SGMII 100M: write_32 0x02_5290 0x05
IP Regeneration
Regeneration of IP files is required when upgrading to a new version of ACDS. This process involves 2
different tools: Qsys and IP Catalog. The following table shows the IPs that need regeneration and the
tools involved.
Table 5: IP Requires Regeneration
IP
Tools
IP File Locations
address_decoder_channel
Qsys
ADDRESS_DECODER/address_decoder_channel.qsys
address_decoder_multi_
channel
Qsys
ADDRESS_DECODER/address_decoder_multi_
channel.qsys
altera_eth_10g_mac
IP Catalog
MAC_NO_1588/altera_eth_10g_mac.qsys
altera_eth_10gkr_phy
IP Catalog
PHY_NO_1588/altera_eth_10gkr_phy.qsys
altera_xcvr_reset_
controller
IP Catalog
XCVR_RESET_CONTROLLER/altera_xcvr_reset_
controller.qsys
nf_xcvr_10g_pll
IP Catalog
nf_atx_pll/nf_xcvr_10g_pll.qsys
nf_xcvr_1g_pll
IP Catalog
nf_xcvr_fpll/nf_xcvr_1g_pll.qsys
pll
IP Catalog
PLL/pll.qsys
pll_2
IP Catalog
PLL/pll_2.qsys
Note: This IP is only
available for design
example with IEEE
1588v2.
Launch the tool and open the IP files listed in the table to regenerate the IP.
Design Example Testbench
Altera provides testbenches to verify the design examples, with or without IEEE 1588v2.
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Testbench Components
7
Testbench Components
The testbench operates in loopback mode. The following figure shows the flow of the packets in the
design examples.
Figure 3: Testbench Block Diagram for Design Examples
Testbench
Avalon-MM
Control
Register
Avalon-ST
Transmit
Frame
Generator
Avalon-ST
Receive
Frame
Monitor
avalon_bfm_wrapper.sv
Avalon Driver
Ethernet
Packet
Monitor
Avalon-MM
DUT
Avalon-ST
Ordinary Clock
Channel 0
Channel 1
Avalon-ST
Loopback
on Serial
Transparent Clock
Ethernet
Packet
Monitor
The following table lists the components in the testbench.
Table 6: Testbench Components and Description
Component
Description
Device under test (DUT)
The design example.
Avalon driver
Uses Avalon-ST master bus functional models (BFMs) to form transmit and
receive paths. The driver also uses the master Avalon-MM BFM to access
the Avalon-MM interfaces of the design example components.
Packet monitors
Monitor transmit and receive datapaths, and display the frames in the
simulator console.
Testbench Files
The following table lists the location of the testbench files.
Table 7: Testbench files location
Design Examples
Design example without IEEE
1588v2
Location
<project directory>/LL_Ethernet_10G_A10_phy_lineside/testbench/
<Modelsim or VCS>/testcase<n>
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Testbench Files
Design Examples
Design example with IEEE
1588v2
Location
<project directory>/LL_Ethernet_10G_A10_phy_lineside_1588/
testbench/<Modelsim or VCS>/testcase<n>
The following table describes the files that implement the design example testbench.
Table 8: Testbench Files
File Name
Description
all_modes.mif
Memory initialization file (MIF) used for reconfiguration to
change speed.
avalon_bfm_wrapper.sv
A wrapper for the Avalon BFMs that the avalon_driver.sv file
uses.
avalon_driver.sv
A SystemVerilog HDL driver that uses the BFMs to form the
transmit and receive path, and access the Avalon-MM
interface.
avalon_if_params_pkg.sv
A SystemVerilog HDL testbench that contains parameters to
configure the BFMs. Because the configuration is specific to
the DUT, you must not change the contents of this file.
avalon_st_eth_packet_monitor.sv
A SystemVerilog HDL testbench that monitors the Avalon-ST
transmit and receive interfaces.
default_test_params_pkg.sv
A SystemVerilog HDL package that contains the default
parameter settings of the testbench.
eth_mac_frame.sv
A SystemVerilog HDL class that defines the Ethernet frames.
The avalon_driver.sv file uses this class.
eth_register_map_params_pkg.sv
A SystemVerilog HDL package that maps addresses to the
Avalon-MM control registers.
ptp_timestamp.sv
A SystemVerilog HDL class that defines the timestamp in the
testbench.
tb_run.tcl
A Tcl script that starts a simulation session in the ModelSim
simulation software.
tb_testcase.sv
A SystemVerilog HDL testbench file that controls the flow of
the testbench.
tb_top_n.sv
The top-level testbench file. This file includes the customized
1G/10GbE MAC, which consists of the device under test
(DUT), a client packet generator, and a client packet monitor
along with other logic blocks.
wave.do
A signal tracing macro script that the ModelSim simulation
software uses to display testbench signals.
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Simulating Testbench
9
Simulating Testbench
The simulation script uses QUARTUS_ROOTDIR environment variable to access Altera simulation
model libraries. You have to set the QUARTUS_ROOTDIR to point to the Quartus II installation path
after installation. If this environment variable is missing, then you must set the variable manually.
Using ModelSim Simulator
To use the ModelSim simulator to simulate the testbench designs, follow these steps:
1. Change the directory.
• For design example without IEEE 1588v2, change directory to <project directory>/LL_Ethernet_10G_
A10_phy_lineside/testbench/Modelsim/testcase<n>
• For design example with IEEE 1588v2, change directory to <project directory>/LL_Ethernet_10G_A10_
phy_lineside_1588/testbench/Modelsim/testcase<n>.
2. Launch Modelsim, and run do tb_run.tcl to set up the required libraries, to compile the generated IP
functional simulation model, and to exercise the simulation model with the provided testbench.
Using VCS Simulator
To use the VCS simulator to simulate the testbench designs, follow these steps:
1. Change the directory.
• For design example without IEEE 1588v2, change the directory to: <project directory>/LL_Ethernet_
10G_A10_phy_lineside/testbench/VCS/testcase<n>.
• For design example with IEEE 1588v2, change the directory to: <project directory>/LL_Ethernet_10G_
A10_phy_lineside_1588/testbench/VCS/testcase<n>.
2. Run ./run.sh to set up the required libraries, to compile the generated IP functional simulation model,
and to exercise the simulation model with the provided testbench.
Test Case
The test cases are included to demonstrate how to change the channel speed to 10G/1G/100M/10M and
MAC & PHY configuration.
This test case uses the following configuration:
• 2 channels
• Circular loopback
Test Scenario for Design Example without IEEE 1588v2
To perform test case, follow these steps:
1. Set the start up with channel configured to 10G mode.
2. Perform basic MAC configuration, PHY speed configuration and FIFO configuration for all 2
channels.
3. Wait for the design example to assert the channel_ready signals for all 2 channels.
4. Send the following packets:
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Test Scenario for Design Example without IEEE 1588v2
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• Normal data frame, 64Bytes
• SVLAN data frame, broadcast, 64Bytes
• VLAN data frame, unicast, 500Bytes
5. Repeat Step 2 to Step 4 for 1G, 100M and 10M speed mode.
6. When the simulation ends, refer to the transcript window for channel 0 MAC TX and RX statistic
counter results.
Figure 4: Channel 0 MAC TX Statistic Counter
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Test Scenario for Design Example without IEEE 1588v2
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Figure 5: Channel 0 MAC RX Statistic Counter
7. If channel 0 Avalon_st RX interface successfully receives all 12 packets, the transcript displays
PASSED.
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Test Scenario for Design Example with IEEE 1588v2
Test Scenario for Design Example with IEEE 1588v2
To perform test case, follow these steps:
1. Set the start up with channel configured to 10G mode.
2. Perform basic MAC configuration, PHY speed configuration, 1588 component configuration and PTP
clock mode configuration for all 2 channels.
3. Wait for the design example to assert the channel_ready signals for all 2 channels.
4. Send the following packets:
• Non-PTP
• No VLAN, PTP over Ethernet, PTP Sync Message, 1-step PTP
• VLAN, PTPover UDP/IPv4, PTP Sync Message,1-step PTP
• Stacked VLAN, PTP over UDP/IPv6, PTP Sync Message, 2-step PTP
• No VLAN, PTP over Ethernet, PTP Delay Request Message, 1-step PTP
• VLAN, PTPover UDP/IPv4, PTP Delay Request Message, 2-step PTP
• Stacked VLAN, PTP over UDP/IPv6, PTP Delay Request Message, 1-step PTP
5. Repeat Step 2 to Step 4 for 1G, 100M and 10M speed mode.
6. When the simulation ends, refer to the transcript window for channel 0 MAC TX and RX statistic
counter results.
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Test Scenario for Design Example with IEEE 1588v2
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Figure 6: Channel 0 MAC TX Statistic Counter
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Clocking Scheme
Figure 7: Channel 0 MAC RX Statistic Counter
7. If channel 0 Avalon_st RX interface successfully receives all 28 packets, the transcript displays
PASSED.
Clocking Scheme
There are n instances of PLL 1 and it is merged into 1 if SHARED_REFCLK_EN = 1.
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Clocking Diagram
Clocking Diagram
The following diagrams show the clocking scheme for the design example without IEEE 1588v2 and
design example with IEEE 1588v2 respectively.
Figure 8: Clocking Scheme for the Design Example without IEEE 1588v2
altera_eth_multi_channel
altera_eth_channel
altera_eth_channel
TX / RX FIFO
Adapters
address_decoder_channel
tx/rx_312_5_clk
S
LL MAC
csr_clk
tx/rx_156_25_clk
Adapters
gmii_tx_clk
gmii_rx_clk
125 MHz
address_decoder_multi_channel 0x02_0000
tx_serial_clk_10g
tx_serial_clk_1g
S
Arria 10 PHY
mgmt_clk
xgmii_tx_clk
xgmii_rx_clk
rx_pma_clkout
0x03_0000
Avalon-MM
tx_clkout
N Channels
Transceiver Reset Controller
156.25 MHz
n Channel (1)
312.5 MHz
PLL
5156.25 MHz
Legend
156.25 MHz
312.5 MHz
125 MHz
125 MHz
xgmii_clk[n]
pll_ref_clk_10g[n]
644.53125 MHz
Note:
1. n = (SHARED_REFCLK_EN == 1)? 1: NUM_CHANNELS
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625 MHz
(NUM CHANNEL - 1) / 10 + 1 Arria 10
ATX PLL
pll_ref_clk_10g(0)
S MDIO
Arria 10 (NUM CHANNEL - 1) / 5 + 1
fPLL
pll_ref_clk_1g(0)
pll_ref_clk_1g[n]
125 MHz
rx_recovered_clk[N]
dc_fifo_tx_clk
156.25 MHz
mm_clk
125 MHz
dc_fifo_rx_clk
156.25 MHz
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Sync-E Support
Figure 9: Clocking Scheme for the Design Example with IEEE 1588v2
altera_eth_multi_channel_1588
altera_eth_channel_1588
altera_eth_channel_1588
PTP Packet Classifier
Adapters
address_decoder_channel
tx/rx_312_5_clk
S
LL MAC
csr_clk
tx/rx_156_25_clk
Adapters
gmii_rx_clk
125 MHz
address_decoder_multi_channel 0x02_0000
tx_serial_clk_10g
tx_serial_clk_1g
1G Pulse
Per Second
period_clk
S 10G Local
TOD
clk
period_clk
S 1G Local
TOD
clk
Slave Master
10G TOD
Sync
Master Slave
1G TOD
Sync
tx_clkout
S
Arria 10 PHY
mgmt_clk
xgmii_tx_clk
xgmii_rx_clk
rx_pma_clkout
0x03_0000
Avalon-MM
10G Pulse
Per Second
gmii_tx_clk
N Channels
Transceiver Reset Controller
156.25 MHz
0x01_0000
(Master TOD)
(1) n Channel
312.5 MHz
PLL 1
5156.25 MHz
625 MHz
(NUM CHANNEL - 1) / 10 + 1 Arria 10
ATX PLL
pll_ref_clk_10g(0)
Legend
156.25 MHz
312.5 MHz
125 MHz
125 MHz
xgmii_clk[n]
pll_ref_clk_10g[n]
644.53125 MHz
S
pll_ref_clk_1g[n]
125 MHz
Arria 10 (NUM CHANNEL - 1) / 5 + 1
fPLL
period_clk
S Master
TOD
clk
(3)
(2)
MDIO
PLL 2
Master Pulse
Per Second
pll_ref_clk_1g(0)
rx_recovered_clk[N]
mm_clk
125 MHz
Notes:
1. n = (SHARED_REFCLK_EN == 1) ? 1 : NUM_CHANNELS.
2. Sampling clock for 10G TOD sync is 31.746031MHz.
3. Sampling clock for 1G TOD sync is 126.984125 MHz.
Sync-E Support
To support Sync-E implementation, separate refclk signals to RX PLL and TX PLL and expose them at
design example. The following diagrams show the signals per channel for design example without IEEE
1588v2 and design example with IEEE 1588v2 respectively.
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Sync-E Support
Figure 10: Signals from PHY to Support Sync-E Implementation for Design Example without IEEE
1588v2
altera_eth_multi_channel
altera_eth_channel
altera_eth_channel
TX / RX FIFO
address_decoder_channel
MAC
rx_recovered_clk
Arria 10 PHY
cdr_ref_clk_10g
cdr_ref_clk_1g
Transceiver Reset Controller
MDIO
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pll_ref_clk_1g[n]
125 MHz
cdr_ref_clk_1g[n]
125 MHz
cdr_ref_clk_10g[n]
644.53125 MHz
Arria 10
fPLL
rx_recovered_clk[N]
pll_ref_clk_10g[n]
644.53125 MHz
Arria 10
ATX PLL
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Enable Ref Clock Sharing
Figure 11: Signals from PHY to Support Sync-E Implementation for Design Example with IEEE 1588v2
altera_eth_multi_channel_1588
altera_eth_channel_1588
altera_eth_channel_1588
PTP Packet Classifier
address_decoder_channel
Pulse Per
Second
LL MAC
Local
TOD
rx_recovered_clk
TOD
Sync
Arria 10 PHY
cdr_ref_clk_10g
cdr_ref_clk_1g
MDIO
Transceiver Reset Controller
Arria 10
ATX PLL
Arria 10
fPLL
Master
TOD
pll_ref_clk_1g[n]
125 MHz
cdr_ref_clk_1g[n]
125 MHz
cdr_ref_clk_10g[n]
644.53125 MHz
rx_recovered_clk[N]
pll_ref_clk_10g[n]
644.53125 MHz
Master
Pulse Per
Second
Enable Ref Clock Sharing
When user set the parameter SHARED_REFCLK_EN to 1, this will enable the ref clock sharing and only 1 set
of pll_ref_clk_10g, pll_ref_clk_1g, cdr_ref_clk_10g and cdr_ref_clk_1g is needed. These ref
clock signals will be used across all channels. There will be N number of rx_recovered_clk regardless of
ref clock sharing setting, where N=number of channels.
Disable Ref Clock Sharing
When you set the parameter SHARED_REFCLK_EN to 0, this will disable the ref clock sharing and N set of
pll_ref_clk_10g, pll_ref_clk_1g, cdr_ref_clk_10g and cdr_ref_clk_1g are needed, where
N=number of channels. These ref clock signals will be connected to their individual channel respectively.
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Reset Scheme
19
Reset Scheme
At the design example level, there are one master_reset_n and <N> channel_reset_n signals. All the
signals are asynchronous and active-low signal. The signals are synced to different clock domain
internally. When the master_reset_n is asserted, the signal will bring down all <N> Ethernet channels
and all modules in the design example.
The channel_reset_n[0..N] only reset all the components in the individual channel.
Master reset is needed when the design example is powered up.
Design Example without IEEE 1588v2
Multi Channel Level Reset Scheme
The following diagram shows the reset scheme at altera_eth_multi_channel level. master_reset_n is
used to reset the whole design example, while channel_reset_n is used to reset the individual Ethernet
channel.
Figure 12: Reset scheme at altera_eth_multi_channel
master_reset_n
eth_multi_channel.v
mm_reset[N:0]
channel_reset_n[N:0]
datapath_reset[N:0]
Channel 0
eth_channel
PLL 1
644 MHz
Channel N
eth_channel
Arria 10
ATX PLL
Arria 10
fPLL
Note:
1. N is the number of channels.
Channel Level Reset Scheme
The following diagram shows the reset scheme per channel. mm_reset is used to reset the registers in
MAC, PHY, MDIO and address_decoder block while datapath_reset is used to reset all digital blocks
including PHY reset controller. However, mm_reset and datapath_reset are tied together at multi
channel level in the design example, therefore they can't be triggered separately.
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Design Example with IEEE 1588v2
Figure 13: Reset scheme at altera_eth_channel
eth_channel_1588.v
datapath_reset
MAC
OR
~phy_rx_block_lock
& ~phy_led_link
PHY
PHY Reset
Controller
mm_reset
MDIO
Address
Decoder
Notes:
1. The mm_reset signal resets all Avalon-MM control blocks.
2. The datapath_reset signal resets all digital blocks, including the PHY reset controller.
Design Example with IEEE 1588v2
Multi Channel Level Reset Scheme
The following diagram shows the reset scheme at altera_eth_multi_channel_1588 level.
master_reset_n is used to reset the whole design example, while channel_reset_n is used to reset the
individual ethernet channel.
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Channel Level Reset Scheme
21
Figure 14: Reset Scheme at altera_eth_multi_channel_1588
master_reset_n
eth_multi_channel_1588.v
mm_reset[N:0]
channel_reset_n[N:0]
datapath_reset[N:0]
Channel 0
eth_channel
Channel N
eth_channel
PLL 1
644 MHz
PLL 2
125 MHz
Master
PPS
Master
TOD
Arria 10
ATX PLL
Arria 10
fPLL
Note:
1. N is the number of channels.
Channel Level Reset Scheme
The following diagram shows the reset scheme per channel. mm_reset is used to reset the registers in
MAC, PHY, TOD, MDIO and address decoder block, while datapath_reset is used to reset MAC, PHY
reset controller and TOD. However, mm_reset and datapath_reset are tied together at multi-channel
level in the design example, therefore it is not possible to trigger them separately.
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Interface Signals
Figure 15: Reset scheme at altera_eth_channel_1588
eth_channel_1588.v
mm_reset
MAC
OR
PHY Reset
Controller
PHY
~phy_rx_block_lock
& ~phy_led_link
datapath_reset
TOD
10G
PPS
10G
TOD
1G
PPS
1G
MDIO
TOD SYN
96B_10G
TOD SYN
64B_10G
TOD SYN
96B_1G
TOD SYN
64B_1G
Address
Decoder
Notes:
1. The mm_reset signal resets all Avalon-MM control blocks.
2. The datapath_reset signal resets all digital blocks, including the PHY reset controller.
Interface Signals
This section describes the interface signals at design example level.
The NUM_UNSHARED_CHANNELS are determined by the equation below:
NUM_UNSHARED_CHANNELS = (SHARED_REFCLK_EN == 1) ? 1: NUM_CHANNELS
NUM_CHANNELS and SHARED_REFCLK_EN are parameters set by user.
Clock and Reset Interface Signals
The following table lists the clock and reset interface signals. These interface signals are applicable to both
design examples.
Table 9: Clock and Reset Interface Signals
Signal
Direction
Width
mm_clk
input
1
pll_ref_clk_1g[]
input
[NUM_UNSHARED_CHANNELS]
Altera Corporation
Description
Configuration clock for AvalonMM interface. Frequency is 125
MHz.
Reference clock for the TX PLL in
1G mode. Frequency is 125 MHz.
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Avalon-MM Interface Signals
Signal
Direction
Width
pll_ref_clk_10g[]
input
[NUM_UNSHARED_CHANNELS]
cdr_ref_clk_1g[]
input
[NUM_UNSHARED_CHANNELS]
cdr_ref_clk_10g[]
input
[NUM_UNSHARED_CHANNELS]
channel_reset_n
input
[NUM_CHANNELS]
master_reset_n
input
1
xgmii_clk
output
[NUM_UNSHARED_CHANNELS]
rx_recovered_clk
output
[NUM_CHANNELS]
23
Description
Reference clock for the TX PLL in
10G mode. Frequency is 644.53125
MHz.
Reference clock for the RX PLL in
1G mode. Frequency is 125 MHz.
Reference clock for the RX PLL in
10G mode. Frequency is 644.53125
MHz.
To reset individual Ethernet
channel. This does not impact the
components running at multi_
channel level, e.g. master TOD,
master PPS and fPLLs. Asynchro‐
nous and active low signal.
To reset the whole design example.
Asynchronous and active low
signal.
Clock used for single data rate
(SDR) XGMII TX & RX interface
in between MAC and PHY. This
clock is also used for Avalon-ST
interface. Frequency is
156.25MHz.
This is the RX clock, which is
recovered from the received data.
Avalon-MM Interface Signals
The following table lists the Avalon-MM interface signals. These interface signals are applicable to both
design examples.
Table 10: Avalon MM Interface Signals
Signal
Directio
n
Width
Description
write
input
1
Assert this signal to request a write.
read
input
1
Assert this signal to request a read.
address[]
input
20
Use this bus to specify the register address you want to read from or
write to.
writedata[]
input
32
Carries the data to be written to the specified register.
readdata[]
output
32
Carries the data read from the specified register.
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Avalon-ST Interface Signals
Signal
Directio
n
Width
output
1
waitrequest
Description
When asserted, this signal indicates that the IP core is busy and not
ready to accept any read or write requests.
Avalon-ST Interface Signals
The following table lists the Avalon-ST interface signals. These interface signals are applicable to both
design examples.
Table 11: Avalon-ST Interface Signals
Signal
avalon_st_tx_
startofpacket[]
avalon_st_tx_
endofpacket[]
avalon_st_tx_
valid[]
avalon_st_tx_
ready[]
avalon_st_tx_
error[][]
avalon_st_tx_data[]
[]
avalon_st_tx_
empty[]
Direction
Width
input
[NUM_CHANNELS]
input
[NUM_CHANNELS]
input
[NUM_CHANNELS]
output
[NUM_CHANNELS]
input
[NUM_CHANNELS][64]
input
[NUM_CHANNELS][3]
input
[NUM_CHANNELS]
Description
Assert this signal to mark the
beginning of the transmit data on the
Avalon-ST interface.
Assert this signal to mark the end of
the transmit data on the Avalon-ST
interface.
Assert this signal to indicate that
avalon_st_tx_data[] and other
signals on this interface are valid.
When asserted, this signal indicates
that the MAC IP core is ready to
accept data.
Assert this signal to indicate the
current transmit packet contains
errors.
Carries the transmit data from the
client.
Use this signal to specify the number
of bytes that are empty (not used)
during cycles that contain the end of
a packet.
0x0=All bytes are valid.
0x1=The last byte is invalid.
0x2=The last two bytes are invalid.
0x3=The last three bytes are invalid.
avalon_st_rx_
startofpacket[]
Altera Corporation
output
[NUM_CHANNELS]
When asserted, this signal marks the
beginning of the receive data on the
Avalon-ST interface.
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Avalon-ST Interface Signals
Signal
avalon_st_rx_
endofpacket[]
avalon_st_rx_
valid[]
avalon_st_rx_
ready[]
avalon_st_rx_
error[][]
Direction
Width
output
[NUM_CHANNELS]
output
[NUM_CHANNELS]
input
[NUM_CHANNELS]
output
[NUM_CHANNELS][64]
25
Description
When asserted, this signal marks the
end of the receive data on the AvalonST interface.
When asserted, this signal indicates
that avalon_st_rx_data[]and other
signals on this interface are valid.
Assert this signal when the client is
ready to accept data.
When set to 1, the respective bits
indicate an error type:
• Bit 0—PHY error. For 10 Gbps,
the data on xgmii_rx_data
contains a control error character
(FE). For 10 Mbps,100 Mbps,1
Gbps, gmii_rx_err or mii_rx_
err is asserted.
• Bit 1—CRC error. The computed
CRC value differs from the
received CRC.
• Bit 2—Undersized frame. The
receive frame length is less than 64
bytes.
• Bit 3—Oversized frame. The
receive frame length is more than
MAX_FRAME_SIZE.
• Bit 4—Payload length error. The
actual frame payload length is
different from the value in the
length/type field.
• Bit 5—Overflow error. The receive
FIFO buffer is full while it is still
receiving data from the MAC IP
core.
avalon_st_rx_data[]
[]
avalon_st_rx_
empty[][]
avalon_st_tx_
status_valid[]
output
[NUM_CHANNELS][3]
output
[NUM_CHANNELS][6]
output
[NUM_CHANNELS]
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Carries the receive data to the client.
Contains the number of bytes that are
empty (not used) during cycles that
contain the end of a packet.
When asserted, this signal qualifies
avalon_st_txstatus_data[] and
avalon_st_txstatus_error[].
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Avalon-ST Interface Signals
Signal
avalon_st_tx_
status_data[][]
Direction
Width
output
[NUM_CHANNELS][40]
Description
Contains information about the
transmit frame.
• Bits 0 to 15: Payload length.
• Bits 16 to 31: Packet length.
• Bit 32: When set to 1, indicates a
stacked VLAN frame.
• Bit 33: When set to 1, indicates a
VLAN frame.
• Bit 34: When set to 1, indicates a
control frame.
• Bit 35: When set to 1, indicates a
pause frame.
• Bit 36: When set to 1, indicates a
broadcast frame.
• Bit 37: When set to 1, indicates a
multicast frame.
• Bit 38: When set to 1, indicates a
unicast frame.
• Bit 39: When set to 1, indicates a
PFC frame.
avalon_st_tx_
status_error[][]
output
[NUM_CHANNELS][7]
When set to 1, the respective bit
indicates the following error type in
the receive frame.
•
•
•
•
•
•
•
Bit 0: Undersized frame.
Bit 1: Oversized frame.
Bit 2: Payload length error.
Bit 3: Unused.
Bit 4: Underflow.
Bit 5: Client error.
Bit 6: Unused.
The error status is invalid when an
overflow occurs.
avalon_st_rxstatus_
valid[]
output
[NUM_CHANNELS]
When asserted, this signal qualifies
avalon_st_txstatus_data[] and
avalon_st_txstatus_error[]. The
MAC IP core asserts this signal in the
same clock cycle avalon_st_rx_
endofpacket is asserted.
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Avalon-ST Interface Signals
Signal
avalon_st_rxstatus_
data[][]
Direction
Width
output
[NUM_CHANNELS][40]
27
Description
Contains information about the
transmit frame.
• Bits 0 to 15: Payload length.
• Bits 16 to 31: Packet length.
• Bit 32: When set to 1, indicates a
stacked VLAN frame.
• Bit 33: When set to 1, indicates a
VLAN frame.
• Bit 34: When set to 1, indicates a
control frame.
• Bit 35: When set to 1, indicates a
pause frame.
• Bit 36: When set to 1, indicates a
broadcast frame.
• Bit 37: When set to 1, indicates a
multicast frame.
• Bit 38: When set to 1, indicates a
unicast frame.
• Bit 39: When set to 1, indicates a
PFC frame.
avalon_st_rxstatus_
error[][]
output
[NUM_CHANNELS][7]
When set to 1, the respective bit
indicates the following error type in
the receive frame.
•
•
•
•
•
•
•
Bit 0: Undersized frame.
Bit 1: Oversized frame.
Bit 2: Payload length error.
Bit 3: Unused.
Bit 4: Underflow.
Bit 5: Client error.
Bit 6: Unused.
The error status is invalid when an
overflow occurs.
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PHY Interface Signals
Signal
Direction
Width
input
[NUM_CHANNELS][2]
avalon_st_pause_
data[][]
Description
Set this signal to the following values
to trigger the corresponding actions.
• 0x0: Stops pause frame generation.
• 0x1: Generates an XON pause
frame.
• 0x2: Generates an XOFF pause
frame. The MAC IP core sets the
pause quanta field in the pause
frame to the value in the tx_
pauseframe_quanta register.
• 0x3: Reserved.
Note: This signal only takes
effect if tx_pauseframe_
enable[2:1] is 00
(default)
PHY Interface Signals
The following table lists the PHY interface signals. These interface signals are applicable to both design
examples.
Table 12: PHY Interface Signals
Signal
Direction
Width
Description
rx_serial_data[]
input
[NUM_CHANNELS]
RX serial input data
tx_serial_data[]
output
[NUM_CHANNELS]
TX serial output data
ethernet_1g_an[]
output
[NUM_CHANNELS]
ethernet_1g_char_err[]
output
[NUM_CHANNELS]
ethernet_1g_disp_err[]
output
[NUM_CHANNELS]
channel_ready[]
output
[NUM_CHANNELS]
Clause 37 Auto-Negotiation status. The
PCS function asserts this signal when
auto-negotiation completes.
10-bit character error
Disparity error signal indicating a 10-bit
running disparity error.
This signal is asserted when the channel
is ready for data transmission.
MDIO Interface Signals
The following table lists the MDIO interface signals. These interface signals are applicable to both design
examples.
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IEEE 1588v2 Timestamp Interface Signals
29
Table 13: MDIO Interface Signals
Signal
Direction
Width
Description
mdio_mdc[]
output
[NUM_CHANNELS]
Management Data clock
mdio_in[]
input
[NUM_CHANNELS]
Input to MDIO interface
mdio_out[]
output
[NUM_CHANNELS]
Output from MDIO interface
mdio_oen[]
output
[NUM_CHANNELS]
Output enable signal
IEEE 1588v2 Timestamp Interface Signals
The following table lists the IEEE 1588v2 timestamp interface signals. These interface signals are only
applicable to design examples with IEEE 1588v2.
Table 14: IEEE 1588v2 Timestamp Interface Signals
Signal
tx_egress_timestamp_96b_
valid[]
Direction
Width
output
[NUM_CHANNELS]
Description
When asserted, this signal
qualifies the timestamp on tx_
egress_timestamp_96b_data[]
for the transmit frame whose
fingerprint is specified by tx_
egress_timestamp_96b_
fingerprint[].
tx_egress_timestamp_96b_
data[][]
output
[NUM_CHANNELS][96]
Carries the 96-bit egress
timestamp in the following
format:
• Bits 48 to 95: 48-bit seconds
field
• Bits 16 to 47: 32-bit nanosec‐
onds field
• Bits 0 to 15: 16-bit fractional
nanoseconds field
tx_egress_timestamp_96b_
fingerprint[][]
output
[NUM_CHANNELS]
[TSTAMP_FP_WIDTH]
The fingerprint of the transmit
frame, which is received on tx_
egress_timestamp_request_
data[]. This fingerprint
specifies the transmit frame the
egress timestamp on tx_egress_
timestamp_96b_data[] is for.
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IEEE 1588v2 Timestamp Interface Signals
Signal
tx_egress_timestamp_64b_
valid[]
Direction
Width
output
[NUM_CHANNELS]
Description
When asserted, this signal
qualifies the timestamp on tx_
egress_timestamp_64b_data[]
for the transmit frame whose
fingerprint is specified by tx_
egress_timestamp_64b_
fingerprint[].
tx_egress_timestamp_64b_
data[][]
output
[NUM_CHANNELS][64]
Carries the 64-bit egress
timestamp in the following
format:
• Bits 16 to 63: 48-bit nanosec‐
onds field
• Bits 0 to 15: 16-bit fractional
nanoseconds field
tx_egress_timestamp_64b_
fingerprint[][]
output
[NUM_CHANNELS]
[TSTAMP_FP_WIDTH]
The fingerprint of the transmit
frame, which is received on tx_
egress_timestamp_request_
data[]. This fingerprint
specifies the transmit frame the
egress timestamp on tx_egress_
timestamp_64b_data[] is for.
rx_ingress_timestamp_96b_
valid[]
output
[NUM_CHANNELS]
When asserted, this signal
qualifies the timestamp on rx_
ingress_timestamp_96b_
data[]. The MAC IP core
asserts this signal in the same
clock cycle it asserts avalon_st_
rx_startofpacket.
rx_ingress_timestamp_96b_
data[][]
output
[NUM_CHANNELS][96]
Carries the 96-bit ingress
timestamp in the following
format:
• Bits 48 to 95: 48-bit seconds
field
• Bits 16 to 47: 32-bit nanosec‐
onds field
• Bits 0 to 15: 16-bit fractional
nanoseconds field
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Packet Classifier Interface Signals
Signal
rx_ingress_timestamp_64b_
valid[]
Direction
Width
output
[NUM_CHANNELS]
31
Description
When asserted, this signal
qualifies the timestamp on rx_
ingress_timestamp_64b_
data[]. The MAC IP core
asserts this signal in the same
clock cycle it asserts avalon_st_
rx_startofpacket.
rx_ingress_timestamp_64b_
data[][]
output
[NUM_CHANNELS][64]
Carries the 64-bit ingress
timestamp in the following
format:
• Bits 16 to 63: 48-bit nanosec‐
onds field
• Bits 0 to 15: 16-bit fractional
nanoseconds field
Packet Classifier Interface Signals
The following table lists the packet classifier interface signals. These interface signals are only applicable to
design examples with IEEE 1588v2.
Table 15: Packet Classifier Interface Signals
Signal
tx_egress_timestamp_request_
in_valid[]
tx_egress_timestamp_request_
in_fingerprint[][]
clock_operation_mode_mode[][]
Directio
n
Width
input
input
[NUM_CHANNELS]
[NUM_CHANNELS][TSTAMP_
FP_WIDTH]
input
[NUM_CHANNELS][2]
Description
Assert this signal when
timestamp is required for
the particular frame. This
signal must be aligned to
the start of an incoming
packet.
A width-configurable
fingerprint that correlates
timestamps for incoming
packets.
Determines the clock
mode.
• 00: Ordinary clock
• 01: Boundary clock
• 10: End to end
transparent clock
• 11: Peer to peer
transparent clock
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Packet Classifier Interface Signals
Signal
pkt_with_crc_mode[]
Directio
n
input
Width
[NUM_CHANNELS]
Description
Indicates whether or not a
packet contains CRC.
• 0: Packet contains
CRC
• 1: Packet does not
contain CRC
tx_ingress_timestamp_valid[]
input
[NUM_CHANNELS]
Indicates the update for
residence time.
• 0: Prevents update for
residence time
• 1: Allows update for
residence time based
on decoded results
When this signal is
deasserted, tx_etstamp_
ins_ctrl_out_
residence_ti me_
update also gets
deasserted.
tx_ingress_timestamp_96b_
data[][]
tx_ingress_timestamp_64b_
data[][]
tx_ingress_timestamp_format[]
Altera Corporation
input
[NUM_CHANNELS][96]
input
[NUM_CHANNELS][64]
input
[NUM_CHANNELS]
96-bit format of ingress
timestamp that holds data
so that the output can
align with the start of an
incoming packet.
64-bit format of ingress
timestamp that holds data
so that the output can
align with the start of an
incoming packet.
Format of the timestamp
to be used for calculating
residence time. This
signal must be aligned to
the start of an incoming
packet. A value of 0
indicates 96 bit timestamp
format while 1 indicates
64 bit timestamp format.
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ToD Interface Signals
33
ToD Interface Signals
The following table lists the ToD interface signals. These interface signals are only applicable to design
examples with IEEE 1588v2.
Table 16: ToD Interface Signals
Signal
master_pulse_per_
second
start_tod_sync[]
pulse_per_second_
10g[]
pulse_per_second_
1g[]
Directio
n
Width
output
1
input
[NUM_CHANNELS]
Description
Pulse per second output from Master PPS module.
The pulse per second output asserts for 10ms.
Start TOD synchronization process. As long as this
signal is asserted high, the synchronization process
will continue and time of day from master TOD will
be repeatedly synchronized to local TOD.
output [NUM_CHANNELS] Pulse per second output from 10G PPS module in
channel-n. The pulse per second output asserts for
10ms.
output [NUM_CHANNELS] Pulse per second output from 1G PPS module in
channel-n. The pulse per second output asserts for
10ms.
Register Map
MSA0 is a 32-bit memory space address that provides access to all the client logic and scalable 1G/10G
design example configuration registers. All registers in this space are 32-bit registers. Access smaller than
32 bits are not supported.
The following table shows the address offset for the design example and client logic at the design example
level.
Table 17: Design Example Block Register Map
Byte Offset
Block
0x00_0000 - 0x00_EFFF
Client Logic
0x00_F000 - 0x00_FFFF
Altera Logic
0x01_0000
Master TOD
0x02_0000
Port 0
0x03_0000
Port 1
0x04_0000
Port 2
0x05_0000
Port 3
0x06_0000
Port 4
0x07_0000
Port 5
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Master TOD
Byte Offset
Block
0x08_0000
Port 6
0x09_0000
Port 7
0x0A_0000
Port 8
0x0B_0000
Port 9
0x0C_0000
Port 10
0x0D_0000
Port 11
0x0E_0000 onwards
Client Logic
The following table shows the address offset for the design example and client logic for each port.
Table 18: Port Sub-block Register Map
Byte Offset
Sub-block
0x0000 - 0x3FFF
Altera Logic
0x4000
PHY
0x7800
10G TOD
0x7900
1G TOD
0x8000
1G/10G MAC
Master TOD
Master TOD registers are applicable only to design examples with IEEE 1588v2.
The base address of the Master ToD registers are defined as follows:
• Master TOD Base Address = MSA0 + 0x01_0000
Table 19: Register Description and Address Offset for 1588 TOD Clock
Byte Offset
R/W
Name
0x0000
RW
SecondsH
• Bits 0 to 15: High-order 16-bit second field
• Bits 16 to 31: Not used.
0x0
0x0004
RW
SecondsL
Bits 0 to 32: Low-order 32-bit second field.
0x0
0x0008
RW
NanoSec
Bits 0 to 32: 32-bit nanosecond field.
0x0
0x0010
RW
Period
Altera Corporation
Description
• Bits 0 to 15: Period in fractional nanosecond
• Bits 16 to 19: Period in nanosecond
• Bits 20 to 31: Not used.
HW Reset
N
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1G TOD
Byte Offset
R/W
Name
0x0014
RW
AdjustPeriod
Description
The period for the offset adjustment.
HW Reset
0x0
• Bits 0 to 15: Period in fractional nanosecond
• Bits 16 to 19: Period in nanosecond
• Bits 20 to 31: Not used.
0x0018
RW
AdjustCount
• Bits 0 to 19: The number of AdjustPeriod
clock cycles used during offset adjustment
• Bits 20 to 31: Not used.
0x0
0x001C
RW
DriftAdjust
The drift of ToD adjusted periodically by adding
a correction value as configured in this register
space.
0x0
• Bits 0 to 15: Adjustment value in fractional
nanosecond (DRIFT_ADJUST_FNS). This
value is added into the current ToD during
the adjustment.
• Bits 16 to 19: Adjustment value in
nanosecond (DRIFT_ADJUST_NS). This
value is added into the current ToD during
the adjustment.
• Bits 20 to 32: Not used.
0x0020
RW
DriftAdjustRate The count of clock cycles for each ToD’s drift
adjustment to take effect.
0x0
• Bits 0 to 15: The number of clock cycles
(ADJUST_RATE). The ToD adjustment
happens once after every period in number of
clock cycles as indicated by this register space.
• Bits 20 to 32: Not used.
1G TOD
1G TOD registers are only applicable to design examples with IEEE 1588v2.
The base address of the 1G TOD registers are defined as follows:
Channel
1G TOD Register Base Address
0
MSA0 + 0x02_7900
1
MSA0 + 0x03_7900
2
MSA0 + 0x04_7900
3
MSA0 + 0x05_7900
4
MSA0 + 0x06_7900
5
MSA0 + 0x07_7900
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1G TOD
Channel
1G TOD Register Base Address
6
MSA0 + 0x08_7900
7
MSA0 + 0x09_7900
8
MSA0 + 0x0A_7900
9
MSA0 + 0x0B_7900
10
MSA0 + 0x0C_7900
11
MSA0 + 0x0D_7900
Table 20: Register Description and Address Offset for 1588 TOD Clock
Byte Offset
R/W
Name
Description
0x0000
RW
SecondsH
• Bits 0 to 15: High-order 16-bit second field
• Bits 16 to 31: Not used.
0x0
0x0004
RW
SecondsL
Bits 0 to 32: Low-order 32-bit second field.
0x0
0x0008
RW
NanoSec
Bits 0 to 32: 32-bit nanosecond field.
0x0
0x0010
RW
Period
0x0014
RW
AdjustPeriod
• Bits 0 to 15: Period in fractional nanosecond
• Bits 16 to 19: Period in nanosecond
• Bits 20 to 31: Not used.
The period for the offset adjustment.
HW Reset
N
0x0
• Bits 0 to 15: Period in fractional nanosecond
• Bits 16 to 19: Period in nanosecond
• Bits 20 to 31: Not used.
0x0018
RW
AdjustCount
• Bits 0 to 19: The number of AdjustPeriod
clock cycles used during offset adjustment
• Bits 20 to 31: Not used.
0x0
0x001C
RW
DriftAdjust
The drift of ToD adjusted periodically by adding
a correction value as configured in this register
space.
0x0
• Bits 0 to 15: Adjustment value in fractional
nanosecond (DRIFT_ADJUST_FNS). This
value is added into the current ToD during
the adjustment.
• Bits 16 to 19: Adjustment value in
nanosecond (DRIFT_ADJUST_NS). This
value is added into the current ToD during
the adjustment.
• Bits 20 to 32: Not used.
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10G TOD
Byte Offset
R/W
0x0020
RW
Name
Description
DriftAdjustRate The count of clock cycles for each ToD’s drift
adjustment to take effect.
HW Reset
0x0
• Bits 0 to 15: The number of clock cycles
(ADJUST_RATE). The ToD adjustment
happens once after every period in number of
clock cycles as indicated by this register space.
• Bits 20 to 32: Not used.
10G TOD
10G TOD registers are only applicable to design examples with IEEE 1588v2.
The base address of the 10G TOD registers are defined as follows:
Channel
10G TOD Register Base Address
0
MSA0 + 0x02_7800
1
MSA0 + 0x03_7800
2
MSA0 + 0x04_7800
3
MSA0 + 0x05_7800
4
MSA0 + 0x06_7800
5
MSA0 + 0x07_7800
6
MSA0 + 0x08_7800
7
MSA0 + 0x09_7800
8
MSA0 + 0x0A_7800
9
MSA0 + 0x0B_7800
10
MSA0 + 0x0C_7800
11
MSA0 + 0x0D_7800
Table 21: Register Description and Address Offset for 1588 TOD Clock
Byte Offset
R/W
Name
Description
0x0000
RW
SecondsH
• Bits 0 to 15: High-order 16-bit second field
• Bits 16 to 31: Not used.
0x0
0x0004
RW
SecondsL
Bits 0 to 32: Low-order 32-bit second field.
0x0
0x0008
RW
NanoSec
Bits 0 to 32: 32-bit nanosecond field.
0x0
0x0010
RW
Period
• Bits 0 to 15: Period in fractional nanosecond
• Bits 16 to 19: Period in nanosecond
• Bits 20 to 31: Not used.
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PHY
Byte Offset
R/W
Name
0x0014
RW
AdjustPeriod
Description
The period for the offset adjustment.
HW Reset
0x0
• Bits 0 to 15: Period in fractional nanosecond
• Bits 16 to 19: Period in nanosecond
• Bits 20 to 31: Not used.
0x0018
RW
AdjustCount
• Bits 0 to 19: The number of AdjustPeriod
clock cycles used during offset adjustment
• Bits 20 to 31: Not used.
0x0
0x001C
RW
DriftAdjust
The drift of ToD adjusted periodically by adding
a correction value as configured in this register
space.
0x0
• Bits 0 to 15: Adjustment value in fractional
nanosecond (DRIFT_ADJUST_FNS). This
value is added into the current ToD during
the adjustment.
• Bits 16 to 19: Adjustment value in
nanosecond (DRIFT_ADJUST_NS). This
value is added into the current ToD during
the adjustment.
• Bits 20 to 32: Not used.
0x0020
RW
DriftAdjustRate The count of clock cycles for each ToD’s drift
adjustment to take effect.
0x0
• Bits 0 to 15: The number of clock cycles
(ADJUST_RATE). The ToD adjustment
happens once after every period in number of
clock cycles as indicated by this register space.
• Bits 20 to 32: Not used.
PHY
PHY registers are applicable to both design examples.
The base address of the PHY registers are defined as follows:
Altera Corporation
Channel
PHY Register Base Address
0
MSA0 + 0x02_4000
1
MSA0 + 0x03_4000
2
MSA0 + 0x04_4000
3
MSA0 + 0x05_4000
4
MSA0 + 0x06_4000
5
MSA0 + 0x07_4000
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PHY
Channel
PHY Register Base Address
6
MSA0 + 0x08_4000
7
MSA0 + 0x09_4000
8
MSA0 + 0x0A_4000
9
MSA0 + 0x0B_4000
10
MSA0 + 0x0C_4000
11
MSA0 + 0x0D_4000
39
Note: For the description of each PHY register, refer to the Arria 10 Transceiver PHY IP User Guide.
Note: The address offset in the following tables is in byte, while the register map table in the Arria 10
Transceiver PHY IP User Guide is in word.
Table 22: PMA Registers
Byte Offset
Bit
R/W
1
RW
reset_tx_digital
2
RW
reset_rx_analog
3
RW
reset_rx_digital
0x1184
RW
phy_serial_loopback
0x1190
RW
pma_rx_set_locktodata
0x1194
RW
pma_rx_set_locktoref
0x1198
RO
pma_rx_is_lockedtodata
0x119C
RO
pma_rx_is_lockedtoref
0
RW
tx_invpolarity
1
RW
rx_invpolarity
2
RW
rx_bitreversal_enable
3
RW
rx_bytereversal_enable
4
RW
force_electrical_idle
0
R
rx_syncstatus
1
R
rx_patterndetect
2
R
rx_rlv
3
R
rx_rmfifodatainserted
4
R
rx_rmfifodatadeleted
5
R
rx_disperr
6
R
rx_errdetect
0x1110
0x12A0
0x12A4
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PHY
Table 23: PCS Registers
Byte Offset
Bit
0x1200
0x1204
0x1208
R/W
Name
RW
Indirect_addr
2
RW
RCLR_ERRBLK_CNT
3
RW
RCLR_BER_COUNT
1
RO
HI_BER
2
RO
BLOCK_LOCK
3
RO
TX_FULL
4
RO
RX_FULL
7
RO
Rx_DATA_READY
Table 24: Arria 10 GMII PCS Registers
Byte Offset
Bit
R/W
9
RW
RESTART_AUTO_ NEGOTIATION
12
RW
AUTO_NEGOTIATION_ ENABLE
15
RW
Reset
2
R
LINK_STATUS
3
R
AUTO_NEGOTIATION_ ABILITY
5
R
AUTO_NEGOTIATION_ COMPLETE
5
RW
FD
6
RW
HD
8:7
RW
PS2,PS1
13:12
RW
RF2,RF1
14
R0
ACK
15
RW
NP
5
R
FD
6
R
HD
8:7
R
PS2,PS1
13:12
R
RF2,RF1
14
R
ACK
15
R
NP
0
R
LINK_PARTNER_AUTO_NEGOTIATION_ABLE
1
R
PAGE_RECEIVE
0x1288
15:0
RW
AN link timer[15:0]
0x128C
4:0
RW
AN link timer[4:0]
0x1240
0x1244
0x1250
0x1254
0x1258
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Byte Offset
0x1290
Bit
R/W
0
RW
SGMII_ENA
1
RW
USE_SGMII_AN
3:2
RW
SGMII_SPEED
41
Name
Table 25: 10GBASE-KR Register Definitions
Byte Offset
0x12C0
0x12C4
Bit
R/W
Name
0
RW
Reset SEQ
1
RW
Disable AN Timer
2
RW
Disable LF Timer
6:4
RW
SEQ Force Mode[2:0]
16
RW
FEC ability
18
RW
FEC request
0
R
SEQ Link Ready
1
R
SEQ AN timeout
2
R
SEQ LT timeout
13:8
RW
16
R
KR FEC ability
17
R
KR FEC err ind ability
SEQ Reconfig Mode[5:0]
1G/10G MAC
1G/10G MAC registers are applicable to both design examples.
The base address of the 1G/10G MAC registers are defined as follows:
Channel
1G/10G MAC Register Base Address
0
MSA0 + 0x02_8000
1
MSA0 + 0x03_8000
2
MSA0 + 0x04_8000
3
MSA0 + 0x05_8000
4
MSA0 + 0x06_8000
5
MSA0 + 0x07_8000
6
MSA0 + 0x08_8000
7
MSA0 + 0x09_8000
8
MSA0 + 0x0A_8000
9
MSA0 + 0x0B_8000
10
MSA0 + 0x0C_8000
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1G/10G MAC
Channel
1G/10G MAC Register Base Address
11
MSA0 + 0x0D_8000
Note: For the description of each 1/10G MAC register, refer to the Low Latency Ethernet 10G MAC
User Guide.
Note: The address offset in this table is in byte, while the register map table in the Low Latency Ethernet
10G MAC User Guide is in word.
Table 26: Primary MAC Address
Byte Offset
R/W
Name
HW Reset
0x2008
RW
primary_mac_addr0
0x0
0x200C
RW
primary_mac_addr1
0x0
Table 27: Transmit Configuration and Status Registers
Byte Offset
R/W
Name
HW Reset
0x4000
RW
tx_packet_control
0x0
0x4004
RO
tx_packet_status
0x0
0x4100
RW
tx_pad_control
0x1
0x4200
RW
tx_crc_control
0x3
0x4400
RW
tx_preamble_control
0x0
0x6004
RW
tx_frame_maxlength
0x4300
RO
tx_underflow_counter0
0x0
0x4304
RO
tx_underflow_counter1
0x0
0x5EE(1518
)
Table 28: Flow Control Registers
Byte Offset
R/W
Name
HW Reset
0x4500
RW
tx_pauseframe_control
0x0
0x4504
RW
tx_pauseframe_quanta
0x0
0x4508
RW
tx_pauseframe_enable
0x1
0x4680
RW
tx_pfc_priority_enable
0x0
0x4600
RW
pfc_pause_quanta_0
0x0
0x4604
RW
pfc_pause_quanta_1
0x0
0x4608
RW
pfc_pause_quanta_2
0x0
0x460C
RW
pfc_pause_quanta_3
0x0
0x4610
RW
pfc_pause_quanta_4
0x0
0x4614
RW
pfc_pause_quanta_5
0x0
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Byte Offset
R/W
Name
43
HW Reset
0x4618
RW
pfc_pause_quanta_6
0x0
0x461C
RW
pfc_pause_quanta_7
0x0
0x4640
RW
pfc_holdoff_quanta_0
0x1
0x4644
RW
pfc_holdoff_quanta_1
0x1
0x4648
RW
pfc_holdoff_quanta_2
0x1
0x464C
RW
pfc_holdoff_quanta_3
0x1
0x4650
RW
pfc_holdoff_quanta_4
0x1
0x4654
RW
pfc_holdoff_quanta_5
0x1
0x4658
RW
pfc_holdoff_quanta_6
0x1
0x465C
RW
pfc_holdoff_quanta_7
0x1
Table 29: Receive Configuration and Status Registers
Byte Offset
R/W
Name
HW Reset
0x0000
RW
rx_transfer_control
0x0
0x0004
RO
rx_transfer_status
0x0
0x0100
RW
rx_padcrc_control
0x1
0x0200
RW
rx_crccheck_control
0x2
0x0400
RW
rx_custom_preamble_forward
0x0
0x0500
RW
rx_preamble_control
0x0
0x2000
RW
rx_frame_control
0x3
0x2004
RW
rx_frame_maxlength
1518
0x2010
RW
rx_frame_spaddr0_0
0x0
0x2014
RW
rx_frame_spaddr0_1
0x0
0x2018
RW
rx_frame_spaddr1_0
0x0
0x201C
RW
rx_frame_spaddr1_1
0x0
0x2020
RW
rx_frame_spaddr2_0
0x0
0x2024
RW
rx_frame_spaddr2_1
0x0
0x2028
RW
rx_frame_spaddr3_0
0x0
0x202C
RW
rx_frame_spaddr3_1
0x0
0x2060
RW
rx_pfc_control
0x1
0x0300
RO
rx_pktovrflow_error
0x0
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Table 30: Transmit Timestamp Registers
Byte Offset
R/W
Name
HW Reset
0x4440
RW
tx_period_10G
0x33333
0x4448
RW
tx_fns_adjustment_10G
0x0
0x444C
RW
tx_ns_adjustment_10G
0x0
0x4460
RW
tx_period_mult_speed
0x80000
0x4468
RW
tx_fns_adjustment_mult_speed
0x0
0x446C
RW
tx_ns_adjustment_mult_speed
0x0
Table 31: Receive Timestamp Registers
Byte Offset
R/W
Name
HW Reset
0x0440
RW
rx_period_10G
0x33333
0x0448
RW
rx_fns_adjustment_10G
0x0
0x044C
RW
rx_ns_adjustment_10G
0x0
0x0460
RW
rx_period_mult_speed
0x80000
0x0468
RW
rx_fns_adjustment_mult_speed
0x0
0x046C
RW
rx_ns_adjustment_mult_speed
0x0
Table 32: Transmit and Receive Statistics Registers
Byte Offset
R/W
Name
HW Reset
0x7000
RO
tx_stats_clr
0x0
0x3000
RO
rx_stats_clr
0x0
0x7008:0x700C
RO
tx_stats_framesOK
0x0
0x3008:0x300C
RO
rx_stats_framesOK
0x0
0x7010:0x7014
RO
tx_stats_framesErr
0x0
0x3010:0x3014
RO
rx_stats_framesErr
0x0
0x7018:0x701C
RO
tx_stats_framesCRCErr
0x0
0x3018:0x301C
RO
rx_stats_framesCRCErr
0x0
0x7020:0x7024
RO
tx_stats_octetsOK
0x0
0x3020:0x3024
RO
rx_stats_octetsOK
0x0
0x7028:0x702C
RO
tx_stats_pauseMACCtrl_Frames
0x0
0x3028:0x302C
RO
rx_stats_pauseMACCtrl_Frames
0x0
0x7030:0x7034
RO
tx_stats_ifErrors
0x0
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Name
45
Byte Offset
R/W
0x3030:0x3034
RO
rx_stats_ifErrors
0x0
0x7038:0x703C
RO
tx_stats_unicast_FramesOK
0x0
0x3038:0x303C
RO
rx_stats_unicast_FramesOK
0x0
0x7040:0x7044
RO
tx_stats_unicast_FramesErr
0x0
0x3040:0x3044
RO
rx_stats_unicast_FramesErr
0x0
0x7048:0x704C
RO
tx_stats_multicast_FramesOK
0x0
0x3048:0x304C
RO
rx_stats_multicast_FramesOK
0x0
0x7050:0x7054
RO
tx_stats_multicast_FramesErr
0x0
0x3050:0x3054
RO
rx_stats_multicast_FramesErr
0x0
0x7058:0x705C
RO
tx_stats_broadcast_FramesOK
0x0
0x3058:0x305C
RO
rx_stats_broadcast_FramesOK
0x0
0x7060:0x7064
RO
tx_stats_broadcast_FramesErr
0x0
0x3060:0x3064
RO
rx_stats_broadcast_FramesErr
0x0
0x7068:0x706C
RO
tx_stats_etherStatsOctets
0x0
0x3068:0x306C
RO
rx_stats_etherStatsOctets
0x0
0x7070:0x7074
RO
tx_stats_etherStatsPkts
0x0
0x3070:0x3074
RO
rx_stats_etherStatsPkts
0x0
0x7078:0x707C
RO
tx_stats_etherStatsUndersizePkts
0x0
0x3078:0x307C
RO
rx_stats_etherStatsUndersizePkts
0x0
0x7080:0x7084
RO
tx_stats_etherStatsOversizePkts
0x0
0x3080:0x3084
RO
rx_stats_etherStatsOversizePkts
0x0
0x7088:0x708C
RO
tx_stats_etherStatsPkts64Octets
0x0
0x3088:0x308C
RO
rx_stats_etherStatsPkts64Octets
0x0
0x7090:0x7094
RO
tx_stats_etherStatsPkts65to127Octets
0x0
0x3090:0x3094
RO
rx_stats_etherStatsPkts65to127Octets
0x0
0x7098:0x709C
RO
tx_stats_etherStatsPkts128to255Octets
0x0
0x3098:0x309C
RO
rx_stats_etherStatsPkts128to255Octets
0x0
0x70A0:0x70A4
RO
tx_stats_etherStatsPkts256to511Octets
0x0
0x30A0:0x30A4
RO
rx_stats_etherStatsPkts256to511Octets
0x0
0x70A8:0x70AC
RO
tx_stats_etherStatsPkts512to1023Octets
0x0
0x30A8:0x30AC
RO
rx_stats_etherStatsPkts512to1023Octets
0x0
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Byte Offset
R/W
Name
HW Reset
0x70B0:0x70B4
RO
tx_stats_etherStatPkts1024to1518Octets
0x0
0x30B0:0x30B4
RO
rx_stats_etherStatPkts1024to1518Octets
0x0
0x70B8:0x70BC
RO
tx_stats_etherStatsPkts1519toXOctets
0x0
0x30B8:0x30BC
RO
rx_stats_etherStatsPkts1519toXOctets
0x0
0x70C0:0x70C4
RO
tx_stats_etherStatsFragments
0x0
0x30C0:0x30C4
RO
rx_stats_etherStatsFragments
0x0
0x70C8:0x70CC
RO
tx_stats_etherStatsJabbers
0x0
0x30C8:0x30CC
RO
rx_stats_etherStatsJabbers
0x0
0x70D0:0x70D4
RO
tx_stats_etherStatsCRCErr
0x0
0x30D0:0x30D4
RO
rx_stats_etherStatsCRCErr
0x0
0x70D8:0x70DC
RO
tx_stats_unicastMACCtrlFrames
0x0
0x30D8:0x30DC
RO
rx_stats_unicastMACCtrlFrames
0x0
0x70E0:0x70E4
RO
tx_stats_multicastMACCtrlFrames
0x0
0x30E0:0x30E4
RO
rx_stats_multicastMACCtrlFrames
0x0
0x70E8:0x70EC
RO
tx_stats_broadcastMACCtrlFrames
0x0
0x30E8:0x30EC
RO
rx_stats_broadcastMACCtrlFrames
0x0
0x70F0:0x70F4
RO
tx_stats_PFCMACCtrlFrames
0x0
0x30F0:0x30F4
RO
rx_stats_PFCMACCtrlFrames
0x0
Document Revision History
Table 33: Document Revision History
Date
September 2015
Altera Corporation
Version
2015.09.30
Changes
Added DriftAdjust and DriftAdjustRate registers to
Master, 1G and 10G TOD register tables.
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Document Revision History
Date
Version
47
Changes
June 2015
2015.06.15
• Updated supported ACDS, Modelsimm and Synopsys
versions.
• Updated Clocking scheme for design example with
and without IEEE 1588v2 from tx_pma_clkout to tx_
clkout.
• Removed timing violation notification during
compilation.
• Added note about upgrading older design example
versions is not supported.
• Added foot note Master TOD, 1G TOD and 10G
TOD register maps about the default value for
'Period'.
• Updated the steps in 'Setting Up the Design Examples'
by combining unzip and setting directory steps.
• Updated 'Channel 0 MAC RX Statistic Counter' by
correcting number of packets from 28 to 12.
• Updated sampling clock for 10G and 1G TOD from
31.75MHz and 126.98MHz to 31.746031MHz and
126.984125MHz respectively.
• Updated 'Reset scheme at altera_eth_channel' and
'Reset scheme at altera_eth_channel_1588' figures
from '~phy_rx_block_lock ~phy_led_link' to '~phy_
rx_block_lock & ~phy_led_link'.
• Updated tx_frame_maxlength and tx_frame_
maxlength hardware reset value to hexadecimal value.
January 2015
2015.01.22
Updated supported ACDS release for software
simulation.
December 2014
2014.12.29
• Updated supported ACDS release for simulation.
• Added tested ACDS release version for hardware
simulation.
• Added timing violation notification during compila‐
tion.
• Updated clocking diagram for both design example
with and without IEEE 1588v2.
• Replaced CMU PLL to fractional PLL for entire
document.
May 2014
2014.05.29
Initial release.
Scalable Low Latency Ethernet 10G MAC using Arria 10 1G/10G PHY
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