EFEC7 IP Core Data Sheet

EFEC7 IP Core
DS-1033-1.3
Data Sheet
The Altera 7% Enhanced Forward Error Correction (EFEC7) IP core includes a highperformance encoder and decoder for Optical Transport Network (OTN) FEC
applications. Bose-Chaudhuri-Hocquenghem (BCH) streaming turbo product codes
correct errors in data transmitted across communication channels with various bit
error rates (BERs). EFEC7 performs high-gain error correction with 7% overhead and
is available for 100 gigabits per second (Gbps)/Optical Channel Transport Unit
(OTU)4 data transmission.
Features
EFEC7 includes the following features:
101 Innovation Drive
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November 2013
■
High-performance encoder and decoder for error detection and correction
■
100 Gbps OTN rate with 640 bit datapath width
■
7% overhead for Stratix ® IV and Stratix V devices
■
Latency of < 30 µs
■
Net electrical coding gain (NECG) of > 9.2 dB
■
Error statistic monitoring, including the following types:
■
Corrected zeros and ones errors
■
Corrected errors and uncorrectable errors
■
100 Gbps/OTU4 frame count
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NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and
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their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor
products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use
of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are
advised to obtain the latest version of device specifications before relying on any published information and before placing orders
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Page 2
Architecture
Architecture
Figure 1 illustrates the system architecture of the EFEC7 IP core. Data from an
incoming client is adapted to OTN before it is written to the OTN mapper. The data is
encoded with redundant data at the FEC encoder before it is transmitted across the
network. The redundant data is decoded at the FEC decoder and identified errors are
corrected before the data is written to the OTN framer. The data is then adapted back
to the original client.
Figure 1. EFEC7 System Architecture
Customer or Altera IP
Client
Adaptation
Altera IP Core
OTN
Mapper
OTN FEC
Encoder
Altera IP Core
OTN
Customer or Altera IP
OTN FEC
Decoder
OTN
Framer
Client
Adaptation
Device Family Support
Table 1 defines the device support levels for Altera IP cores.
Table 1. Altera IP Core Device Support Levels
FPGA Device Families
HardCopy® Device Families
Preliminary support—The IP core is verified with
preliminary timing models for this device family. The IP core
meets all functional requirements, but might still be
undergoing timing analysis for the device family. It can be
used in production designs with caution.
HardCopy Companion—The IP core is verified with
preliminary timing models for the HardCopy companion
device. The IP core meets all functional requirements, but
might still be undergoing timing analysis for the HardCopy
device family. It can be used in production designs with
caution.
Final support—The IP core is verified with final timing
models for this device family. The IP core meets all
functional and timing requirements for the device family and
can be used in production designs.
HardCopy Compilation—The IP core is verified with final
timing models for the HardCopy device family. The IP core
meets all functional and timing requirements for the device
family and can be used in production designs.
Table 2 lists the level of support for EFEC7 in each of the Altera device families.
Table 2. Device Family Support
Device Family
Support
Stratix IV GT
Final
Stratix IV E/GX
Preliminary
Stratix V E/GX/GS/GT
Preliminary
All other device families
Not available
IP Core Verification
Before releasing a version of the EFEC7 IP core, Altera runs comprehensive regression
tests to verify its quality and correctness.
EFEC7 IP Core
November 2013
Altera Corporation
Performance and Resource Utilization
Page 3
Performance and Resource Utilization
Stratix IV devices use combinational adaptive look-up tables (ALUTs) and logic
registers. Table 3 shows the typical performance for 100 Gbps EFEC7 on the
Stratix IV GT (EP4S100G5H40I1(N)) device as reported by the Quartus® II software.
Table 3. Performance - EFEC7 on Stratix IV GT (1)
ALUTS
Logic
Registers
Decoder
Memory
(M9K)
Memory
(144K)
f MAX (MHz)
Encoder
—
—
—
—
—
Decoder
—
—
—
—
—
Options
Net
Electrical
Gain (NECG)
> 9.2 dB
Latency
< 30 µs
Note to Table 3:
(1) Please contact Altera’s OTN account manager at otn_info@altera.com for detailed performance information.
Figure 2 shows the Input BER and Output BER of the EFEC7 in comparison to the
International Telecommunication Union, Telecommunication Standardization Sector
(ITU-T) G.709 standardized FEC application.
Figure 2. EFEC7 Bit Error Rate
Input Bit Error Rate
1.00E-02
1.00E-03
1.00E-04
1.00E-05
1.00E-05
Output Bit Error Rate
1.00E-07
1.00E-09
1.00E-11
1.00E-13
1.00E-15
1.00E-17
Altera EFEC7
G.709 FEC
November 2013
Altera Corporation
EFEC7 IP Core
Page 4
Port Listing
Port Listing
Table 4 lists the encoder input and output ports for connecting to the EFEC7 IP core.
Table 4. Encoder I/O Port Listing
I/O
Port Width
(Bits)
Port
Description
Input
sys_clk
1
Clock port.
Input
i_rst
1
This reset port is expected to meet removal and
recovery constraints for sys_clk. This is an
asynchronous reset and is active high.
Input
i_enable_n
1
Enable encoder and decoder port. This is a
synchronous signal and is active low.
Input
i_max_column_width
8
This input signals the OTN column count to
adjust for the various OTN overhead rates
supported by this application.
Input
i_row
2
Input OTN frame row port. This is a
synchronous signal.
Input
i_col
8
Input OTN frame column port. This is a
synchronous signal.
Input
i_data_en
1
Input enable data port. This is a synchronous
signal and is active high.
Input
i_data
640
Input data port.
Output
o_row
2
Output OTN frame row port. This is a
synchronous signal.
Output
o_col
8
Output OTN frame column port. This is a
synchronous signal.
Output
o_data_en
1
Output enable data port. This is a synchronous
signal and is active high.
Output
o_data
640
Output data port.
Table 5 lists the decoder input and output ports for connecting to the EFEC7 IP core.
Table 5. Decoder I/O Port Listing (Part 1 of 2)
I/O
Port Width
(Bits)
Port
Description
Input
sys_clk
1
Clock port.
Input
i_rst
1
This reset port is expected to meet removal and
recovery constraints for sys_clk. This is an
asynchronous reset and is active high.
Input
i_enable_n
1
Enable encoder and decoder port. This is a
synchronous signal and is active low.
Input
i_max_column_width
8
This input signals the OTN column count to
adjust for the various OTN overhead rates
supported by this application.
Input
i_error_scrambler_en_n
1
This input enables error scrambling. This is a
synchronous signal and is active low.
EFEC7 IP Core
November 2013
Altera Corporation
Port Listing
Page 5
Table 5. Decoder I/O Port Listing (Part 2 of 2)
I/O
Port Width
(Bits)
Port
Description
Input
i_row
2
Input OTN frame row port. This is a
synchronous signal.
Input
i_col
8
Input OTN frame column port. This is a
synchronous signal.
Input
i_data_en
1
Input enable data port. This is a synchronous
signal and is active high.
Input
i_data
640
Input data port.
1
This input controls performance latch counters.
The input latch counter pulses to receive the
value count from one latch to the next latch. This
is a synchronous signal and is active high.
32
This output signals the number of zeros errors
within the performance interval controlled by
i_latch_counters. This is a synchronous
signal.
32
This output signals the number of ones errors
within the performance interval controlled by
i_latch_counters. This is a synchronous
signal.
Input
i_latch_counters
Output
o_0s_fec_errors
Output
o_1s_fec_errors
Output
o_fec_errors
32
This output signals the total number of errors
within the performance interval controlled by
i_latch_counters. This is a synchronous
signal.
Output
o_uncorrectables
32
This output signals the number of uncorrectable
RS codes. It is controlled by
i_latch_counters.
Output
o_otu4_frames
32
Output OTU4 frames port. This is a synchronous
signal and is controlled by i_latch_counters.
Output
o_row
2
Output OTN frame row port. This is a
synchronous signal.
Output
o_col
8
Output OTN frame column port. This is a
synchronous signal.
Output
o_data_en
1
Output enable data port. This is a synchronous
signal and is active high.
Output
o_data
640
Output data port.
Document Revision History
Table 6 shows the revision history for this document.
Table 6. Document Revision History
Date
Version
Changes
November 2013
1.3
Updated NECG
May 2012
1.2
Added otn_info@altera.com mailbox.
November 2013
Altera Corporation
EFEC7 IP Core
Page 6
Port Listing
Table 6. Document Revision History
Date
Version
Changes
March 2012
1.1
Updated NECG.
February 2012
1.0
Initial release.
EFEC7 IP Core
November 2013
Altera Corporation