Evaluating Power for Altera Devices ® July 2001, ver. 3.1 Introduction Application Note 74 A critical element of system reliability is the capacity of electronic devices to safely dissipate the heat generated during operation. The thermal characteristics of a circuit depend on the device and package used, the operating temperature, the operating current, and the system’s ability to dissipate heat. You should complete a power evaluation early in the design process to help identify potential heat-related problems in the system and to prevent the system from exceeding the device’s maximum allowed junction temperature. This application note discusses how to evaluate and manage power, and provides sample worksheets for performing a power evaluation. Power Evaluation The actual power dissipated by most applications is significantly lower than the power the package can dissipate. However, a thermal analysis should be performed for all projects. To evaluate the power usage in your system, use the following steps: 1. 2. 3. Estimate the power consumption of the application. Calculate the maximum power for the device and package. Compare the estimated and maximum power values. Table 1 shows the variables used for estimating power consumption. Table 1. Variables Used for Evaluating Power Consumption (Part 1 of 2) Variable Altera Corporation A-AN-074-3.1 Unit ICCCSTANDBY mA K µA/(MHz × LE) fMAX MHz N LE ICCINT mA PINT mW MCTON LE MCDEV LE MCUSED LE PDCOUT mW 1 AN 74: Evaluating Power for Altera Devices Table 1. Variables Used for Evaluating Power Consumption (Part 2 of 2) Variable Unit CAVE pF PACOUT mW PIO mW PEST mW θJA ˚ C/W TJ ˚C TA ˚C PMAX W Estimating Power Consumption Use the following formula to compute the estimated power consumption (PEST) of the application: PEST = PINT + PIO Where: PINT = ICCINT × VCCINT PIO = PACOUT + PDCOUT Therefore: PEST = (ICCINT × VCCINT) + (PACOUT + PDCOUT) The no-load power (PINT) value can be obtained from the “Power Consumption” section in each device family data sheet. Because this value is “unloaded,” it is necessary to add the power dissipated by the I/O buffers—PDCOUT from steady-state outputs and the PACOUT current from frequently switching outputs. PDCOUT depends on the number of steady-state outputs, the logic levels they drive, and the resistive load on each output, as shown in the following formula: d PDCOUT = ∑ PDCn n=1 Where: 2 d PDCn Vn fn = = = = Number of DC outputs DC output power of output n Voltage swing of output n Switching frequency of output n Altera Corporation AN 74: Evaluating Power for Altera Devices Table 2 shows the DC power dissipated by the output drivers of a device with VCCIO set at 5 V under typical types of loads. The DC power dissipated by the output driver does not equal the VCC × ICCIO value because most of the DC power is consumed by the load. If you are using a 2.5-V or 3.3-V device or a non-5.0-V VCCIO, you can compute the power based on the device’s IOH and IOL figures shown in the device family data sheet. Table 2. DC Power Dissipated Load Driven PDCn (mW) 1-K pull-up resistor for low outputs 0.49 1-K pull-down resistor for high outputs 5.04 Bipolar for low outputs 0.16 Bipolar for high outputs 0.0576 CMOS inputs Negligible PACOUT depends on the capacitive load on each output and the frequency at which each output switches, as shown in the following formula: a PACOUT = ∑ Cn Vn fn × VCCIO n=1 Where: a Cn Vn fn = = = = Number of AC outputs Capacitive load on output n Voltage swing of output n Switching frequency of output n The following equation shows the frequency of each output (fn), in terms of the maximum clock frequency (fMAX) of the design and the average ratio of I/O pins toggling at each clock (togIO): fn = (0.5) × fMAX × togIO Inserting the equation for fn into the PACOUT equation and resolving the summation for an average capacitive load yields the following formula: PACOUT = (0.5) × OUT × CAVE × VO × fMAX × togIO × VCCIO Where: Altera Corporation OUT = Total number of output and bidirectional pins 3 AN 74: Evaluating Power for Altera Devices Table 3 shows the VCCIO and VO values for Altera® devices. Table 3. VCCIO & VO Values VCCIO (V) VO (V) 5.0 3.8 3.3 3.3 2.5 2.5 For example, the following equation provides the power consumed by driving a capacitive load for applications with VCCIO = 5 V: PACOUT = (0.5) × OUT × CAVE × 3.8 V × fMAX × togIO × 5.0 V Calculating Maximum Power for the Device & Package The following formulas are used to calculate the maximum allowed power (P MAX) for a device: MAX T J – TA = ------------------θ JA or T J – TC P MAX = -----------------θ JC The maximum allowed power is dependent on the maximum allowed junction temperature (TJ) of the silicon, the ambient temperature of operation (TA), and the package’s thermal resistance (θJA) when configured in the system. The maximum junction temperature is specified in the Altera device family data sheets. The ambient temperature depends on the application. The worst-case P MAX value is estimated using the formula with θ JA, the junction-to-ambient thermal resistance. The θ JA value for Altera devices is provided for still air (with convection cooling only), and for a forced-air flow of 100 feet/second, 200 feet/second, and 400 feet/second. If heat-sinking is used to dissipate heat and θ JA for a heat sink is given, you should use the case temperature (TC) and the junctionto-case thermal resistance (θ JC) to calculate P MAX for a device. θ JC is a measure of the lowest possible thermal resistance. f 4 For thermal resistance values (θ JC and θ JA) of Altera devices, refer to the Altera Device Packaging Information Data Sheet. Altera Corporation AN 74: Evaluating Power for Altera Devices Comparing Maximum Allowed Power & Estimated Power To avoid reliability problems, you should compare the values calculated for the maximum allowed power and estimated power. The estimated power should be the smaller of the two values. If the estimated power exceeds the maximum allowed power, refer to “Thermal Management” on page 10 for suggestions on how to reduce power requirements for a design. Figure 1 shows a sample worksheet for evaluating power. Figure 1. Power Evaluation Worksheet (Part 1 of 2) Design___________________________ Device_________________________ Estimating the Power Consumption of the Application Internal Power Calculation for All Altera Devices FLEX 10K, FLEX 8000 & FLEX 6000 Devices Standby current (ICCSTANDBY) Coefficient for ICC calculation. See the appropriate device family data sheet for this value. Maximum clock frequency (fMAX) Total number of logic elements (LEs) used in the device (N) ICCSTANDBY = K= fMAX = N= mA µA/(MHz × LE) MHz LE Average ratio of logic cells toggling (togLC) at each clock (typically 0.125) togLC = Total internal current (ICCINT) ICCINT = mA PINT = mW ICCINT = ICC0 + K × fMAX × N × togLC Total internal power (PINT) PINT = VCC × ICCINT MAX 9000, MAX 7000 & MAX 3000A Devices Coefficients for ICC calculation. See the appropriate device family data sheet for these values. A= mA/LE B= mA/LE C= Number of macrocells with the Turbo Bit™ on (MCTON) Number of macrocells in the device (MCDEV) Number of macrocells in the design (MCUSED) Maximum clock frequency (fMAX) mA/(MHz × LE) MCTON = LE MCDEV = LE MCUSED = LE fMAX = MHz Average ratio of logic cells toggling (togLC) at each clock (typically 0.125) togLC = Total internal current (ICCINT) ICCINT = mA PINT = mW ICCINT = (A × MCTON) + [B × (MCDEV – MCTON)] + (C × MCUSED × fMAX × togLC) Total internal power (PINT) PINT = VCC × ICCINT Altera Corporation 5 AN 74: Evaluating Power for Altera Devices Figure 1. Power Evaluation Worksheet (Part 2 of 2) External Power Calculation for All Altera Devices Power consumed by the DC output load (PDCOUT) PDCOUT = mW PDCOUT = PDCn Average capacitive load (CAVE) at output pins CAVE = Number of output/bidirectional pins in the design (OUT) OUT = Average ratio of I/O pins toggling (togIO) at each clock (typically 0.125) togIO = Power consumed by AC output load (PACOUT) pF PACOUT = mW PIO = mW PEST = mW PACOUT = 1/2 × OUT × CAVE × VO × fMAX × togIO × VCCIO × 0.001 Total external power (PIO) PIO = PDCOUT + PACOUT Total Power Calculation for All Altera Devices Estimated total power (PEST) PEST = PINT + PIO Calculating Maximum Allowed Power for the Device & Package Thermal resistance of the device Maximum junction temperature (TJ) as specified in the appropriate device family data sheet. Ambient temperature (TA) of the design Maximum power (PMAX) allowed for the device TJ = ˚ C/W ˚C TA = ˚C θJA = PMAX = W PMAX = (TJ – TA) / θJA Comparing Maximum Power Allowed & Estimated Power Is PEST < PMAX? 6 Yes or No Altera Corporation AN 74: Evaluating Power for Altera Devices Tables 4 and 5 show design parameters for the sample power evaluations shown in Figures 2 and 3. The design parameters are unique to the sample designs and are not found in device family data sheets. Table 4. Parameters for the Sample FLEX 10K Design Parameter OUT Description Number of outputs Number of 1-KΩ pull-up resistors Type of load Value 150 50 CMOS inputs Type of load 100 CAVE Average capacitance 35 pF N Number of logic elements used 2,747 LE fMAX Maximum operating frequency 20 MHz PDCOUT Static power consumed by outputs (0.49 mW × 50) + (0 mW × 231) = 24.5 mW Table 5. Parameters for the Sample MAX 9000 Design Parameter Value MCTON 139 MCDEV 560 MCUSED 500 MCTOFF 421 fMAX 40 MHz OUT 211 Number of 1-KΩ pull-down resistors 10 CMOS inputs 201 CAVE 35 pF PDCOUT (5.04 mW × 10) + (0 mW × 201) = 50 mW Figures 2 and 3 provide power evaluations for sample designs implemented in FLEX® 10K and MAX® 9000 devices, respectively. Altera Corporation 7 AN 74: Evaluating Power for Altera Devices Figure 2. Sample Power Evaluation for a FLEX 10K Device (Part 1 of 2) dsp_fir.tdf Design___________________________ EPF10K50VBC356-2 Device_________________________ Estimating the Power Consumption of the Application Internal Power Calculation FLEX 10K, FLEX 8000 & FLEX 6000 Devices Standby current (ICCSTANDBY) Coefficient for ICC calculation. See the appropriate device family data sheet for this value. Maximum clock frequency (fMAX) Total number of logic elements used in the device (N) ICCSTANDBY = 0.500 mA K= 45 µA/(MHz × LE) fMAX = 50 MHz N= 2,747 Average ratio of logic cells toggling (togLC) at each clock (typically 0.125) togLC = 0.125 LE Total internal current (ICCINT) ICCINT = 773.09 mA PINT = 2,551.2 mW PDCOUT = 35 mW CAVE = 35 pF ICCINT = ICCSTANDBY + K × fMAX × N × togLC Total internal power (PINT) PINT = VCC × ICCINT External Power Calculation for All Altera Devices Power consumed by the DC output load (PDCOUT) PDCOUT = PDCn Average capacitive load (CAVE) at output pins Number of output/bidirectional pins in the design (OUT) OUT = 150 Average ratio of I/O pins toggling (togIO) at each clock (typically 0.125) togIO = 0.125 PACOUT = 178.66 mW PIO = 213.66 mW PEST = 2,764.9 mW Power consumed by AC output load (PACOUT) PACOUT = 1/2 × OUT × CAVE × 3.3 V × fMAX × togIO × 3.3 V × 0.001 Total external power (PIO) PIO = PDCOUT + PACOUT Total Power Calculation for All Altera Devices Estimated total power (PEST) PEST = PINT + PIO 8 Altera Corporation AN 74: Evaluating Power for Altera Devices Figure 2. Sample Power Evaluation for a FLEX 10K Device (Part 2 of 2) Calculating Maximum Allowed Power for the Device & Package θJA = 8 Maximum junction temperature (TJ) as specified in the appropriate device family data sheet. TJ = 85 ˚ C/W ˚C Ambient temperature (TA) of the design TA = 40 ˚C 5.625 W Thermal resistance of the device Maximum power (PMAX) allowed for the device PMAX = PMAX = (TJ – TA) / θJA Comparing Maximum Power Allowed & Estimated Power Is PEST < PMAX? Yes or No Figure 3. Sample Power Evaluation for a MAX 9000 Device (Part 1 of 2) atm_pkt.tdf Design___________________________ EPM9560ARC304-10 Device_________________________ Estimating the Power Consumption of the Application Internal Power Calculation MAX 9000, MAX 7000 & MAX 3000A Devices Coefficients for ICC calculation. See the appropriate device family data sheet for these values. A= 0.68 mA/LE B= 0.26 mA/LE C= 0.052 mA/(MHz × LE) Number of macrocells with the Turbo Bit on (MCTON) MCTON = 139 LE Number of macrocells in the device (MCDEV) MCDEV = 560 LE MCUSED = 500 LE fMAX = 40 MHz Average ratio of logic cells toggling (togLC) at each clock (typically 0.125) togLC = 0.125 Total internal current (ICCINT) ICCINT = 333.98 mA PINT = 1,669.9 mW 50 mW pF Number of macrocells in the design (MCUSED) Maximum clock frequency (fMAX) ICCINT = (A × MCTON) + [B × (MCDEV – MCTON)] + (C × MCUSED × fMAX × togLC) Total internal power (PINT) PINT = VCC × ICCINT External Power Calculation for All Altera Devices Power consumed by the DC output load (PDCOUT) PDCOUT = PDCOUT = PDCn Average capacitive load (CAVE) at output pins CAVE = 35 Number of output/bidirectional pins in the design (OUT) OUT = 211 Average ratio of I/O pins toggling (togIO) at each clock (typically 0.125) Power consumed by AC output load (PACOUT) Altera Corporation togIO = 0.125 PACOUT = 350.79 mW 9 AN 74: Evaluating Power for Altera Devices Figure 3. Sample Power Evaluation for a MAX 9000 Device (Part 2 of 2) PACOUT = 1/2 × OUT × CAVE × 3.8 V × fMAX × togIO × 5 V × 0.001 Total external power (PIO) PIO = 400.79 mW 2,070.69 mW PIO = PDCOUT + PACOUT Total Power Calculation for All Altera Devices Estimated total power (PEST) PEST = PEST = PINT + PIO Calculating Maximum Allowed Power for the Device & Package Thermal resistance of the device Maximum junction temperature (TJ) as specified in the appropriate device family data sheet. Ambient temperature (TA) of the design Maximum power (PMAX) allowed for the device θJA = 8 TJ = 90 ˚ C/W ˚C TA = 70 ˚C PMAX = 2.5 W PMAX = (TJ – TA) / θJA Comparing Maximum Power Allowed & Estimated Power Is PEST < PMAX? Thermal Management 10 Yes or No The following guidelines reduce power dissipation and heat build-up for an application: ■ Use available low-power features of the device. By turning the Turbo Bit™ off, Classic™ devices and individual macrocells in MAX 9000, MAX 7000, and MAX 3000A devices can be configured for lowpower operation, with only a nominal increase in propagation delays. Macrocells in MAX 9000, MAX 7000, or MAX 3000A devices that do not need to run in high-performance mode should be set to low-power mode. ■ Choose a different device package. A ceramic or higher-pin-count package can be used. Ceramic packages dissipate more heat than plastic packages. Also, packages with higher pin counts can dissipate more heat through the connections to the printed circuit board (PCB). ■ Use forced-air cooling and/or heat-sinking. Forced-air cooling improves the efficiency of convection cooling, which reduces the surface temperature of the device. A heat sink connected to a device significantly increases heat dissipation by radiating heat via the metal mass. Altera Corporation AN 74: Evaluating Power for Altera Devices Revision History Altera Corporation ■ Slow the operation in portions of the circuit. I CC is proportional to the frequency of operation. Slowing parts of a circuit lowers the I CC and hence reduces the power. Altera devices provide global or array clock sources for all registers. Signals that do not require high-speed operation can use a slower array clock that significantly reduces the system power consumption. ■ Reduce the number of outputs. DC and AC current is required to support all I/O pins on the device. Reducing the number of I/O pins may reduce the current necessary for the device, and thereby reduce the power. ■ Reduce the amount of circuitry in the device. Power depends on the amount of internal logic that switches at any given time. Reducing the amount of logic in a device reduces the current in the device. The same effect may be achieved by using a larger device, which also provides increased heat dissipation and maintains a single-device solution. ■ Choose a different device family. Some device families consume less power than others. For example, the MAX 7000 family provides more power-saving features than the MAX 5000 family. The Classic family provides power-saving features for low-density designs, and low-speed designs consume less power when implemented in FLEX devices. ■ Modify the design to reduce power. Identify areas in the design that can be revised to reduce the power requirements. Common solutions include reducing the number of switching nodes and/or required logic, and removing redundant or unnecessary signals. For assistance in locating less obvious changes, contact Altera Applications at (800) 800-EPLD. The information contained in Application Note 74 (Evaluating Power for Altera Devices) version 3.1 supersedes information published in previous versions. In version 3.1, the MAX device in Figure 3 was updated. 11 Operating Requirements for Altera Devices ® 101 Innovation Drive San Jose, CA 95134 (408) 544-7000 http://www.altera.com Applications Hotline: (800) 800-EPLD Customer Marketing: (408) 544-7104 Literature Services: (408) 3-ALTERA [email protected] 12 Altera, MAX, and FLEX are registered trademarks of Altera Corporation. The following are trademarks of Altera Corporation: Classic, MAX 7000, MAX 3000A, MAX 9000, FineLine BGA, FLEX 10K, FLEX 8000, FLEX 6000, and Turbo Bit. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. Copyright 2001 Altera Corporation. All rights reserved. Altera Corporation Printed on Recycled Paper.