Arria 10 Device Datasheet .

Arria 10 Device Datasheet
2015.09.15
A10-DATASHEET
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This datasheet describes the electrical characteristics, switching characteristics, configuration specifications, and I/O timing for Arria® 10 devices.
Arria 10 devices are offered in extended and industrial grades. Extended devices are offered in –E1 (fastest), –E2, and –E3 speed grades. Industrial
grade devices are offered in the –I1, –I2, and –I3 speed grades.
The suffix after the speed grade denotes the power options offered in Arria 10 devices.
• L—Low static power
• S—Standard power
• M—Enabled with the VCC PowerManager feature (you can power VCC and VCCP at nominal voltage of 0.90 V or lower voltage of 0.83 V)
Related Information
Arria 10 Device Overview
Provides more information about the densities and packages of devices in the Arria 10 family.
Electrical Characteristics
The following sections describe the operating conditions and power consumption of Arria 10 devices.
Operating Conditions
Arria 10 devices are rated according to a set of defined parameters. To maintain the highest possible performance and reliability of the Arria 10
devices, you must consider the operating requirements described in this section.
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Absolute Maximum Ratings
Absolute Maximum Ratings
This section defines the maximum operating conditions for Arria 10 devices. The values are based on experiments conducted with the devices and
theoretical modeling of breakdown and damage mechanisms. The functional operation of the device is not implied for these conditions.
Caution: Conditions outside the range listed in the following table may cause permanent damage to the device. Additionally, device operation at
the absolute maximum ratings for extended periods of time may have adverse effects on the device.
Table 1: Absolute Maximum Ratings for Arria 10 Devices—Preliminary
Symbol
(1)
Description
Condition
Minimum
Maximum
Unit
VCC
Core voltage power supply
—
–0.50
1.21
V
VCCP
Periphery circuitry and transceiver fabric interface power
supply
—
–0.50
1.21
V
VCCERAM
Embedded memory power supply
—
–0.50
1.36
V
VCCPT
Power supply for programmable power technology and I/O
pre-driver
—
–0.50
2.46
V
VCCBAT
Battery back-up power supply for design security volatile key
register
—
–0.50
2.46
V
VCCPGM
Configuration pins power supply
(1)
–0.50
2.46
V
VCCIO
I/O buffers power supply
3 V I/O
–0.50
4.10
V
LVDS I/O
–0.50
2.46
V
VCCA_PLL
Phase-locked loop (PLL) analog power supply
—
–0.50
2.46
V
VCCT_GXB
Transmitter power
—
–0.50
1.34
V
VCCR_GXB
Receiver power
—
–0.50
1.34
V
VCCH_GXB
Transmitter output buffer power
—
–0.50
2.46
V
VCCL_HPS
HPS core voltage and periphery circuitry power supply
—
–0.50
1.27
V
VCCIO_HPS
HPS I/O buffers power supply
3 V I/O
–0.50
4.10
V
LVDS I/O
–0.50
2.46
V
The LVDS I/O values are applicable to all dedicated and dual-function configuration I/Os.
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Maximum Allowed Overshoot and Undershoot Voltage
Symbol
Description
Condition
Minimum
Maximum
Unit
VCCIOREF_HPS
HPS I/O pre-driver power supply
—
–0.50
2.46
V
VCCPLL_HPS
HPS PLL power supply
—
–0.50
2.46
V
IOUT
DC output current per pin
—
–25
25
mA
TJ
Operating junction temperature
—
–55
125
°C
TSTG
Storage temperature (no bias)
—
–65
150
°C
3
Maximum Allowed Overshoot and Undershoot Voltage
During transitions, input signals may overshoot to the voltage listed in the following table and undershoot to –2.0 V for input currents less than
100 mA and periods shorter than 20 ns.
The maximum allowed overshoot duration is specified as a percentage of high time over the lifetime of the device. A DC signal is equivalent to
100% duty cycle.
For example, a signal that overshoots to 2.70 V for LVDS I/O can only be at 2.70 V for ~4% over the lifetime of the device.
Table 2: Maximum Allowed Overshoot During Transitions for Arria 10 Devices—Preliminary
This table lists the maximum allowed input overshoot voltage and the duration of the overshoot voltage as a percentage of device lifetime. The LVDS I/O
values are applicable to the VREFP_ADC and VREFN_ADC I/O pins.
Symbol
Vi (AC)
(2)
Description
AC input
voltage
Condition (V)
Overshoot Duration as % at TJ = 100°C
Unit
3.80
100
%
2.55
3.85
42
%
2.60
3.90
18
%
2.65
3.95
9
%
2.70
4.00
4
%
> 2.70
> 4.00
No overshoot allowed
%
LVDS I/O (2)
3 V I/O
2.50
The LVDS I/O values are applicable to all dedicated and dual-function configuration I/Os.
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Recommended Operating Conditions
Recommended Operating Conditions
This section lists the functional operation limits for the AC and DC parameters for Arria 10 devices.
Recommended Operating Conditions
Table 3: Recommended Operating Conditions for Arria 10 Devices—Preliminary
This table lists the steady-state voltage values expected from Arria 10 devices. Power supply ramps must all be strictly monotonic, without plateaus.
Symbol
VCC
VCCP
VCCPGM
VCCERAM
(3)
(4)
(5)
Description
Core voltage power supply
Periphery circuitry and transceiver
fabric interface power supply
Configuration pins power supply
Embedded memory power supply
Condition
Minimum (3)
Typical
Maximum (3)
Unit
Standard and low power
0.87
0.9 (4)
0.93
V
VCC PowerManager (5)
0.8, 0.87
0.83, 0.9
0.86, 0.93
V
SmartVID
0.8
—
0.93
V
Standard and low power
0.87
0.93
V
VCC PowerManager (5)
0.8, 0.87
0.83, 0.9
0.86, 0.93
V
SmartVID
0.8
—
0.93
V
1.8 V
1.71
1.8
1.89
V
1.5 V
1.425
1.5
1.575
V
1.2 V
1.14
1.2
1.26
V
0.9 V
0.87
0.9(4)
0.93
V
0.9
(4)
This value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the
PDN tool for the additional budget for the dynamic tolerance requirements.
You can operate –1 and –2 speed grade devices at 0.9 V or 0.95 V typical value. You can operate -3 speed grade device at only 0.9 V typical value.
Core performance shown in this datasheet is applicable for the operation at 0.9 V. Operating at 0.95 V results in higher core performance and higher
power consumption. For more information about the performance and power consumption of 0.95 V operation, refer to the Quartus® II software
timing reports, PowerPlay Power Analyzer report, and Early Power Estimator (EPE).
You can operate VCC PowerManager devices at either 0.83 V or 0.9 V. Power VCC and VCCP at 0.9 V to achieve –1 speed grade performance. Power
VCC and VCCP at 0.83 V to achieve lower performance using the lowest power.
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Symbol
(6)
(7)
(8)
Description
VCCBAT (6)
Battery back-up power supply
(For design security volatile key
register)
VCCPT
Power supply for programmable
power technology and I/O pre-driver
VCCIO
(3)
Recommended Operating Conditions
I/O buffers power supply
Condition
Minimum (3)
Typical
Maximum (3)
Unit
1.8 V
1.71
1.8
1.89
V
1.2 V
1.14
1.2
1.26
V
1.8 V
1.71
1.8
1.89
V
3.0 V (for 3 V I/O only)
2.85
3.0
3.15
V
2.5 V (for 3 V I/O only)
2.375
2.5
2.625
V
1.8 V
1.71
1.8
1.89
V
1.5 V
1.425
1.5
1.575
V
1.35 V
(7)
1.35
(7)
V
1.25 V
1.19
1.25
1.31
V
1.2 V
(7)
1.2
(7)
V
VCCA_PLL
PLL analog voltage regulator power
supply
—
1.71
1.8
1.89
V
VREFP_ADC
Precision voltage reference for
voltage sensor
—
1.2475
1.25
1.2525
V
VI (8)
DC input voltage
3 V I/O
–0.3
—
3.3
V
LVDS I/O
–0.3
—
2.19
V
VO
Output voltage
—
0
—
VCCIO
V
TJ
Operating junction temperature
Extended
0
—
100
°C
Industrial
–40
—
100
°C
5
This value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the
PDN tool for the additional budget for the dynamic tolerance requirements.
If you do not use the design security feature in Arria 10 devices, connect VCCBAT to a 1.5-V or 1.8-V power supply. Arria 10 power-on reset (POR)
circuitry monitors VCCBAT. Arria 10 devices do not exit POR if VCCBAT is not powered up.
For minimum and maximum voltage values, refer to the I/O Standard Specifications section.
The LVDS I/O values are applicable to all dedicated and dual-function configuration I/Os.
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Transceiver Power Supply Operating Conditions
Symbol
Description
tRAMP (9)(10)
Power supply ramp time
Condition
Minimum (3)
Typical
Maximum (3)
Unit
Standard POR
200 µs
—
100 ms
—
Fast POR
200 µs
—
4 ms
—
Related Information
I/O Standard Specifications on page 15
Transceiver Power Supply Operating Conditions
Table 4: Transceiver Power Supply Operating Conditions for Arria 10 GX/SX Devices—Preliminary
Symbol
Description
Condition (11)
Minimum
Typical
Maximum (1
Unit
Chip-to-Chip ≤ 17.4 Gbps
1.0
1.03
1.06
V
0.92
0.95
0.98
V
(12)
2)
Or
VCCT_GXB[L,R]
Transmitter power supply
Backplane (13) ≤ 16.0 Gbps
Chip-to-Chip ≤ 11.3 Gbps
Or
Backplane (13) ≤ 10.3125 Gbps
(3)
(9)
(10)
(11)
(12)
(13)
This value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the
PDN tool for the additional budget for the dynamic tolerance requirements.
This is also applicable to HPS power supply. For HPS power supply, refer to tRAMP specifications for standard POR when HPS_PORSEL = 0 and
tRAMP specifications for fast POR when HPS_PORSEL = 1.
tramp is the ramp time of each individual power supply, not the ramp time of all combined power supplies.
These data rate ranges vary depending on the transceiver speed grade. Refer to Transceiver Performance for Arria 10 GX/SX Devices for exact data
rate ranges.
This value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the
PDN tool for the additional budget for the dynamic tolerance requirements.
Backplane applications assume advanced equalization circuitry, such as decision feedback equalization (DFE), is enabled to compensate for signal
impairments. Chip-to-chip links are assumed to be applications with short reach channels that do not require DFE.
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Transceiver Power Supply Operating Conditions
Symbol
Description
Condition (11)
Minimum
Typical
Maximum (1
Unit
Chip-to-Chip ≤ 17.4 Gbps
1.0
1.03
1.06
V
0.92
0.95
0.98
V
1.710
1.8
1.890
V
(12)
2)
7
Or
VCCR_GXB[L,R]
Receiver power supply
Backplane (13) ≤ 16.0 Gbps
Chip-to-Chip ≤ 11.3 Gbps
Or
Backplane (13) ≤ 10.3125 Gbps
VCCH_GXB[L,R]
Transceiver high voltage power
—
Note: Most VCCR_GXB and VCCT_GXB pins associated with unused transceiver channels can be grounded on a per-side basis to minimize
power consumption. Refer to the Quartus II pin report for information about pinning out the package to minimize power consumption for
your specific design.
(11)
(12)
These data rate ranges vary depending on the transceiver speed grade. Refer to Transceiver Performance for Arria 10 GX/SX Devices for exact data
rate ranges.
This value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the
PDN tool for the additional budget for the dynamic tolerance requirements.
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Transceiver Power Supply Operating Conditions
Table 5: Transceiver Power Supply Operating Conditions for Arria 10 GT Devices—Preliminary
Symbol
Description
Condition (14)
Minimum (12)
Typical
Maximum (12)
Unit
Chip-to-Chip < 28.3 Gbps (15)
1.08
1.11
1.14
V
1.0
1.03
1.06
V
0.92
0.95
0.98
V
1.08
1.11
1.14
V
1.0
1.03
1.06
V
0.92
0.95
0.98
V
Or
Backplane (13) < 17.4 Gbps
Chip-to-Chip < 15 Gbps
VCCT_GXB[L,R]
Or
Transmitter power supply
Backplane
(13)
< 14.2 Gbps
Chip-to-Chip < 11.3 Gbps
Or
Backplane (13) < 10.3125 Gbps
Chip-to-Chip < 28.3 Gbps (15)
Or
Backplane (13) < 17.4 Gbps
Chip-to-Chip < 15 Gbps
VCCR_GXB[L,R]
Receiver power supply
Or
Backplane (13) < 14.2 Gbps
Chip-to-Chip < 11.3 Gbps
Or
Backplane (13) < 10.3125 Gbps
(14)
These data rate ranges vary depending on the transceiver speed grade. Refer to Transceiver Performance for Arria 10 GT Devices table for exact data
rate ranges.
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HPS Power Supply Operating Conditions
Description
Condition (14)
Minimum (12)
Typical
Maximum (12)
Unit
Transceiver high voltage power
supply
—
1.710
1.8
1.890
V
Symbol
VCCH_GXB[L,R]
9
Related Information
• Transceiver Performance for Arria 10 GT Devices on page 26
Provides the data rate ranges for different transceiver speed grades.
• Transceiver Performance for Arria 10 GX/SX Devices on page 22
Provides the data rate ranges for different transceiver speed grades.
HPS Power Supply Operating Conditions
Table 6: HPS Power Supply Operating Conditions for Arria 10 SX Devices—Preliminary
This table lists the steady-state voltage and current values expected from Arria 10 system-on-a-chip (SoC) devices with ARM®-based hard processor system
(HPS). Power supply ramps must all be strictly monotonic, without plateaus. Refer to Recommended Operating Conditions for Arria 10 Devices table for
the steady-state voltage values expected from the FPGA portion of the Arria 10 SoC devices.
Symbol
VCCL_HPS
VCCIO_HPS
VCCIOREF_HPS
(14)
(15)
(16)
Description
HPS core voltage and periphery
circuitry power supply
HPS I/O buffers power supply
HPS I/O pre-driver power supply
Condition
Minimum (16)
Typical
Maximum (16)
Unit
HPS processor speed =
1.2 GHz
0.87
0.9
0.93
V
HPS processor speed =
1.5 GHz, –1 speed grade
0.92
0.95
0.98
V
3.0 V
2.85
3.0
3.15
V
2.5 V
2.375
2.5
2.625
V
1.8 V
1.71
1.8
1.89
V
—
1.71
1.8
1.89
V
These data rate ranges vary depending on the transceiver speed grade. Refer to Transceiver Performance for Arria 10 GT Devices table for exact data
rate ranges.
28.3 Gbps is the maximum data rate for GT channels. 17.4 Gbps is the maximum data rate for GX channels.
This value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the
PDN tool for the additional budget for the dynamic tolerance requirements.
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DC Characteristics
Symbol
VCCPLL_HPS
Description
HPS PLL analog voltage regulator
power supply
Condition
Minimum (16)
Typical
Maximum (16)
Unit
—
1.71
1.8
1.89
V
Related Information
Recommended Operating Conditions on page 4
Provides the steady-state voltage values for the FPGA portion of the device.
DC Characteristics
The OCT variation after power-up calibration specifications will be available in a future release of the Arria 10 Device Datasheet.
Supply Current and Power Consumption
Altera offers two ways to estimate power for your design—the Excel-based Early Power Estimator (EPE) and the Quartus II PowerPlay Power
Analyzer feature.
Use the Excel-based EPE before you start your design to estimate the supply current for your design. The EPE provides a magnitude estimate of the
device power because these currents vary greatly with the usage of the resources.
The Quartus II PowerPlay Power Analyzer provides better quality estimates based on the specifics of the design after you complete place-androute. The PowerPlay Power Analyzer can apply a combination of user-entered, simulation-derived, and estimated signal activities that, when
combined with detailed circuit models, yield very accurate power estimates.
Related Information
• PowerPlay Early Power Estimator User Guide
Provides more information about power estimation tools.
• PowerPlay Power Analysis chapter, Quartus II Handbook
Provides more information about power estimation tools.
(16)
This value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the
PDN tool for the additional budget for the dynamic tolerance requirements.
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I/O Pin Leakage Current
I/O Pin Leakage Current
Table 7: I/O Pin Leakage Current for Arria 10 Devices—Preliminary
If VO = VCCIO to VCCIOMAX, 300 μA of leakage current per I/O is expected.
Symbol
Description
Condition
Min
Max
Unit
II
Input pin
VI = 0 V to VCCIOMAX
–80
80
µA
IOZ
Tri-stated I/O pin
VO = 0 V to VCCIOMAX
–80
80
µA
Bus Hold Specifications
The bus-hold trip points are based on calculated input voltages from the JEDEC standard.
Table 8: Bus Hold Parameters for Arria 10 Devices—Preliminary
VCCIO (V)
Parameter
(17)
(18)
Symbol
Condition
1.2
1.5
1.8
2.5
3.0
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Bus-hold,
low,
sustaining
current
ISUSL
VIN > VIL
(max)
8 (17),
26 (18)
—
12 (17),
32 (18)
—
30 (17),
55 (18)
—
60
—
70
—
µA
Bus-hold,
high,
sustaining
current
ISUSH
VIN < VIH
(min)
–8 (17),
–26 (18)
—
–12 (17),
–32 (18)
—
–30 (17),
–55 (18)
—
–60
—
–70
—
µA
Bus-hold,
low,
overdrive
current
IODL
0 V < VIN
< VCCIO
—
125
—
175
—
200
—
300
—
500
µA
This value is only applicable for LVDS I/O bank.
This value is only applicable for 3 V I/O bank.
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OCT Calibration Accuracy Specifications
VCCIO (V)
Parameter
Symbol
Condition
1.2
1.5
1.8
2.5
3.0
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Bus-hold,
high,
overdrive
current
IODH
0 V < VIN
< VCCIO
—
–125
—
–175
—
–200
—
–300
—
–500
µA
Bus-hold
trip point
VTRIP
—
0.3
0.9
0.38
1.13
0.68
1.07
0.70
1.7
0.8
2
V
OCT Calibration Accuracy Specifications
If you enable on-chip termination (OCT) calibration, calibration is automatically performed at power up for I/Os connected to the calibration
block.
Table 9: OCT Calibration Accuracy Specifications for Arria 10 Devices—Preliminary
Calibration accuracy for the calibrated on-chip series termination (RS OCT) and on-chip parallel termination (RT OCT) are applicable at the moment of
calibration. When process, voltage, and temperature (PVT) conditions change after calibration, the tolerance may change.
Symbol
Description
Condition (V)
Calibration Accuracy
–E1, –I1
–E2, –I2
–E3, –I3
Unit
48-Ω, 60-Ω, 80-Ω,
and 240-Ω RS
Internal series termination with
calibration (48-Ω, 60-Ω, 80-Ω, and
240-Ω setting)
VCCIO = 1.2
±15
±15
±15
%
34-Ω and 40-Ω RS
Internal series termination with
calibration (34-Ω and 40-Ω setting)
VCCIO = 1.5, 1.35, 1.25,
1.2
±15
±15
±15
%
25-Ω RS
Internal series termination with
calibration
VCCIO = 1.8, 1.5, 1.2
±15
±15
±15
%
50-Ω RS
Internal series termination with
calibration
VCCIO = 1.8, 1.5, 1.2
±15
±15
±15
%
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OCT Without Calibration Resistance Tolerance Specifications
Symbol
Description
Condition (V)
POD12 I/O standard,
Calibration Accuracy
Unit
–E1, –I1
–E2, –I2
–E3, –I3
±15
±15
±15
%
34-Ω, 40-Ω, 48-Ω,
and 60-Ω RS
Internal series termination with
calibration (34-Ω, 40-Ω, 48-Ω, and
60-Ωsetting)
34-Ω, 40-Ω, 48-Ω,
60-Ω, 80-Ω, 120-Ω,
and 240-Ω RT
Internal parallel termination with
POD12 I/O standard,
calibration (34-Ω, 40-Ω, 48-Ω, 60-Ω,
VCCIO = 1.2
80-Ω, 120-Ω, and 240-Ω setting)
±15
±15
±15
%
60-Ω and 120-Ω RT
Internal parallel termination with
VCCIO = 1.5, 1.35, 1.25,
calibration (60-Ω and 120-Ω setting) 1.2
–10 to +40
–10 to +40
–10 to +40
%
VCCIO = 1.2
20-Ω, 30-Ω, and 40- Internal parallel termination with
Ω RT
calibration (20-Ω, 30-Ω, and 40-Ω
setting)
VCCIO = 1.5, 1.35, 1.25
–10 to +40
–10 to +40
–10 to +40
%
50-Ω RT
VCCIO = 1.8, 1.5, 1.2
–10 to +40
–10 to +40
–10 to +40
%
Internal parallel termination with
calibration (50-Ω setting)
13
OCT Without Calibration Resistance Tolerance Specifications
Table 10: OCT Without Calibration Resistance Tolerance Specifications for Arria 10 Devices—Preliminary
This table lists the Arria 10 OCT without calibration resistance tolerance to PVT changes.
Symbol
Description
Condition (V)
Resistance Tolerance
–E1, –I1
–E2, –I2
–E3, –I3
Unit
25-Ω RS
Internal series termination without
calibration
(25-Ω setting)
VCCIO = 1.8, 1.5
±25
±35
±40
%
VCCIO = 1.2
±25
±35
±40
%
50-Ω RS
Internal series termination without
calibration
(50-Ω setting)
VCCIO = 1.8, 1.5
±25
±35
±40
%
VCCIO = 1.2
±25
±35
±40
%
100-Ω RD
Internal differential termination
(100-Ω setting)
VCCIO = 1.8
±25
±35
±40
%
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Pin Capacitance
Figure 1: Equation for OCT Variation Without Recalibration—Preliminary
The definitions for the equation are as follows:
•
•
•
•
•
•
The ROCT value calculated shows the range of OCT resistance with the variation of temperature and VCCIO.
RSCAL is the OCT resistance value at power-up.
ΔT is the variation of temperature with respect to the temperature at power up.
ΔV is the variation of voltage with respect to the VCCIO at power up.
dR/dT is the percentage change of RSCAL with temperature.
dR/dV is the percentage change of RSCAL with voltage.
Pin Capacitance
Table 11: Pin Capacitance for Arria 10 Devices—Preliminary
Symbol
Description
Value
Unit
CIO_COLUMN
Input capacitance on column I/O pins
2.5
pF
COUTFB
Input capacitance on dual-purpose clock output/feedback pins
2.5
pF
Internal Weak Pull-Up Resistor
All I/O pins, except configuration, test, and JTAG pins, have an option to enable weak pull-up.
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I/O Standard Specifications
15
Table 12: Internal Weak Pull-Up Resistor Values for Arria 10 Devices—Preliminary
Symbol
Description
Value of the I/O pin pull-up resistor before and during
configuration, as well as user mode if you have enabled
the programmable pull-up resistor option.
RPU
Condition (V) (19)
Value (20)
Unit
VCCIO = 3.0 ±5%
25
kΩ
VCCIO = 2.5 ±5%
25
kΩ
VCCIO = 1.8 ±5%
25
kΩ
VCCIO = 1.5 ±5%
25
kΩ
VCCIO = 1.35 ±5%
25
kΩ
VCCIO = 1.25 ±5%
25
kΩ
VCCIO = 1.2 ±5%
25
kΩ
Related Information
Arria 10 Device Family Pin Connection Guidelines
Provides more information about the pins that support internal weak pull-up and internal weak pull-down features.
I/O Standard Specifications
Tables in this section list the input voltage (VIH and VIL), output voltage (VOH and VOL), and current drive characteristics (IOH and IOL) for various
I/O standards supported by Arria 10 devices.
For minimum voltage values, use the minimum VCCIO values. For maximum voltage values, use the maximum VCCIO values.
You must perform timing closure analysis to determine the maximum achievable frequency for general purpose I/O standards.
Related Information
Recommended Operating Conditions on page 4
(19)
(20)
Pin pull-up resistance values may be lower if an external source drives the pin higher than VCCIO.
Valid with ±10% tolerances to cover changes over PVT.
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Single-Ended I/O Standards Specifications
Single-Ended I/O Standards Specifications
Table 13: Single-Ended I/O Standards Specifications for Arria 10 Devices—Preliminary
VCCIO (V)
VIL (V)
VIH (V)
VOL (V)
VOH (V)
Min
Typ
Max
Min
Max
Min
Max
Max
Min
IOL (21)
(mA)
3.0-V
LVTTL
2.85
3
3.15
–0.3
0.8
1.7
3.3
0.4
2.4
2
–2
3.0-V
LVCMOS
2.85
3
3.15
–0.3
0.8
1.7
3.3
0.2
VCCIO – 0.2
0.1
–0.1
2.5 V
2.375
2.5
2.625
–0.3
0.7
1.7
3.3
0.4
2
1
–1
1.8 V
1.71
1.8
1.89
–0.3
0.35 × VCCIO
0.65 × VCCIO
VCCIO + 0.3
0.45
VCCIO – 0.45
2
–2
1.5 V
1.425
1.5
1.575
–0.3
0.35 × VCCIO
0.65 × VCCIO
VCCIO + 0.3
0.25 × VCCIO
0.75 × VCCIO
2
–2
1.2 V
1.14
1.2
1.26
–0.3
0.35 × VCCIO
0.65 × VCCIO
VCCIO + 0.3
0.25 × VCCIO
0.75 × VCCIO
2
–2
I/O Standard
IOH (21) (mA)
Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications
Table 14: Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications for Arria 10 Devices—Preliminary
I/O Standard
(21)
VCCIO (V)
VREF (V)
VTT (V)
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
SSTL-18
Class I, II
1.71
1.8
1.89
0.833
0.9
0.969
VREF – 0.04
VREF
VREF + 0.04
SSTL-15
Class I, II
1.425
1.5
1.575
0.49 × VCCIO
0.5 × VCCIO
0.51 × VCCIO
0.49 × VCCIO
0.5 × VCCIO
0.51 × VCCIO
SSTL-135
1.283
1.35
1.418
0.49 × VCCIO
0.5 × VCCIO
0.51 × VCCIO
0.49 × VCCIO
0.5 × VCCIO
0.51 × VCCIO
SSTL-125
1.19
1.25
1.31
0.49 × VCCIO
0.5 × VCCIO
0.51 × VCCIO
0.49 × VCCIO
0.5 × VCCIO
0.51 × VCCIO
To meet the IOL and IOH specifications, you must set the current strength settings accordingly. For example, to meet the 3.0-V LVTTL specification
(2 mA), you should set the current strength settings to 2 mA. Setting at lower current strength may not meet the IOL and IOH specifications in the
datasheet.
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Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications
VCCIO (V)
I/O Standard
VREF (V)
VTT (V)
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
SSTL-12
1.14
1.2
1.26
0.49 × VCCIO
0.5 × VCCIO
0.51 × VCCIO
0.49 × VCCIO
0.5 × VCCIO
0.51 × VCCIO
HSTL-18
Class I, II
1.71
1.8
1.89
0.85
0.9
0.95
—
VCCIO/2
—
HSTL-15
Class I, II
1.425
1.5
1.575
0.68
0.75
0.9
—
VCCIO/2
—
HSTL-12
Class I, II
1.14
1.2
1.26
0.47 × VCCIO
0.5 × VCCIO
0.53 × VCCIO
—
VCCIO/2
—
HSUL-12
1.14
1.2
1.3
0.49 × VCCIO
0.5 × VCCIO
0.51 × VCCIO
—
—
—
POD12
1.16
1.2
1.24
0.69 × VCCIO
0.7 × VCCIO
0.71 × VCCIO
—
VCCIO
—
Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications
Table 15: Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications for Arria 10 Devices—Preliminary
(22)
VIL(DC) (V)
VIH(DC) (V)
VIL(AC) (V)
VIH(AC) (V)
VOL (V)
VOH (V)
Min
Max
Min
Max
Max
Min
Max
Min
IOL (22)
(mA)
SSTL-18
Class I
–0.3
VREF –0.125
VREF + 0.125
VCCIO + 0.3
VREF – 0.25
VREF + 0.25
VTT – 0.603
VTT + 0.603
6.7
–6.7
SSTL-18
Class II
–0.3
VREF –0.125
VREF + 0.125
VCCIO + 0.3
VREF – 0.25
VREF + 0.25
0.28
VCCIO –0.28
13.4
–13.4
SSTL-15
Class I
—
VREF – 0.1
VREF + 0.1
—
VREF – 0.175
VREF + 0.175
0.2 × VCCIO
0.8 × VCCIO
8
–8
SSTL-15
Class II
—
VREF – 0.1
VREF + 0.1
—
VREF – 0.175
VREF + 0.175
0.2 × VCCIO
0.8 × VCCIO
16
–16
I/O Standard
IOH (22)
(mA)
To meet the IOL and IOH specifications, you must set the current strength settings accordingly. For example, to meet the SSTL15CI specification
(8 mA), you should set the current strength settings to 8 mA. Setting at lower current strength may not meet the IOL and IOH specifications in the
datasheet.
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VIL(DC) (V)
VIH(DC) (V)
VIL(AC) (V)
VIH(AC) (V)
VOL (V)
VOH (V)
Min
Max
Min
Max
Max
Min
Max
Min
IOL (22)
(mA)
SSTL-135
—
VREF – 0.09
VREF + 0.09
—
VREF – 0.16
VREF + 0.16
0.2 × VCCIO
0.8 × VCCIO
—
—
SSTL-125
—
VREF – 0.09
VREF + 0.09
—
VREF – 0.15
VREF + 0.15
0.2 × VCCIO
0.8 × VCCIO
—
—
SSTL-12
—
VREF – 0.10
VREF + 0.10
—
VREF – 0.15
VREF + 0.15
0.2 × VCCIO
0.8 × VCCIO
—
—
HSTL-18
Class I
—
VREF –0.1
VREF + 0.1
—
VREF – 0.2
VREF + 0.2
0.4
VCCIO – 0.4
8
–8
HSTL-18
Class II
—
VREF – 0.1
VREF + 0.1
—
VREF – 0.2
VREF + 0.2
0.4
VCCIO – 0.4
16
–16
HSTL-15
Class I
—
VREF – 0.1
VREF + 0.1
—
VREF – 0.2
VREF + 0.2
0.4
VCCIO – 0.4
8
–8
HSTL-15
Class II
—
VREF – 0.1
VREF + 0.1
—
VREF – 0.2
VREF + 0.2
0.4
VCCIO –0.4
16
–16
HSTL-12
Class I
–0.15
VREF – 0.08
VREF + 0.08
VCCIO + 0.15
VREF – 0.15
VREF + 0.15
0.25 × VCCIO
0.75 × VCCIO
8
–8
HSTL-12
Class II
–0.15
VREF – 0.08
VREF + 0.08
VCCIO + 0.15
VREF – 0.15
VREF + 0.15
0.25 × VCCIO
0.75 × VCCIO
16
–16
HSUL-12
—
VREF – 0.13
VREF + 0.13
—
VREF – 0.22
VREF + 0.22
0.1 × VCCIO
0.9 × VCCIO
—
—
–0.15
VREF – 0.08
VREF + 0.08
VCCIO + 0.15
VREF – 0.15
VREF + 0.15
(0.7 – 0.15) ×
VCCIO
(0.7 + 0.15) ×
VCCIO
—
—
I/O Standard
POD12
(22)
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Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications
IOH (22)
(mA)
To meet the IOL and IOH specifications, you must set the current strength settings accordingly. For example, to meet the SSTL15CI specification
(8 mA), you should set the current strength settings to 8 mA. Setting at lower current strength may not meet the IOL and IOH specifications in the
datasheet.
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Differential SSTL I/O Standards Specifications
19
Differential SSTL I/O Standards Specifications
Table 16: Differential SSTL I/O Standards Specifications for Arria 10 Devices—Preliminary
I/O Standard
VCCIO (V)
VSWING(DC) (V)
VSWING(AC) (V)
VIX(AC) (V)
Min
Typ
Max
Min
Max
Min
Max
Min
Typ
Max
SSTL-18 Class I,
II
1.71
1.8
1.89
0.25
VCCIO + 0.6
0.5
VCCIO + 0.6
VCCIO/2 –
0.175
—
VCCIO/2 + 0.175
SSTL-15 Class I,
II
1.425
1.5
1.575
0.2
(23)
2(VIH(AC) –
VREF)
2(VREF –
VIL(AC))
VCCIO/2 –
0.15
—
VCCIO/2 + 0.15
SSTL-135
1.283
1.35
1.45
0.18
(23)
2(VIH(AC) –
VREF)
2(VIL(AC) –
VREF)
VCCIO/2 –
0.15
VCCIO/2
VCCIO/2 + 0.15
SSTL-125
1.19
1.25
1.31
0.18
(23)
2(VIH(AC) –
VREF)
2(VIL(AC) –
VREF)
VCCIO/2 –
0.15
VCCIO/2
VCCIO/2 + 0.15
SSTL-12
1.14
1.2
1.26
0.16
(23)
2(VIH(AC) –
VREF)
2(VIL(AC) –
VREF)
VREF – 0.15
VCCIO/2
VREF + 0.15
POD12
1.16
1.2
1.24
0.16
—
0.3
—
VREF – 0.08
—
VREF + 0.08
Differential HSTL and HSUL I/O Standards Specifications
Table 17: Differential HSTL and HSUL I/O Standards Specifications for Arria 10 Devices—Preliminary
VCCIO (V)
I/O Standard
(23)
VDIF(DC) (V)
VDIF(AC) (V)
VIX(AC) (V)
VCM(DC) (V)
Min
Typ
Max
Min
Max
Min
Max
Min
Typ
Max
Min
Typ
Max
HSTL-18
Class I, II
1.71
1.8
1.89
0.2
—
0.4
—
0.78
—
1.12
0.78
—
1.12
HSTL-15
Class I, II
1.425
1.5
1.575
0.2
—
0.4
—
0.68
—
0.9
0.68
—
0.9
The maximum value for VSWING(DC) is not defined. However, each single-ended signal needs to be within the respective single-ended limits (VIH(DC)
and VIL(DC)).
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Differential I/O Standards Specifications
I/O Standard
VCCIO (V)
VDIF(DC) (V)
VDIF(AC) (V)
VIX(AC) (V)
VCM(DC) (V)
Min
Typ
Max
Min
Max
Min
Max
Min
Typ
Max
Min
Typ
Max
HSTL-12
Class I, II
1.14
1.2
1.26
0.16
VCCIO +
0.3
0.3
VCCIO +
0.48
—
0.5 ×
VCCIO
—
0.4 ×
VCCIO
0.5 ×
VCCIO
0.6 ×
VCCIO
HSUL-12
1.14
1.2
1.3
2(VIH(DC)
– VREF)
2(VREF –
VIH(DC))
2(VIH(AC)
– VREF)
2(VREF –
VIH(AC))
0.5 ×
VCCIO –
0.12
0.5 ×
VCCIO
0.5 ×
VCCIO
+0.12
0.4 ×
VCCIO
0.5 ×
VCCIO
0.6 ×
VCCIO
Differential I/O Standards Specifications
Table 18: Differential I/O Standards Specifications for Arria 10 Devices—Preliminary
Differential inputs are powered by VCCPT which requires 1.8 V.
I/O Standard
PCML
LVDS
(24)
(26)
(27)
(28)
Min
Typ
Max
Min
Condition
VICM(DC) (V)
Max
Min
Condition
VOD (V)
Max
Min
Typ
(25)
VOCM (V)
Max
Min
Typ
(25)
Max
Transmitter, receiver, and input reference clock pins of high-speed transceivers use the CML I/O standard. For transmitter, receiver, and
reference clock I/O pin specifications, refer to Transceiver Specifications for Arria 10 GX, SX, and GT Devices table.
VCM =
1.25 V
—
0
DMAX
≤700 Mbps
1.85
1
DMAX >
700 Mbps
1.6
1.71
1.8
1.89
100
RSDS (HIO)
1.71
1.8
1.89
100
VCM =
1.25 V
—
0.3
—
Mini-LVDS
(HIO) (28)
1.71
1.8
1.89
200
—
600
0.4
—
(26)
(27)
(25)
VID (mV) (24)
VCCIO (V)
0.247
—
0.6
1.125
1.25
1.375
1.4
0.1
0.2
0.6
0.5
1.2
1.4
1.325
0.25
—
600
1
1.2
1.4
The minimum VID value is applicable over the entire common mode range, VCM.
RL range: 90 ≤ RL ≤ 110 Ω.
For optimized LVDS receiver performance, the receiver voltage input range must be within 1.0 V to 1.6 V for data rates above 700 Mbps and 0 V to
1.85 V for data rates below 700 Mbps.
For optimized RSDS receiver performance, the receiver voltage input range must be within 0.3 V to 1.4 V.
For optimized Mini-LVDS receiver performance, the receiver voltage input range must be within 0.4 V to 1.325 V.
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Switching Characteristics
I/O Standard
LVPECL (29)
VID (mV) (24)
VCCIO (V)
Min
1.71
Typ
1.8
Max
1.89
Min
300
Condition
—
VICM(DC) (V)
Max
—
VOD (V)
Min
Condition
Max
0.6
DMAX
≤700 Mbps
1.7
1
DMAX >
700 Mbps
1.6
(25)
VOCM (V)
(25)
Min
Typ
Max
Min
Typ
Max
—
—
—
—
—
—
Related Information
Transceiver Specifications for Arria 10 GX, SX, and GT Devices
Provides the specifications for transmitter, receiver, and reference clock I/O pin.
Switching Characteristics
This section provides the performance characteristics of Arria 10 core and periphery blocks for extended grade devices.
(24)
(25)
(29)
The minimum VID value is applicable over the entire common mode range, VCM.
RL range: 90 ≤ RL ≤ 110 Ω.
For optimized LVPECL receiver performance, the receiver voltage input range must be within 0.85 V to 1.75 V for data rates above 700 Mbps and
0.45 V to 1.95 V for data rates below 700 Mbps.
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Transceiver Performance Specifications
Transceiver Performance Specifications
Transceiver Performance for Arria 10 GX/SX Devices
Table 19: Transmitter and Receiver Data Rate Performance—Preliminary
Symbol/Description
Condition
Transceiver
Speed Grade
1
Transceiver
Speed Grade
2
Transceiver
Speed Grade
3
Transceiver
Speed Grade
4
Transceiver
Speed Grade
5 (30)
Unit
17.4
15
14.2
12.5
8
Gbps
11.3
11.3
11.3
11.3
8
Gbps
Maximum
data rate
VCCR_GXB =
VCCT_GXB =
1.03 V
Chip-to-Chip (31)
Backplane (31)
(30)
(31)
(32)
Maximum
data rate
VCCR_GXB =
VCCT_GXB =
0.95 V
TX Minimum
Data Rate
611
RX Minimum
Data Rate
1.0 (32)
Maximum
data rate
16
14.2
12.5
Mbps
Gbps
10.3125
6.5536
Gbps
Transceiver speed grade 5 supports PCIe Gen3.
Backplane applications assume advanced equalization circuitry, such as decision feedback equalization (DFE), is enabled to compensate for signal
impairments. Chip-to-chip links are assumed to be applications with short reach channels that do not require DFE.
Arria 10 transceivers can support data rates down to 125 Mbps with over sampling.
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Transceiver Performance for Arria 10 GX/SX Devices
Symbol/Description
Condition
Transceiver
Speed Grade
1
Transceiver
Speed Grade
2
Transceiver
Speed Grade
3
Transceiver
Speed Grade
4
Transceiver
Speed Grade
5 (30)
Unit
10.3125
10.3125
10.3125
10.3125
6.5536
Gbps
23
VCCR_GXB =
VCCT_GXB =
1.03 V
Maximum
data rate
VCCR_GXB =
VCCT_GXB =
0.95 V
TX Minimum
Data Rate
611
RX Minimum
Data Rate
1.0 (32)
Mbps
Gbps
Table 20: ATX PLL Performance—Preliminary
Symbol/Description
Supported Output
Frequency
(30)
Condition
Maximum
Frequency
Transceiver
Speed Grade 1
Transceiver
Speed Grade 2
Transceiver
Speed Grade 3
Transceiver
Speed Grade 4
Transceiver
Speed Grade 5
Unit
8.7
7.5
7.1
6.25
4
GHz
Minimum
Frequency
305.5
MHz
Transceiver speed grade 5 supports PCIe Gen3.
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High-Speed Serial Transceiver-Fabric Interface Performance for Arria 10...
Table 21: Fractional PLL Performance—Preliminary
Symbol/Description
Supported Output
Frequency
Condition
Transceiver
Speed Grade 1
Transceiver
Speed Grade 2
Transceiver
Speed Grade 3
Transceiver
Speed Grade 4
Transceiver
Speed Grade 5
Unit
6.25
6.25
6.25
6.25
4
GHz
Maximum
Frequency
Minimum
Frequency
305.5
MHz
Table 22: CMU PLL Performance—Preliminary
Symbol/Description
Supported Output
Frequency
Condition
Maximum
Frequency
Transceiver
Speed Grade 1
Transceiver
Speed Grade 2
Transceiver
Speed Grade 3
Transceiver
Speed Grade 4
Transceiver
Speed Grade 5
Unit
5.15625
5.15625
5.15625
5.15625
4
GHz
Minimum
Frequency
305.5
MHz
Related Information
Transceiver Power Supply Operating Conditions on page 6
High-Speed Serial Transceiver-Fabric Interface Performance for Arria 10 GX/SX Devices
Table 23: High-Speed Serial Transceiver-Fabric Interface Performance for Arria 10 GX/SX Devices—Preliminary
Core Speed Grade with Power Options
Symbol/Description
Condition (V)
-E1M /
-I1M
-E1L / -E1S / -I1L
-E2L / -I2L
-E3S /
-I3S / M3
Unit
20-bit interface - FIFO
VCC = 0.9
516
516
400
400
MHz
20-bit interface - Registered
VCC = 0.9
491
491
400
400
MHz
32-bit interface - FIFO
VCC = 0.9
441
441
404
335
MHz
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High-Speed Serial Transceiver-Fabric Interface Performance for Arria 10...
25
Core Speed Grade with Power Options
Symbol/Description
Condition (V)
-E1M /
-I1M
-E1L / -E1S / -I1L
-E2L / -I2L
-E3S /
-I3S / M3
Unit
32-bit interface - Registered
VCC = 0.9
441
441
404
335
MHz
64-bit interface - FIFO
VCC = 0.9
272
272
234
222
MHz
64-bit interface - Registered
VCC = 0.9
272
272
234
222
MHz
PCIe Gen3 HIP-Fabric interface
VCC = 0.9
300
300
250
250
MHz
20-bit interface - FIFO
VCC = 0.83
400
—
—
—
MHz
20-bit interface - Registered
VCC = 0.83
400
—
—
—
MHz
32-bit interface - FIFO
VCC = 0.83
335
—
—
—
MHz
32-bit interface - Registered
VCC = 0.83
335
—
—
—
MHz
64-bit interface - FIFO
VCC = 0.83
222
—
—
—
MHz
64-bit interface - Registered
VCC = 0.83
222
—
—
—
MHz
PCIe Gen3 HIP-Fabric interface
VCC = 0.83
250
—
—
—
MHz
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Transceiver Performance for Arria 10 GT Devices
Transceiver Performance for Arria 10 GT Devices
Table 24: Transmitter and Receiver Data Rate Performance—Preliminary
Symbol/Description
Chip-to-chip (33)
Condition
GT Channel
VCCR_GXB = VCCT_GXB = 1.11
V
(34)
28.3/28.1 (35)
26
20
Gbps
GX Channel
17.4
15
15
Gbps
Maximum data rate
GT Channel
VCCR_GXB = VCCT_GXB = 1.03
V
GX Channel
15
14.2
12.5
Gbps
Maximum data rate
GT Channel
VCCR_GXB = VCCT_GXB = 0.95
V
GX Channel
11.3
11.3
11.3
Gbps
RX Minimum data rate
(34)
(35)
(36)
Unit
Maximum data rate
TX Minimum data rate
(33)
Transceiver
Transceiver
Transceiver
Speed Grade 2 Speed Grade 3 Speed Grade 4
GT Channel
GX Channel
GT Channel
GX Channel
611
Mbps
1.0 (36)
Gbps
Backplane applications assume advanced equalization circuitry, such as decision feedback equalization (DFE), is enabled to compensate for signal
impairments. Chip-to-chip links are assumed to be applications with short reach channels that do not require DFE.
GT channels are only available when VCCT_GXB = 1.1 V and VCCR_GXB = 1.1 V.
To achieve 28.3 Gbps, you must use a -1 core speed grade and a -2 transceiver speed grade device configuration. To achieve 28.1 Gbps, you must use
a -2 core speed grade and a -2 transceiver speed grade device configuration.
Arria 10 transceivers can support data rates down to 125 Mbps with over sampling.
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Transceiver Performance for Arria 10 GT Devices
Symbol/Description
Backplane (33)
Condition
Transceiver
Transceiver
Transceiver
Speed Grade 2 Speed Grade 3 Speed Grade 4
Maximum data rate
GT Channel
VCCR_GXB = VCCT_GXB = 1.11
V
GX Channel
Maximum data rate
GT Channel
VCCR_GXB = VCCT_GXB = 1.03
V
GX Channel
Maximum data rate
GT Channel
VCCR_GXB = VCCT_GXB = 0.95
V
GX Channel
TX Minimum data rate
RX Minimum data rate
Unit
17.4
14.2
14.2
Gbps
14.2
12.5
10.3125
Gbps
10.3125
10.3125
10.3125
Gbps
GT Channel
GX Channel
GT Channel
GX Channel
27
611
Mbps
1.0 (36)
Gbps
Table 25: ATX PLL Performance—Preliminary
Symbol/Description
Supported Output
Frequency
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Condition
Maximum
frequency
Minimum
frequency
Transceiver Speed
Grade 2
Transceiver Speed
Grade 3
Transceiver Speed
Grade 4
Unit
14.15
13
10
GHz
305.5
MHz
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Table 26: Fractional PLL Performance—Preliminary
Symbol/Description
Supported Output
Frequency
Condition
Transceiver Speed
Grade 2
Transceiver Speed
Grade 3
Transceiver Speed
Grade 4
Unit
Maximum
frequency
6.25
GHz
Minimum
frequency
305.5
MHz
Table 27: CMU PLL Performance—Preliminary
Symbol/Description
Supported Output
Frequency
Condition
Maximum
frequency
Transceiver Speed
Grade 2
Transceiver Speed
Grade 3
Transceiver Speed
Grade 4
Unit
5.15625
5.15625
5.15625
GHz
Minimum
frequency
305.5
MHz
Related Information
Transceiver Power Supply Operating Conditions on page 6
High-Speed Serial Transceiver-Fabric Interface Performance for Arria 10 GT Devices
Table 28: High-Speed Serial Transceiver-Fabric Interface Performance for Arria 10 GT Devices—Preliminary
Symbol/Description
Condition (V)
Core Speed Grade with Power Options
-1
-2
-3
Unit
20-bit interface - FIFO
VCC = 0.9
516
400
400
MHz
20-bit interface - Registered
VCC = 0.9
491
400
400
MHz
32-bit interface - FIFO
VCC = 0.9
441
404
335
MHz
32-bit interface - Registered
VCC = 0.9
441
404
335
MHz
64-bit interface - FIFO
VCC = 0.9
439
407
313
MHz
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Transceiver Specifications for Arria 10 GX, SX, and GT Devices
Symbol/Description
Condition (V)
Core Speed Grade with Power Options
-1
-2
-3
29
Unit
64-bit interface - Registered
VCC = 0.9
439
407
313
MHz
PCIe Gen3 HIP-Fabric interface
VCC = 0.9
300
250
250
MHz
Transceiver Specifications for Arria 10 GX, SX, and GT Devices
Table 29: Reference Clock Specifications—Preliminary
Symbol/Description
Supported I/O Standards
Condition
Transceiver Speed Grades 1, 2, 3, 4, and 5
Min
Dedicated reference clock
pin
Typ
Max
Unit
CML, Differential LVPECL, LVDS, and HCSL
RX reference clock pin
CML, Differential LVPECL, and LVDS
Input Reference Clock Frequency (CMU
PLL)
61
—
800
MHz
Input Reference Clock Frequency (ATX
PLL)
100
—
800
MHz
Input Reference Clock Frequency (fPLL
PLL)
20
—
800
MHz
Rise time
20% to 80%
—
—
400
ps
Fall time
80% to 20%
—
—
400
ps
Duty cycle
—
45
—
55
%
Spread-spectrum modulating clock
frequency
PCI Express® (PCIe®)
30
—
33
kHz
Spread-spectrum downspread
PCIe
—
0 to –0.5
—
%
On-chip termination resistors
—
—
100
—
Ω
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Symbol/Description
Absolute VMAX
Condition
Transceiver Speed Grades 1, 2, 3, 4, and 5
Unit
Min
Typ
Max
Dedicated reference clock
pin
—
—
1.6
V
RX reference clock pin
—
—
1.2
V
Absolute VMIN
—
–0.4
—
—
V
Peak-to-peak differential input voltage
—
200
—
1600
mV
VCCR_GXB = 0.95 V
—
600
—
mV
VCCR_GXB = 1.03 V
—
700
—
mV
VCCR_GXB = 1.11 V
—
700
—
mV
HCSL I/O standard for
PCIe reference clock
250
—
550
mV
100 Hz
—
—
–70
dBc/Hz
1 kHz
—
—
–90
dBc/Hz
10 kHz
—
—
–100
dBc/Hz
100 kHz
—
—
–110
dBc/Hz
≥ 1 MHz
—
—
–120
dBc/Hz
Transmitter REFCLK Phase Jitter (100
MHz)
10 kHz to 1.5 MHz
(PCIe)
—
—
3
ps (rms)
RREF
—
—
2.0 k ±1%
—
Ω
VICM (AC coupled)
VICM (DC coupled)
Transmitter REFCLK Phase Noise (622
MHz) (37)
(37)
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Transceiver Specifications for Arria 10 GX, SX, and GT Devices
To calculate the REFCLK phase noise requirement at frequencies other than 622 MHz, use the following formula: REFCLK phase noise at f (MHz) =
REFCLK phase noise at 622 MHz + 20*log(f/622).
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Transceiver Specifications for Arria 10 GX, SX, and GT Devices
31
Table 30: Transceiver Clocks Specifications—Preliminary
Symbol/Description
CLKUSR pin for transceiver
calibration
reconfig_clk
Transceiver Speed Grades 1, 2, 3, 4, and 5
Condition
Unit
Min
Typ
Max
Transceiver
Calibration
100
—
125
MHz
Reconfiguration
interface
100
—
125
MHz
Channel Span
Unit
Table 31: Transceiver Clock Network Maximum Data Rate Specifications
Clock Network
(38)
Maximum Performance
ATX (38)
fPLL
CMU
x1
17.4
12.5
10.3125
6 channels
Gbps
x6
17.4
12.5
N/A
6 channels
Gbps
x6 PLL feedback
17.4
12.5
N/A
Side-wide
Gbps
xN at 0.95 V
10.5
10.5
N/A
Up two banks and
down two banks
Gbps
xN at 1.03 V
15.0
12.5
N/A
Up two banks and
down two banks
Gbps
xN at 1.11 V
16.0
12.5
N/A
Up two banks and
down two banks
Gbps
ATX maximum data rate support per speed grade.
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Table 32: Receiver Specifications—Preliminary
Symbol/Description
(42)
Typ
Max
Unit
Absolute VMAX for a
receiver pin (40)
—
—
—
1.2
V
Absolute VMIN for a
receiver pin
—
-0.4
—
—
V
Maximum peak-to-peak
differential input voltage
VID (diff p-p) before device
configuration (41)
—
—
—
1.6
V
VCCR_GXB = 1.11 V
—
—
2.0
V
VCCR_GXB = 1.03 V
—
—
2.0
V
VCCR_GXB = 0.95 V
—
—
2.4
V
—
50
—
—
mV
85-Ω setting
—
85 ± 30%
—
Ω
100-Ω setting
—
100 ± 30%
—
Ω
Differential on-chip
termination resistors
(41)
Min
—
Minimum differential eye
opening at receiver serial
input pins (42)
(39)
Transceiver Speed Grades 1, 2, 3, 4, and 5
Supported I/O Standards
Maximum peak-to-peak
differential input voltage
VID (diff p-p) after device
configuration (41)
(40)
Condition
High Speed Differential I/O (39), CML, Differential LVPECL, and LVDS
High Speed Differential I/O is the dedicated I/O standard for the transmitter in Arria 10 transceivers.
The device cannot tolerate prolonged operation at this absolute maximum.
DC coupling specifications are pending silicon characterization.
The differential eye opening specification at the receiver input pins assumes that Receiver Equalization is disabled. If you enable Receiver Equaliza‐
tion, the receiver circuitry can tolerate a lower minimum eye opening, depending on the equalization level.
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Transceiver Specifications for Arria 10 GX, SX, and GT Devices
Symbol/Description
(45)
(46)
Unit
Typ
Max
VCCR_GXB = 0.95 V
—
600
—
mV
VICM (AC and DC coupled) VCCR_GXB = 1.03 V
—
700
—
mV
VCCR_GXB = 1.11 V
—
700
—
mV
tLTR(43)
—
—
—
10
µs
tLTD(44)
—
4
—
—
µs
tLTD_manual(45)
—
4
—
—
µs
tLTR_LTD_manual(46)
—
15
—
—
µs
Run Length
—
—
—
200
UI
PCIe-only
-300
—
300
PPM
All other protocols
-1000
—
1000
PPM
DC Gain Setting = 0
—
-10
—
dB
DC Gain Setting = 1
—
-6.5
—
dB
DC Gain Setting = 2
—
-3
—
dB
DC Gain Setting = 3
—
0.5
—
dB
DC Gain Setting = 4
—
4
—
dB
Programmable DC Gain
(43)
Transceiver Speed Grades 1, 2, 3, 4, and 5
Min
CDR PPM tolerance
(44)
Condition
33
tLTR is the time required for the receive CDR to lock to the input reference clock frequency after coming out of reset.
tLTD is time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodata signal goes high.
tLTD_manual is the time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodata signal goes high when the CDR is
functioning in the manual mode.
tLTR_LTD_manual is the time the receiver CDR must be kept in lock to reference (LTR) mode after the rx_is_lockedtoref signal goes high when the
CDR is functioning in the manual mode.
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Transceiver Specifications for Arria 10 GX, SX, and GT Devices
Table 33: Transmitter Specifications—Preliminary
Symbol/Description
Supported I/O Standards
Condition
Transceiver Speed Grades 1, 2, 3, 4, and 5
Min
—
Typ
Unit
Max
High Speed Differential I/O (47)
—
85-Ω setting
—
85 ± 20%
—
Ω
100-Ω setting
—
100 ± 20%
—
Ω
120-Ω setting
—
120 ± 20%
—
Ω
150-Ω setting
—
150 ± 20%
—
Ω
VCCT = 0.95 V
—
450
—
mV
VCCT = 1.03 V
—
500
—
mV
VCCT = 1.11 V
—
550
—
mV
VCCT = 0.95 V
—
450
—
mV
VCCT = 1.03 V
—
500
—
mV
VCCT = 1.11 V
—
550
—
mV
Rise time (48)
20% to 80%
20
—
130
ps
Fall time (48)
80% to 20%
20
—
130
ps
Intra-differential pair skew
TX VCM = 0.5 V and
slew rate of 15 ps
—
—
15
ps
Differential on-chip
termination resistors
VOCM (AC coupled)
VOCM (DC coupled)
Table 34: Typical Transmitter VOD Settings—Preliminary
(47)
(48)
Symbol
VOD Setting
VOD/VCCT Ratio
VOD differential value = VOD/VCCT ratio x VCCT
31
1.00
High Speed Differential I/O is the dedicated I/O standard for the transmitter in Arria 10 transceivers.
The Quartus II software automatically selects the appropriate slew rate depending on the configured data rate or functional mode.
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Transceiver Specifications for Arria 10 GX, SX, and GT Devices
Symbol
Arria 10 Device Datasheet
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VOD Setting
VOD/VCCT Ratio
30
0.97
29
0.93
28
0.90
27
0.87
26
0.83
25
0.80
24
0.77
23
0.73
22
0.70
21
0.67
20
0.63
19
0.60
18
0.57
17
0.53
16
0.50
15
0.47
14
0.43
13
0.40
12
0.37
35
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Core Performance Specifications
Core Performance Specifications
Clock Tree Specifications
Table 35: Clock Tree Performance for Arria 10 Devices—Preliminary
Performance
Parameter
–E1L,–E1M (49), –E1S, –I1L,
–I1M (49), –I1S
–E2L, –E2S, –I2L, –I2S
–E1M (50), –I1M (50), –E3S,
–I3S
Unit
Global clock, regional clock, and small
periphery clock
644
644
644
MHz
Large periphery clock
525
525
525
MHz
PLL Specifications
Fractional PLL Specifications
Table 36: Fractional PLL Specifications for Arria 10 Devices—Preliminary
Symbol
fIN
(49)
(50)
(51)
Parameter
Input clock frequency
fINPFD
Input clock frequency to the phase
frequency detector (PFD)
fVCO
PLL voltage-controlled oscillator
(VCO) operating range
Condition
Min
Typ
–1 speed grade
50
–2 speed grade
Max
Unit
—
1000
(51)
MHz
50
—
TBD (51)
MHz
–3 speed grade
50
—
TBD (51)
MHz
—
50
—
325
MHz
–1, –2, –3 speed
grade
3.125
—
6.25
GHz
When you power VCC and VCCP at nominal voltage of 0.90 V.
When you power VCC and VCCP at lower voltage of 0.83 V.
This specification is limited in the Quartus II software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O
standard.
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Fractional PLL Specifications
Symbol
(53)
(54)
Condition
Min
Typ
Max
Unit
—
40
—
60
%
–1, –2, –3 speed
grade
—
—
644
MHz
tEINDUTY
Input clock duty cycle
fOUT
Output frequency for internal
global or regional clock
fDYCONFIGCLK
Dynamic configuration clock for
mgmt_clk and scanclk
—
—
—
100
MHz
tLOCK
Time required to lock from end-ofdevice configuration or deassertion
of areset
—
—
—
1
ms
tDLOCK
Time required to lock dynamically
(after switchover or reconfiguring
any non-post-scale counters/delays)
—
—
—
1
ms
Low
—
TBD
—
MHz
Medium
—
TBD
—
MHz
High
—
TBD
—
MHz
fCLBW
(52)
Parameter
PLL closed-loop bandwidth
tPLL_PSERR
Accuracy of PLL phase shift
—
—
—
±50
ps
tARESET
Minimum pulse width on the
areset signal
—
10
—
—
ns
tINCCJ (52)(53)
Input clock cycle-to-cycle jitter
FREF ≥ 100 MHz
—
—
TBD
UI (p-p)
FREF < 100 MHz
—
—
TBD
ps (p-p)
tFOUTPJ (54)
Period jitter for clock output in
fractional mode
FOUT ≥ 100 MHz
—
—
TBD
ps (p-p)
FOUT < 100 MHz
—
—
TBD
mUI (p-p)
37
A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source with jitter
< 120 ps.
FREF is fIN/N, specification applies when N = 1.
External memory interface clock output jitter specifications use a different measurement method, which are available in Memory Output Clock Jitter
Specification for Arria 10 Devices table.
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I/O PLL Specifications
Symbol
Parameter
Condition
Min
Typ
Max
Unit
tFOUTCCJ (54)
Cycle-to-cycle jitter for clock
output in fractional mode
FOUT ≥ 100 MHz
—
—
TBD
ps (p-p)
FOUT < 100 MHz
—
—
TBD
mUI (p-p)
tOUTPJ (54)
Period jitter for clock output in
integer mode
FOUT ≥ 100 MHz
—
—
TBD
ps (p-p)
FOUT < 100 MHz
—
—
TBD
mUI (p-p)
tOUTCCJ (54)
Cycle-to-cycle jitter for clock
output in integer mode
FOUT ≥ 100 MHz
—
—
TBD
ps (p-p)
FOUT < 100 MHz
—
—
TBD
mUI (p-p)
dKBIT
Bit number of Delta Sigma
Modulator (DSM)
—
—
32
—
bit
Related Information
Memory Output Clock Jitter Specifications on page 54
Provides more information about the external memory interface clock output jitter specifications.
I/O PLL Specifications
Table 37: I/O PLL Specifications for Arria 10 Devices—Preliminary
Symbol
fIN
fINPFD
fVCO
(55)
Parameter
Input clock frequency
Input clock frequency to the PFD
PLL VCO operating range
Condition
Min
Typ
Max
Unit
–1 speed grade
10
—
800 (55)
MHz
–2 speed grade
10
—
700 (55)
MHz
–3 speed grade
10
—
650
MHz
—
10
—
325
MHz
–1 speed grade
600
—
1600
MHz
–2 speed grade
600
—
1434
MHz
–3 speed grade
600
—
1250
MHz
(55)
This specification is limited in the Quartus II software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O
standard.
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I/O PLL Specifications
Symbol
Parameter
Condition
Min
Typ
Max
Unit
fCLBW
PLL closed-loop bandwidth
—
0.1
—
8
MHz
tEINDUTY
Input clock or external feedback
clock input duty cycle
—
40
—
60
%
fOUT
Output frequency for internal global
or regional clock (C counter)
–1, –2, –3 speed
grade
—
—
644
MHz
–1 speed grade
—
—
800
MHz
–2 speed grade
—
—
720
MHz
–3 speed grade
—
—
650
MHz
fOUT_EXT
Output frequency for external clock
output
tOUTDUTY
Duty cycle for dedicated external
clock output (when set to 50%)
—
45
50
55
%
tFCOMP
External feedback clock
compensation time
—
—
—
10
ns
fDYCONFIGCLK
Dynamic configuration clock for
mgmt_clk and scanclk
—
—
—
100
MHz
tLOCK
Time required to lock from end-ofdevice configuration or deassertion
of areset
—
—
—
1
ms
tDLOCK
Time required to lock dynamically
(after switchover or reconfiguring
any non-post-scale counters/delays)
—
—
—
1
ms
tPLL_PSERR
Accuracy of PLL phase shift
—
—
—
±50
ps
tARESET
Minimum pulse width on the areset
signal
—
10
—
—
ns
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I/O PLL Specifications
Symbol
Parameter
Condition
Min
Typ
Max
Unit
FREF ≥ 100 MHz
—
—
TBD
UI (p-p)
FREF < 100 MHz
—
—
TBD
ps (p-p)
tINCCJ (56)(57)
Input clock cycle-to-cycle jitter
tOUTPJ_DC
Period jitter for dedicated clock
output
FOUT ≥ 100 MHz
—
—
TBD
ps (p-p)
FOUT < 100 MHz
—
—
TBD
mUI (p-p)
tOUTCCJ_DC
Cycle-to-cycle jitter for dedicated
clock output
FOUT ≥ 100 MHz
—
—
TBD
ps (p-p)
FOUT < 100 MHz
—
—
TBD
mUI (p-p)
tOUTPJ_IO (58)
Period jitter for clock output on the
regular I/O
FOUT ≥ 100 MHz
—
—
TBD
ps (p-p)
FOUT < 100 MHz
—
—
TBD
mUI (p-p)
tOUTCCJ_IO (58)
Cycle-to-cycle jitter for clock output
on the regular I/O
FOUT ≥ 100 MHz
—
—
TBD
ps (p-p)
FOUT < 100 MHz
—
—
TBD
mUI (p-p)
tCASC_OUTPJ_DC
Period jitter for dedicated clock
output in cascaded PLLs
FOUT ≥ 100 MHz
—
—
TBD
ps (p-p)
FOUT < 100 MHz
—
—
TBD
mUI (p-p)
Related Information
Memory Output Clock Jitter Specifications on page 54
Provides more information about the external memory interface clock output jitter specifications.
(56)
(57)
(58)
A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source with jitter
< 120 ps.
FREF is fIN/N, specification applies when N = 1.
External memory interface clock output jitter specifications use a different measurement method, which are available in Memory Output Clock Jitter
Specification for Arria 10 Devices table.
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DSP Block Specifications
41
DSP Block Specifications
Table 38: DSP Block Performance Specifications for Arria 10 Devices (VCC and VCCP at 0.9 V Typical Value)—Preliminary
Performance
Mode
(59)
(60)
–E1L, –E1M
(59), –E1S
–I1L, –
I1M (59), –I1S
–E2L, –E2S
–I2L, –I2S
–E1M (60), –
E3S
–I1M (60), –I3S
Unit
Fixed-point 18 × 19 multiplication
mode
548
528
456
438
364
346
MHz
Fixed-point 27 × 27 multiplication
mode
541
522
450
434
358
344
MHz
Fixed-point 18 × 18 multiplier adder
mode
548
529
459
440
370
351
MHz
Fixed-point 18 × 18 multiplier adder
summed with 36-bit input mode
539
517
444
422
349
326
MHz
Fixed-point 18 × 19 systolic mode
548
529
459
440
370
351
MHz
Complex 18 × 19 multiplication mode
548
528
456
438
364
346
MHz
Floating point multiplication mode
548
527
447
427
347
326
MHz
Floating point adder or substract mode
488
471
388
369
288
266
MHz
Floating point multiplier adder or
substract mode
483
465
386
368
290
270
MHz
Floating point multiplier accumulate
mode
510
490
418
393
326
294
MHz
Floating point vector one mode
502
482
404
382
306
282
MHz
Floating point vector two mode
474
455
383
367
293
278
MHz
When you power VCC and VCCP at nominal voltage of 0.90 V.
When you power VCC and VCCP at lower voltage of 0.83 V.
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Memory Block Specifications
Table 39: DSP Block Performance Specifications for Arria 10 Devices (VCC and VCCP at 0.95 V Typical Value)—Preliminary
Mode
Performance
Unit
–I1L, –I1M (59), –I1S
–I2L, –I2S
Fixed-point 18 × 19 multiplication mode
635
517
MHz
Fixed-point 27 × 27 multiplication mode
633
517
MHz
Fixed-point 18 × 18 multiplier adder mode
635
516
MHz
Fixed-point 18 × 18 multiplier adder summed with 36-bit input
mode
631
509
MHz
Fixed-point 18 × 19 systolic mode
635
516
MHz
Complex 18 × 19 multiplication mode
635
517
MHz
Floating point multiplication mode
635
501
MHz
Floating point adder or substract mode
564
468
MHz
Floating point multiplier adder or substract mode
564
475
MHz
Floating point multiplier accumulate mode
581
482
MHz
Floating point vector one mode
574
471
MHz
Floating point vector two mode
550
450
MHz
Memory Block Specifications
To achieve the maximum memory block performance, use a memory block clock that comes through global clock routing from an on-chip PLL
and set to 50% output duty cycle. Use the Quartus II software to report timing for the memory block clocking schemes.
When you use the error detection cyclical redundancy check (CRC) feature, there is no degradation in fMAX.
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Memory Block Specifications
43
Table 40: Memory Block Performance Specifications for Arria 10 Devices—Preliminary
Resources Used
Memory
MLAB
(61)
Performance
ALUTs
Memory
Block
–E1L,
–E1M (61),
–E1S
–I1L,
–I1M (61), –
I1S
–E1M (62),
–I1M (62)
–E2L, –E2S,
–I2L, –I2S
–E3S, –I3S
Unit
Single port, all supported
widths (×16/×32)
0
1
700
660
490
570
490
MHz
Simple dual-port, all
supported widths (×16/×32)
0
1
700
660
490
570
490
MHz
Simple dual-port with read
and write at the same address
0
1
460
450
330
400
330
MHz
ROM, all supported width
(×16/×32)
0
1
700
660
490
570
490
MHz
Mode
When you power VCC and VCCP at nominal voltage of 0.90 V.
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Memory Block Specifications
Resources Used
Memory
M20K Block
(61)
(62)
(62)
Performance
ALUTs
Memory
Block
–E1L,
–E1M (61),
–E1S
–I1L,
–I1M (61), –
I1S
–E1M (62),
–I1M (62)
–E2L, –E2S,
–I2L, –I2S
–E3S, –I3S
Unit
Single-port, all supported
widths
0
1
730
690
510
625
530
MHz
Simple dual-port, all
supported widths
0
1
730
690
510
625
530
MHz
Simple dual-port with the
read-during-write option set
to Old Data, all supported
widths
0
1
550
520
410
470
410
MHz
Simple dual-port with ECC
enabled, 512 × 32
0
1
470
450
360
410
360
MHz
Simple dual-port with ECC
and optional pipeline registers
enabled, 512 × 32
0
1
620
590
470
520
470
MHz
True dual port, all supported
widths
0
1
730
690
510
625
530
MHz
ROM, all supported widths
0
1
730
690
510
680
570
MHz
Mode
When you power VCC and VCCP at nominal voltage of 0.90 V.
When you power VCC and VCCP at lower voltage of 0.83 V.
When you power VCC and VCCP at lower voltage of 0.83 V.
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Temperature Sensing Diode Specifications
45
Temperature Sensing Diode Specifications
Internal Temperature Sensing Diode Specifications
Table 41: Internal Temperature Sensing Diode Specifications for Arria 10 Devices—Preliminary
Temperature Range
Accuracy
Offset Calibrated
Option
Sampling
Rate
Conversion
Time
Resolution
Minimum Resolution with no
Missing Codes
–40 to 125 °C
±5 °C
No
1 MHz
< 5 ms
10 bits
10 bits
External Temperature Sensing Diode Specifications
Table 42: External Temperature Sensing Diode Specifications for Arria 10 Devices—Preliminary
Description
Min
Typ
Max
Unit
Ibias, diode source current
10
—
100
μA
Vbias, voltage across diode
0.3
—
0.9
V
Series resistance
—
—
<1
Ω
Diode ideality factor
—
1.03
—
—
Internal Voltage Sensor Specifications
Table 43: Internal Voltage Sensor Specifications for Arria 10 Devices—Preliminary
Parameter
Minimum
Typical
Maximum
Unit
Resolution
10
—
12
Bit
Sampling rate
—
—
500
Ksps
Differential non-linearity (DNL)
—
—
±1
LSB
Integral non-linearity (INL)
—
—
±3
LSB
Input capacitance
—
20
—
pF
Signal to noise and distortion ratio (SNR)
60
—
—
dB
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Periphery Performance Specifications
Parameter
Minimum
Typical
Maximum
Unit
—
—
20
MHz
Input signal range for Vsigp
0
—
1.5
V
Common mode voltage on Vsign
0
—
0.25
V
Input signal range for Vsigp – Vsign
0
—
1.25
V
Input signal range for Vsigp
0
—
1.25
V
–0.625
—
0.625
V
Clock frequency
Unipolar Input Mode
Bipolar Input Mode
Input signal range for Vsigp – Vsign
Periphery Performance Specifications
This section describes the periphery performance, high-speed I/O, and external memory interface.
Actual achievable frequency depends on design and system specific factors. Ensure proper timing closure in your design and perform HSPICE/
IBIS simulations based on your specific design and system setup to determine the maximum achievable frequency in your system.
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High-Speed I/O Specifications
47
High-Speed I/O Specifications
Table 44: High-Speed I/O Specifications for Arria 10 Devices—Preliminary
When serializer/deserializer (SERDES) factor J = 3 to 10, use the SERDES block.
For LVDS applications, you must use the PLLs in integer PLL mode.
You must calculate the leftover timing margin in the receiver by performing link timing closure analysis. You must consider the board skew margin,
transmitter channel-to-channel skew, and receiver sampling margin to determine the leftover timing margin.
Symbol
(63)
(65)
(66)
–E2L, –E2S, –I2L, –I2S
–E1M (64), –I1M (64), –E3S,
–I3S
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
fHSCLK_in (input clock frequency)
True Differential I/O Standards
Clock boost
factor
W = 1 to 40 (65)
10
—
800
10
—
700
10
—
625
MHz
fHSCLK_in (input clock frequency)
Single Ended I/O Standards
Clock boost
factor
W = 1 to 40 (65)
10
—
625
10
—
625
10
—
525
MHz
—
—
—
800 (66)
—
—
700 (66)
—
—
625 (66)
MHz
fHSCLK_OUT (output clock
frequency)
(64)
Condition
–E1L, –E1M (63), –E1S, –I1L,
–I1M (63), –I1S
When you power VCC and VCCP at nominal voltage of 0.90 V.
When you power VCC and VCCP at lower voltage of 0.83 V.
Clock Boost Factor (W) is the ratio between the input data rate and the input clock rate.
This is achieved by using the PHY clock network.
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High-Speed I/O Specifications
Symbol
Condition
–E1L, –E1M (63), –E1S, –I1L,
–I1M (63), –I1S
Min
Typ
SERDES factor
J = 4 to 10 (68)(70)
(70)
—
SERDES factor
J = 3 (68)(70)(69)
(70)
—
SERDES factor J
= 2, uses DDR
registers
(70)
SERDES factor J
= 1, uses DDR
registers
Max
–E2L, –E2S, –I2L, –I2S
Min
Typ
(70)
—
(71)
(70)
—
—
840 (71)(72)
(70)
(70)
—
420 (71)(72)
Total jitter for
data rate,
600 Mbps –
1.6 Gbps
—
—
Total jitter for
data rate,
< 600 Mbps
—
tDUTY (73)
TX output clock
duty cycle for
Differential I/O
Standards
tRISE & & tFALL (69)
TCCS (73)(67)
Unit
Min
Typ
Max
(70)
—
1250 (71)
Mbps
(71)
(70)
—
(71)
Mbps
—
(71)(72)
(70)
—
(71)(72)
Mbps
(70)
—
(71)(72)
(70)
—
(71)(72)
Mbps
160
—
—
200
—
—
250
ps
—
0.1
—
—
0.12
—
—
0.15
UI
45
50
55
45
50
55
45
50
55
%
True Differential
I/O Standards
—
—
160
—
—
180
—
—
200
ps
True Differential
I/O Standards
—
—
150
—
—
150
—
—
150
ps
1600
(71)
Max
–E1M (64), –I1M (64), –E3S,
–I3S
1434
(71)
(69)
True Differential I/O
Standards - fHSDR
(data rate) (67)
Transmitter
tx Jitter - True
Differential I/O
Standards
(74)
(63)
(64)
When you power VCC and VCCP at nominal voltage of 0.90 V.
When you power VCC and VCCP at lower voltage of 0.83 V.
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Symbol
Condition
Receiver
fHSDR (data rate)
(without DPA) (67)
DPA (FIFO DPA run length
mode)
(67)
(69)
(70)
(71)
(72)
(73)
(74)
–E1L, –E1M (63), –E1S, –I1L,
–I1M (63), –I1S
–E2L, –E2S, –I2L, –I2S
–E1M (64), –I1M (64), –E3S,
–I3S
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
—
—
1600
—
—
1434
—
—
1250
Mbps
—
—
(71)
—
—
(71)
—
—
(71)
Mbps
SERDES factor
J = 3 to 10
(70)
—
(75)
(70)
—
(75)
(70)
—
(75)
Mbps
SERDES factor J
= 2, uses DDR
registers
(70)
—
(72)
(70)
—
(72)
(70)
—
(72)
Mbps
SERDES factor J
= 1, uses DDR
registers
(70)
—
(72)
(70)
—
(72)
(70)
—
(72)
Mbps
—
—
—
10000
—
—
10000
—
—
10000
UI
SERDES factor
True Differential I/O J = 4 to 10 (68)(70)(69)
Standards - fHSDRDPA
SERDES factor
(data rate)
J = 3 (68)(70)(69)
(68)
49
High-Speed I/O Specifications
Requires package skew compensation with PCB trace length.
The Fmax specification is based on the fast clock used for serial data. The interface Fmax is also dependent on the parallel clock domain which is design
dependent and requires timing analysis.
The VCC and VCCP must be on a combined power layer and a maximum load of 5 pF for chip-to-chip interface.
The minimum specification depends on the clock source (for example, the PLL and clock pin) and the clock routing resource (global, regional, or
local) that you use. The I/O differential buffer and serializer do not have a minimum toggle rate.
Pending silicon characterization.
The maximum ideal data rate is the SERDES factor (J) x the PLL maximum output frequency (fOUT) provided you can close the design timing and
the signal integrity meets the interface requirements.
Not applicable for DIVCLK = 1.
This applies to default pre-emphasis and VOD settings only.
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DPA Lock Time Specifications
Symbol
DPA (soft
DPA run length
CDR mode)
Condition
–E1L, –E1M (63), –E1S, –I1L,
–I1M (63), –I1S
–E2L, –E2S, –I2L, –I2S
–E1M (64), –I1M (64), –E3S,
–I3S
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
SGMII/GbE
protocol
—
—
5
—
—
5
—
—
5
UI
All other
protocols
—
—
50 data
transition
per 208
UI
—
—
50 data
transition
per 208
UI
—
—
50 data
transition
per 208
UI
—
Soft CDR
mode
Soft-CDR ppm
tolerance
—
—
—
300
—
—
300
—
—
300
± ppm
Non DPA
mode
Sampling Window
—
—
—
300
—
—
300
—
—
300
ps
DPA Lock Time Specifications
Figure 2: DPA Lock Time Specifications with DPA PLL Calibration Enabled
rx_reset
DPA Lock Time
rx_dpa_locked
256 data
transitions
(63)
(64)
(75)
(63)
(64)
96 slow
clock cycles
256 data
transitions
96 slow
clock cycles
256 data
transitions
When you power VCC and VCCP at nominal voltage of 0.90 V.
When you power VCC and VCCP at lower voltage of 0.83 V.
You can estimate the achievable maximum data rate for non-DPA mode by performing link timing closure analysis. You must consider the board
skew margin, transmitter delay margin, and receiver sampling margin to determine the maximum data rate supported.
When you power VCC and VCCP at nominal voltage of 0.90 V.
When you power VCC and VCCP at lower voltage of 0.83 V.
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DPA Lock Time Specifications
51
Table 45: DPA Lock Time Specifications for Arria 10 Devices—Preliminary
The specifications are applicable to both commercial and industrial grades. The DPA lock time is for one channel. One data transition is defined as a 0-to-1
or 1-to-0 transition.
Standard
SPI-4
Parallel Rapid I/O
Miscellaneous
(76)
Training Pattern
Number of Data
Transitions in One
Repetition of the Training
Pattern
Number of Repetitions per
256 Data Transitions (76)
Maximum Data Transition
00000000001111111111
2
128
640
00001111
2
128
640
10010000
4
64
640
10101010
8
32
640
01010101
8
32
640
This is the number of repetitions for the stated training pattern to achieve the 256 data transitions.
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LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications
LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications
Figure 3: LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications for a Data Rate Equal to 1.6 Gbps
LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specification
Jitter Amphlitude (UI)
25
8.5
0.35
0.1
F1
F3
F2
F4
Jitter Frequency (Hz)
Table 46: LVDS Soft-CDR/DPA Sinusoidal Jitter Mask Values for a Data Rate Equal to 1.6 Gbps—Preliminary
Jitter Frequency (Hz)
Altera Corporation
Sinusoidal Jitter (UI)
F1
10,000
25.00
F2
17,565
25.00
F3
1,493,000
0.35
F4
50,000,000
0.35
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DLL Range Specifications
53
Figure 4: LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications for a Data Rate Less than 1.6 Gbps
Sinusoidal Jitter Amplitude
20db/dec
0.1 UI
P-P
baud/1667
20 MHz
Frequency
DLL Range Specifications
Table 47: DLL Frequency Range Specifications for Arria 10 Devices—Preliminary
Arria 10 devices support memory interface frequencies lower than 667 MHz, although the reference clock that feeds the DLL must be at least 667 MHz. To
support interfaces below 667 MHz, multiply the reference clock feeding the DLL to ensure the frequency is within the supported range.
Parameter
Performance (for All Speed Grades)
Unit
667 – 1333
MHz
DLL operating frequency range
DQS Logic Block Specifications
Table 48: DQS Phase Shift Error Specifications for DLL-Delayed Clock (tDQS_PSERR) for Arria 10 Devices—Preliminary
This error specification is the absolute maximum and minimum error.
Symbol
tDQS_PSERR
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Performance (for All Speed Grades)
Unit
5
ps
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Memory Output Clock Jitter Specifications
Memory Output Clock Jitter Specifications
Table 49: Memory Output Clock Jitter Specifications for Arria 10 Devices—Preliminary
The clock jitter specification applies to the memory output clock pins clocked by an integer PLL, or generated using differential signal-splitter and double
data I/O circuits clocked by a PLL output routed on a PHY clock network as specified. Altera recommends using PHY clock networks for better jitter
performance.
The memory output clock jitter is applicable when an input jitter of 10 ps peak-to-peak is applied with bit error rate (BER) 10–12, equivalent to 14 sigma.
Parameter
PHY clock
Clock Network
Symbol
–E1L, –E1M (77), –E1S,
–I1L, –I1M (77), –I1S
–E1M (78), –I1M (78),
–E3S, –I3S
–E2L, –E2S, –I2L, –I2S
Min
Max
Min
Max
Min
Max
Unit
Clock period jitter
tJIT(per)
58
58
58
58
58
58
ps
Cycle-to-cycle period jitter
tJIT(cc)
58
58
58
58
58
58
ps
tJIT(duty)
58
58
58
58
58
58
ps
Duty cycle jitter
OCT Calibration Block Specifications
Table 50: OCT Calibration Block Specifications for Arria 10 Devices—Preliminary
Symbol
(77)
(78)
Description
Min
Typ
Max
Unit
—
—
20
MHz
OCTUSRCLK
Clock required by OCT calibration blocks
TOCTCAL
Number of OCTUSRCLK clock cycles required for
RS OCT /RT OCT calibration
> 1000
—
—
Cycles
TOCTSHIFT
Number of OCTUSRCLK clock cycles required for
OCT code to shift out
—
32
—
Cycles
TRS_RT
Time required between the dyn_term_ctrl and oe
signal transitions in a bidirectional I/O buffer to
dynamically switch between RS OCT and RT OCT
—
2.5
—
ns
When you power VCC and VCCP at nominal voltage of 0.90 V.
When you power VCC and VCCP at lower voltage of 0.83 V.
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HPS Specifications
55
Figure 5: Timing Diagram for on oe and dyn_term_ctrl Signals
RX
Tristate
TX
Tristate
RX
oe
dyn_term_ctrl
TRS_RT
TRS_RT
HPS Specifications
This section provides HPS specifications and timing for Arria 10 devices. The specifications are preliminary.
HPS Reset Input Requirements
Table 51: HPS Reset Input Requirements for Arria 10 Devices—Preliminary
Description
Min
Max
Unit
HPS cold reset pulse width
600
—
ns
HPS warm reset pulse width
600
—
ns
Cold reset deassertion to BSEL sampling, using osc 1 clock
—
1000
osc1 clocks
Cold reset deassertion to BSEL sampling, using secure clock,
without RAM clearing
—
100
μs
Cold reset deassertion to BSEL sampling, using secure clock, with
RAM clearing
—
50
ms
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HPS Clock Performance
HPS Clock Performance
Table 52: HPS Clock Performance for Arria 10 Devices—Preliminary
Symbol/Description
–3 Speed Grade
–2 Speed Grade
–1 Speed Grade
Unit
mpu_base_clk
800
1200
1500
MHz
noc_base_clk
400
400
500
MHz
h2f_user0_clk
400
400
400
MHz
h2f_user1_clk
400
400
400
MHz
hmc_free_clk
433
544
667
MHz
Min
Typ
Max
Unit
Clock input range
10
—
50
MHz
Clock input jitter tolerance
—
—
2
%
Clock input duty cycle
45
50
55
%
HPS PLL Specifications
HPS PLL Input Requirements
Table 53: HPS PLL Input Requirements for Arria 10 Devices—Preliminary
Description
HPS PLL Performance
Table 54: HPS PLL Performance for Arria 10 Devices—Preliminary
Description
HPS PLL VCO output
Altera Corporation
–3 Speed Grade
–2 Speed Grade
–1 Speed Grade
Min
Max
Min
Max
Min
Max
320
1600
320
2400
320
3000
Unit
MHz
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HPS PLL Output Specifications
57
HPS PLL Output Specifications
The maximum HPS PLL lock time is 10 μs for all speed grades.
Quad SPI Flash Timing Characteristics
Table 55: Quad Serial Peripheral Interface (SPI) Flash Timing Requirements for Arria 10 Devices—Preliminary
The input parameters are still pending characterization. Note that Arria 10 HPS boot loader calibrates the input timing automatically.
Symbol
Description
Min
Typ
Max
Unit
Tsclk
SCLK_OUT clock period
10
—
—
ns
Tdutycycle
SCLK_OUT duty cycle
45
50
55
%
Tdssfrst(79)
QSPI_SS asserted to first SCLK_OUT edge
0.5
—
3
ns
Tdsslst(79)
Last SCLK_OUT edge to QSPI_SS deasserted
–2
—
0.5
ns
Tdo
QSPI_DATA output delay
1
—
3
ns
Minimum delay of slave select deassertion
between two back-to-back transfer
1
—
—
SCLK_OUT
Tdssb2b
(80)
Figure 6: Quad SPI Flash Serial Input Timing Diagram
Tdsslst (min)
Tdssfrst (max)
QSPI_SS
SCLK_OUT
QSPI_DATA
(79)
(80)
Tdsslst (max)
Tdssfrst (min)
Tdo (max)
Tdo (min)
OUT0
OUT1
IN
You can increase this delay using the delay register in the Quad SPI module.
This delay is programmable in whole QSPI_CLK increments using the delay register in the Quad SPI module.
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SPI Timing Characteristics
SPI Timing Characteristics
Table 56: SPI Master Timing Requirements for Arria 10 Devices—Preliminary
You can adjust the input delay timing using the rx_sample_dly register.
Symbol
(81)
Description
Min
Typ
Max
Unit
16.67
—
—
ns
Tspi_clk
SPI_CLK clock period
Tdutycycle
SPI_CLK duty cycle
45
50
55
%
Tdssfrst
SPI_SS asserted to first SPI_CLK edge
1.5
—
3.5
ns
Tdsslst
Last SPI_CLK edge to SPI_SS deasserted
–0.6
—
1.4
ns
Tdio
Master-out slave-in (MOSI) output delay
1
—
4
ns
Tsu
Input setup in respect to SPI_CLK rising edge
2
—
—
ns
Th
Input hold in respect to SPI_CLK rising edge
0
—
—
ns
Tdssb2b
Minimum delay of slave select deassertion
between two back-to-back transfers (frames)
1
—
—
SPI_CLK
(81)
You can adjust this delay using the rx_sample_dly register in the SPI Master module. A delay of 0 is not allowed.
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SPI Timing Characteristics
59
Figure 7: SPI Master Timing Diagram
Tdsslst (min)
Tdssfrst (max)
SPI_SS
Tdsslst (max)
Tdssfrst (min)
SPI_CLK
Tdio (max)
Tdio (min)
SPI_MOSI
OUT0
OUT1
Tsu
Th
IN
SPI_MISO
Table 57: SPI Slave Timing Requirements for Arria 10 Devices—Preliminary
Symbol
(82)
Description
Min
Typ
Max
Unit
Tclk
SPI_CLK clock period
20
—
—
ns
Tdutycycle
SPI_CLK duty cycle
45
50
55
%
Ts
SPI slave input setup time
5
—
—
ns
Th
SPI slave input hold time
5
—
—
ns
Tssfsu
SPI_SS asserted to first active SPI_CLK edge setup (82)
5
—
—
ns
Tssfh
SPI_SS asserted to first active SPI_CLK edge hold
5
—
—
ns
Tsslsu
SPI_SS deasserted to last active SPI_CLK edge setup (82)
5
—
—
ns
Tsslh
SPI_SS deasserted to last active SPI_CLK edge hold (82)
5
—
—
ns
Td
Master-in slave-out (MISO) output delay
1
—
4
ns
(82)
The active edge depends on clock polarity and operating protocol.
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SD/MMC Timing Characteristics
Figure 8: SPI Slave Timing Diagram
Tsslh
Tssfu
SPI_SS
SPI_CLK
SPI_MISO
Tssfh
Tsslsu
Td (max)
Td (min)
OUT0
OUT1
Ts
Th
IN
SPI_MOSI
SD/MMC Timing Characteristics
Table 58: Secure Digital (SD)/MultiMediaCard (MMC) Timing Requirements for Arria 10 Devices—Preliminary
These timings apply to SD, MMC, and embedded MMC cards operating at 1.8 V and 3.3 V.
Symbol
Description
Min
Typ
Max
Unit
SDMMC_CLK_OUT clock period (Identification
mode)
—
2500
—
ns
SDMMC_CLK_OUT clock period (Standard SD
mode)
—
40
—
ns
SDMMC_CLK_OUT clock period (High speed
SD mode)
—
20
—
ns
Tdutycycle
SDMMC_CLK_OUT duty cycle
45
50
55
%
Tsu
SDMMC_CMD/SDMMC_D[7:0] input setup (83)
4.0
—
—
ns
Tclk
(83)
These values assume the use of the phase shift implemented in the Boot ROM using smplsel = 0 and TMMC_CLK = 50 MHz (20 ns) in this equation: 4
– (TMMC_CLK × smpl_sel / 8) ns. The smplsel field is in the sdmmc register in the System Manager module.
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USB ULPI Timing Characteristics
Symbol
Th
Td
Description
Min
Typ
Max
Unit
SDMMC_CMD/SDMMC_D[7:0] input hold (84)
1.0
—
—
ns
SDMMC_CMD/SDMMC_D[7:0] output delay
5.5
—
12.5
ns
(85)
61
Figure 9: SD/MMC Timing Diagram
SDMMC_CLK_OUT
Td
SDMMC_CMD and SDMMC_D (Out)
Command/Data Out
TSU
Th
SDMMC_CMD and SDMMC_D (In)
Command/Data In
USB ULPI Timing Characteristics
Table 59: USB 2.0 Transceiver Macrocell Interface Plus (UTMI+) Low Pin Interface (ULPI) Timing Requirements for Arria 10 Devices—Preliminary
Symbol
Tclk
(84)
(85)
Description
USB_CLK clock period
Min
Typ
Max
Unit
—
16.667
—
ns
These values assume the use of the phase shift implemented in the Boot ROM using smplsel = 0 and TMMC_CLK = 50 MHz (20 ns) in this equation: 1
+ (TMMC_CLK × smpl_sel / 8) ns. The smplsel field is in the sdmmc register in the System Manager module.
These values assume the use of the phase shift implemented in the Boot ROM using drvsel = 3 and TMMC_CLK = 50 MHz (20 ns) in the following
equations:
• For min value: (TMMC_CLK × drv_sel / 8) – 2 ns
• For max value: (TMMC_CLK × drv_sel / 8) + 5 ns
The drvsel field is in the sdmmc register in the System Manager module.
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Ethernet Media Access Controller (EMAC) Timing Characteristics
Symbol
Description
Min
Typ
Max
Unit
Td
Clock to USB_STP/USB_DATA[7:0] output delay
1.5
—
8
ns
Tsu
Setup time for USB_DIR/USB_NXT/USB_
DATA[7:0]
2
—
—
ns
Th
Hold time for USB_DIR/USB_NXT/USB_
DATA[7:0]
1
—
—
ns
Figure 10: USB ULPI Timing Diagram
USB_CLK
USB_STP
Td
To PHY
USB_DATA[7:0]
From PHY
TSU
USB_DIR and USB_NXT
Th
Ethernet Media Access Controller (EMAC) Timing Characteristics
Table 60: Reduced Gigabit Media Independent Interface (RGMII) TX Timing Requirements for Arria 10 Devices—Preliminary
Symbol
Description
Min
Typ
Max
Unit
Tclk (1000Base-T)
TX_CLK clock period
—
8
—
ns
Tclk (100Base-T)
TX_CLK clock period
—
40
—
ns
Tclk (10Base-T)
TX_CLK clock period
—
400
—
ns
Tdutycycle
TX_CLK duty cycle
45
50
55
%
Td
TX_CLK to TXD/TX_CTL output data delay
–0.5
—
0.5
ns
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63
Figure 11: RGMII TX Timing Diagram
TX_CLK
TX_D[3:0]
Td
TX_CTL
Table 61: RGMII RX Timing Requirements for Arria 10 Devices—Preliminary
Symbol
Description
Min
Typ
Unit
Tclk (1000Base-T)
RX_CLK clock period
—
8
ns
Tclk (100Base-T)
RX_CLK clock period
—
40
ns
Tclk (10Base-T)
RX_CLK clock period
—
400
ns
Tsu
RX_D/RX_CTL setup time
1
—
ns
Th
RX_D/RX_CTL hold time
2.5
—
ns
Figure 12: RGMII RX Timing Diagram
RX_CLK
TSU
Th
RX_D[3:0]
RX_CTL
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Ethernet Media Access Controller (EMAC) Timing Characteristics
Table 62: Reduced Media Independent Interface (RMII) Clock Timing Requirements for Arria 10 Devices—Preliminary
Symbol
Description
Min
Typ
Max
Unit
Tclk (100Base-T)
TX_CLK clock period
—
20
—
ns
Tclk (10Base-T)
TX_CLK clock period
—
20
—
ns
Tdutycycle
Clock duty cycle, internal clock source
45
50
55
%
Tdutycycle
Clock duty cycle, external clock source
35
50
65
%
Table 63: RMII TX Timing Requirements for Arria 10 Devices—Preliminary
Symbol
Td
Description
TX_CLK to TXD/TX_CTL output data delay
Min
Max
Unit
0.45
4
ns
Table 64: RMII RX Timing Requirements for Arria 10 Devices—Preliminary
Symbol
Description
Min
Unit
Tsu
RX_D/RX_CTL setup time
1
ns
Th
RX_D/RX_CTL hold time
0.4
ns
Table 65: Management Data Input/Output (MDIO) Timing Requirements for Arria 10 Devices—Preliminary
Symbol
Description
Min
Typ
Max
Unit
—
400
—
ns
10.2
—
20
ns
Tclk
MDC clock period
Td
MDC to MDIO output data delay
Tsu
Setup time for MDIO data
10
—
—
ns
Th
Hold time for MDIO data
10
—
—
ns
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I2C Timing Characteristics
65
Figure 13: MDIO Timing Diagram
MDC
Td
MDIO_OUT
TSU
Th
MDIO_IN
I2C Timing Characteristics
Table 66: I2C Timing Requirements for Arria 10 Devices—Preliminary
Symbol
(86)
Description
Standard Mode
Fast Mode
Min
Max
Min
Max
Unit
Tclk
Serial clock (SCL) clock period
10
—
2.5
—
μs
tHIGH
SCL high period
4
—
0.6
—
μs
tLOW
SCL low period
4.7
—
1.3
—
μs
tSU;DAT
Setup time for serial data line (SDA) data to
SCL
0.25
—
0.1
—
μs
tHD;DAT(86)
Hold time for SCL to SDA data
0
3.15
0
0.6
μs
tVD;DAT and
tVD;ACK
SCL to SDA output data delay
—
3.45
—
0.9
μs
tSU;STA
Setup time for a repeated start condition
4.7
—
0.6
—
μs
tHD;STA
Hold time for a repeated start condition
4
—
0.6
—
μs
tSU;STO
Setup time for a stop condition
4
—
0.6
—
μs
You must enable an internal delay in the embedded software. The delay is programmable using the ic_sda_hold register in the I2C controller.
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I2C Timing Characteristics
Symbol
Standard Mode
Description
Fast Mode
Min
Max
Min
Max
Unit
tBUF
SDA high pulse duration between STOP and
START
4.7
—
1.3
—
μs
tr
SCL rise time
—
1000
20
300
ns
tf
SCL fall time
—
300
20 × (Vdd /
5.5 V) (87)
300
ns
tr
SDA rise time
—
1000
20
300
ns
tf
SDA fall time
—
300
20 × (Vdd /
5.5 V) (87)
300
ns
Figure 14: I2C Timing Diagram
tf
tr
tSU;DAT
SDA
tHD;DAT
tf
tHIGH
tr
tVD;DAT
SCL
tHD;STA
Tclk
tLOW
tBUF
SDA
tSU;STA
tHD;STA
tVD;ACK
tSU;STO
SCL
(87)
Vdd is the I2C bus voltage.
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NAND Timing Characteristics
67
NAND Timing Characteristics
Table 67: NAND ONFI 1.0 Timing Requirements for Arria 10 Devices—Preliminary
Symbol
Min
Max
Unit
tWP(88)
Write enable pulse width
10
—
ns
tWH(88)
Write enable hold time
7
—
ns
tRP(88)
Read enable pulse width
10
—
ns
tREH(88)
Read enable hold time
7
—
ns
tCLS(88)
Command latch enable to write enable setup time
10
—
ns
tCLH
Command latch enable to write enable hold time
5
—
ns
tCS(88)
Chip enable to write enable setup time
15
—
ns
tCH(88)
Chip enable to write enable hold time
5
—
ns
tALS
Address latch enable to write enable setup time
10
—
ns
tALH(88)
Address latch enable to write enable hold time
5
—
ns
tDS(88)
Data to write enable setup time
7
—
ns
tDH(88)
Data to write enable hold time
5
—
ns
tCEA
Chip enable to data access time
—
100
ns
tREA
Read enable to data access time
—
40
ns
tRHZ
Read enable to data high impedance
—
200
ns
tRR
Ready to read enable low
20
—
ns
Write enable high to R/B low
—
200
ns
(88)
(88)
tWB
(88)
(88)
Description
This timing is software programmable.
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NAND Timing Characteristics
Figure 15: NAND Command Latch Timing Diagram
CLE
tCLS
tCLH
tCS
tCH
CE
tWP
WE
tALS
tALH
ALE
tDS
IO0-7
R/B
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tDH
Command
tWB
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69
Figure 16: NAND Address Latch Timing Diagram
tCLS
CLE
tCS
tWC
CE
tWP
WE
ALE
IO0-7
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tWH
tALS
tALH
tDS
tDH
Address
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NAND Timing Characteristics
Figure 17: NAND Data Input Cycle Timing Diagram
tCLH
CLE
tCH
CE
tWP
tWP
tWP
WE
tWH
tALS
ALE
tDS
tDH
tDS
DIN 0
IOx
tDH
tDS
DIN 1
tDH
DIN n
Figure 18: NAND Data Output Cycle Timing Diagram
tCEA
CE
tRP
tRP
RE
tREH
tRR
R/B
IOx
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tRP
tREA
tRHZ
DOUT 0
tREA
tRHZ
DOUT 1
tREA
tRHZ
DOUT n
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71
Figure 19: NAND Extended Data Output (EDO) Cycle Timing Diagram
CE
tRP
RE
tREH
tRR
tREA
R/B
tREA
tRHOH
DOUT 0
IOx
tRHZ
DOUT 1
DOUT n
tCEA
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NAND Timing Characteristics
Figure 20: NAND Read Status Timing Diagram
tCLR
tCLS
CLE
tCLH
tCS
tCH
tCEA
CE
WE
RE
IO0-7
tWP
tRHZ
tDS
tDH
70h
Status
tREA
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ARM Trace Timing Characteristics
73
Figure 21: NAND Read Status Enhanced Timing Diagram
CLE
tCLS
tCLH
tCH
tCS
tCEA
CE
tWP
WE
tALH
tWP
tALS
tWH
tALH
ALE
RE
tDS
78h
IO0-7
tREA
tDH
R1
R2
R3
tRHZ
Status
ARM Trace Timing Characteristics
Table 68: ARM Trace Timing Requirements for Arria 10 Devices—Preliminary
Symbol
Description
Min
Typ
Max
Unit
Tclk
CLK clock period
5
—
—
ns
Tdutycycle
CLK maximum duty cycle
45
50
55
%
Td
CLK to D0–D3 output data delay
–0.5
—
1
ns
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GPIO Interface
Figure 22: ARM Trace Timing Diagram
Tclk
D0 - D3 (DDR)
D0
D1
D2
td
D3
D4
td
GPIO Interface
The general-purpose I/O (GPIO) interface has debounce circuitry included to remove signal glitches. The debounce clock frequency ranges from
125 Hz to 32 kHz. The minimum pulse width is 2 debounce clock cycles and the minimum detectable GPIO pulse width is 62.5 us. Any pulses
shorter than 2 debounce clock cycles are filtered.
Configuration Specifications
This section provides configuration specifications and timing for Arria 10 devices.
POR Specifications
Power-on reset (POR) delay is defined as the delay between the time when all the power supplies monitored by the POR circuitry reach the
minimum recommended operating voltage to the time when the nSTATUS is released high and your device is ready to begin configuration.
Table 69: Fast and Standard POR Delay Specification for Arria 10 Devices—Preliminary
POR Delay
Fast
Standard
(89)
Minimum
Maximum
Unit
4
12 (89)
ms
100
300
ms
The maximum pulse width of the fast POR delay is 12 ms, providing enough time for the PCIe hard IP to initialize after the POR trip.
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JTAG Configuration Timing
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Related Information
MSEL Pin Settings
Provides more information about POR delay based on MSEL pin settings for each configuration scheme.
JTAG Configuration Timing
Table 70: JTAG Timing Parameters and Values for Arria 10 Devices—Preliminary
Symbol
Description
Min
Max
Unit
30, 167 (90)
—
ns
tJCP
TCK clock period
tJCH
TCK clock high time
14
—
ns
tJCL
TCK clock low time
14
—
ns
tJPSU (TDI)
TDI JTAG port setup time
2
—
ns
tJPSU (TMS)
TMS JTAG port setup time
3
—
ns
tJPH
JTAG port hold time
5
—
ns
tJPCO
JTAG port clock to output
—
11
ns
tJPZX
JTAG port high impedance to valid output
—
14
ns
tJPXZ
JTAG port valid output to high impedance
—
14
ns
FPP Configuration Timing
DCLK-to-DATA[] Ratio (r) for FPP Configuration
Fast passive parallel (FPP) configuration requires a different DCLK-to-DATA[] ratio when you turn on encryption or the compression feature.
Depending on the DCLK-to-DATA[] ratio, the host must send a DCLK frequency that is r times the DATA[] rate in byte per second (Bps) or word per
second (Wps). For example, in FPP ×16 where the r is 2, the DCLK frequency must be 2 times the DATA[] rate in Wps.
(90)
The minimum TCK clock period is 167 ns if VCCBAT is within the range 1.2 V – 1.5 V when you perform the volatile key programming.
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FPP Configuration Timing when DCLK-to-DATA[] = 1
Table 71: DCLK-to-DATA[] Ratio for Arria 10 Devices—Preliminary
You cannot turn on encryption and compression at the same time for Arria 10 devices.
Configuration Scheme
FPP (8-bit wide)
FPP (16-bit wide)
FPP (32-bit wide)
Encryption
Compression
DCLK-to-DATA[] Ratio (r)
Off
Off
1
On
Off
1
Off
On
2
Off
Off
1
On
Off
2
Off
On
4
Off
Off
1
On
Off
4
Off
On
8
FPP Configuration Timing when DCLK-to-DATA[] = 1
Note: When you enable decompression or the design security feature, the DCLK-to-DATA[] ratio varies for FPP ×8, FPP ×16, and FPP ×32. For the
respective DCLK-to-DATA[] ratio, refer to the DCLK-to-DATA[] Ratio for Arria 10 Devices table.
Table 72: FPP Timing Parameters When the DCLK-to-DATA[] Ratio is 1 for Arria 10 Devices—Preliminary
Use these timing parameters when the decompression and design security features are disabled.
Symbol
(91)
Parameter
Minimum
Maximum
Unit
tCF2CD
nCONFIG low to CONF_DONE low
—
600
ns
tCF2ST0
nCONFIG low to nSTATUS low
—
600
ns
tCFG
nCONFIG low pulse width
2
—
μs
tSTATUS
nSTATUS low pulse width
268
1,506 (91)
μs
tCF2ST1
nCONFIG high to nSTATUS high
—
1,506 (92)
μs
This value is applicable if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width.
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FPP Configuration Timing when DCLK-to-DATA[] = 1
Symbol
Parameter
Minimum
Maximum
Unit
tCF2CK (93)
nCONFIG high to first rising edge on DCLK
1,506
—
μs
tST2CK
nSTATUS high to first rising edge of DCLK
2
—
μs
5.5
—
ns
0
—
ns
(93)
tDSU
DATA[] setup time before rising edge on DCLK
tDH
DATA[] hold time after rising edge on DCLK
tCH
DCLK high time
0.45 × 1/fMAX
—
s
tCL
DCLK low time
0.45 × 1/fMAX
—
s
tCLK
DCLK
1/fMAX
—
s
—
125
MHz
—
100
MHz
175
437
μs
4 × maximum DCLK
period
—
—
tCD2CU +
(600 × CLKUSR
period)
—
—
fMAX
period
DCLK frequency (FPP
×8/×16)
DCLK frequency (FPP
×32)
tCD2UM
CONF_DONE high to user mode
tCD2CU
CONF_DONE high to CLKUSR enabled
tCD2UMC
(94)
CONF_DONE high to user mode with CLKUSR option
on
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Related Information
FPP Configuration Timing
Provides the FPP configuration timing waveforms.
(92)
(93)
(94)
This value is applicable if you do not delay configuration by externally holding the nSTATUS low.
If nSTATUS is monitored, follow the tST2CK specification. If nSTATUS is not monitored, follow the tCF2CK specification.
The minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device.
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FPP Configuration Timing when DCLK-to-DATA[] >1
FPP Configuration Timing when DCLK-to-DATA[] >1
Table 73: FPP Timing Parameters When the DCLK-to-DATA[] Ratio is >1 for Arria 10 Devices—Preliminary
Use these timing parameters when you use the decompression and design security features.
Symbol
(97)
(98)
Maximum
Unit
nCONFIG low to CONF_DONE low
—
600
ns
tCF2ST0
nCONFIG low to nSTATUS low
—
600
ns
tCFG
nCONFIG low pulse width
2
—
μs
tSTATUS
nSTATUS low pulse width
268
1,506 (95)
μs
tCF2ST1
nCONFIG high to nSTATUS high
—
1,506 (95)
μs
nCONFIG high to first rising edge on DCLK
1,506
—
μs
tST2CK (96)
nSTATUS high to first rising edge of DCLK
2
—
μs
tDSU
DATA[] setup time before rising edge on DCLK
tDH
(96)
—
ns
DATA[] hold time after rising edge on DCLK
N–1/fDCLK
(97)
—
s
tCH
DCLK high time
0.45 × 1/fMAX
—
s
tCL
DCLK low time
0.45 × 1/fMAX
—
s
tCLK
DCLK period
1/fMAX
—
s
fMAX
(95)
Minimum
tCF2CD
tCF2CK
(96)
Parameter
5.5
DCLK frequency (FPP
×8/×16)
—
125
MHz
DCLK frequency (FPP
×32)
—
100
MHz
—
40
ns
—
40
ns
175
437
μs
tR
Input rise time
tF
Input fall time
tCD2UM
CONF_DONE high to user mode
(98)
You can obtain this value if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width.
If nSTATUS is monitored, follow the tST2CK specification. If nSTATUS is not monitored, follow the tCF2CK specification.
N is the DCLK-to-DATA ratio and fDCLK is the DCLK frequency the system is operating.
The minimum and maximum numbers apply only if you use the internal oscillator as the clock source for initializing the device.
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AS Configuration Timing
Symbol
tCD2CU
Parameter
CONF_DONE high to CLKUSR enabled
tCD2UMC
CONF_DONE high to user mode with CLKUSR option
on
Minimum
Maximum
Unit
4 × maximum DCLK
period
—
—
tCD2CU +
(600 × CLKUSR
period)
—
—
79
Related Information
FPP Configuration Timing
Provides the FPP configuration timing waveforms.
AS Configuration Timing
Table 74: AS Timing Parameters for AS ×1 and AS ×4 Configurations in Arria 10 Devices—Preliminary
The minimum and maximum numbers apply only if you choose the internal oscillator as the clock source for initializing the device.
The tCF2CD, tCF2ST0, tCFG, tSTATUS, and tCF2ST1 timing parameters are identical to the timing parameters for passive serial (PS) mode listed in PS Timing
Parameters for Arria 10 Devices table.
Symbol
Parameter
Minimum
Maximum
Unit
tCO
DCLK falling edge to AS_DATA0/ASDO output
—
4
ns
tSU
Data setup time before falling edge on DCLK
1
—
ns
tDH
Data hold time after falling edge on DCLK
1.5
—
ns
tCD2UM
CONF_DONE high to user mode
175
437
μs
tCD2CU
CONF_DONE high to CLKUSR enabled
4 × maximum DCLK
period
—
—
tCD2CU + (600 ×
CLKUSR period)
—
—
tCD2UMC
CONF_DONE high to user mode with CLKUSR option
on
Related Information
• PS Configuration Timing on page 80
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DCLK Frequency Specification in the AS Configuration Scheme
• AS Configuration Timing
Provides the AS configuration timing waveform.
DCLK Frequency Specification in the AS Configuration Scheme
Table 75: DCLK Frequency Specification in the AS Configuration Scheme—Preliminary
This table lists the internal clock frequency specification for the AS configuration scheme.
The DCLK frequency specification applies when you use the internal oscillator as the configuration clock source.
The AS multi-device configuration scheme does not support DCLK frequency of 100 MHz.
You can only set 12.5, 25, 50, and 100 MHz in the Quartus II software.
Parameter
DCLK frequency in AS configuration
scheme
Minimum
Typical
Maximum
Unit
5.3
7.9
12.5
MHz
10.6
15.7
25.0
MHz
21.3
31.4
50.0
MHz
42.6
62.9
100.0
MHz
PS Configuration Timing
Table 76: PS Timing Parameters for Arria 10 Devices—Preliminary
Symbol
(99)
(100)
Parameter
Minimum
Maximum
Unit
tCF2CD
nCONFIG low to CONF_DONE low
—
600
ns
tCF2ST0
nCONFIG low to nSTATUS low
—
600
ns
tCFG
nCONFIG low pulse width
2
—
μs
tSTATUS
nSTATUS low pulse width
268
1,506 (99)
μs
tCF2ST1
nCONFIG high to nSTATUS high
—
1,506
μs
(100)
This value is applicable if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width.
This value is applicable if you do not delay configuration by externally holding the nSTATUS low.
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Initialization
Symbol
Parameter
Minimum
Maximum
Unit
tCF2CK (101)
nCONFIG high to first rising edge on DCLK
1,506
—
μs
tST2CK
nSTATUS high to first rising edge of DCLK
2
—
μs
5.5
—
ns
0
—
ns
(101)
tDSU
DATA[] setup time before rising edge on DCLK
tDH
DATA[] hold time after rising edge on DCLK
tCH
DCLK high time
0.45 × 1/fMAX
—
s
tCL
DCLK low time
0.45 × 1/fMAX
—
s
tCLK
DCLK period
1/fMAX
—
s
fMAX
DCLK frequency
—
125
MHz
tCD2UM
CONF_DONE high to user mode (102)
175
437
μs
tCD2CU
CONF_DONE high to CLKUSR enabled
4 × maximum DCLK
period
—
—
tCD2UMC
CONF_DONE high to user mode with CLKUSR option
tCD2CU + (600 ×
CLKUSR period)
—
—
on
81
Related Information
PS Configuration Timing
Provides the PS configuration timing waveform.
Initialization
Table 77: Initialization Clock Source Option and the Maximum Frequency for Arria 10 Devices—Preliminary
Initialization Clock Source
(101)
(102)
Configuration Scheme
Maximum Frequency (MHz)
Internal Oscillator
AS, PS, and FPP
12.5
CLKUSR (103)(104)
AS, PS, and FPP
100
Minimum Number of Clock Cycles
600
If nSTATUS is monitored, follow the tST2CK specification. If nSTATUS is not monitored, follow the tCF2CK specification.
The minimum and maximum numbers apply only if you choose the internal oscillator as the clock source for initializing the device.
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Configuration Files
Configuration Files
Table 78: Uncompressed .rbf Sizes for Arria 10 Devices—Preliminary
Use this table to estimate the file size before design compilation. Different configuration file formats, such as a hexadecimal file (.hex) or tabular text file
(.ttf) format, have different file sizes.
For the different types of configuration file and file sizes, refer to the Quartus II software. However, for a specific version of the Quartus II software, any
design targeted for the same device has the same uncompressed configuration file size.
Variant
Arria 10 GX
Arria 10 GT
(103)
(104)
Product Line
Configuration .rbf Size
(bits)
IOCSR .rbf Size (bits)
Recommended EPCQ-L Serial Configuration
Device
GX 016
81,923,582
1,356,716
EPCQ-L256 or higher density
GX 022
81,923,582
1,356,716
EPCQ-L256 or higher density
GX 027
122,591,622
1,360,284
EPCQ-L256 or higher density
GX 032
122,591,622
1,360,284
EPCQ-L256 or higher density
GX 048
177,341,246
1,454,656
EPCQ-L256 or higher density
GX 057
252,831,072
1,549,028
EPCQ-L256 or higher density
GX 066
252,831,072
1,549,028
EPCQ-L256 or higher density
GX 900
351,292,512
1,885,396
EPCQ-L512 or higher density
GX 1150
351,292,512
1,885,396
EPCQ-L512 or higher density
GT 900
351,292,512
1,885,396
EPCQ-L512 or higher density
GT 1150
351,292,512
1,885,396
EPCQ-L512 or higher density
To enable CLKUSR as the initialization clock source, turn on the Enable user-supplied start-up clock (CLKUSR) option in the Quartus II software
from the General panel of the Device and Pin Options dialog box.
If you use the CLKUSR pin for AS and transceiver calibration simultaneously, the only allowed frequency is 100 MHz.
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Configuration Files
Variant
Arria 10 SX
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Product Line
Configuration .rbf Size
(bits)
IOCSR .rbf Size (bits)
Recommended EPCQ-L Serial Configuration
Device
SX 016
81,923,582
1,356,716
EPCQ-L256 or higher density
SX 022
81,923,582
1,356,716
EPCQ-L256 or higher density
SX 027
122,591,622
1,360,284
EPCQ-L256 or higher density
SX 032
122,591,622
1,360,284
EPCQ-L256 or higher density
SX 048
177,341,246
1,454,656
EPCQ-L256 or higher density
SX 057
252,831,072
1,549,028
EPCQ-L256 or higher density
SX 066
252,831,072
1,549,028
EPCQ-L256 or higher density
83
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Minimum Configuration Time Estimation
Minimum Configuration Time Estimation
Table 79: Minimum Configuration Time Estimation for Arria 10 Devices—Preliminary
The estimated values are based on the configuration uncompressed raw binary file (.rbf) sizes in Uncompressed .rbf Sizes for Arria 10 Devices table.
Active Serial (105)
Variant
Arria 10 GX
Arria 10 GT
(105)
Fast Passive Parallel (106)
Product Line
Width
DCLK
(MHz)
Minimum Configura‐
tion Time (ms)
Width
DCLK
(MHz)
Minimum Configuration
Time (ms)
GX 016
4
100
204.81
32
100
25.60
GX 022
4
100
204.81
32
100
25.60
GX 027
4
100
306.48
32
100
38.31
GX 032
4
100
306.48
32
100
38.31
GX 048
4
100
443.35
32
100
55.42
GX 057
4
100
632.08
32
100
79.01
GX 066
4
100
632.08
32
100
79.01
GX 900
4
100
883.20
32
100
110.40
GX 1150
4
100
883.20
32
100
110.40
GT 900
4
100
883.20
32
100
110.40
GT 1150
4
100
883.20
32
100
110.40
DCLK frequency of 100 MHz using external CLKUSR.
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Remote System Upgrades
Active Serial (105)
Variant
Fast Passive Parallel (106)
Product Line
Width
DCLK
(MHz)
Minimum Configura‐
tion Time (ms)
Width
DCLK
(MHz)
Minimum Configuration
Time (ms)
SX 016
4
100
204.81
32
100
25.60
SX 022
4
100
204.81
32
100
25.60
SX 027
4
100
306.48
32
100
38.31
SX 032
4
100
306.48
32
100
38.31
SX 048
4
100
443.35
32
100
55.42
SX 057
4
100
632.08
32
100
79.01
SX 066
4
100
632.08
32
100
79.01
Arria 10 SX
85
Related Information
Configuration Files on page 82
Remote System Upgrades
Table 80: Remote System Upgrade Circuitry Timing Specifications for Arria 10 Devices—Preliminary
Parameter
Minimum
Maximum
Unit
—
40
MHz
tRU_nCONFIG (108)
250
—
ns
tRU_nRSTIMER (109)
250
—
ns
fMAX_RU_CLK
(105)
(106)
(106)
(107)
(108)
(109)
(107)
DCLK frequency of 100 MHz using external CLKUSR.
Maximum FPGA FPP bandwidth may exceed bandwidth available from some external storage or control logic.
Maximum FPGA FPP bandwidth may exceed bandwidth available from some external storage or control logic.
This clock is user-supplied to the remote system upgrade circuitry. If you are using the ALTREMOTE_UPDATE megafunction IP core, the clock
user-supplied to the ALTREMOTE_UPDATE IP core must meet this specification.
This is equivalent to strobing the reconfiguration input of the ALTREMOTE_UPDATE IP core high for the minimum timing specification.
This is equivalent to strobing the reset_timer input of the ALTREMOTE_UPDATE IP core high for the minimum timing specification.
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User Watchdog Internal Circuitry Timing Specifications
Related Information
• Remote System Upgrade State Machine
Provides more information about configuration reset (RU_CONFIG) signal.
• User Watchdog Timer
Provides more information about reset_timer (RU_nRSTIMER) signal.
User Watchdog Internal Circuitry Timing Specifications
Table 81: User Watchdog Internal Oscillator Frequency Specifications for Arria 10 Devices—Preliminary
Parameter
User watchdog internal oscillator frequency
Minimum
Typical
Maximum
Unit
5.3
7.9
12.5
MHz
I/O Timing
Altera offers two ways to determine I/O timing—the Excel-based I/O Timing and the Quartus II Timing Analyzer.
Excel-based I/O timing provides pin timing performance for each device density and speed grade. The data is typically used prior to designing the
FPGA to get an estimate of the timing budget as part of the link timing analysis.
The Quartus II Timing Analyzer provides a more accurate and precise I/O timing data based on the specifics of the design after you complete
place-and-route.
Related Information
Arria 10 I/O Timing Spreadsheet
Provides the Arria 10 Excel-based I/O timing spreadsheet.
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Programmable IOE Delay
87
Programmable IOE Delay
Table 82: IOE Programmable Delay for Arria 10 Devices—Preliminary
For the exact values for each setting, use the latest version of the Quartus II software.
(110)
(111)
Fast Model
Slow Model
Available
Settings
Minimum
Offset (111)
Extended
Industrial
–I1L
–I2S
–I3S
–E2S
–E3S
Input Delay
Chain Setting
(IO_IN_DLY_
CHN)
64
0
1.829
1.820
4.128
4.764
5.485
4.764
5.485
ns
Output Delay
Chain Setting
(IO_OUT_
DLY_CHN)
16
0
0.433
0.430
0.990
1.145
1.326
1.145
1.326
ns
Parameter (110)
Unit
You can set this value in the Quartus II software by selecting Input Delay Chain Setting or Output Delay Chain Setting in the Assignment Name
column.
Minimum offset does not include the intrinsic delay.
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Glossary
Glossary
Table 83: Glossary
Term
Differential I/O Standards
Definition
Receiver Input Waveforms
Single-Ended Waveform
Positive Channel (p) = VIH
VID
Negative Channel (n) = VIL
VCM
Ground
Differential Waveform
VID
p-n=0V
VID
Transmitter Output Waveforms
Single-Ended Waveform
Positive Channel (p) = VOH
VOD
Negative Channel (n) = VOL
VCM
Ground
Differential Waveform
VOD
p-n=0V
VOD
fHSCLK
Left/right PLL input clock frequency.
fHSDR
High-speed I/O block—Maximum/minimum LVDS data transfer rate
(fHSDR = 1/TUI), non-DPA.
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Glossary
Term
89
Definition
fHSDRDPA
High-speed I/O block—Maximum/minimum LVDS data transfer rate
(fHSDRDPA = 1/TUI), DPA.
J
High-speed I/O block—Deserialization factor (width of parallel data bus).
JTAG Timing Specifications
JTAG Timing Specifications:
TMS
TDI
t JCH
t JCP
t JCL
tJPH
t JPSU
TCK
tJPZX
t JPXZ
tJPCO
TDO
Preliminary
Some tables show the designation as “Preliminary”. Preliminary characteristics are created using
simulation results, process data, and other known parameters.
Final numbers are based on actual silicon characterization and testing. The numbers reflect the actual
performance of the device under worst-case silicon process, voltage, and junction temperature conditions.
There are no preliminary designations on finalized tables.
RL
Receiver differential input discrete resistor (external to the Arria 10 device).
Sampling window (SW)
Timing Diagram—the period of time during which the data must be valid in order to capture it correctly.
The setup and hold times determine the ideal strobe position in the sampling window, as shown:
Bit Time
0.5 x TCCS
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Sampling Window
(SW)
RSKM
0.5 x TCCS
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Glossary
Term
Single-ended voltage referenced I/O
standard
Definition
The JEDEC standard for the SSTL and HSTL I/O defines both the AC and DC input signal values. The
AC values indicate the voltage levels at which the receiver must meet its timing specifications. The DC
values indicate the voltage levels at which the final logic state of the receiver is unambiguously defined.
After the receiver input has crossed the AC value, the receiver changes to the new logic state.
The new logic state is then maintained as long as the input stays beyond the DC threshold. This approach
is intended to provide predictable receiver timing in the presence of input waveform ringing.
Single-Ended Voltage Referenced I/O Standard
V CCIO
V OH
V IH(AC)
V REF
V IH(DC)
V IL(DC)
V IL(AC)
V OL
V SS
tC
High-speed receiver/transmitter input and output clock period.
TCCS (channel-to-channel-skew)
The timing difference between the fastest and slowest output edges, including the tCO variation and clock
skew, across channels driven by the same PLL. The clock is included in the TCCS measurement (refer to
the Timing Diagram figure under SW in this table).
tDUTY
High-speed I/O block—Duty cycle on high-speed transmitter output clock.
tFALL
Signal high-to-low transition time (80–20%)
tINCCJ
Cycle-to-cycle jitter tolerance on the PLL clock input
tOUTPJ_IO
Period jitter on the GPIO driven by a PLL
tOUTPJ_DC
Period jitter on the dedicated clock output driven by a PLL
tRISE
Signal low-to-high transition time (20–80%)
Timing Unit Interval (TUI)
The timing budget allowed for skew, propagation delays, and the data sampling window.
(TUI = 1/(Receiver Input Clock Frequency Multiplication Factor) = tC/w).
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Glossary
Term
Definition
VCM(DC)
DC Common mode input voltage.
VICM
Input Common mode voltage—The common mode of the differential signal at the receiver.
VID
Input differential voltage swing—The difference in voltage between the positive and complementary
conductors of a differential transmission at the receiver.
VDIF(AC)
AC differential input voltage—Minimum AC input differential voltage required for switching.
VDIF(DC)
DC differential input voltage— Minimum DC input differential voltage required for switching.
VIH
Voltage input high—The minimum positive voltage applied to the input which is accepted by the device
as a logic high.
VIH(AC)
High-level AC input voltage
VIH(DC)
High-level DC input voltage
VIL
Voltage input low—The maximum positive voltage applied to the input which is accepted by the device as
a logic low.
VIL(AC)
Low-level AC input voltage
VIL(DC)
Low-level DC input voltage
VOCM
Output Common mode voltage—The common mode of the differential signal at the transmitter.
VOD
Output differential voltage swing—The difference in voltage between the positive and complementary
conductors of a differential transmission at the transmitter.
VSWING
Differential input voltage
VIX
Input differential cross point voltage
VOX
Output differential cross point voltage
W
High-speed I/O block—Clock Boost Factor
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Document Revision History
Document Revision History
Date
September 2015
Version
2015.09.15
Changes
Made the following changes:
• Changed voltages in the "Transceiver Power Supply Operating Conditions for Arria 10 GX/SX Devices"
table.
• Changed maximum data rate conditions in the "Transmitter and Receiver Data Rate Performance" table.
• Changed conditions in the "Transmitter and Receiver Data Rate Performance" table in the Transceiver
Performance for Arria 10 GT Devices section.
• Changed conditions in the "Reference Clock Specifications" table.
• Changed the clock networks in the "Transceiver Clock Network Maximum Data Rate Specifications" table.
• Changed conditions in the "Receiver Specifications" table.
• Changed conditions in the "Transmitter Specifications" table.
June 2015
2015.06.12
• Changed the specifications for the backplane maximum data rate condition in the "Transmitter and Receiver
Data Rate Performance" table for Arria 10 GX/SX devices.
• Changed the specifications for transmitter REFCLK phase noise in the "Reference Clock Specifications" table.
• Added note in the following tables:
• Absolute Maximum Ratings for Arria 10 Devices: VCCPGM
• Maximum Allowed Overshoot During Transitions for Arria 10 Devices: LVDS I/O
• Recommended Operating Conditions for Arria 10 Devices: VI
• Added HPS Specifications.
• Updated recommended EPCQ-L serial configuration devices in the Uncompressed .rbf Sizes table.
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Date
May 2015
Version
2015.05.08
93
Changes
Made the following changes:
• Changed the specifications for the VICM (AC coupled) parameter in the "Reference Clock Specifications"
table.
• Changed the maximum frequency in the "CMU PLL Performance" table in the Transceiver Performance for
GT Devices section.
• Added a footnote to the transceiver speed grade 5 column in the "Transmitter and Receiver Data Rate
Performance" table.
May 2015
2015.05.04
• Updated the Maximum Allowed Overshoot During Transitions for Arria 10 Devices table.
• Added a note to tramp in the Recommended Operating Conditions for Arria 10 Devices table. Note: tramp is
the ramp time of each individual power supply, not the ramp time of all combined power supplies.
• Changed the minimum, typical, and maximum values for the transmitter and receiver power supply in the
"Transceiver Power Supply Operating Conditions for Arria 10 GT Devices" table.
• Added –1 speed grade in the condition column for VCCL_HPS at 0.95 V in HPS Power Supply Operating
Conditions for Arria 10 SX Devices table.
• Added –I1S, –I2S, and –E2S speed grades to the following tables:
•
•
•
•
•
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• Clock Tree Performance for Arria 10 Devices
• DSP Block Performance Specifications for Arria 10 Devices
• Memory Block Performance Specifications for Arria 10 Devices
• High-Speed I/O Specifications for Arria 10 Devices
• Memory Output Clock Jitter Specifications for Arria 10 Devices
Updated fIN minimum value from 27 MHz to 50 MHz for all speed grades in the Fractional PLL Specifica‐
tions for Arria 10 Devices table.
Changed the description for fINPFD to "Input clock frequency to the PFD" in the I/O PLL Specifications for
Arria 10 Devices table.
Updated DSP Block Performance Specifications for Arria 10 Devices table for VCC and VCCP at 0.9 V typical
value. Added DSP specifications for VCC and VCCP at 0.95 V typical value.
Updated Ibias minimum value from 8 μA to 10 μA and maximum value from 200 μA to 100 μA in the
External Temperature Sensing Diode Specifications for Arria 10 Devices table.
Added DPA (soft CDR mode) specifications in High-Speed I/O Specifications for Arria 10 Devices table.
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Document Revision History
Date
Version
Changes
• Added desription in POR Specificaitons section: Power-on reset (POR) delay is defined as the delay between
the time when all the power supplies monitored by the POR circuitry reach the minimum recommended
operating voltage to the time when the nSTATUS is released high and your device is ready to begin configura‐
tion.
• Moved the following timing diagrams to the Configuration, Design Security, and Remote System Upgrades
in Arria 10 Devices chapter.
• FPP Configuration Timing Waveform When the DCLK-to-DATA[] Ratio is 1
• FPP Configuration Timing Waveform When the DCLK-to-DATA[] Ratio is >1
• AS Configuration Timing Waveform
• PS Configuration Timing Waveform
• Removed the DCLK-to-DATA[] ratio when both encryption and compression are turned on. Added
description to the table: You cannot turn on encryption and compression at the same time for Arria 10
devices.
• Updated the AS Timing Parameters for AS ×1 and AS ×4 Configurations in Arria 10 Devices table as
follows:
•
•
•
•
•
•
Altera Corporation
• Changed the symbol for data hold time from tH to tDH.
• Updated the minimum value for tSU from 0 ns to 1 ns.
• Updated the minimum value for tDH from 2.5 ns to 1.5 ns.
Added a note to the DCLK Frequency Specification in the AS Configuration Scheme table. Note: You can
only set 12.5, 25, 50, and 100 MHz in the Quartus II software.
Added a note to the Initialization Clock Source Option and the Maximum Frequency for Arria 10 Devices.
Note: If you use the CLKUSR pin for AS and transceiver calibration simultaneously, the only allowed
frequency is 100 MHz.
Changed Arria 10 GS to Arria 10 SX in Uncompressed .rbf Sizes and Minimum Configuration Time
Estimation tables.
Added IO_IN_DLY_CHN and IO_OUT_DLY_CHN in the IOE Programmable Delay table.
Changed the Min/Typ/Max description for the VICM (AC coupled) parameter in the "Reference Clock
Specifications" table.
Changed the Min/Typ/Max values in the "Transceiver Power Supply Operating Conditions for Arria 10 GX/
SX Devices" table.
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Date
Version
95
Changes
• Changed the Min/Typ/Max values in the "Transceiver Power Supply Operating Conditions for Arria 10 GT
Devices" table.
• Added a footnote to the maximum data rate for GT channels in the "Transceiver Performance for GT
Devices" section.
• Made the following changes to the "Transceiver Performance for Arria 10 GX/SX Devices" section.
• Changed the maximum data rate condition for chip-to-chip and backplane in the "Transmitter and
Receiver Data Rate Performance" table.
• Added TX minimum data rate to the "Transmitter and Receiver Data Rate Performance" table.
• Changed the minimum frequency in the "ATX PLL Performance" table.
• Changed the minimum frequency in the "Fractional PLL Performance" table.
• Changed the minimum and maximum frequency in the "CMU PLL Performance" table.
• Made the following changes to the "Transceiver Performance for Arria 10 GT Devices" section.
•
•
•
•
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• Added TX minimum data rate to the "Transmitter and Receiver Data Rate Performance" table.
• Changed the maximum data rate condition for chip-to-chip and backplane in the "Transmitter and
Receiver Data Rate Performance" table.
• Changed the minimum frequency in the "ATX PLL Performance" table.
• Changed the minimum frequency in the "Fractional PLL Performance" table.
• Changed the minimum frequency in the "CMU PLL Performance" table.
Added voltage condition to the maximum peak-to-peak diff p-p after configuration and to the VICM specifi‐
cations in the "Receiver Specifications" table.
Changed the voltage conditions for VOCM in the "Transmitter Specifications" table.
Changed the VOD/VCCT Ratios in the "Typical Transmitter VOD Settings" table.
Added the "Transceiver Clock Network Maximum Data Rate Specifications" table.
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Document Revision History
Date
Version
January 2015
2015.01.23
Changes
• Added a note in the "Transceiver Power Supply Operating Conditions" section.
• Made the following changes to the "Reference Clock Specifications" table:
• Added the input reference clock frequency parameters for the CMU PLL, ATX PLL, and fPLL PLL.
• Changed the maximum specification for rise time and fall time.
• Added the VICM (AC and DC coupled) parameters.
• Changed the maximum value for Transmitter REFCLK Phase Noise (622 MHz) when ≥ 1 MHz.
• Changed the Min, Typ, and Max values for the reconfig_clk signal in the "Transceiver Clocks Specifica‐
tions" table.
• Made the following changes to the "Receiver Specifications" table:
• Added the maximum peak-to-peak differential input voltage after device configuration specifications.
• Changed the minimum specification for the minimum differential eye opening at receiver serial input
pins parameter.
• Removed the 120-ohm and 150-ohm conditions for the differential on-chip termination resistors
parameter.
• Added the VICM (AC and DC coupled) parameter.
• Added the Programmable DC Gain parameter.
• Made the following changes to the "Transmitter Specifications" table:
• Added the VOCM (AC coupled) parameter.
• Added the VOCM (DC coupled) parameter.
• Changed the rise and fall time mimimum and maximum specifications.
• Added the "Typical Transmitter VOD Settings" table.
• Added a note to VCC, VCCP, and VCCERAM typical values in Recommended Operating Conditions table.
Note: You can operate –1 and –2 speed grade devices at 0.9 V or 0.95 V typical value. You can operate -3
speed grade device at only 0.9 V typical value. Core performance shown in this datasheet is applicable for the
operation at 0.9 V. Operating at 0.95 V results in higher core performance and higher power consumption.
For more information about the performance and power consumption of 0.95 V operation, refer to the
Quartus II software timing reports and Early Power Estimator (EPE).
• Removed military grade operating junction temperature specifications (TJ) in Recommended Operating
Conditions table.
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Arria 10 Device Datasheet
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A10-DATASHEET
2015.09.15
Document Revision History
Date
Version
97
Changes
• Updated the VCCIO range for HSTL-18 I/O standard in Differential HSTL and HSUL I/O Standards for
Arria 10 Devices table as follows:
• Min: Updated from 1.425 V to 1.71 V
• Typ: Updated from 1.5 V to 1.8 V
• Max: Updated from 1.575 V to 1.89 V
• Added a statement to Differential I/O Standards Specifications for Arria 10 Devices table: Differential inputs
are powered by VCCPT which requires 1.8 V.
• Added statement in I/O Standard Specifications: You must perform timing closure analysis to determine the
maximum achievable frequency for general purpose I/O standards.
• Updated fractional PLL specifications.
• Updated fOUT_C to fOUT and updated the maximum value to 644 MHz for all speed grades.
• Updated fVCO minimum value from 2.4 GHz to 3.125 GHz.
• Removed fOUT_L, kVALUE, and fRES parameters.
• Updated I/O PLL specifications.
• Updated fOUT_C to fOUT and updated the maximum value to 644 MHz for all speed grades.
• Updated fOUT_EXT maximum value to 800 MHz (–1 speed grade), 720 MHz (–2 speed grade), and 650
MHz (–3 speed grade).
• Removed fRES parameter.
• Updated the description in Periphery Performance Specifications to mention that proper timing closure is
required in design.
• Updated AS Timing Parameters for AS x1 and AS x4 Configurations in Arria 10 Devices.
• Updated tSU minimum value from 1.5 ns to 0 ns.
• Updated tH minimum value from 0 ns to 2.5 ns.
• Updated CLKUSR initialization clock source maximum frequency from 125 MHz to 100 MHz for passive
configuration schemes (PS and FPP).
Arria 10 Device Datasheet
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A10-DATASHEET
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Document Revision History
Date
Version
Changes
• Added uncompressed .rbf sizes and minimum configuration time estimation for Arria 10 GX and GS
devices.
• Updated uncompressed .rbf sizes for Arria 10 GX 900 and 1150 devices, and Arria 10 GT 900 and 1150
devices.
• Updated configuration .rbf size from 335,106,890 bits to 351,292,512 bits.
• Updated IOCSR .rbf size from 6,702,138 bits to 1,885,396 bits.
• Updated minimum configuration time estimation for Arria 10 GX 900 and 1150 devices, and Arria 10 GT
900 and 1150 devices for the following configuration modes:
• Active serial: Updated from 837.77 ms to 883.20 ms.
• Fast Passive Parallel: Updated from 104.72 ms to 110.40 ms.
August 2014
2014.08.18
• Changed the 3 V I/O conditions in Table 2.
• Table 3:
• Added a note to the Minimum and Maximum operating conditions.
• Changed VCCERAM values.
• Changed the Maximum recommended operating conditions for 3 V I/O VI.
• Added a note to the I/O pin pull-up tolerance in Table 12.
• Changed the VIH values for LVTTL, LVCMOS and 2.5 I/O standards in Table 13.
• Table 14, Table 15, and Table 16:
• Added SSTL-12 I/O standard.
• Removed Class I, II for SSTL-135 and SSTL-125 I/O standards.
• Table 19:
• Changed the minimum data rate specification for transmitter and receiver data rates.
• Changed the minimum frequency specification for the fractional PLL.
• Changed the minimum frequency specification for the CMU PLL.
• Changed the Core Speed Grade with Power Options section in Table 20.
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Arria 10 Device Datasheet
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A10-DATASHEET
2015.09.15
Document Revision History
Date
Version
99
Changes
• Table 21:
• Changed the minimum data rate specification for transmitter and receiver data rates.
• Changed the minimum frequency specification for the Fractional PLL.
• Changed the minimum frequency specification for the CMU PLL.
• Changed the minimum frequency of the ATX PLL.
• Table 23:
•
•
•
•
•
• Added a note to the High Speed Differential I/O standard.
• Changed the specifications for CLKUSR pin.
Added columns in Table 29.
Changed the maximum fHSCLK_in and txJitter in Table 32.
Changed the minimum formula for tCD2UMC in Table 42, Table 43, Table 44, and Table 46.
Changed the CLKUSR maximum frequency and minimum number of cycles in Table 47.
Table 48:
• Changed the IOCSR .rbf size.
• Added Recommended EPCQ-L Serial Configuration Device.
• Changed the DCLK frequency and minimum configuration time for FPP in Table 49.
• Added the following tables:
• External Temperature Sensing Diode Specifications for Arria 10 Devices
• IOE Programmable Delay for Arria 10 Devices
• Removed the following figures:
• CTLE Response in High Gain Mode for Arria 10 Devices with Data Rates ≥ 8 Gbps
• Removed the CTLE Response in High Gain Mode for Arria 10 Devices with Data Rates < 8 Gbps
March 2014
2014.03.14
Updated Table 3, Table 5, Table 21, Table 23, Table 24, Table 32, and Table 41.
December 2013
2013.12.06
Updated Figure 1 and Figure 2.
December 2013
2013.12.02
Initial release.
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